KR870011787A - Signal receiver for TV receiver - Google Patents

Signal receiver for TV receiver Download PDF

Info

Publication number
KR870011787A
KR870011787A KR1019860004277A KR860004277A KR870011787A KR 870011787 A KR870011787 A KR 870011787A KR 1019860004277 A KR1019860004277 A KR 1019860004277A KR 860004277 A KR860004277 A KR 860004277A KR 870011787 A KR870011787 A KR 870011787A
Authority
KR
South Korea
Prior art keywords
output
input
receiver
analog
phase buffer
Prior art date
Application number
KR1019860004277A
Other languages
Korean (ko)
Inventor
노창우
Original Assignee
구자학
주식회사 금성사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 구자학, 주식회사 금성사 filed Critical 구자학
Priority to KR1019860004277A priority Critical patent/KR870011787A/en
Publication of KR870011787A publication Critical patent/KR870011787A/en

Links

Landscapes

  • Electronic Switches (AREA)
  • Studio Circuits (AREA)

Abstract

내용 없음No content

Description

텔레비젼 수상기용 신호 처리장치Signal receiver for TV receiver

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명장치의 개략구성도1 is a schematic configuration diagram of an apparatus of the present invention

제2도는 본 발명장치에서 사용된 프로그램의 유통도2 is a flow chart of a program used in the apparatus of the present invention.

Claims (1)

TV 수상기내의 영상신호 입력단자를 아날로그 디지털변환기(1)와 아날로그스위치(9)의 입력단자(a)에 연결하고 아날로그 디지털변환기(1)의 출력은 랫치(2)를 통하여 3상버퍼(3)에 연결하며, 3상버퍼(3)의 데이터출력을 메모리(4)와 3상버퍼(3′)에 연결하고, 3상버퍼(3′)의 출력을 랫치(32′)을통하여 디지털아날로그반환기(6)에 연결하며, 디자탈아날로그변환기(6)의 출력을 아날로그스위치(9)의 입력(b)에 연결하고, 메모리(4)의 어드레스 입력을 마이크로처리기(5)에 어드레스출력에 연결하되, 마이크로처리기(5)의 출력(WR,RD)을 각각 3상버퍼(23,3′)의 제어단자에 연결함과 동시에 반전기(7)와 NAND게이트(8)의 일측입력에 연결하며, 반전기(7)의 출력은NAND게이트(8)의 타측입력에 연결하되, NAND 게이트(8)의 출력은 아날로그스위치(9)의 제어단자(C)에 연결하여 된 텔레비전 수상기용 신호처리장치.The video signal input terminal in the TV receiver is connected to the input terminal (a) of the analog-to-digital converter (1) and the analog switch (9), and the output of the analog-to-digital converter (1) is connected to the three-phase buffer (3) through the latch (2). ), The data output of the three-phase buffer (3) is connected to the memory (4) and three-phase buffer (3 '), and the output of the three-phase buffer (3') through the latch (32 ') To the return (6), the output of the digital analog converter (6) to the input (b) of the analog switch (9), and the address input of the memory (4) to the address output to the microprocessor (5). Connect the outputs (WR, RD) of the microprocessor (5) to the control terminals of the three-phase buffers (23, 3 ') and at the same time to one input of the inverter (7) and the NAND gate (8). In addition, the output of the inverter 7 is connected to the other input of the NAND gate 8, the output of the NAND gate 8 is connected to the control terminal (C) of the analog switch 9 Appointed television receiver signal processor. ※ 참고사항:최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019860004277A 1986-05-30 1986-05-30 Signal receiver for TV receiver KR870011787A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019860004277A KR870011787A (en) 1986-05-30 1986-05-30 Signal receiver for TV receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019860004277A KR870011787A (en) 1986-05-30 1986-05-30 Signal receiver for TV receiver

Publications (1)

Publication Number Publication Date
KR870011787A true KR870011787A (en) 1987-12-26

Family

ID=72935217

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860004277A KR870011787A (en) 1986-05-30 1986-05-30 Signal receiver for TV receiver

Country Status (1)

Country Link
KR (1) KR870011787A (en)

Similar Documents

Publication Publication Date Title
JPS5724005A (en) Digital signal processor
KR860700300A (en) Input memory circuit means and its distribution method
KR870011787A (en) Signal receiver for TV receiver
KR830008221A (en) Numerical Control Device
JPS5478926A (en) Digital set circuit
KR890003240A (en) Video signal processing device
KR860004360A (en) Microprocessor Interface Device for Telecommunication System
KR930003568A (en) Controller
JPS57191753A (en) Register controlling system
SU1149400A2 (en) Scaling device with check
KR930020843A (en) Clock signal selection circuit
JPS57164320A (en) Reset system for microprocessor
KR900001258A (en) Converter circuit of encrypted cable TV
KR880008129A (en) Scalable Attribute Circuit
KR870011547A (en) Data signal processor using 8-bit and 16-bit central processing unit
KR910017298A (en) Global memory control system of digital signal processor
JPS57196363A (en) Automatic switching device of single chip microcomputer mode
KR910017321A (en) High speed digital signal analysis device
KR880005802A (en) Teletext secret page information signal sorting circuit
KR850005108A (en) Digital Device Reliability Improvement Inspection System
JPS5547525A (en) Data transmission method
KR890010887A (en) Compensation circuit of audio pulse
KR920010447A (en) Data loss prevention circuit between CPUs using dual port RAM
KR880008174A (en) Interrupt processing control circuit that processes multiple interrupt signals with one interrupt terminal
KR870011797A (en) Outdoor group addressable inverter

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application