KR870006642A - 로듐피복금 ic 금속처리방법 - Google Patents
로듐피복금 ic 금속처리방법 Download PDFInfo
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- KR870006642A KR870006642A KR860010174A KR860010174A KR870006642A KR 870006642 A KR870006642 A KR 870006642A KR 860010174 A KR860010174 A KR 860010174A KR 860010174 A KR860010174 A KR 860010174A KR 870006642 A KR870006642 A KR 870006642A
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- 229910052751 metal Inorganic materials 0.000 title claims description 103
- 239000002184 metal Substances 0.000 title claims description 103
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 title claims 5
- 229910052737 gold Inorganic materials 0.000 title claims 5
- 239000010931 gold Substances 0.000 title claims 5
- 229910052703 rhodium Inorganic materials 0.000 title claims 5
- 239000010948 rhodium Substances 0.000 title claims 5
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 title claims 5
- 238000003672 processing method Methods 0.000 title 1
- 238000000034 method Methods 0.000 claims description 21
- 230000004888 barrier function Effects 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims 10
- 150000002739 metals Chemical class 0.000 claims 9
- 239000011248 coating agent Substances 0.000 claims 8
- 238000000576 coating method Methods 0.000 claims 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims 7
- 238000005260 corrosion Methods 0.000 claims 6
- 230000007797 corrosion Effects 0.000 claims 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims 4
- 229910052802 copper Inorganic materials 0.000 claims 4
- 239000010949 copper Substances 0.000 claims 4
- 230000003647 oxidation Effects 0.000 claims 4
- 238000007254 oxidation reaction Methods 0.000 claims 4
- 229910052709 silver Inorganic materials 0.000 claims 4
- 239000004332 silver Substances 0.000 claims 4
- 238000009792 diffusion process Methods 0.000 claims 3
- 229910052697 platinum Inorganic materials 0.000 claims 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 2
- 230000001464 adherent effect Effects 0.000 claims 1
- 239000002659 electrodeposit Substances 0.000 claims 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims 1
- 238000002844 melting Methods 0.000 claims 1
- 230000008018 melting Effects 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
내용 없음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본원발명에 의한 금속처리의 준비로서, 집적회로의 형성공정의 중간단계를 나타내는 단면도.
제2도는 제1도의 회로부를 나타내며, 본원발명의 금속처리공정의 두단계를 나타내는 단면도.
제3도는 제2도의 회로부를 나타내며, 마스크제거와 장벽금속에 칭단계를 나타내는 단면도.
Claims (17)
- 칩 위의 제1유전층에 전기접촉개구를 형성하며, 상기 접촉개구를 포함하여 제1소정패턴에 의하여 제1유전층에 제1금속처리를 피복하며, 제1금속처리는 제1유전층에 대략 수직인 측벽을 가지며, 금속처리에 있어서의 기계적 응력을 해제하는데 충분한 온도(T)로 칩을 어닐링하며, 상기 측벽을 포함하여 제1유전층 및 제1금속처리를 피복하기 위하여 칩 위에 제2유전층을 피복하며, 제1금속처리의 한 측벽으로부터 소정 간격으로 제2금속처리와 제1금속 처리 부분과 전도선을 전기접속시키는 접촉점을 포함하여 제2소정패턴에 의하여 제2유전체위에제2금속처리를 피복하며, 제1금속처리의 피복단계는 제1유전체 및 접촉개구에 제1금속층을 피복하고, 제1금속층 상부에 제2금속층을 피복하여 상기측벽과 같은 넓이로 양에지부 사이에 피복되며, 제1금속은 제1강성특성을 지닌 고도의 전도성금속이며, 제2금속은 제2강성특성을 지닌 전도성금속이며, 제2금속은 어닐링온도(T)에서 제1금속보다 강성이 더 크므로, 이와 같이 피복된 형태로 어닐링에 의해 제1금속처리를 유지하는 것을 특징으로 하는 금속처리방법.
- 제1항에 있어서, 제1 및 제2금속의 강성특성은 온도에 따라 변하며, 어닐링온도(T)에서 제2금속은 비 T/TM1이하의 비 T/TM2를 가지며, 다만 TM1및 TM2는 각각 제1 및 제2금속의 융점인 것을 특징으로 하는 상기 방법.
- 제1항에 있어서, 제1 및 제2금속은 각각 특성적 저항력을 가지며, 제1금속의 저항력은 제2금속의 저항력 이하이며, 피복단계는 소정 두께로 제1 및 제2금속을 각각 피복하며, 제2금속층의 두께는 제1금속층의 두께보다 얇은 것을 특징으로 하는 상기 방법.
- 제3항에 있어서, 제1 및 제2금속은 어닐링온도에서 상호 확산력을 가지며, 따라서 이들 금속은 어닐링온도(T)에서 상호 부착성이 있지만 충분히 낮으며, 제2금속의 제1금속으로의 확산이 제1금속층의 두께의 소부분에 한정되는 것을 특징으로 하는 상기 방법.
- 제1항에 있어서, 제1 및 제2금속은 내부식성금속이며, 부가피복인 것을 특징으로 하는 상기 방법.
- 제1항에 있어서, 제1 및 제2금속은 전착인 것을 특징으로 하는 상기 방법.
- 제1항에 있어서, 최소한 제2금속은 내부식성 및 내산화성이며, 제2금속은 제1금속의 산화 또는 부식전에 제1금속에 피복되는 것을 특징으로 하는 상기 방법.
- 제1항에 있어서, 피복단계는 상기 제1금속으로서 금, 은 및 동중 하나를 전착한 다음, 제2금속으로서 로듐 및 플래티눔 중 하나를 전착하는 것을 특징으로 하는 상기 방법.
- 제8항에 있어서, 제1금속은 은 또는 동이며, 제1금속이 부식 또는 산화되기전에 제2금속을 전착하는 것을 특징으로 하는 상기 방법.
- 제8항에 있어서, 제1금속은 금이며, 제2금속은 로듐인 것을 특징으로 하는 상기 방법.
- 제8항에 있어서, 제1금속은 제1두께로 전착되며, 제2금속은 제1두께보다 얇은 제2두께로 전착되며, 어닐링온도(T)는 제1금속의 제2금속으로의 확산이 제2두께보다 얇은 두께로 되는 온도로 제한되는 것을 특징으로 하는 상기 방법.
- 칩 위의 제1표면유전층에 전기 접촉개구를 형성하며, 상기 접촉개구를 포함하여 제1소정패턴에 의하여 제1유전층에 제1금속처리를 피복하며, 제1금속처리는 제1유전층에 대략 수직인 측벽을 가지며, 금속처리에 있어서의 기계적용력을 해제하는데 충분한 온도(T)로 칩을 어닐링하며, 상기 측벽을 포함하여 제1유전층 및 제1금속처리를 피복하기 위하여 칩 위에 제2유전층을 피복하며, 제1금속처리의 한측벽으로부터 소정간격으로 제2금속처리와 제1금속 처리부분과 전도선을 전기접속시키는 접촉점을 포함하여 제2소정패턴에 의하여 제2유전체위에 제2금속처리를 피복하며, 제1금속처리의 피복단계는 제1유전체 및 접촉개구에 제1금속층을 피복하고, 제1금속층 상부에 제2금속층을 피복하여, 상기 측벽과 같은 넓이로 양에지부 사이에 피복되며, 제1금속은 그룹IB금속이며, 제2금속은 내부식 및 내산화 플래티늄 그룹금속이며, 제1 및 제2금속의 피복단계는 제2금속이 거의 산화 및 부식이 없을 때 제1금속위에 피복되도록 배열되며, 따라서 제2금속처리에 대하여 부식 및 산화가 없는 접촉점을 제공하는 것을 특징으로 하는 금속처리방법.
- 제12항에 있어서, 피복 단계는 상기 제1금속으로서 금, 은 및 동 중 하나를 전착한 다음, 제2금속으로서 로듐 및 플래티눔 중 하나를 전착하는 것을 특징으로 하는 상기 방법.
- 기준면을 지닌 기판을 제공하며, 상기 기준면에 제1유전층을 형성하며, 송정회로위치에 칩표면의 일부분을 노출시키기 위하여 유전체에 접촉개구를 형성하며, 유전층과 칩표면의 노출부분에 전도장벽측을 피복하며, 장벽층에 마스크를 적용하며, 상기 접촉개구 및 그 부근을 포함하여 장벽층의 소정부분을 노출시키기 위하여 마스크를 페터닝하고, 전도장벽층의 노출부에 제1금속층을 전착하며, 제1금속은 기본적으로 그룹IB 금속으로 구성되며, 제2금속층을 제1금속층 상부에 전착하며, 제2금속은 기본적으로 플래티눔 그룹금속으로 구성되며, 전착된 제1 및 제2금속층의 측벽을 노출시키며, 장벽층의 인접영역을 노출시키기 위하여 마스크를 제거하고, 상기 및1 제2금속을 포함한 기판을 어닐링하며, 제1 및 제2금속층을 함께 집적회로의 제1 금속처리를 형성하며, 그 하부에 배설되어 있는 제1유전층을 노출시키기 위하여 상기 인접 영역의 장벽층을 선택적으로 에칭하며, 제2금속, 제1금속처리의 측벽 및 제1유전층의 인접영역을 피복하기 위하여 제2유전층을 피복하며, 상기 측벽으로부터 소정 간격으로 제1금속처리 부위의 바이어스와 상기 부분에 따라서 뻗은 도전전을 포함하여 제2유전층에 제2금속처리를 형성하는 것을 특징으로 하는 2층 집적회로의 금속처리방법.
- 제14항에 있어서, 제1금속은 은 또는 동이며, 제1금속이 부식 또는 산화되기전에 제2금속을 전착하는 것을 특징으로 하는 상기 방법.
- 제14항에 있어서, 제1금속은 금이며, 제2금속은 로듐 것을 특징으로 하는 상기 방법.
- 제14항에 있어서, 제1금속은 제1두께로 전착되며, 제2금속은 제1두께본다 얇은 제2두께로 전착되며, 어닐링온도는 제2금속의 제1금속으로의 확산이 제2두께보다 얇은 두께로 되는 온도로 제한되는 것을 특징으로 하는 상기 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US803,703 | 1985-12-02 | ||
| US803703 | 1985-12-02 | ||
| US06/803,703 US4687552A (en) | 1985-12-02 | 1985-12-02 | Rhodium capped gold IC metallization |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR870006642A true KR870006642A (ko) | 1987-07-13 |
| KR900007691B1 KR900007691B1 (ko) | 1990-10-18 |
Family
ID=25187223
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019860010174A KR900007691B1 (ko) | 1985-12-02 | 1986-11-29 | 로듐피복금 ic 금속처리방법 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4687552A (ko) |
| EP (1) | EP0226385B1 (ko) |
| JP (1) | JPS62133738A (ko) |
| KR (1) | KR900007691B1 (ko) |
| DE (1) | DE3673620D1 (ko) |
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| US4770897A (en) * | 1987-05-05 | 1988-09-13 | Digital Equipment Corporation | Multilayer interconnection system for multichip high performance semiconductor packaging |
| US5039381A (en) * | 1989-05-25 | 1991-08-13 | Mullarkey Edward J | Method of electroplating a precious metal on a semiconductor device, integrated circuit or the like |
| US5256274A (en) * | 1990-08-01 | 1993-10-26 | Jaime Poris | Selective metal electrodeposition process |
| US5145571A (en) * | 1990-08-03 | 1992-09-08 | Bipolar Integrated Technology, Inc. | Gold interconnect with sidewall-spacers |
| US5151168A (en) * | 1990-09-24 | 1992-09-29 | Micron Technology, Inc. | Process for metallizing integrated circuits with electrolytically-deposited copper |
| US5387332A (en) * | 1993-07-14 | 1995-02-07 | Straus; Martin | Cleaner/conditioner for the direct metallization of non-conductors and printed circuit boards |
| US6146743A (en) * | 1997-02-21 | 2000-11-14 | Medtronic, Inc. | Barrier metallization in ceramic substrate for implantable medical devices |
| US5855995A (en) * | 1997-02-21 | 1999-01-05 | Medtronic, Inc. | Ceramic substrate for implantable medical devices |
| KR100269878B1 (ko) | 1997-08-22 | 2000-12-01 | 윤종용 | 반도체소자의금속배선형성방법 |
| US7244677B2 (en) | 1998-02-04 | 2007-07-17 | Semitool. Inc. | Method for filling recessed micro-structures with metallization in the production of a microelectronic device |
| WO1999040615A1 (en) | 1998-02-04 | 1999-08-12 | Semitool, Inc. | Method and apparatus for low-temperature annealing of metallization micro-structures in the production of a microelectronic device |
| US6632292B1 (en) | 1998-03-13 | 2003-10-14 | Semitool, Inc. | Selective treatment of microelectronic workpiece surfaces |
| US6565729B2 (en) | 1998-03-20 | 2003-05-20 | Semitool, Inc. | Method for electrochemically depositing metal on a semiconductor workpiece |
| US6497801B1 (en) * | 1998-07-10 | 2002-12-24 | Semitool Inc | Electroplating apparatus with segmented anode array |
| US6297154B1 (en) * | 1998-08-28 | 2001-10-02 | Agere System Guardian Corp. | Process for semiconductor device fabrication having copper interconnects |
| US7438788B2 (en) | 1999-04-13 | 2008-10-21 | Semitool, Inc. | Apparatus and methods for electrochemical processing of microelectronic workpieces |
| US7351314B2 (en) | 2003-12-05 | 2008-04-01 | Semitool, Inc. | Chambers, systems, and methods for electrochemically processing microfeature workpieces |
| US7020537B2 (en) | 1999-04-13 | 2006-03-28 | Semitool, Inc. | Tuning electrodes used in a reactor for electrochemically processing a microelectronic workpiece |
| US7189318B2 (en) | 1999-04-13 | 2007-03-13 | Semitool, Inc. | Tuning electrodes used in a reactor for electrochemically processing a microelectronic workpiece |
| EP1192298A4 (en) | 1999-04-13 | 2006-08-23 | Semitool Inc | APPENDIX FOR THE ELECTROCHEMICAL TREATMENT OF A WORKPIECE |
| US7585398B2 (en) | 1999-04-13 | 2009-09-08 | Semitool, Inc. | Chambers, systems, and methods for electrochemically processing microfeature workpieces |
| US7351315B2 (en) | 2003-12-05 | 2008-04-01 | Semitool, Inc. | Chambers, systems, and methods for electrochemically processing microfeature workpieces |
| US6916412B2 (en) | 1999-04-13 | 2005-07-12 | Semitool, Inc. | Adaptable electrochemical processing chamber |
| US7264698B2 (en) | 1999-04-13 | 2007-09-04 | Semitool, Inc. | Apparatus and methods for electrochemical processing of microelectronic workpieces |
| US20020000380A1 (en) * | 1999-10-28 | 2002-01-03 | Lyndon W. Graham | Method, chemistry, and apparatus for noble metal electroplating on a microelectronic workpiece |
| US6780374B2 (en) | 2000-12-08 | 2004-08-24 | Semitool, Inc. | Method and apparatus for processing a microelectronic workpiece at an elevated temperature |
| US6471913B1 (en) | 2000-02-09 | 2002-10-29 | Semitool, Inc. | Method and apparatus for processing a microelectronic workpiece including an apparatus and method for executing a processing step at an elevated temperature |
| AU2001282879A1 (en) | 2000-07-08 | 2002-01-21 | Semitool, Inc. | Methods and apparatus for processing microelectronic workpieces using metrology |
| US6462416B1 (en) * | 2001-07-13 | 2002-10-08 | Advanced Micro Devices, Inc. | Gradated barrier layer in integrated circuit interconnects |
| KR100455382B1 (ko) * | 2002-03-12 | 2004-11-06 | 삼성전자주식회사 | 듀얼 다마신 구조를 가지는 반도체 소자의 금속 배선 형성방법 |
| US20050230262A1 (en) * | 2004-04-20 | 2005-10-20 | Semitool, Inc. | Electrochemical methods for the formation of protective features on metallized features |
| DE102006056620B4 (de) | 2006-11-30 | 2010-04-08 | Advanced Micro Devices, Inc., Sunnyvale | Halbleiterstruktur und Verfahren zu ihrer Herstellung |
| WO2008066884A1 (en) * | 2006-11-30 | 2008-06-05 | Advanced Micro Devices, Inc. | Semiconductor structure with interconnect comprising silver and method of forming the same |
| US8372744B2 (en) * | 2007-04-20 | 2013-02-12 | International Business Machines Corporation | Fabricating a contact rhodium structure by electroplating and electroplating composition |
| US9604338B2 (en) * | 2015-08-04 | 2017-03-28 | Texas Instruments Incorporated | Method to improve CMP scratch resistance for non planar surfaces |
| CN108122820B (zh) * | 2016-11-29 | 2020-06-02 | 中芯国际集成电路制造(上海)有限公司 | 互连结构及其制造方法 |
| US10699948B2 (en) | 2017-11-13 | 2020-06-30 | Analog Devices Global Unlimited Company | Plated metallization structures |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3699010A (en) * | 1971-03-22 | 1972-10-17 | North American Rockwell | Beam lead plating process |
| NL7412383A (nl) * | 1974-09-19 | 1976-03-23 | Philips Nv | Werkwijze voor het vervaardigen van een in- richting met een geleiderpatroon. |
| US4182781A (en) * | 1977-09-21 | 1980-01-08 | Texas Instruments Incorporated | Low cost method for forming elevated metal bumps on integrated circuit bodies employing an aluminum/palladium metallization base for electroless plating |
| JPS5450284A (en) * | 1977-09-28 | 1979-04-20 | Matsushita Electronics Corp | Forming method of electrode wiring layers |
| US4344223A (en) * | 1980-11-26 | 1982-08-17 | Western Electric Company, Inc. | Monolithic hybrid integrated circuits |
| GB2147311B (en) * | 1983-09-29 | 1987-10-21 | Hara J B O | Electrodepositing precious metal alloys |
-
1985
- 1985-12-02 US US06/803,703 patent/US4687552A/en not_active Expired - Fee Related
-
1986
- 1986-11-28 JP JP61284083A patent/JPS62133738A/ja active Pending
- 1986-11-29 KR KR1019860010174A patent/KR900007691B1/ko not_active IP Right Cessation
- 1986-12-02 EP EP86309387A patent/EP0226385B1/en not_active Expired - Lifetime
- 1986-12-02 DE DE8686309387T patent/DE3673620D1/de not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US4687552A (en) | 1987-08-18 |
| KR900007691B1 (ko) | 1990-10-18 |
| EP0226385B1 (en) | 1990-08-22 |
| DE3673620D1 (de) | 1990-09-27 |
| EP0226385A1 (en) | 1987-06-24 |
| JPS62133738A (ja) | 1987-06-16 |
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