KR870003618A

KR870003618A - Digital automatic gain control system

Info

Publication number: KR870003618A
Application number: KR1019850007233A
Authority: KR
Inventors: 민성기; 명찬규; 이재신
Original assignee: 강진구; 삼성반도체통신 주식회사
Priority date: 1985-09-30
Filing date: 1985-09-30
Publication date: 1987-04-18

Abstract

내용 없음No content

Description

Digital automatic gain control system

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 디지탈 자동 이득 조절 시스템의 불럭도2 is a block diagram of a digital automatic gain adjustment system according to the present invention.

제3도는 제2도의 잡음오동작 방지회로의 구체회로도3 is a detailed circuit diagram of the noise malfunction prevention circuit of FIG.

제4도는 제3도의 각 부분의 타이밍도4 is a timing diagram of each part of FIG.

제5도는 전압비교기를 A/D변환기를 사용한 경우의 실시예의 회로도.5 is a circuit diagram of an embodiment where a voltage comparator is used for the A / D converter.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

9,9' : 잡음오동작회로 10,10' : 래치회로9,9 ': Noise malfunction circuit 10,10': Latch circuit

11 : 파형정형회로 12 : 선택기11 waveform shaping circuit 12 selector

13 : 분주기 17 : 클럭발생기13: divider 17: clock generator

Claims

In the automatic gain control system, a latching comparator (8) (8 ') and the latching comparator for inputting a reference voltage, an output of a sampling clock pulse and an amplifier and outputting a logic state by comparing the reference voltage with an output level of the amplifier. A noise malfunction prevention circuit (9) 9 'that outputs a logic state by counting the sampling clock according to the state of the logic output by inputting a logic output and the sampling clock of The waveform shaping and delay circuit 11 and the noise malfunction preventing circuit 9 generating or outputting the clock pulses and the reset pulses of the up-down counter 6 by inputting the clock pulses of 7) through the divider 13 or integratedly. A latch circuit (10) (10 ') and the latch circuit for inputting the output of the " 9' ", the sampling pulse and the reset pulse to latch according to the output clocks of the noise malfunction prevention circuits (9) and (9 '). Up car according to the output status of Putting down or counting up-down counter (6) and a digital automatic gain control circuit, characterized by consisting of a step gain controller (1) for adjusting the gain in accordance with the count.

A logic gate 14 (14) according to claim 1, wherein the noise malfunction prevention circuits 9 (9 ') input the outputs of the latching comparators (8) (8') and output sampling pulses according to the output state of the comparator. Bit counter and logic circuit 17 reset according to the output state of the latching comparators 8 and 8 'by counting the sampling pulses of the gate and the sampling pulses of the gate. Circuit composed of 17 '.

The clock pulse generator 7 resets and counts the output clock when the selector 12 performs down counting, and selects the divided clock through the divider 13 when up counting. Circuit.

The circuit according to claim 1, characterized in that the latching comparator (8) (8 ') is replaced with an analog-to-digital converter (20) and a logic circuit (21).

The circuit according to claim 1, wherein the output of the up-down counter and the output of the latch circuit (10) (10 ') are input to the output terminal of the up-down counter (6) so that the logic gates display the output states of the underrange and overrange.

※ Note: The disclosure is based on the initial application.