JPS59219A - Digital trigger circuit - Google Patents

Abstract

PURPOSE:To prevent a malfunction caused by a noise, by comparing a digital input signal with a trigger and a hysteresis level, and constituting a digital trigger circuit having hysteresis characteristics. CONSTITUTION:A digital signal 11 is inputted to digital comparators 12, 14, is compared with a high level setting signal 28 and a low level setting signal 29 by the comparators 12, 14, respectively, and when it crosses each setting signal 28, 29, an output signal is applied to an AND gate 16 and an NOR gate 18. Outputs of these gates 16, 18 are given to a J-KFF20, and in response to a combination of outputs of the comparators 12, 14, a trigger signal is generated by the timing of a sampling clock 21. Also, by an OR gate 22 which inputs the outputs of the gates 16, 18 and a circuit by a D-type FF24, another trigger signal 27 is generated. Subsequently, the digital signal is compared with two reference levels, a digital trigger circuit having hysteresis characteristics is obtained, and a malfunction caused by a noise is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital trigger circuit, and particularly to a digital trigger circuit that does not cause malfunctions due to noise.

In devices that use an analog-to-digital converter (hereinafter referred to as ADC) and require a trigger signal, either an analog signal or a digital signal can be used to generate the trigger signal. For example, in conventional oscilloscopes and frequency counters, as illustrated in FIG. is used. Here, the analog comparator 6 that generates the trigger signal 8 is provided with some hysteresis characteristics to remove noise. Such an analog comparator 6 is well known in the art.

The prior art digital trigger circuit shown in FIG. 2 has had problems in the past. This digital trigger circuit converts an analog signal 13 into an N-bit digital signal 11 by an ADC 15, which is set in a clip-flop 19 by a declock 21 to generate a trigger signal 26. In this digital trigger circuit,
The noise on the analog signal 13 causes the value of the digital signal 11 to fluctuate. If the N-bit digital signal 11 that fluctuates in this way is used to generate the trigger signal 26, there is a problem that a false trigger signal will be generated. This problem in the conventional digital trigger circuit will be explained using the waveform diagram of FIG. In FIG. 3, it is assumed that the digital signal level 32 has fallen from the level 515 at point a, and that the trigger level 512 has been set.

At the next clock, the digital signal level 32 drops to level 511 and rises again due to noise to point b, which is greater than the trigger level 512, at which point a false trigger signal is generated.

This false trigger signal occurs long before the correct trigger signal at point C. A circuit that obtains a trigger signal from a digital signal has potential advantages such as being able to accurately set the trigger level and having no DC level drift, but due to the drawbacks mentioned above, it is not suitable for various applications. is not suitable.

SUMMARY OF THE INVENTION It is an object of the present invention to overcome the above-mentioned drawbacks of conventional digital Φ trigger circuits and to provide a digital trigger circuit that does not generate false trigger signals. To achieve this objective, in the present invention, a signal band with a certain width, ie, a trigger band, is set, and the digital signal must cross this entire band before the trigger signal is generated. I'll do it like that. FIG. 4 is a waveform diagram for explaining the present invention, and in addition to the trigger level 512 shown in FIG. 3, a hysteresis level 514 is set to suppress the trigger band. In FIG. 4, a trigger signal is generated only when digital signal level 32 crosses the entire trigger band between hysteresis level 514 and trigger level 512 in both directions. That is, referring to FIG. 4, the digital signal level 32 crosses the trigger band in a downward direction from point a, which has a level greater than the trigger level 512, to point e, which has a level less than the hysteresis level, and continues upward. A trigger signal is generated when the bird finishes crossing the band and reaches point C.

Therefore, as long as the digital signal level 32 does not completely cross the trigger band, noise spikes such as those shown at points b and d will not produce false trigger signals.

Alternatively, a trigger signal may be generated when the digital signal level 32 crosses the trigger band in one direction.

Hereinafter, the present invention will be explained in detail based on the drawings.

FIG. 5 is a block diagram of a digital tri-circuit according to an embodiment of the present invention. In FIG. 5, N bits A-
An N-bit digital signal 11 from a DC (not shown) output is used to generate a trigger signal 26. This digital signal 11 is applied to an input capo-zo and is led to two digital comparators 12,14. The digital comparators 12 and 14 each receive a high level setting signal 28. A low level setting signal 29 is provided and is used to set a high point and a low point (or high level and low level), respectively. When the digital signal 11 crosses these set points, each digital comparator 12.14 generates an output signal. These output signals are connected to AND gate 16. N'OR
Gate 18. A trigger signal 26 is generated at the timing of a sampling clock 21 in response to a predetermined combination of output signals of a digital comparator 12.14. In this circuit, the high and low points are the trigger level 512 and hysteresis level explained in FIG.
Each corresponds to level 514. That is, when the digital signal level 32 in FIG. 4 falls from point a completely across the trigger band and reaches point e, the inputs to the flip-flops J and J are respectively "0".

1'', the Q output becomes 1o'' at the timing of the sampling clock 21 at this point.

When the digital signal level 32 rises again and reaches point C, the inputs to J become "1" and "0", respectively, so the Q output becomes "1" at the timing of the sampling clock 21. This Q output, that is, the rise of the trigger signal 26 is used as the trigger timing.

Another trigger signal 27 is generated by a circuit consisting of OR gate 22 and D flip-flop 24 in FIG. In this circuit, the output of the zero gate 22,
That is, the D input of the D7 lip-flop 24 becomes "l" when the digital signal 11 is greater than the high point or less than the low point, and when it is between the island point and the low point.
0”.

Therefore, the sampling clock 21 immediately after the digital signal 11 exits the trigger band between the high and low points.
The trigger signal 27 becomes "1" at the timing.

As explained above, by comparing the digital signal input with two reference levels (in Figure 4, the trigger level 512 and the hysteresis level 514),
Hysteresis characteristic? A digital trigger circuit with It is clear that the present invention is not limited to what is shown in FIG.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an analog trigger circuit according to the prior art, FIG. 2 is a block diagram showing a digital trigger circuit according to the prior art, and FIG. FIG. 4 is a waveform diagram for explaining the present invention, and FIG. 5 is a block diagram of a digital trigger circuit which is an embodiment of the present invention. ll: Digital signal 12.14: Digital comparator 20: Clip to J- 70 knob 21: Sampling clock 28: High level setting signal 29: Low level setting signal Applicant Yokozutsu Hewlett Packard Co., Ltd. Attorney Patent attorney Tsugu Hasegawa FIG 2 FIG 3 FIG 4 FIG 5

Claims (1)

[Scope of Claims] Means for inputting a digital signal representing an analog cough and comparing it with a first level to output a first signal; and means for inputting the digital signal and comparing it with a second level to generate a second signal. and means for generating a trigger signal in response to the first signal and the second signal.