JP2512205B2 - A / D converter - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital (A / D) converter for converting an analog signal into a digital signal.

2. Description of the Related Art With the development of digital technology in recent years, the performance of an A / D converter, which is an interface between analog and digital signals, has an important effect. An example of an A / D converter that has been conventionally used is shown in FIG. 4 and will be described. The A / D converter shown in FIG. 4 is called a successive approximation type and operates as follows.

(1) The MSB (most significant bit) of the successive approximation register 43 is set to “1” and the others are set to “0”, and this is set to a D / A converter (hereinafter DAC).
Output to 44).

(2) The analog input and the output of the DAC 44 are compared by the comparator 41, and according to the output of the comparator 41, the register control circuit 42
If (analog input) ≥ (DAC44 output), set the bit in question to "1", set the lower bit to "1", and if (analog input) <(DAC44 output) The bit in question is set to “0” and the next lower bit is set to “1”.

(3) Repeat steps (1) and (2) from MSB to LSB (least significant bit).

(4) Data is taken out from the successive approximation register 43 and output as a digital output.

However, in the above-described conventional configuration, if the number of bits is increased to increase the resolution, the conversion time increases, so that the comparator 41 and the DAC 44 have a very high speed to maintain the sampling frequency. Action is required. Moreover, there is a problem that the closer it is to the LSB, the more easily it is affected by ambient noise.

The present invention solves the above-mentioned problems, and provides an A / D conversion device which is not easily affected by ambient noise and which does not require the speedup of elements to be used by increasing the number of bits.

Means for Solving the Problems In order to achieve this object, the present invention provides a plurality of A / D converters for converting an analog signal into a digital signal, and a plurality of A / D converters for converting the analog signal into a plurality of signals having different levels. Level converting means respectively input to the plurality of A / D converters, and one output of the plurality of A / D converter outputs as a reference output, the other output of the plurality of A / D converter outputs And a level detecting device that adjusts the level of the other output according to the output of the ratio detecting device, and selectively switches between the level adjusting device output and the reference output. Based on the output levels of the plurality of A / D converters, a switching operation is performed immediately when the output levels of the plurality of outputs exceed a predetermined value, and the operation of the ratio detecting means is temporarily stopped. , The plural When the zero-cross and minute levels of the plurality of outputs are detected after a certain time has elapsed since the output level of became less than or equal to a predetermined level, and then the zero-cross was detected before the predetermined time further passed. Is configured to perform the switching operation near the zero crossing and near the minute level when the zero crossing is not detected.

Operation With the above-described configuration, the present invention is provided with A / D converters exclusively for each of a plurality of input levels set in advance, and by digitally switching the digital output according to the state of each digital output. A high-resolution A / D converter is realized by using a low-resolution A / D converter that is not easily affected by ambient noise and is not affected by noise accompanying switching because it is digitally switched. Is something that can be done. Moreover, the operating speed of the element used may be the same as the conventional one.

Furthermore, signal switching is performed immediately when the waveform level becomes high, and when the waveform level becomes low, after a certain period of time, near the zero cross or near the minute level. Since it is the location of the amplitude, there is almost no waveform discontinuity associated with switching.

Examples Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an A / D converter according to the present invention. Referring to FIG. 1, reference numeral 1 denotes a low-pass filter (hereinafter, referred to as LPF), which limits a band of an analog input signal. An amplifier 2 amplifies the analog signal output from the LPF 1. Here, the gain is twice (about
6 dB) is used. 3 and 4 are A / D converters with uniform characteristics (hereinafter referred to as ADCs) that convert analog signals into digital signals. Here, one having a 4-bit resolution is used. Reference numeral 5 is a ratio detector, which compares the data output from the ADCs 3 and 4 only when the output of the level detector 7 is "0", calculates the ratio so that they match, and calculates the 4-bit coefficient. Output as data. 6 is a multiplier,
Multiplies the 4-bit data given to inputs X and Y, rounds the 7-bit least significant bit of the multiplication result, and rounds the upper 6 bits.
The amplitude of the bits is limited and the lower 5 bits are output from P.
Note that X and P are two's complement numbers with a sign, and is an unsigned absolute binary number. Reference numeral 7 is a level detector, which outputs "1" when the absolute value of the output of the ADC4 exceeds a certain value and outputs "0" when it is less than that value. Here, when the input is ± 7 or more, "1" from terminal A
Is output, and when the input is ± 2 or more, “1” is output from the terminal B. 8 is a selector control circuit,
Sign bit of the output of level detector 7 and the output of ADC4 (hereinafter
The selector 9 is controlled based on MSB). Reference numeral 9 denotes a selector which outputs a signal given to the terminal A if the control signal given to the terminal C is "1", and outputs a signal given to the terminal B if it is "0".
Outputs the signal given to. Although the terminal A has a 5-bit input, the terminal B has a 4-bit input, and when the data given to the terminal B is output, the sign bit of the data is added to the upper one bit to provide a 5-bit output.

Next, the operation of FIG. 1 will be described. The analog input band-limited by LPF1 is directly input to ADC3 and the amplifier 2 is input to ADC4.
It is given after being amplified by 2 times. Since the characteristics of ADC3 and 4 are the same, if an analog input that prevents ADC4 from overflowing is given, ADC4 will
This means that twice the value is output as compared with. Therefore, if the output of ADC4 is shifted by 1 bit (corresponding to double) to the lower order, the outputs of ADC3 and 4 will match.

Here, since the amplifier 2 is an analog element, in reality, the gain does not exactly double and an error exists. For this reason, the outputs of the ADCs 3 and 4 do not match. Therefore, the ratio detector 5 calculates the ratio according to the magnitude relation between the two and outputs the coefficient data to the Y input of the multiplier 6 so that the two match. . At this time, the coefficient data calculation method of the ratio detector 5 is AD
The quotient obtained by dividing the output value of C4 by the output value of ADC3 may be obtained, but for example, for the input whose output value of ADC3 is “0100”, the output value of ADC4 at this time is stored. You may do it.

Now, when a large amplitude analog input is given, ADC4 overflows and only ADC3 operates normally. At this time, the level detector 7 detects that the ADC 4 has overflowed, at this time the ratio detector 5 suspends its operation, and the selector 9 operates based on the control signal from the selector control circuit 8.
A signal input from the A / DC 3 to the terminal A via the multiplier 6 is selected. When an analog input that does not cause the ADC 4 to overflow is given, the level detector 7 detects that the ADC 4 does not overflow, and at this time, the ratio detector 5 performs the operation as described above, and the multiplier 6 outputs the P The output matches the output of ADC4 within the calculation error range. These outputs are switched using the selector 9 based on the control signal of the selector control circuit 8.

Here, the operation of the selector control circuit 8 will be described in detail.

FIG. 2 is a block diagram showing a specific example of the selector control circuit 8 in FIG. In FIG. 2, 20 is a counter, which counts the clock signal CLK input from the terminal C when the reset terminal R is "0". Here, a 4 kHz pulse is input as the clock, and when 128 is counted, "1" is output from Q1, and when 192 is counted, "1" is output from Q2. When "1" is given to the reset terminal R, the counter is reset and both Q1 and Q2 become "0". Reference numeral 21 is a D flip-flop, which is supplied with the clock signal CLK like the counter 20. 23 and 24 are D flip-flops with reset, 25 is set and D with reset
It is a flip-flop. 22 is an exclusive OR gate (hereinafter referred to as an EOR gate), and 26 is a logical product gate (hereinafter referred to as an AND gate) whose one input is negative logic.

FIG. 3 is a waveform diagram for explaining the operation of the A / D conversion device of FIG. In FIG. 3, (A) shows the output signal of ADC3,
(B) shows the output signal (C) of the A terminal of the level detector 7, and the Y output of the selector control circuit 8 respectively.
The threshold value Vt, -Vt in (A) represents the level at which the ADC 4 overflows, and Vs, -Vs represents the minute level detected by the level detector 7.

Next, the operation of the selector control circuit 8 shown in FIG. 2 will be described with reference to FIGS. The most significant bit (MSB) of the output of the ADC 4 is given to the terminal C of the selector control circuit 8. This signal is given to one input of the FOR gate 22, delayed by the D flip-flop 21 and given to the other input of the EOR gate 22. Therefore E
The output of the OR gate 22 outputs a pulse signal every time the MSB of the output of the ADC 4 is inverted. Where MSB of ADC4 output is ADC
It matches the sign of the output of 3, and the sign reversal naturally occurs near zero. That is, EOR gate 22
Generates a pulse signal every time the ADC3 output crosses zero.

Now, when the output of the ADC3 becomes smaller than Vt, the output of the A terminal of the level detector 7 is inverted from "1" to "0" (time t1 in FIG. 3). Since the A terminal output of the level detector 7 is given to the counter 20 and the reset terminals R of the D flip-flops 23, 24, 25, these resets are released and the counter 20 starts counting the clock signal CLK. At this point, the D flip-flop 23 has not yet received one clock, so the Q output is "0", and the Q output of the D flip-flop 24 is also "0", so the AND gate 26
The output of the D flip-flop is also "0".
The terminal of 25 is “1”, that is, the output Y of the selector control circuit 8.
Is "1". When the counter 20 counts the clock signal CLK 128 times, first the terminal Q1 becomes "1". Therefore, the output terminal Q of the D flip-flop 23 changes from "0" to "1" (time t2 in FIG. 3). Here, the clock signal CLK is 4 kHz
Therefore, after the output of ADC3 becomes smaller than the threshold Vt 32
In ms, the terminal Q of the D flip-flop 23 changes from "0" to "1". After this, the first zero-cross point (time t in Fig. 3)
In 3), a pulse signal is output from the EOR gate 22 and the terminal of the D flip-flop 25 is inverted from "1" to "0" (time t3 in FIG. 3). That is, the selector control circuit 8 inverts the output Y from "1" to "0" at the first zero-cross point 32 ms after the output of the ADC3 becomes smaller than the threshold value Vt.

Next, when a signal having a level higher than the threshold value Vt is input to the level detector 7, the output of the level detector 7 immediately becomes "1" (time t4 in FIG. 3), and therefore the counter 20 and the D flip-flop 23 , 24, 25 are reset, and the output Y immediately becomes "1" (time t4 in FIG. 3). Next, when the input of the level detector 7 becomes equal to or lower than the threshold value Vt (time t in FIG.
5) From this point, the counter 20 starts counting operation, the Q output of the D flip-flop 23 becomes “1” 32 ms later, and the D flip-flop 25 waits for the pulse signal from the EOR gate 22. (Time t6 in FIG. 3). After that, the counter 20 further counts the clock signal CLK 64 times (192 times in total) during a further 16 ms, and the terminal Q2 becomes "1". Therefore, the output terminal Q of the D flip-flop 24
Changes from "0" to "1" (time t7 in FIG. 3). However, at this time, since the output of the ADC3 is larger than Vs, "1" is input from the output of the B terminal of the level detector 7 to the negative logic input terminal of the AND gate 26.
Output is "0". That is, the D flip-flop 25
"0" is input to the set terminal of, and the terminal remains "1". After that, when the output of ADC3 first becomes less than Vs (time t8 in FIG. 3), the output from the B terminal of level detector 7 is changed to AN.
"0" is input to the negative logic input terminal of the D gate 26, "1" is input from the AND gate 26 to the set terminal of the D flip-flop 25, and the terminal is inverted from "1" to "0" (third Figure time
t8). That is, the selector control circuit 8 outputs the output Y from "1" to "0" when the output of the ADC3 first becomes smaller than Vs when the output of the ADC3 does not reach the zero cross within 32 ms or more and 48 ms after the output becomes smaller than the threshold Vt. Flip to ".

As described above, the selector 9 A / D-converts the signal amplified by the amplifier 2 when the signal amplitude of the input analog input is small and outputs it, and when the signal amplitude of the analog input is large, the selector 9 directly outputs the signal. By performing the / D conversion and outputting this, and performing the switching operation at this time as described above, 1
The frequency of discontinuity of waveform due to switching is greatly reduced without frequent switching between cycles, and there is less problem of discontinuity of waveform due to switching. Therefore, the occurrence of distortion at the time of switching can be suppressed to a small level. At this time, if there is a DC offset in the analog input, zero crossing may not occur for a long time even if the signal level becomes small.At this time, however, if the minute signal level Vs is set appropriately, the operation as described above will occur. Is appropriately switched by. In this way, regardless of the magnitude of the analog input signal amplitude, A /
Since D conversion can be performed and a high-performance analog amplifier 2 can be easily obtained, the gain of the amplifier 2 is not so much a problem by configuring as described above. It is possible to obtain an A / D converter with high bit and high resolution. Here, it is not always necessary to use a high-resolution A / D converter, and the operating speed may be the same as conventional one. In addition, since how many bits the output of the A / D converter is made depends on how much the gain of the amplifier 2 is set, the number of output bits is changed by changing the gain of the amplifier 2 as necessary. be able to.
Further, since the output switching and the like are all performed by digital operations, there is no influence of noise and click sound accompanying this.

In this embodiment, the analog input is amplified to ADC4
However, it is also possible to directly input the signal to ADC4 and input the signal attenuated by the attenuator to ADC3. Also, two A / D converters are used in the above embodiment, but three or more A / D converters may be used and analog inputs of different levels may be added to each. In addition, the time constant of the selector control circuit 8 (counting time of the counter 20 in FIG. 2) is set to 32ms, 48ms.
However, it can be changed depending on the application. Further, although the output of the ADC4 is used for the input of the level detector 7, the same operation can be configured by using the output of the ADC3, and the MS of the output of the ADC4 is input to the C terminal input of the selector control circuit 8.
The same operation can be performed using B.

As described above, according to the present invention, a plurality of A / D converters (A / DC3, 4) for converting an analog signal into a digital signal and a plurality of A / D converters for converting the analog signal into different signals are provided. Level converting means (amplifier 2) respectively input to the plurality of A / D converters, and the plurality of A / D converters using one output of the plurality of A / D converter outputs as a reference output. A ratio detecting means (ratio detector 5) for obtaining a ratio of the output to another output, and a level adjusting device (multiplier 6) for adjusting the level of the other output according to the output of the ratio detecting means. , The level adjusting device output or the reference output is selectively switched to output,
Based on the level of the A / D converter output, as soon as the levels of the plurality of outputs exceed a predetermined value, a switching operation is performed and the operation of the ratio detecting means is temporarily stopped, and the levels of the plurality of outputs are set to a predetermined level. Zero levels and minute levels of the plurality of outputs are detected after a lapse of a certain time after reaching the level or less, and if a zero cross is detected before the lapse of a predetermined time after that, the zero cross is near the zero cross. If is not detected, by performing the switching operation near the minute level, even if the analog signal level becomes small, it is possible to A / D-convert an analog signal with a large amplitude at all times. It is not easily affected by noise, and since it is digitally switched, it is not affected by noise due to switching and high resolution A / D conversion. The device can be implemented using an A / D converter of lower resolution, yet the operation speed of the device to be used are those that can achieve excellent A / D converter that may be conventional. Moreover, when switching the signal, when the waveform level becomes high, immediately when the waveform level becomes low, the switching is made near the zero cross or near the minute level after a certain time has passed.
Since switching does not occur within one cycle of the waveform and the switching location is a location of small amplitude, almost no waveform discontinuity associated with switching occurs.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the A / D conversion device according to the present invention, FIG. 2 is a block diagram showing an embodiment of the selector control circuit 8 of FIG. 1, and FIG. FIG. 4 is a waveform diagram for explaining the operation of the A / D converter, and FIG. 4 is a block diagram showing an example of a conventional A / D converter. 1 ... Low-pass filter, 2 ... Amplifier, 3,4 ... A / D converter, 5 ... Ratio detector, 6 ... Multiplier, 7 ... Level detector, 8 ... Selector control circuit , 9 ... Selector.

Claims (1)

(57) [Claims] 1. A plurality of A / D converters for converting an analog signal into a digital signal, and levels for converting an analog signal into a plurality of signals having different levels and inputting to each of the plurality of A / D converters. A conversion means, and a ratio detection means for obtaining a ratio of one output of the plurality of A / D converter outputs to another output of the plurality of A / D converter outputs using one output as a reference output, A level adjusting device for adjusting the level of the other output according to the output of the ratio detecting means, and one of the level adjusting device output and the reference output is selectively switched to output, and the plurality of A Based on the output level of the / D converter, when the output levels of the plurality of outputs exceed a predetermined value, the switching operation is immediately performed and the operation of the ratio detecting means is temporarily stopped, and the output levels of the plurality of outputs are set to the predetermined level. Became below After a certain time has passed, the zero crosses and minute levels of the plurality of outputs are detected, and if a zero cross is detected before the predetermined time further passes, the zero cross is not detected near the zero cross. In this case, the A / D converter is designed to perform the switching operation near the minute level.