KR870002643A - 직접회로용 패케이지 - Google Patents

직접회로용 패케이지 Download PDF

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Publication number
KR870002643A
KR870002643A KR1019860006353A KR860006353A KR870002643A KR 870002643 A KR870002643 A KR 870002643A KR 1019860006353 A KR1019860006353 A KR 1019860006353A KR 860006353 A KR860006353 A KR 860006353A KR 870002643 A KR870002643 A KR 870002643A
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KR
South Korea
Prior art keywords
integrated circuit
height
ridges
circuit package
package
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Application number
KR1019860006353A
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English (en)
Other versions
KR900001987B1 (ko
Inventor
가즈또 쯔지
쯔요시 아오끼
미찌오 오노
리끼오 스지우라
Original Assignee
야마모도 다꾸마
후지쓰 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 야마모도 다꾸마, 후지쓰 가부시끼가이샤 filed Critical 야마모도 다꾸마
Publication of KR870002643A publication Critical patent/KR870002643A/ko
Application granted granted Critical
Publication of KR900001987B1 publication Critical patent/KR900001987B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01067—Holmium [Ho]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

내용 없음

Description

직접회로용 패케이지
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 인쇄회로 기판상 납땜된 PLCC의 횡단측면도의 개략도.
제2도는 융기부와 그의 연관 리이드를 확대하여 보인 횡단측면도의 개략도.
제7도는 본 발명의 PLCC의 융기부들과 그들에 연관된 리이드들의 확대부분 사시도의 개략도.

Claims (2)

  1. (a) 내부에 집적회로를 내장하며 또한 상면, 밑면 및 4개의 측면들을 갖고 있되, 상기 밑면은 다수의 융기부들을 갖고 있으며, 상기 융기부들은 각 측면을 따라 정렬되며 또한 예정된 거리만큼 상호연결구에 의해 인접한 융기부로부터 격리되어 그에 연결되며, 상기 상호연결구는 상기 봉합과 동일한 재료로 제조되어상기 밑면의 밖으로 돌출하며 또한 상기 밑면으로부터 측정된 상기 융기부의 높이 보다 낮은 높이를 갖는 봉함과, 그리고 (b) 각 리드의 단부가 상기 봉함 내부에 봉입된 상기 집적회로의 단자패드에 연결되며, 상기 각 측면을 통하여 상기 밑면을 향해 상기 측면을 따라 연장되며, 그리고 상기 리이드는 상기 밑면을 향하여 상기 융기부를 따라 만곡되어 그 위로 더 연장되는 다수의 리이드들을 포함하는 것이 특징인 집적회로용 패케이지.
  2. 제1항에서, 상기 상호연결부의 높이는 상기 밑면으로부터 측정된 상기 융기부의 높이의 1/3보다는 크나 2/3보다는 작은 것이 특징인 집적회로용 패케이지.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019860006353A 1985-08-10 1986-08-01 집적회로용 패케이지 KR900001987B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1985122952U JPH0325410Y2 (ko) 1985-08-10 1985-08-10
JP60-122952 1985-08-10

Publications (2)

Publication Number Publication Date
KR870002643A true KR870002643A (ko) 1987-04-06
KR900001987B1 KR900001987B1 (ko) 1990-03-30

Family

ID=14848683

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860006353A KR900001987B1 (ko) 1985-08-10 1986-08-01 집적회로용 패케이지

Country Status (5)

Country Link
US (1) US4724280A (ko)
EP (1) EP0212521B1 (ko)
JP (1) JPH0325410Y2 (ko)
KR (1) KR900001987B1 (ko)
DE (1) DE3679473D1 (ko)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5005070A (en) * 1988-12-19 1991-04-02 Hewlett-Packard Company Soldering interconnect method and apparatus for semiconductor packages
US4989069A (en) * 1990-01-29 1991-01-29 Motorola, Inc. Semiconductor package having leads that break-away from supports
US6072239A (en) 1995-11-08 2000-06-06 Fujitsu Limited Device having resin package with projections
US6376921B1 (en) * 1995-11-08 2002-04-23 Fujitsu Limited Semiconductor device, method for fabricating the semiconductor device, lead frame and method for producing the lead frame
US6159770A (en) * 1995-11-08 2000-12-12 Fujitsu Limited Method and apparatus for fabricating semiconductor device
US6329711B1 (en) 1995-11-08 2001-12-11 Fujitsu Limited Semiconductor device and mounting structure
JP3026426B2 (ja) * 1996-08-29 2000-03-27 沖電気工業株式会社 樹脂封止型半導体装置とその製造方法及びその金型構造
JP3842444B2 (ja) 1998-07-24 2006-11-08 富士通株式会社 半導体装置の製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4079511A (en) * 1976-07-30 1978-03-21 Amp Incorporated Method for packaging hermetically sealed integrated circuit chips on lead frames
US4089575A (en) * 1976-09-27 1978-05-16 Amp Incorporated Connector for connecting a circuit element to the surface of a substrate
US4495376A (en) * 1981-07-27 1985-01-22 Texas Instruments Incorporated Carrier for integrated circuit
US4465898A (en) * 1981-07-27 1984-08-14 Texas Instruments Incorporated Carrier for integrated circuit
US4463217A (en) * 1981-09-14 1984-07-31 Texas Instruments Incorporated Plastic surface mounted high pinout integrated circuit package
JPS58169948A (ja) * 1982-03-30 1983-10-06 Fujitsu Ltd 樹脂封止型半導体装置

Also Published As

Publication number Publication date
EP0212521B1 (en) 1991-05-29
DE3679473D1 (de) 1991-07-04
JPS6249245U (ko) 1987-03-26
EP0212521A1 (en) 1987-03-04
KR900001987B1 (ko) 1990-03-30
US4724280A (en) 1988-02-09
JPH0325410Y2 (ko) 1991-06-03

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