KR860002929A - Equipment for processing multiple asynchronous synthetic video signals - Google Patents
Equipment for processing multiple asynchronous synthetic video signals Download PDFInfo
- Publication number
- KR860002929A KR860002929A KR1019850006920A KR850006920A KR860002929A KR 860002929 A KR860002929 A KR 860002929A KR 1019850006920 A KR1019850006920 A KR 1019850006920A KR 850006920 A KR850006920 A KR 850006920A KR 860002929 A KR860002929 A KR 860002929A
- Authority
- KR
- South Korea
- Prior art keywords
- sample
- signal
- video signal
- composite video
- coupled
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/445—Receiver circuitry for the reception of television signals according to analogue transmission standards for displaying additional information
- H04N5/45—Picture in picture, e.g. displaying simultaneously another television channel in a region of the screen
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
- H04N9/641—Multi-purpose receivers, e.g. for auxiliary information
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
- H04N9/74—Circuits for processing colour signals for obtaining special effects
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Processing Of Color Television Signals (AREA)
- Studio Circuits (AREA)
Abstract
내용 없음No content
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제2도는 본 발명의 실시예에 합체하는 픽스 인 픽스(pix-in-pix) 텔레비젼 수상기의 블럭 다이어그램.2 is a block diagram of a pix-in-pix television receiver incorporating an embodiment of the present invention.
제3도는 제2도에 도시된 수상기에 사용된 주/보조 신호 처리기의 블럭 다이어그램.3 is a block diagram of a primary / secondary signal processor used in the receiver shown in FIG.
제6도는 색도 처리 회로의 블럭 다이어그램.6 is a block diagram of a color processing circuit.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 채널 선택기 12 : 마이크로 프로세서10: channel selector 12: microprocessor
14 : 아나로그 스위치 16 : 안테나14: analog switch 16: antenna
18 : 분할기 22,24 : 동조 IF 증폭기 및 검파기 회로18: Splitter 22,24: Tuning IF Amplifier and Detector Circuit
26 : 보조 동기 구분자 28 : 주 동기 구분자26: secondary synchronous separator 28: primary synchronous separator
29 : AND 게이트 30 : 위상 고정 루프29 AND gate 30 phase locked loop
34 : A/D 변환기 40 : 주/보조 신호 처리기34: A / D Converter 40: Primary / Secondary Signal Processor
50 : 보조 메모리 52 : 주/보조 신호 멀티플렉서50: secondary memory 52: primary / secondary signal multiplexer
60 : 멀티플렉서 제어회로 70 : 주 메모리60: multiplexer control circuit 70: main memory
80 : 디지탈 메트릭스 310 : 콤 필터80: digital matrix 310: comb filter
320 : 가산기 330 : 피이킹 필터320: adder 330: peaking filter
340 : 멀티플렉서 350 : 저역통과필터340: multiplexer 350: low pass filter
352 : 지연소자 360 : 감산기352: delay element 360: subtractor
370 : 대역필터 380 : 색도처리기370: Band filter 380: Color processor
390 : AND 게이트 410,412 : 이동 레지스터390 AND gate 410 412 shift register
420,430 : 가산기 600 : 디멀티플렉서420,430: Adder 600: Demultiplexer
610,620 : 버스 650,651 : 절대값 회로610,620: bus 650,651: absolute value circuit
655 : 감산기 652,656 : 지연소자655: subtractor 652,656: delay element
658,670,679 : 가산기 662 : 래치658,670,679: adder 662: latch
666,667 : 버퍼 669 : 멀티플렉서666,667: Buffer 669: Multiplexer
672 : 위상 에러 검출기 706 : 멀티플렉서672: phase error detector 706: multiplexer
710 : 계수기 712 : 누산기710: counter 712: accumulator
716,726,724 : 래치 718 : 분할기 회로716,726,724: Latch 718: Divider Circuit
721 : 감산기 722 : 디멀티플렉서721 Subtractor 722 Demultiplexer
801,817 : 인버어터 802,803,811 : AND 게이트801,817: Inverter 802,803,811: AND gate
804,814 : 계수기 805 : RS 플립플럽804,814: counter 805: RS flip flop
806 : 멀티플렉서 807 : 주파수 분할기806: Multiplexer 807: Frequency Divider
808,818 : 지연소자 813,814 : 계수기808,818: delay element 813,814: counter
815 : 디코더815: Decoder
Claims (11)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/653,074 US4623915A (en) | 1984-09-21 | 1984-09-21 | Apparatus for processing multiple time division multiplexed asynchronous composite video signals |
US653074 | 1996-05-21 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR860002929A true KR860002929A (en) | 1986-04-30 |
KR930005601B1 KR930005601B1 (en) | 1993-06-23 |
Family
ID=24619395
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019850006920A KR930005601B1 (en) | 1984-09-21 | 1985-09-21 | Apparatus for processing multiple time division multiplexed asynchronous composite video signals |
Country Status (7)
Country | Link |
---|---|
US (1) | US4623915A (en) |
EP (1) | EP0175590B1 (en) |
JP (1) | JPH07108030B2 (en) |
KR (1) | KR930005601B1 (en) |
DE (1) | DE3584710D1 (en) |
HK (1) | HK213196A (en) |
SG (1) | SG152594G (en) |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4882577A (en) * | 1985-06-07 | 1989-11-21 | Hughes Aircraft Company | Calligraphic control for image superimposition |
JP2575108B2 (en) * | 1985-10-29 | 1997-01-22 | ソニー株式会社 | 2 screen TV receiver |
JPH0638652B2 (en) * | 1985-12-28 | 1994-05-18 | ソニー株式会社 | Television receiver |
CA1256984A (en) * | 1985-12-28 | 1989-07-04 | Kunio Hakamada | Television receiver |
JPS62159582A (en) * | 1986-01-06 | 1987-07-15 | Sony Corp | Television receiver |
EP0245745B1 (en) * | 1986-05-12 | 1993-10-27 | Hitachi, Ltd. | Image processing system |
JP2794661B2 (en) * | 1986-09-20 | 1998-09-10 | ソニー株式会社 | TV receiver |
US4750039A (en) * | 1986-10-10 | 1988-06-07 | Rca Licensing Corporation | Circuitry for processing a field of video information to develop two compressed fields |
US4724487A (en) * | 1987-02-17 | 1988-02-09 | Rca Corporation | Interlace inversion detector for a picture-in-picture video signal generator |
US4839728A (en) * | 1987-03-23 | 1989-06-13 | Rca Licensing Corporation | Picture-in-picture video signal generator |
CA1323418C (en) * | 1987-03-27 | 1993-10-19 | David E. Trytko | Video effects system with recirculation video combine and output combine |
US4782391A (en) * | 1987-08-19 | 1988-11-01 | Rca Licensing Corporation | Multiple input digital video features processor for TV signals |
KR910001515B1 (en) * | 1987-12-30 | 1991-03-09 | 삼성전자 주식회사 | Card picture-in picture generating circuit for tv and vtr |
NL8801413A (en) * | 1988-06-02 | 1990-01-02 | Philips Nv | TV-RECEIVER. |
JPH0213074A (en) * | 1988-06-29 | 1990-01-17 | Toshiba Corp | Multichannel image display circuit |
US4998171A (en) * | 1988-07-05 | 1991-03-05 | Samsung Electronics Co., Ltd. | Automatic shift circuit for a sub-picture screen for picture-in-picture feature |
KR950010887B1 (en) * | 1988-07-08 | 1995-09-25 | Samsung Electronics Co Ltd | Multi-screen producting image control circuit |
US4961071A (en) * | 1988-09-23 | 1990-10-02 | Krooss John R | Apparatus for receipt and display of raster scan imagery signals in relocatable windows on a video monitor |
US4914516A (en) * | 1989-04-20 | 1990-04-03 | Thomson Consumer Electronics, Inc. | Fast response picture-in-picture circuitry |
US4987493A (en) * | 1989-08-01 | 1991-01-22 | Rca Licensing Corporation | Memory efficient interlace apparatus and method as for a picture in a picture display |
DE58908084D1 (en) * | 1989-10-06 | 1994-08-25 | Siemens Ag | Circuit arrangement for picture-in-picture overlay in a television set with only one tuner. |
JPH05324821A (en) * | 1990-04-24 | 1993-12-10 | Sony Corp | High-resolution video and graphic display device |
US5434625A (en) * | 1990-06-01 | 1995-07-18 | Thomson Consumer Electronics, Inc. | Formatting television pictures for side by side display |
JPH04314278A (en) * | 1991-04-12 | 1992-11-05 | Sony Corp | Video signal receiver |
EP0555756A3 (en) * | 1992-02-10 | 1994-06-22 | Hitachi Ltd | Colour video signal processing method and device |
US5351129A (en) * | 1992-03-24 | 1994-09-27 | Rgb Technology D/B/A Rgb Spectrum | Video multiplexor-encoder and decoder-converter |
US5987209A (en) * | 1994-08-05 | 1999-11-16 | Funai Electric Co., Ltd. | Video signal receiver in which a reference signal is shared by a PLL circuit which sets the output frequency of a local RF-IF oscillator and by the chrominance signal generator |
CA2191632A1 (en) * | 1996-02-13 | 1997-08-14 | James Lee Combs | Video processor for processing two analog composite video signals |
JP3464924B2 (en) * | 1998-03-13 | 2003-11-10 | 株式会社東芝 | Synchronous control circuit |
US6356871B1 (en) * | 1999-06-14 | 2002-03-12 | Cirrus Logic, Inc. | Methods and circuits for synchronizing streaming data and systems using the same |
US7545937B2 (en) * | 2001-12-12 | 2009-06-09 | Thomson Licensing | Chrominance processing arrangement having immunity to colorstripe encoding |
US20040075741A1 (en) * | 2002-10-17 | 2004-04-22 | Berkey Thomas F. | Multiple camera image multiplexer |
DE60306391T2 (en) * | 2003-11-24 | 2006-10-19 | Alcatel | Procedure for displaying content |
JP4691193B1 (en) * | 2010-04-13 | 2011-06-01 | 株式会社東芝 | Video display device and video processing method |
JP6090204B2 (en) * | 2014-02-21 | 2017-03-08 | ヤマハ株式会社 | Acoustic signal generator |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5676691A (en) * | 1979-11-28 | 1981-06-24 | Hitachi Ltd | Television receiver with plurality of screen display |
US4467356A (en) * | 1981-09-24 | 1984-08-21 | Mccoy Reginald F H | Transmitting two television signals through one channel |
JPS5859671A (en) * | 1981-10-06 | 1983-04-08 | Toshiba Corp | Picture signal processing circuit |
JPS58166893A (en) * | 1982-03-29 | 1983-10-03 | Hitachi Ltd | Receiver of plural color screens |
JPS6135483U (en) * | 1984-07-31 | 1986-03-04 | 日本電気ホームエレクトロニクス株式会社 | television receiver |
-
1984
- 1984-09-21 US US06/653,074 patent/US4623915A/en not_active Expired - Fee Related
-
1985
- 1985-09-20 DE DE8585306720T patent/DE3584710D1/en not_active Expired - Fee Related
- 1985-09-20 EP EP85306720A patent/EP0175590B1/en not_active Expired - Lifetime
- 1985-09-20 JP JP60209890A patent/JPH07108030B2/en not_active Expired - Lifetime
- 1985-09-21 KR KR1019850006920A patent/KR930005601B1/en not_active IP Right Cessation
-
1994
- 1994-10-19 SG SG152594A patent/SG152594G/en unknown
-
1996
- 1996-12-05 HK HK213196A patent/HK213196A/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0175590A2 (en) | 1986-03-26 |
DE3584710D1 (en) | 1992-01-02 |
KR930005601B1 (en) | 1993-06-23 |
JPH07108030B2 (en) | 1995-11-15 |
SG152594G (en) | 1995-03-17 |
HK213196A (en) | 1996-12-06 |
JPS6184193A (en) | 1986-04-28 |
EP0175590B1 (en) | 1991-11-21 |
US4623915A (en) | 1986-11-18 |
EP0175590A3 (en) | 1988-04-20 |
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Legal Events
Date | Code | Title | Description |
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A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 19980529 Year of fee payment: 6 |
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LAPS | Lapse due to unpaid annual fee |