SU1552404A1 - Digital corrector of high-frequency pre-emphasis of chrominance signal in secam system - Google Patents

Abstract

The invention relates to television technology. The purpose of the invention is to simplify the device by replacing multipliers with adders with weight coefficients. type 2 ^N while improving the accuracy of the high-frequency correction. The corrector contains adders 1 and 9, el-delays 2, 4, 6, 7 and 10 and multipliers 3, 5 and 8. The recursive part of this equalizer forms the specified phase response and approximate frequency response. The non-recursive part has a quasilinear phase response. Therefore, when the signal passes through the non-recursive part, the resulting FPH does not change, but only an additional correction of the frequency response is performed. High accuracy of the correction of distortions and reduced requirements for the speed of the element base are achieved by separating all the adders by delay delays. 1 il.

Description

The invention relates to television reception equipment and can be used in television (TV) receivers and video monitoring devices of the SECAM system.

The aim of the invention is to simplify the device. by replacing the multipliers with adders to form the weighting factors 2 ^minutes while increasing the accuracy vysokochastotj hydrochloric correction.

'The drawing shows the structural! electric circuit of the digital corrector of high-frequency predistortions of the color signal of the SECAM system.

The digital corrector of high-frequency predistortions (CWP) of the color signal of the SECAM system contains a first adder 1, a first delay element 2, a first delay multiplier 3, a second delay element 4, a second multiplier 5, a third 6 and a fourth 7 delay elements, a third multiplier 8, a second adder 9 and fifth element 10 delay. In this case, the first 3, second 5 and third 8 multipliers have multiplication factors (1-1 / 16), (1-1 / 8) and (1-1 / 32), respectively.

Digital KVP works as follows.

The input signal after the analog-to-digital converter is supplied to; the input of the first adder 1. The sampling frequency of the input signal is equal to four times the tuning frequency of the digital CVP, in which case the digital CVP is described by the equation

Υ (Ν) = Χ (Ν) + Α · Υ (Ν-2), (1) where A = 0.9062 ... 0.9082.

We denote the sequence at the input of the device through X (N), the sequence at the output of the first delay element 2, through Z (N), and the output sequence, through Y (N). The coefficients of the first 3, second 5, and third 8 multipliers are denoted, respectively, by A1, A2, and AZ, which are chosen in this way.

Α1 · Α2 = A = 0.8203,

A1-AZ = a = 0.9082.

(2)

Since the samples of the signal from the output of the first delay element 2 passes through two multipliers 3 and 5 by the coefficients A1 and A2 and four delay elements 2, 4, 7 and 10 and then go to the second input of the first adder 1, and the input sequence X (N ) passes only through the first delay element 2, then the sequence at the output of the first delay element 2 can be written as

W (N) = X (N-1) +

A1 · Α2 · Ζ (Ν-4). (3) signal output delay delay arrive

Since the samples of the first element 2 to the output of the device through the second adder 9 and through the first 3 and third multipliers by the coefficients A1 and AZ, the second 4 and third 6 delay elements and the second adder 9, the output sequence can be found from the expression

Υ (Ν) = W (N) + Ab A3 W (N-2). (4) *

Substituting (3) in (4), we obtain

Υ (Ν) = Χ (Ν-Ί) + -Α · Υ (Ν-2), (5) which, up to a constant delay equal to one measure, coincides with <expression (1).

The recursive part of the digital CVP forms a given phase response and approximate frequency response. The non-recursive part has a highly linear phase response. Therefore, when the signal passes through the non-recursive part, the resulting phase response does not change, but only an additional correction of the frequency response is performed.

The invention provides less hardware costs due to the implementation of multipliers in the form of adders, higher accuracy of predistortion correction and lower requirements for the speed of the element base due to the separation of all adders by delay elements.

Claims (1)

Claim A SECAM system digital high-frequency predistortion corrector containing a first adder connected in series, the input of which is an input to the device, a first delay element and a first multiplier, a second delay element and a second multiplier connected in series, a third and fourth delay element, a third multiplier and a second adder, the output of which is the output of the device, characterized in that, in order to simplify the device by replacing the multipliers with adders with weight coefficients ida 2, while increasing the accuracy of high-frequency correction, the fifth delay element is introduced, the output of the first multiplier connected to the input of the second delay element, the output of the first delay element connected to the first input of the second adder, the output of the second delay element connected to the input of the third delay element through a third multiplier, the output of which is connected to the second input of the second adder, and the output of the second multiplier is connected through a fourth delay element and a fifth delay element connected in series and with the U second input of the first adder, the first, second and third multipliers have multiplication factors respectively (1-1 / 16), (1-1 / 8) and (1-1 / 32).