JPS58166893A - Receiver of plural color screens - Google Patents

Abstract

PURPOSE:To improve the quality of an inserted screen without increasing the number of sampling frequencies, by sampling the color difference signals of a slave screen by a dot sequential system by means of the clock signal having a shifted specific angle phase for each scanning line to be sampled. CONSTITUTION:Signals B-Y and R-Y are written to a color difference signals memory 45 with reversed timings to each other and for each sampling scanning line. Thus it is possible for the color difference signal to complement the omitted part for each sampling scanning line. No evil effect is virtually given to the quality of pictures even though the sequence of the color difference signals is changed. In such a way, a clock signal obtained by giving a division 50R to the reading clock signal obtained from a reading clock signal producing circuit 43 and another clock signal having the phase shifted by 180 deg. with phase inversion 62R are switched by a changeover switch 61R for each scanning line to control a switch 51R when the color difference signal written into the memory 45 is demodulated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a television receiver (Picture 1nPic) in which a screen of another channel can be inserted into a part of the screen.
abbreviated as ture,, ld lower P, in P) KW
In particular, the present invention relates to a nine-color multi-screen receiver that improves the image quality of the inserted screen without increasing the number of samples.

Figure 's1 is a conceptual diagram of PinP, where 1 is a television receiver, 2 is a cathode ray tube, 3 is a main screen section, and 4 is a child [i section] which is inserted by reducing the size of another TV screen.

In PinP, as is clear from the figure, Iaij
The i-side and sub-screens are designed so that each channel can be selected independently.

In the following description, a so-called two-screen television receiver with one sub-screen will be taken as an example, but it goes without saying that the present invention can also be applied to a television receiver that displays a plurality of sub-screens.

Figure 1lI2 shows an example of the method of inserting a child screen, where ■ is a child 1iN before narrowing and l is a child 1iN with a child screen inserted and 9@paintings. Screen reduction rate (scanning cycle after reduction) / (scanning cycle of original signal)
Assuming that, the screen reduction ratio of the sub screen is set to % in vertical and horizontal directions, and the scanning lines are extracted from the screen of sub screen 1 with 3 lines, Vc, 1 line, and OII*
* After compressing the horizontal period and synchronizing with the parent screen, the parent 11i1iK is inserted. Scanning lines (1) to (2) show part of the scanning lines after reduction tIi.

FIG. 3 is a diagram of a conventional example of nine consecutive parts of the @WCWla. In the figure, 11 is an antenna, 12 is a child screen insertion circuit, 13 is an image processing circuit 11, 14 is a cathode ray tube, and 21.31 is an I for the main screen and for the child screen, respectively.
This is an IF/video detection circuit. Here, sub screen insertion circuit 1
12Y constituting 2 is a luminance signal, 12B, 12R, 1
2G Fi B-Y and RY, respectively.

This is a small screen insertion circuit for each color difference signal G-Y.

In addition, 25.55Fi is a synchronization separation circuit for the main screen and child screen, respectively, 24.54 is a color signal processing circuit for the main screen and child screen, respectively, and 35FiG-Y signal synthesis circuit)
40 is a luminance signal memory section, 41 is a color difference signal memory section, and 42 and 45 are write and read clock signal generation circuits, respectively.

Next, the operation of the circuit shown in FIG. aI3 will be explained with a focus on inserting a sub-screen. The radio waves received by the antenna 11 are selected by the small screen tuner 31 and input to the small screen IF/video detection circuit 52. The child screen synchronization separation circuit 33 separates the synchronization signal from the output of the scissors 1liii surface work F/video detection circuit 52. Based on this synchronization signal, a clock signal 100 is output from the write clock signal generation circuit 42. And I for the child IIi side? -Image detection circuit 52
Nine luminance signals 1 are outputted from the luminance signal memory section 40 and stored in the luminance signal memory section 40 according to the clock signal 100.

On the other hand, the read clock signal generation circuit 4s generates a clock signal 110 based on the synchronization signal of the video signal for the main screen obtained by the synchronization S circuit 2s.

Then, the small screen luminance signal stored in the luminance signal memory 1340 as described above is used as the wrinkle reading clock signal 11.
Read by 0. The luminance signal thus summed and read is the child IIM insertion circuit 12! The main screen brightness signal Y
, and the video signal #! is inserted from the sub-plane insertion circuit 12Y.
& is output to the weir circuit 15.

Similarly, the sub-screen color difference signals B-Y and RY are extracted from the sub-screen luminance signal by the sub-screen color signal processing circuit 54 and obtained by the writing click signal generation path 42! The color difference signal 491 is alternately set point by point by the lock signal 100.
141.

Further, the B-! of the child screen read out from the color difference signal memory section 41 by the clock signal 110 outputted from the readout clock signal generation circuit 43! .

The R-Y signal is input to the G-Y signal synthesis head 12 circuit 55, and the G-Y signal is output from the scissors circuit 35. And these small screen color difference signals B-Y.

R-Y and G-Y are the child screen insertion circuit 12B, respectively.
12R, 12GK! B-Y extracted from the video signal for the main screen.

It is inserted into each color difference signal of R-Y and G-Y. This inserted signal is sent to the signal processing circuit 13aC. In this manner, an image including a sub-IIM as shown in FIG. 111, for example, is displayed on the cathode ray tube 14 by the signal sent from the image signal processing circuit 13.

FIG. 44 is a detailed diagram of the color difference signal memory section 41 of FIG. Further, FIG. 5 shows a time chart of the main parts of the signals shown in FIG. In FIG. 4, 44 is 1 pixel memory, 4
5 is a color difference signal memory, SOW.

50R are frequency dividers, 511, 51R, 51R1
ta and ms diagrams indicate changeover switches, respectively #F-
, 100 is a write clock signal, 101 is a write changeover switch control signal, 110 is a readout clock signal, 111 is a readout changeover switch control signal, 1
12 is a color difference signal memory output signal, 113 is a 1-pixel memory output signal, 114 is a demodulated BY signal, and 115 is a demodulated R-4 signal.

Next, the operation of the circuit shown in FIG. 4 will be explained using FIG. The clock signal 100 output from the write clock generation circuit 42 is frequency-divided by the frequency division Bsow to become a signal 101. When the signal 101 is input to the changeover switch 51W, the changeover switch 51W changes the logic of the signal 101 to ff1-1.
At logic 6, the B-Y signal is sent to the color difference signal memory 45, and at logic 0°, the R-Y signal is sent to the color difference signal memory 45.These color difference signals 1-! and R-Y are sent to the color difference signal memory 45 at the falling edge of the clock signal 100. written.

Next, at the falling edge of the clock signal 110 output from the read clock generation circuit 43, the clock signal 110 is output to the color difference signal memory 4.
The sub-screen color difference signal is read from 5.

The color difference signal memory output signal 112 is set by the changeover switch 51R.
1 and 51R1, and 11
It is sent to the IIt elementary memory 44. 1 pixel memory 44ij
The signal 112 for one picture element is stored. 9, the branch clock signal 110 is divided by the divider 50R, divided by 0@501
The readout switch control signal 1 is the output signal of
11 is a changeover switch 51R.

Controls 51R3.

Now, as shown in FIG.
If the color difference signal B - Y is read out from the color difference signal memory 45 at the end of 9 at 110, then,
This color difference signal B-Y is guided to the fixed contacts of the changeover switches 51R1 and 51B, and the 1-pixel memory 4
4 is stored. At this time, since the read changeover switch control signal 111 is logic 1@, the movable contacts of the changeover switches 51R1 and 51R are at the dotted line position O in the figure.

Therefore, as shown in FIG. 5, a 9B-Y signal 114 is obtained from the changeover switch 51R1, and a 1 pixel memo 1J4 is obtained from the changeover switch 51-.
Since the 9R-4 signal 115 is outputted from the 9@B-4 signal stored in 4, the 9R-4 signal 115 is outputted from the 11IiR pre-order.

Next, when the color difference signal RY is read out from the color difference signal memory 45 at the falling edge of the clock signal 110, this R-
The Y signal is guided by the switching switch f 51 R, and to the fixed contact of the 51 bird. At this time, the change-over switch control signal 111 for exposure is at logic jl@O1, so the change-over switch 511m and the movable contact of the 5-toe are at the position indicated by the solid line in the figure. This rounding switch 51fi1 is read out at the falling edge of the clock signal 110, and is stored in the 1-element memory 44.
A signal 114 is outputted, and a nine R-Y signal 115 is outputted from the selector switch 51 at the falling edge of the clock signal 110.

Similarly, the clock signals 110 to . 110~, the B-Y signals are sequentially output from the color difference signal memory 45.
R-! The signal is read out. At this time, the movable contacts of the changeover switches 51R1 and 51R are sequentially switched from the position indicated by the dotted line to the position indicated by the solid line.
B-Y signal 114 and R-Y@ signal 115 are obtained from each of the signals 114 and 51, as shown in FIG.

Here, the changeover switch 51W is changed over by the write changeover switch control signal 101 to output the color difference signal B.
-Y and R-Y are sampled, and the color difference signal memory 4
When writing to tn7(.

Note that FIG. 6 is a diagram schematically showing Sundelinda points for each scanning line, and 5 indicates the sampling point of the B-Y signal and 6 indicates the sampling point of the R-Y signal. If the signal period varies, in the conventional device, as shown in Figure 6, the B-Y signal 5 and the R-Y signal 6 are sampled alternately at the period t-, and the B-Y Signal 5 and R-Y
The sampling points of signal 6 are arranged in the vertical direction.

Figure 7 shows the color difference signal B-Y shown in Figure 6.

The sampling points of only the B-Y signal are extracted and shown from among the R-Y sun cylinder points.

As is clear from FIG. 7, even if sampling is performed using a writing block with a cycle of 1a, if the B-Y and RY signals are sampled alternately one point at a time (dot-sequential method), the resulting color difference signal will be f. So the period is 2t.

It will be sampled using the same clock. Therefore, there are many missing parts in the horizontal direction, and the degree of horizontal dissolution is poor.

As a countermeasure to this problem, it is possible to shorten the sampling period of each color difference signal in order to sample the missing part, but this would increase the number of samples and require a large memory capacity. There are nine drawbacks. For example, each color difference signal has a cycle of 1. If sampling is performed at 100%, a write clock with a cycle of t8/2 is required, which doubles the number of samples and memory capacity, resulting in an increase in system cost.

SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the drawbacks of the prior art described above and to provide a color multi-screen receiver that can obtain image quality equivalent to doubling the number of samplings and memory capacity without increasing the number of samplings and memory capacity. .

% of the invention! , is 180 per scan line sampled.
By sampling the child-plane color difference signal in a point-sequential manner using a clock signal with a phase shift, horizontal omissions in each color difference signal are interpolated.

The present invention will be explained below by way of examples. The 8th figure is
An example of the present invention is shown. This embodiment is different from the conventional device shown in FIG.
2R, changeover switch 61W, 61R, and frequency divider 6
Including SW and 6SR, it is 9 points. In addition, in the figure, blocks with the same symbols as those in FIG. 4 indicate the same or similar blocks as those in FIG. 114, and FIG. 9 shows the signals of the main part of FIG.

Next, the operation of this embodiment will be explained using Figure 9. The write clock signal generation circuit 42 outputs a clock signal 100 having the same period as in the conventional device. This clock signal 100 is frequency-divided by frequency division @SOW. Output 101 of frequency division @50W is changeover switch 41W
and one fixed contact of the phase inversion circuit 62WK.
, the output 102 of the phase inversion circuit 62w is connected to the changeover switch 4.
It is led to the other fixed contact of 1W.

On the other hand, the synchronization signal separated by the child screen synchronization separation circuit 33 is frequency-divided by a frequency divider 631, resulting in a signal 105#i as shown in FIG.
During the period 101, the movable contact of the changeover switch 611F is placed in the dotted line position, and during the logic 101 period, the movable contact is placed in the solid line position. Note that each period of logic 11- and 10'' of signal 103 is equal to one horizontal scanning period. Therefore, during periods t to 1 of signal 103 in FIG. Therefore, signal 101
is sent to changeover switch 51WK. On the other hand, signal 103
Later, during the period ~t1, the switching contact of the changeover switch 6110 is in the position indicated by the solid line, and the signal 102 is at the position of the changeover switch 61W.
K is sent. Therefore, the signal 104 sent to the changeover switch 51W through the changeover switch 61W is j
The waveform will be as shown in Figure 49.

When the signal 104 is logic 011, the selector switch 51W switches to KI! as shown by the dotted line. Since it is ribboned, R
-Select Y signal. On the other hand, when the logic is 10-, the signals are connected as shown by the solid line and the BY signal is selected. therefore,
The output 104 of the changeover switch 51W is the signal 1 in FIG.
05, time 1. - One horizontal scanning period is R
-Y, B-Y.

The samples are sampled in the order of R-YB-Y, . . . .

In addition, during the next horizontal scanning period, that is, from time 1 m to 1 m, B -'l , R-Y , B -Y , R-Y
, ...-.

It is sampled in the song. Similarly, during the next horizontal scanning period, although not shown, the scanning order is the same as in the first horizontal scanning period, R-Y,
B-Y, R-Y, B-Y,...
It becomes a wish.

If this is expressed in the same format as in Figure i16 above, '
It will look like the Ig10 diagram. That is, one sampling scanning period on -Kan is the R-Y signal 6. R-Y signal 5. B-
Y signal 6. . . . During one sampling scanning period of the 0th order, which is sampled alternately point by point, the BY signal 5. R-Y signal 6. B-Y signal5. One point at a time is sunciled alternately in this order. Thereafter, the color difference signals are sampled in the same manner, and as shown in FIG. 10, the color difference signals sampled in the vertical direction change every sampling scanning line.

Therefore, according to this embodiment, since the B-Y signal and the R-Y signal are written to the color difference signal memory 45 at opposite timings for each sampling scan line, each color difference signal is written for each sampling scan line. Missing parts can be interpolated. In other words, sampling period 1. This is equivalent to sampling each color difference signal. In addition,
Even if the order of the color difference signals sampled for each sampling scanning line is changed as in this embodiment, there is almost no adverse effect on the image quality because the line correlation of television video signals is strong.

As described above, when demodulating the color difference signal written in the color difference signal memory 45, a clock signal obtained by frequency-dividing the read clock signal obtained by the read clock signal generation circuit 43 by the divider 50R and a phase inversion circuit are used. The change-over switch 51R may be controlled by inverting the phase with the change-over switch 62R and changing the phase by 180 degrees, and by switching between the clock signal and the companion clock signal for each scanning line with the change-over switch 61R. In order to switch the changeover switch 61R for each scanning line, the clock signal obtained from the main screen synchronization separation circuit 23 is frequency-divided by a divider 65R and controlled by nine clock signals.

Although one embodiment of the present invention has been described with the changeover switch as a switch having mechanical contacts, general &
It will be clear that C is an electronic switch.

As described above, according to the present invention, in a P in P television that samples and reduces the slave 11irfJ signal, the image quality can be improved without increasing the number of samplings of the slave screen color difference signal and the memory capacity of the color difference signal memory. It has the effect of being able to Another advantage is that the present invention can be implemented without increasing system cost.

[Brief explanation of drawings]

Figure @1 is a conceptual diagram of PinP TV, Figure 2 is an explanatory diagram of an example of scanning lines when inserting a sub screen, Figure Jli3 is a block diagram of a conventional PinP TV receiver, and Figure 4 is @ Figure 3 is a block diagram of the main part, Figure 186 is a time chart of the main part of the signal in Figure 4, Figure 186 is an explanatory diagram of a conventional color difference signal sampling example, and Figure 7 is a diagram of one color difference signal in Figure 6. FIG. 8 is a block diagram of an embodiment of the present invention.
Figure 9 is a time chart of the main parts of the signals in Figure 8.
FIG. 0 shows an explanatory diagram of an example of color difference signal sampling according to the present invention. 23... Synchronization separation circuit for main screen, 33... Synchronization separation circuit for child screen, 41... Color difference signal memory section, 42...
・Writing clock signal generation circuit, 43...Reading clock signal generation circuit, 44...141 & elementary memory,
45...Color difference signal memory, SOW, 50R. 63W, 6AR... Frequency divider, 51W, to 51. To 51, 41W, 61R... changeover switch, 62W
, +621...Phase inversion circuit agent Patent attorney Michi Hiraki 4-1 Illustration 2

Claims (1)

[Claims] (1) In a color multi-screen receiver that inserts one or more TV screens as a sub-screen in a part of the 1111 TV screen, the sub-screen color difference signal memory stores the two color difference signals of the sub-screen in units of pixels. Recommendation 1 used for sampling
means for obtaining a clock signal of 1, a means for obtaining a clock signal of 180 degrees out of phase with the clock signal of 1;
Means for switching between the l110 clock signal and the i42 clock signal based on the synchronization signal of the television signal, and means for switching the two color difference signals using the switched clock signal of Kuri 1 and the clock signal of Shima 2 in 1 sun and 19 da points. It is provided with means for alternately switching and inputting Ktli notes into the memo memory every time,
A color multi-screen receiver characterized in that the switching means switches between the 1s1 clock signal and the second clock signal for each scanning line to be sampled, and sums the color difference signals of the sub-screen so as to write them into the memory.