KR840005227A - 데이타 처리 시스템 - Google Patents

데이타 처리 시스템 Download PDF

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Publication number
KR840005227A
KR840005227A KR1019830002878A KR830002878A KR840005227A KR 840005227 A KR840005227 A KR 840005227A KR 1019830002878 A KR1019830002878 A KR 1019830002878A KR 830002878 A KR830002878 A KR 830002878A KR 840005227 A KR840005227 A KR 840005227A
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KR
South Korea
Prior art keywords
measurement
information
performance
data processing
performance measurement
Prior art date
Application number
KR1019830002878A
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English (en)
Other versions
KR870000115B1 (ko
Inventor
모또가즈 가또오
Original Assignee
야마모도 다꾸마
후지쑤 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 야마모도 다꾸마, 후지쑤 가부시끼가이샤 filed Critical 야마모도 다꾸마
Publication of KR840005227A publication Critical patent/KR840005227A/ko
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Publication of KR870000115B1 publication Critical patent/KR870000115B1/ko

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/24—Marginal checking or other specified testing methods not covered by G06F11/26, e.g. race tests
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/348—Circuit details, i.e. tracer hardware
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Debugging And Monitoring (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

내용 없음

Description

데이타 처리 시스템
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 종래방식의 시스템
제2도는 본 발명의 한가지 실시예의 구성도
제3도는 본 발명에 의한 로그 에어리어(log area)의 예시도
제4도는 측정 제어테이블의 예시도
제5도에서부터 제9도까지는 성능 측정 설정부의 처리 설명도
제10도와 제11도는 성능 측정처리부의 처리 설명도
제12도는 적절한 예에 의한 데이타 처리시스템의 하트웨어의 구성도

Claims (4)

  1. 성능 측정항목에 해당되는 측정 정보를 축적하는 측정 정보축적 수단, 성능측정항목정보와 성능측정상태 정보를 축적하는 측정제어 정보 축적수단, 타이머, 측정제어 정보 축적 수단에 대해 설정되는 정보를 제어하는 측정제어 정보 설정처리부 및 상기 타이머에 의해 명령되는 개입중단을 샘플링 함으로써 시동되어 성능측정 항목 정보와 성능측정 상태 정보로 된 측정 정보축적 수단에 측정정보를 수집하는 성능측정처리부로 구성됨을 특징으로 하는 데이타 처리 시스템.
  2. 청구범위 제1항에 있어서, 성능측정 설정용 명령을 발생하는 구조를 구성하고, 명령의 개입중단에 의해 측정 제어정보 설정처리부를 시동시킴을 특징으로 하는 데이타 처리 시스템.
  3. 청구범위 제1항 또는 제2항에 있어서, 상기 성능측정 상태 정보로서 상기 타이머에 설정되는 샘플링 주기 정보를 생산함을 특징으로 하는 데이타 처리 시스템.
  4. 청구범위 제1항 에서 부터 제3항까지중 어느 한가지 청구범위에 있어서 측정 제어 정보 설정 처리부와성능 측정처리부에 의한 처리를 주기억상의 퍼엄웨어 영역에 있는 명령균에 의해 처리함을 특징으로 하는 테이타 처리 시스템.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019830002878A 1982-06-30 1983-06-27 데이타 처리 시스템 KR870000115B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP113317 1982-06-30
JP57-113317 1982-06-30
JP57113317A JPS593651A (ja) 1982-06-30 1982-06-30 フア−ムウエアによる性能測定システム

Publications (2)

Publication Number Publication Date
KR840005227A true KR840005227A (ko) 1984-11-05
KR870000115B1 KR870000115B1 (ko) 1987-02-11

Family

ID=14609160

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019830002878A KR870000115B1 (ko) 1982-06-30 1983-06-27 데이타 처리 시스템

Country Status (9)

Country Link
US (1) US4601008A (ko)
EP (1) EP0098169B1 (ko)
JP (1) JPS593651A (ko)
KR (1) KR870000115B1 (ko)
AU (1) AU546369B2 (ko)
BR (1) BR8303530A (ko)
CA (1) CA1198825A (ko)
DE (1) DE3379851D1 (ko)
ES (1) ES523749A0 (ko)

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US5301312A (en) * 1991-08-21 1994-04-05 International Business Machines Corporation Method and system for utilizing benign fault occurrence to measure interrupt-blocking times
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JP3727382B2 (ja) * 1994-12-26 2005-12-14 三菱電機株式会社 制御ソフトウェア実行システムの制御方法
US5881222A (en) * 1995-01-23 1999-03-09 International Business Machines Corporation Method and apparatus for detecting performance problems in a windows-based computer system
US6148437A (en) * 1998-05-04 2000-11-14 Hewlett-Packard Company System and method for jump-evaluated trace designation
US6681240B1 (en) 1999-05-19 2004-01-20 International Business Machines Corporation Apparatus and method for specifying maximum interactive performance in a logical partition of a computer system independently from the maximum interactive performance in other partitions
US6959291B1 (en) 1999-05-19 2005-10-25 International Business Machines Corporation Management of a concurrent use license in a logically-partitioned computer
US6691146B1 (en) 1999-05-19 2004-02-10 International Business Machines Corporation Logical partition manager and method
US6467007B1 (en) * 1999-05-19 2002-10-15 International Business Machines Corporation Processor reset generated via memory access interrupt
US7770034B2 (en) * 2003-12-16 2010-08-03 Intel Corporation Performance monitoring based dynamic voltage and frequency scaling
US7200824B1 (en) * 2004-11-16 2007-04-03 Altera Corporation Performance/power mapping of a die
US7346787B2 (en) * 2004-12-07 2008-03-18 Intel Corporation System and method for adaptive power management
US7814485B2 (en) * 2004-12-07 2010-10-12 Intel Corporation System and method for adaptive power management based on processor utilization and cache misses
WO2007043144A1 (ja) * 2005-10-05 2007-04-19 Hewlett-Packard Development Company, L.P. 負荷試験装置およびその方法
JP5029245B2 (ja) * 2007-09-20 2012-09-19 富士通セミコンダクター株式会社 プロファイリング方法及びプログラム
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JPWO2009147738A1 (ja) * 2008-06-05 2011-10-20 富士通株式会社 情報処理装置及びその制御方法並びにモニタプログラム
US20110145559A1 (en) * 2009-12-16 2011-06-16 Thomson Steven S System and method for controlling central processing unit power with guaranteed steady state deadlines
US9104411B2 (en) 2009-12-16 2015-08-11 Qualcomm Incorporated System and method for controlling central processing unit power with guaranteed transient deadlines
US9128705B2 (en) * 2009-12-16 2015-09-08 Qualcomm Incorporated System and method for controlling central processing unit power with reduced frequency oscillations
US9176572B2 (en) 2009-12-16 2015-11-03 Qualcomm Incorporated System and method for controlling central processing unit power with guaranteed transient deadlines
US8650426B2 (en) 2009-12-16 2014-02-11 Qualcomm Incorporated System and method for controlling central processing unit power in a virtualized system
US8689037B2 (en) 2009-12-16 2014-04-01 Qualcomm Incorporated System and method for asynchronously and independently controlling core clocks in a multicore central processing unit
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Also Published As

Publication number Publication date
BR8303530A (pt) 1984-02-07
EP0098169A3 (en) 1985-10-09
AU546369B2 (en) 1985-08-29
KR870000115B1 (ko) 1987-02-11
ES8405173A1 (es) 1984-05-16
EP0098169B1 (en) 1989-05-10
AU1641183A (en) 1984-01-05
CA1198825A (en) 1985-12-31
EP0098169A2 (en) 1984-01-11
US4601008A (en) 1986-07-15
JPS6226732B2 (ko) 1987-06-10
DE3379851D1 (en) 1989-06-15
JPS593651A (ja) 1984-01-10
ES523749A0 (es) 1984-05-16

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