KR20240140160A - 지지 기판 상에 박막을 전사하는 방법 - Google Patents
지지 기판 상에 박막을 전사하는 방법 Download PDFInfo
- Publication number
- KR20240140160A KR20240140160A KR1020247029081A KR20247029081A KR20240140160A KR 20240140160 A KR20240140160 A KR 20240140160A KR 1020247029081 A KR1020247029081 A KR 1020247029081A KR 20247029081 A KR20247029081 A KR 20247029081A KR 20240140160 A KR20240140160 A KR 20240140160A
- Authority
- KR
- South Korea
- Prior art keywords
- thin film
- temperature
- substrate
- transferring
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H01L21/76254—
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P10/00—Bonding of wafers, substrates or parts of devices
- H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
- H10P10/128—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates by direct semiconductor to semiconductor bonding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
- H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
-
- H01L21/187—
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- H01L21/324—
-
- H01L21/68785—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P54/00—Cutting or separating of wafers, substrates or parts of devices
- H10P54/50—Cutting or separating of wafers, substrates or parts of devices by scoring, breaking or cleaving
- H10P54/52—Cutting or separating of wafers, substrates or parts of devices by scoring, breaking or cleaving by cleaving
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/76—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches
- H10P72/7604—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support
- H10P72/7624—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support characterised by the mechanical construction of the susceptor, stage or support
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10P95/90—Thermal treatments, e.g. annealing or sintering
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
Landscapes
- Element Separation (AREA)
- Recrystallisation Techniques (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR2200842A FR3132384B1 (fr) | 2022-01-31 | 2022-01-31 | Procede de transfert d’une couche mince sur un substrat support |
| FRFR2200842 | 2022-01-31 | ||
| PCT/EP2022/086726 WO2023143818A1 (fr) | 2022-01-31 | 2022-12-19 | Procede de transfert d'une couche mince sur un substrat support |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20240140160A true KR20240140160A (ko) | 2024-09-24 |
Family
ID=81325210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020247029081A Pending KR20240140160A (ko) | 2022-01-31 | 2022-12-19 | 지지 기판 상에 박막을 전사하는 방법 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US20250391704A1 (https=) |
| EP (1) | EP4473553B1 (https=) |
| JP (1) | JP2025504573A (https=) |
| KR (1) | KR20240140160A (https=) |
| CN (1) | CN118591862A (https=) |
| FR (1) | FR3132384B1 (https=) |
| TW (1) | TW202335092A (https=) |
| WO (1) | WO2023143818A1 (https=) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6540827B1 (en) * | 1998-02-17 | 2003-04-01 | Trustees Of Columbia University In The City Of New York | Slicing of single-crystal films using ion implantation |
| FR2839385B1 (fr) * | 2002-05-02 | 2004-07-23 | Soitec Silicon On Insulator | Procede de decollement de couches de materiau |
-
2022
- 2022-01-31 FR FR2200842A patent/FR3132384B1/fr active Active
- 2022-12-19 CN CN202280088314.4A patent/CN118591862A/zh active Pending
- 2022-12-19 EP EP22836231.5A patent/EP4473553B1/fr active Active
- 2022-12-19 JP JP2024545103A patent/JP2025504573A/ja active Pending
- 2022-12-19 US US18/834,441 patent/US20250391704A1/en active Pending
- 2022-12-19 KR KR1020247029081A patent/KR20240140160A/ko active Pending
- 2022-12-19 WO PCT/EP2022/086726 patent/WO2023143818A1/fr not_active Ceased
- 2022-12-20 TW TW111148934A patent/TW202335092A/zh unknown
Also Published As
| Publication number | Publication date |
|---|---|
| US20250391704A1 (en) | 2025-12-25 |
| EP4473553C0 (fr) | 2025-12-17 |
| FR3132384A1 (fr) | 2023-08-04 |
| JP2025504573A (ja) | 2025-02-12 |
| FR3132384B1 (fr) | 2024-01-12 |
| CN118591862A (zh) | 2024-09-03 |
| WO2023143818A1 (fr) | 2023-08-03 |
| EP4473553B1 (fr) | 2025-12-17 |
| TW202335092A (zh) | 2023-09-01 |
| EP4473553A1 (fr) | 2024-12-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0105 | International application |
St.27 status event code: A-0-1-A10-A15-nap-PA0105 |
|
| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-2-2-P10-P22-nap-X000 |
|
| D13 | Search requested |
Free format text: ST27 STATUS EVENT CODE: A-1-2-D10-D13-SRH-X000 (AS PROVIDED BY THE NATIONAL OFFICE) |
|
| D13-X000 | Search requested |
St.27 status event code: A-1-2-D10-D13-srh-X000 |