TW202335092A - 用於將薄層移轉至載體底材之方法 - Google Patents

用於將薄層移轉至載體底材之方法 Download PDF

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Publication number
TW202335092A
TW202335092A TW111148934A TW111148934A TW202335092A TW 202335092 A TW202335092 A TW 202335092A TW 111148934 A TW111148934 A TW 111148934A TW 111148934 A TW111148934 A TW 111148934A TW 202335092 A TW202335092 A TW 202335092A
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TW
Taiwan
Prior art keywords
temperature
carrier substrate
donor substrate
thin layer
heat treatment
Prior art date
Application number
TW111148934A
Other languages
English (en)
Chinese (zh)
Inventor
迪帝爾 蘭盧
那迪亞 班穆罕默德
奧列格 科諾強克
馬森 費德瑞克
海倫 格蘭沛絲
Original Assignee
法商索泰克公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 法商索泰克公司 filed Critical 法商索泰克公司
Publication of TW202335092A publication Critical patent/TW202335092A/zh

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00Bonding of wafers, substrates or parts of devices
    • H10P10/12Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H10P10/128Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates by direct semiconductor to semiconductor bonding
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1914Preparing SOI wafers using bonding
    • H10P90/1916Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00Cutting or separating of wafers, substrates or parts of devices
    • H10P54/50Cutting or separating of wafers, substrates or parts of devices by scoring, breaking or cleaving
    • H10P54/52Cutting or separating of wafers, substrates or parts of devices by scoring, breaking or cleaving by cleaving
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/76Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches
    • H10P72/7604Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support
    • H10P72/7624Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support characterised by the mechanical construction of the susceptor, stage or support
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90Thermal treatments, e.g. annealing or sintering
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/181Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
TW111148934A 2022-01-31 2022-12-20 用於將薄層移轉至載體底材之方法 TW202335092A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2200842A FR3132384B1 (fr) 2022-01-31 2022-01-31 Procede de transfert d’une couche mince sur un substrat support
FRFR2200842 2022-01-31

Publications (1)

Publication Number Publication Date
TW202335092A true TW202335092A (zh) 2023-09-01

Family

ID=81325210

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111148934A TW202335092A (zh) 2022-01-31 2022-12-20 用於將薄層移轉至載體底材之方法

Country Status (8)

Country Link
US (1) US20250391704A1 (https=)
EP (1) EP4473553B1 (https=)
JP (1) JP2025504573A (https=)
KR (1) KR20240140160A (https=)
CN (1) CN118591862A (https=)
FR (1) FR3132384B1 (https=)
TW (1) TW202335092A (https=)
WO (1) WO2023143818A1 (https=)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6540827B1 (en) * 1998-02-17 2003-04-01 Trustees Of Columbia University In The City Of New York Slicing of single-crystal films using ion implantation
FR2839385B1 (fr) * 2002-05-02 2004-07-23 Soitec Silicon On Insulator Procede de decollement de couches de materiau

Also Published As

Publication number Publication date
US20250391704A1 (en) 2025-12-25
EP4473553C0 (fr) 2025-12-17
FR3132384A1 (fr) 2023-08-04
JP2025504573A (ja) 2025-02-12
FR3132384B1 (fr) 2024-01-12
CN118591862A (zh) 2024-09-03
WO2023143818A1 (fr) 2023-08-03
EP4473553B1 (fr) 2025-12-17
KR20240140160A (ko) 2024-09-24
EP4473553A1 (fr) 2024-12-11

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