KR20240128894A - 다이 장착형 전압 레귤레이터를 갖춘 3d 반도체 패키지 - Google Patents

다이 장착형 전압 레귤레이터를 갖춘 3d 반도체 패키지 Download PDF

Info

Publication number
KR20240128894A
KR20240128894A KR1020247024100A KR20247024100A KR20240128894A KR 20240128894 A KR20240128894 A KR 20240128894A KR 1020247024100 A KR1020247024100 A KR 1020247024100A KR 20247024100 A KR20247024100 A KR 20247024100A KR 20240128894 A KR20240128894 A KR 20240128894A
Authority
KR
South Korea
Prior art keywords
die
region
semiconductor package
voltage regulator
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
KR1020247024100A
Other languages
English (en)
Korean (ko)
Inventor
가브리엘 에이치. 로
라자 스와미나싼
라훌 아가르왈
브레트 피. 윌커슨
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20240128894A publication Critical patent/KR20240128894A/ko
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H01L25/16—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/427—Power or ground buses
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
    • H01L23/49816—
    • H01L23/5283—
    • H01L23/5286—
    • H01L23/53209—
    • H01L23/5384—
    • H01L23/5385—
    • H01L23/5386—
    • H01L25/0652—
    • H01L27/0688—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Geometry (AREA)
KR1020247024100A 2021-12-20 2022-12-07 다이 장착형 전압 레귤레이터를 갖춘 3d 반도체 패키지 Pending KR20240128894A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/556,346 2021-12-20
US17/556,346 US12165981B2 (en) 2021-12-20 2021-12-20 3D semiconductor package with die-mounted voltage regulator
PCT/US2022/052129 WO2023121876A1 (en) 2021-12-20 2022-12-07 3d semiconductor package with die-mounted voltage regulator

Publications (1)

Publication Number Publication Date
KR20240128894A true KR20240128894A (ko) 2024-08-27

Family

ID=86768936

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020247024100A Pending KR20240128894A (ko) 2021-12-20 2022-12-07 다이 장착형 전압 레귤레이터를 갖춘 3d 반도체 패키지

Country Status (6)

Country Link
US (2) US12165981B2 (https=)
EP (1) EP4454014A4 (https=)
JP (1) JP2024546903A (https=)
KR (1) KR20240128894A (https=)
CN (1) CN118613911A (https=)
WO (1) WO2023121876A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230034737A1 (en) * 2021-07-30 2023-02-02 Intel Corporation Composite ic die package including ic die directly bonded to front and back sides of an interposer
US12355006B2 (en) * 2022-02-16 2025-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of manufacturing thereof
CN116936531A (zh) * 2022-03-29 2023-10-24 辉达公司 具有集成功率转换器模块的集成电路基板设计及其制造方法
US12581663B2 (en) * 2022-12-22 2026-03-17 International Business Machines Corporation Heterogeneous integration structure with voltage regulation

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8716855B2 (en) * 2010-11-10 2014-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit system with distributed power supply comprising interposer and voltage regulator module
US9831148B2 (en) 2016-03-11 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package including voltage regulators and methods forming same
KR102663810B1 (ko) * 2016-12-30 2024-05-07 삼성전자주식회사 전자 소자 패키지
US11515291B2 (en) 2018-08-28 2022-11-29 Adeia Semiconductor Inc. Integrated voltage regulator and passive components
CN112913014B (zh) 2018-10-26 2024-03-26 华为技术有限公司 用于集成稳压器(ivr)应用的电感器
US11671010B2 (en) 2020-02-07 2023-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Power delivery for multi-chip-package using in-package voltage regulator
US12288750B2 (en) * 2021-09-24 2025-04-29 Intel Corporation Conformal power delivery structure for direct chip attach architectures

Also Published As

Publication number Publication date
US20230197619A1 (en) 2023-06-22
US20250070031A1 (en) 2025-02-27
EP4454014A4 (en) 2026-03-25
WO2023121876A1 (en) 2023-06-29
JP2024546903A (ja) 2024-12-26
CN118613911A (zh) 2024-09-06
US12165981B2 (en) 2024-12-10
EP4454014A1 (en) 2024-10-30

Similar Documents

Publication Publication Date Title
US12165981B2 (en) 3D semiconductor package with die-mounted voltage regulator
US11244938B2 (en) Electronic device package
US7279795B2 (en) Stacked die semiconductor package
US7745263B2 (en) System and method for routing supply voltages or other signals between side-by-side die and a lead frame for system in a package (SIP) devices
US10784202B2 (en) High-density chip-to-chip interconnection with silicon bridge
US20140131854A1 (en) Multi-chip module connection by way of bridging blocks
CN103262239B (zh) 具有堆迭电源转换器的半导体元件
US20100052111A1 (en) Stacked-chip device
US20150331438A1 (en) Complete power management system implemented in a single surface mount package
US20130277855A1 (en) High density 3d package
TWI762058B (zh) 半導體封裝件
US20120112352A1 (en) Integrated circuit system with distributed power supply
CN105489566A (zh) 半导体封装结构
US20240347443A1 (en) Over and under interconnects
CN102057481B (zh) 具有电源和接地通孔的封装
CN103620777B (zh) 关于包括多存储器裸片的半导体封装体的布置和方法
CN202394957U (zh) 半导体晶圆及封装构造
TWI747067B (zh) 晶圓級扇出特殊應用積體電路橋接記憶體堆疊
CN115223958B (zh) 具有去耦电容器的集成电路封装
KR20250071143A (ko) 스위치 셀을 포함하는 3차원 집적 회로
KR20260052041A (ko) 적층형 집적 회로 디바이스들
CN119695045A (zh) 半导体封装组件

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P11 Amendment of application requested

Free format text: ST27 STATUS EVENT CODE: A-2-2-P10-P11-NAP-X000 (AS PROVIDED BY THE NATIONAL OFFICE)

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000