KR20240106322A - Gate driver and display apparatus - Google Patents

Abstract

This specification relates to a gate driver that can improve the reliability of the gate driver and reduce power consumption by reducing leakage current. The gate driver according to some embodiments includes a plurality of stages each outputting a plurality of scan signals. Each of the plurality of stages includes an output buffer that outputs a scan signal through an output line in response to the control of the first control node and the control of the second control node, and a first control unit that controls the first control node. , and a second control unit that controls the second control node, the first control unit includes a charging unit that precharges the first control node, and a discharge unit that discharges the first control node, and the charging unit includes a third control node. a first charging transistor controlled by a first input signal to precharge the third control node before the precharging period of the first control node; It may include a boosting capacitor connected between the gate electrode and the source electrode of the charging transistor, and a discharge transistor that is controlled by the output of the output buffer to discharge the first control node to the first gate-off voltage.

Description

Gate driver and display device {GATE DRIVER AND DISPLAY APPARATUS}

This specification relates to a gate driver and display device that can improve the reliability of the gate driver by reducing leakage current and reduce power consumption.

A display device may include a display panel and a driving circuit that drives the display panel. Each subpixel of the display panel can be independently driven by a thin film transistor (TFT).

A gate driver that controls the TFT of subpixels may be placed in the bezel area of the display panel.

The TFT applied to the gate driver may deteriorate depending on the applied voltage and stress time, and when the TFT deteriorates, the threshold voltage may shift and leakage current may increase. If the TFT's leakage current increases, the output waveform of the gate driver may be distorted, which may reduce reliability and increase power consumption.

The content of the background technology described above is technical information that the inventor of this specification possessed to derive examples of this specification or acquired in the process of deriving examples of this specification, and must be disclosed to the general public before filing an application for this specification. It cannot be said to be a well-known technology.

This specification provides a gate driver and a display device that can improve the reliability of the gate driver by reducing leakage current and reduce power consumption.

The problems to be solved in the various embodiments of this specification are not limited to the problems mentioned above, and other problems not mentioned are clear to those skilled in the art from the description below. It will be understandable.

A gate driver according to some embodiments includes a plurality of stages that each output a plurality of scan signals, and each of the plurality of stages responds to the control of the first control node and the control of the second control node, so that the output line It includes an output buffer for outputting a scan signal, a first control unit for controlling the first control node, and a second control unit for controlling the second control node, wherein the first control unit includes a charging unit for precharging the first control node. , a discharge unit that discharges the first control node, and a charging unit, a first charge transistor that is controlled by a third control node to precharge the first control node, and is controlled by a first input signal of the first control node. Controlled by a second charging transistor for precharging the third control node before the precharging period, a boosting capacitor connected between the gate electrode and the source electrode of the first charging transistor, and the output of the output buffer to charge the first control node. 1 It may include a discharge transistor that discharges to a gate-off voltage.

A display device according to some embodiments includes a display panel including a display area that displays an image through subpixels and a bezel area surrounding the display area, and gate lines disposed in the bezel area and connected to the subpixels, respectively. It may include a gate driver according to some embodiments that supplies a plurality of scan signals respectively.

A display device according to some embodiments includes a display panel including a display area that displays an image through subpixels and a bezel area surrounding the display area, a first type of gate disposed in the bezel area and connected to the subpixels. A gate driver according to some embodiments that supplies a plurality of scan signals to each of the lines, and a light emission control device that supplies a light emission control signal to each of the second type gate lines disposed in the bezel area and connected to the subpixels. May include drivers.

Specific details according to various embodiments other than the means of solving the above-mentioned problems are included in the description and drawings below.

In the gate driver and the display device using the same according to some embodiments, most of the TFTs in each stage have the lower gate and source contact structures of double gate TFTs, thereby preventing leakage current and ensuring the stability of the gate signal, so the gate driver's Reliability can be improved and power consumption can be reduced.

In the gate driver and the display device using the same according to some embodiments, the pull-up TFT in each stage has the lower gate and carry contact structure of the double gate TFT, thereby preventing leakage current and ensuring the stability of the gate signal, so the gate driver Reliability can be improved and power consumption can be reduced.

A gate driver and a display device using the same according to some embodiments use a double gate TFT with a lower gate floating structure as the precharging TFT in each stage and additionally include a boosting capacitor and a TFT to strengthen the precharging role of the control node. Since the stability of the gate signal can be secured, the reliability of the gate driver can be improved.

Since the contents of the problem to be solved, the means for solving the problem, and the effects mentioned above do not specify the essential features of the claims, the scope of the claims is not limited by the matters described in the contents of the invention.

Figure 1 is a block diagram showing the configuration of a display device according to an embodiment.
Figure 2 is an equivalent circuit diagram illustrating a pixel circuit configuration of a subpixel according to an embodiment.
Figure 3 is a block diagram schematically illustrating the configuration of a scan driver according to an embodiment.
Figure 4 is a diagram illustrating a single gate TFT configuration applied to a gate driver according to an embodiment.
FIG. 5 is a diagram illustrating a first type double gate TFT configuration applied to a gate driver according to an embodiment.
FIG. 6 is a diagram illustrating a second type double gate TFT configuration applied to a gate driver according to an embodiment.
FIG. 7 is a diagram illustrating a third type double gate TFT configuration applied to a gate driver according to an embodiment.
Figure 8 is an equivalent circuit diagram illustrating the stage circuit configuration of a gate driver according to an embodiment.
FIG. 9 is a driving waveform diagram of the stage shown in FIG. 8.
Figure 10 is an equivalent circuit diagram illustrating the stage circuit configuration of a gate driver according to an embodiment.
FIG. 11 is a driving waveform diagram of the stage shown in FIG. 10.
Figure 12 is an equivalent circuit diagram illustrating the stage circuit configuration of a gate driver according to an embodiment.
Figure 13 is an equivalent circuit diagram illustrating the stage circuit configuration of a gate driver according to an embodiment.

The advantages and features of the present specification and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below and will be implemented in various different forms, but the present embodiments only serve to ensure that the disclosure of the present specification is complete, and are common knowledge in the technical field to which the present specification pertains. It is provided to fully inform those who have the scope of the invention, and this specification is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present specification are illustrative, and the present specification is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present specification, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present specification, the detailed description will be omitted. When “includes,” “has,” “consists of,” etc. mentioned in the specification are used, other parts may be added unless “only” is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When analyzing a component, the error range is interpreted to include the error range even if there is no separate explicit description of the error range.

In the case of a description of a positional relationship, for example, if the positional relationship of two parts is described as “on top,” “at the top,” “at the bottom,” “next to,” etc., for example, “right away.” Alternatively, there may be one or more other parts between the two parts, unless "directly" is used.

In the case of a description of a temporal relationship, if a temporal relationship is described with “after,” “sequently,” “next,” “before,” etc., unless “immediately” or “directly” is used, it is not continuous. Cases may also be included.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical idea of the present specification.

In describing the components of this specification, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the components are not limited by the term. When a component is described as being “connected,” “coupled,” or “connected” to another component, that component may be connected or connected to that other component directly, but indirectly, unless specifically stated otherwise. It should be understood that other components may be “interposed” between each component that is connected or capable of being connected.

“At least one” should be understood to include any combination of one or more of the associated components. For example, “at least one of the first, second, and third components” means not only the first, second, or third component, but also two of the first, second, and third components. It can be said to include a combination of all or more components.

Each feature of the various embodiments of the present specification can be combined or combined with each other, partially or entirely, and various technological interconnections and operations are possible, and each embodiment may be implemented independently of each other or together in a related relationship. It may be possible.

Hereinafter, embodiments of the present specification will be examined through the attached drawings and examples. The scale of the components shown in the drawings is different from the actual scale for convenience of explanation, and is therefore not limited to the scale shown in the drawings.

FIG. 1 is a block diagram schematically showing the configuration of a display device according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram illustrating a pixel circuit configuration of a subpixel according to an embodiment, and FIG. 3 is an embodiment. This is a block diagram schematically illustrating the configuration of a scan driver according to . 4 to 7 are diagrams illustrating single gate TFT and first to third types of double gate TFT configurations applied to a scan driver according to an embodiment.

The display device according to one embodiment includes an Organic Light Emitting Diode (OLED) display device, a Quantum-dot Light Emitting Diode display device, or an Inorganic Light Emitting Diode display device. It may be an electroluminescent display device (Electroluminescent Display).

Referring to FIG. 1, a display device according to an embodiment includes a display panel 100, a gate driver (GD) built into the display panel 100, a data driver (DD) connected to the display panel 100, and a gate driver. It may include a timing controller (TCON) that controls the (GD) and data driver (DD), a level shifter (LS) connected between the timing controller (TCON) and the gate driver (GD), etc.

The display panel 100 is a rigid display panel or a flexible display panel capable of changing shape, such as a foldable, bendable, rollable, or stretchable display panel. It may be a display panel.

The display panel 100 may include a display area DA and bezel areas BZ1 to BZ4 surrounding the display area DA and located on the outside.

The display panel 100 can display an image using a display area (DA) in which a plurality of subpixels (SP) are arranged in a matrix form. The pixel matrix disposed in the display area DA may include a plurality of row lines and a plurality of column lines composed of a plurality of subpixels SP.

In one embodiment, the display panel 100 may further include a touch sensor screen disposed in the display area DA to sense the user's touch.

Each subpixel SP may be one of a red subpixel that emits red light, a green subpixel that emits green light, a blue subpixel that emits blue light, and a white subpixel that emits white light. A unit pixel may include at least two subpixels (SP).

Each subpixel SP may include a light emitting device and a plurality of TFTs that independently drive the light emitting device. The display panel 100 includes a data line (DL) connected to each subpixel (SP), gate lines (GL1[n], GL2[n], GL3[n], n is a natural number), a power line, and other signals. A plurality of signal lines including a line may be disposed.

For example, as shown in FIG. 2, the pixel circuit of each subpixel (SP) includes a driving TFT (DT), a switching TFT (ST1), an initialization TFT (ST2), and a light emitting element that supply current to the light emitting element (ED). It may include a control TFT (ET) and storage capacitors (Cst1, Cst2). The pixel circuit of each subpixel (SP) may be driven to include an initialization period, sampling period, program period, and emission period for each frame.

In one embodiment, each subpixel (P) includes first to third gate lines (GL1, GL2, GL3), data lines (DL), and first and second power lines (PL1, PL2), and may be connected to the initialization voltage line (IL).

In one embodiment, the first gate line GL1 may receive a first scan signal SCAN1 from the scan driver SD, and the second gate line GL2 may receive a second scan signal SCAN2. there is. The third gate line GL3 may receive the emission control signal EM from the emission control driver EMD. The data line DL may receive a data voltage Vdata from the data driver DD. The first power line PL may be supplied with a first high-potential power supply voltage ELVDD, and the second power line PL2 may be supplied with a low-potential power supply voltage ELVSS from a power circuit (not shown). The initialization voltage line (IL) may be supplied with the initialization voltage (Vini) from the power circuit or the gate driver (GD).

The switching TFT (ST1) is controlled by the first gate line (GL1) and can connect the data line (DL) and the first node (N1) connected to the gate electrode (G) of the driving TFT (DT). During the initialization period, sampling period, and program period, the switching TFT (ST1) is turned on by the first scan signal (SCAN1) of the first gate line (GL1), and the reference voltage ( Vref) and data voltage (Vdata) may be sequentially supplied to the first node (N1).

The initialization TFT (ST2) is controlled by the second gate line (GL2) and has a second node (N2) commonly connected to the source electrode (S) of the driving TFT (DT) and the anode of the light emitting element (ED), and an initialization voltage. The line (IL) can be connected. During the initialization period, the initialization TFT (ST2) is turned on by the second scan signal (SCAN2) of the second gate line (GL2), and sets the initialization voltage (Vini) of the initialization voltage line (IL) to the second node (N2). ) can be supplied to.

The emission control TFT (ET) is controlled by the third gate line (GL3) and can connect the first power line (PL1) and the drain electrode (D) of the driving TFT (DT). During the emission period, the emission control TFT (ET) is turned on by the emission control signal (EM) of the third gate line (GL3) to drive the first power voltage (ELVDD) of the first power line (PL1). It can be supplied to the drain electrode (D) of (DT).

The first storage capacitor (Cst1) is connected between the first node (N1) and the second node (N2) to charge the data voltage (Vdata-Vth) for which the threshold voltage (Vth) of the driving TFT (DT) is compensated. there is. During the sampling period, the voltage of the source electrode (S) rises until the gate-source voltage (Vgs) becomes the threshold voltage (Vth) due to the source follow operation of the driving TFT (DT), thereby increasing the voltage of the first storage electrode (S). The capacitor Cst1 can charge the threshold voltage (Vth) of the driving TFT (DT).

The second storage capacitor (Cst2) is connected between the first power line 103 and the second node (N2) commonly connected to the source electrode (S) of the driving TFT (DT) and the anode of the light emitting element (ED). , the potential of the second node N2 can be stably maintained during the light emission period.

During the light emission period, the driving TFT (DT) controls the light emission intensity of the light emitting element (ED) by controlling the current (Ids) flowing into the light emitting element (ED) according to the driving voltage (Vgs) charged in the storage capacitor (Cst1). You can.

The light emitting element (ED) has an anode connected to the source electrode (S) of the driving TFT (DT), a cathode connected to a second power line (PL2) that supplies a low potential power supply voltage (ELVSS), and a space between the anode and the cathode. It may be provided with an organic light-emitting layer. The light emitting element (ED) may generate light with a brightness proportional to the current value of the driving current supplied from the driving TFT (DT).

The gate driver GD may be disposed in at least one of the plurality of bezel areas BZ1 to BZ2 located on the outside of the display area DA. For example, the gate driver GD is disposed in one of the first and second bezel areas BZ1 and BZ2 facing each other with the display area DA in between, or in the first and second bezel areas BZ1 and BZ2. BZ2) Can be placed on both sides. The gate driver (GD) may be disposed as a GIP (Gate In Panel) type composed of TFTs formed in the same process as the TFTs disposed in the display area (DA).

The gate driver (GD) operates a plurality of gate lines (GL1[n], GL2[n]) among the gate lines (GL1[n] to GL3[n]) connected to the subpixels (P) of each pixel row line. ) and an emission control driver (EMD) that drives at least one gate line (GL3[n]).

The number of gate lines (GL1[n] ~ GL3[n]) connected to the subpixels (SP) of each row line, the number of scan drivers (SD), and the number of emission control drivers (EMD) are It is not limited to what is shown in FIG. 1 and may vary depending on the detailed configuration of the pixel circuit constituting each subpixel SP.

Each of the scan driver (SD) and the emission control driver (EMD) may operate by receiving a plurality of gate control signals supplied from the timing controller (TCON) through the level shifter (LS). In one embodiment, each of the scan driver (SD) and the emission control driver (EMD) may receive a plurality of gate control signals from the timing controller (TCON).

The level shifter (LS) can generate a plurality of gate control signals by receiving control signals from the timing controller (TCON) and level shifting or logic processing them, and supply them to the scan driver (SD) and the emission control driver (EMD).

The scan driver (SD) performs a shift operation of the shift register using a plurality of gate control signals supplied from the level shifter (LS), thereby shifting the gate lines (GL1[n], GL2[n]) arranged for each row line. Scan signals can be supplied to.

Referring to FIG. 3, in one embodiment, the scan driver (SD) includes a plurality of stages (??, ST(N-1), ST(N), ST(N+1) that sequentially drive a plurality of gate lines. , ??).

In Figure 3, among the stages of the scan driver (SD), there are three stages (GOUT(N-1), GOUT(N), GOUT(N+1), each of which generates three outputs (N is a positive integer). Only ST(N-1), ST(N), and ST(N+1)) are shown schematically. Each stage (ST(N)) receives at least one clock signal from a plurality of clock signals (CLKs) with different phases, and outputs an input clock pulse in response to either the start signal or the output of another stage. It can be output as a scan signal (GOUT(N)). The output (GOUT(N)) of each stage (ST(N)) can be transmitted as a carry signal to other stages.

The emission control driver (EMD) may supply an emission control signal to at least one gate line (GL3[n]) arranged for each row line using a plurality of gate control signals supplied from the level shifter (LS). The emission control driver (EMD) may include a plurality of emission control stages that each supply emission control signals to a plurality of gate lines.

The data driver DD may convert digital data supplied along with data control signals from the timing controller TCON into analog data signals and supply each data voltage to each data line DL of the display panel 100. The data driver DD may convert digital data into an analog data voltage using grayscale voltages divided by a plurality of reference gamma voltages supplied from a gamma voltage generator (not shown).

The data driver DD may include at least one data drive integrated circuit (IC) (DIC) that drives a plurality of data lines DL disposed on the display panel 100. Each data drive IC (DIC) may be individually mounted on each circuit film (COF). The circuit film (COF) on which the data drive IC (DIC) is mounted may be bonded to the bezel area (BZ3) where the pad area of the display panel 100 is disposed through an anisotropic conductive film (ACF). The circuit film (COF) may be Chip On Film (COF). In addition to COF, Flexible Printed Circuit (FPC) or Flexible Flat Cable (FFC) may be used.

The timing controller (TCON) can control the gate driver (GD) and data driver (DD) using timing control signals supplied from the host system and internally stored timing setting information.

The timing controller (TCON) generates control signals for timing control so that the level shifter (LS) can generate a plurality of gate control signals that control the driving timing of the gate driver (GD) and supply them to the gate driver (GD). This can be supplied to the level shifter (LS). In one embodiment, the timing controller (TCON) may generate a plurality of gate control signals and supply them to the gate driver (GD).

The timing controller (TCON) may generate a plurality of data control signals that control the driving timing of the data driver (DD) and supply them to the data driver (DD). The controller (TCON) according to one embodiment can receive input image data and perform various image processing including image quality correction, deterioration correction, and luminance correction to reduce power consumption, and send the image processed data to a data driver ( DD) can be supplied.

A plurality of TFTs disposed in the display area (DA) of the display panel 100 and the bezel area (BZ1 to BZ4) including the gate driver (GD) include an amorphous TFT using an amorphous silicon semiconductor layer and a polysilicon semiconductor layer. It may include at least one of poly TFT and oxide TFT using a metal oxide semiconductor layer.

For example, oxide TFT, which has higher mobility than amorphous silicon TFT, can be processed at lower temperatures than poly-silicon TFT, and is easier to apply to large areas, can be applied to the display panel 100, and Coplanar, which has good TFT characteristics, can be applied to the display panel 100. ) type oxide TFT can be applied.

In one embodiment, a gate driver (GD) using an oxide TFT, that is, a scan driver (SD) and an emission control driver (EMD), uses at least one of the double gate TFTs (MT1, MT2, and MT3) shown in FIGS. 5 to 7. It can contain one.

Figure 4 illustrates a single gate TFT (MT). The double gate TFTs (MT1, MT2, MT3) shown in FIGS. 5 to 7 have a gate electrode (G) disposed on the semiconductor layer (ACT) as the upper gate electrode, and a light blocking electrode disposed under the semiconductor layer (ACT). The layer LS can be used as a lower gate electrode.

The double gate TFT (MT1) shown in FIG. 5 may have a bottom gate floating structure in which the light blocking layer (LS) is in a floating state. In one embodiment, the double gate TFT (MT1) may have a gate contact structure in which the light blocking layer (LS) is connected to the upper gate electrode (G).

The double gate TFT (MT2) shown in FIG. 6 may have a lower gate and source contact structure in which the light blocking layer (LS) is connected to the source electrode (S).

The double gate TFT (MT3) shown in FIG. 7 may have a lower gate and carry contact structure in which the light blocking layer (LS) is connected to the carry terminal (CR).

When the n-channel type oxide TFT is turned on by the gate-on voltage (Von), positive bias temperature stress (PBTS) can be applied by the positive driving voltage (Vgs), and the high drain current High Drain Current Stress (HDCS) can be applied by (High Drain Current). When the n-channel type oxide TFT is turned off by the gate-off voltage (Voff), negative bias temperature-illumination stress (NBTiS: Negative Bias Temperature Illumination Stress) can be applied by the negative driving voltage (Vgs).

The single gate TFT (MT) shown in FIG. 4 and the double gate TFT (MT1) with the lower gate floating structure shown in FIG. 5 have characteristics in which the initial threshold voltage (Vth) is shifted in the negative direction, and HDCS and NBTiS Due to poor characteristics, leakage current may occur.

The double gate TFT (MT2) with the lower gate and source contact structure shown in FIG. 6 and the double gate TFT (MT3) with the lower gate and carry contact structure shown in FIG. 7 have positive initial threshold voltage (Vth). Due to the good direction shift characteristics and HDCS and NBTiS characteristics, a positive shift of the threshold voltage (Vth) is possible, preventing leakage current and improving TFT device reliability.

Most TFTs in the gate driver (GD) according to an embodiment have the lower gate and source contact structures of the double gate TFT (MT2) shown in FIG. 6, thereby preventing leakage current and ensuring the stability of the gate signal. The reliability of the gate driver (GD) can be improved and power consumption can be reduced.

When using two gate-off voltages in the gate driver (GD) according to one embodiment, applying the lower gate and source contact structure of the double gate TFT (MT2) shown in FIG. 6 to the pull-up transistor that outputs the scan signal , the same voltage is applied to the lower gate and source electrodes, so leakage current may occur in the off section of the pull-up transistor. To prevent this, the pull-up transistor may have the bottom gate and carry contact structures of the double gate TFT (MT3) shown in FIG. 7. In this case, the lower gate voltage connected to the carry output becomes lower than the source electrode voltage in the off section of the pull-up transistor, thereby preventing leakage current and securing the stability of the gate signal, thereby improving the reliability of the gate driver (GD). and power consumption can be reduced. A detailed explanation of this will be provided later.

The charging TFT that precharges the node (Q) that controls the pull-up transistor in the gate driver (GD) according to one embodiment has a source electrode and a drain electrode that change depending on the current direction, so the lower gate shown in FIG. 6 and the double gate TFT (MT2) of the source contact structure is not applied. Instead, in one embodiment, the charging TFT of the Q node may use a double gate TFT (MT1) with a bottom gate floating structure shown in FIG. 5. Additionally, the gate driver (GD) according to one embodiment can secure the stability of the gate signal by strengthening the precharging of the Q node by additionally including a boosting capacitor and a TFT connected to the charging TFT of the Q node, so that the gate driver (GD) reliability can be improved. A detailed explanation of this will be provided later.

Referring to Figures 4 to 7, each of the oxide TFTs (MT, MT1 to MT3) includes a buffer film (BF) on a substrate (SUB), a semiconductor layer (ACT) on the buffer film (BF), and a semiconductor layer (ACT). A gate insulating layer (GI) and a gate electrode (G) stacked on top of each other, an interlayer insulating layer (ILD) covering the gate electrode (G), and a contact between the insulating layers (ILD, GI) disposed on the interlayer insulating layer (ILD). A passivation layer ( PAS) may be included.

The substrate (SUB) may be a glass substrate or a plastic substrate using polymer resin. The plastic substrate may include at least one of polyimide (PI), polycarbonate (PC), polyethylene (PE), polyester, polyethylene terephthalate (PET), and polystyrene (PS), which has flexible properties.

The light blocking layer (LS) on the substrate (SUB) includes an opaque metal material and blocks (absorbs) external light to prevent light from entering the channel region (CH) of the semiconductor layer (ACT).

The buffer layer ( _BF ) covering the light blocking layer (LS) on the substrate (SUB) _is a single layer or It may have a multi-layer structure. The buffer layer (BF) can prevent impurities such as hydrogen from flowing into the semiconductor layer (ACT) through the substrate (SUB).

The semiconductor layer (ACT) on the buffer layer (BF) may include an oxide semiconductor material. For example, the semiconductor layer (ACT) is ZO (ZnO)-based, IZO-based (InZnO)-based, IGZO (InGaZnO)-based, TO (SnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZTO (InGaZnSnO)-based )-based, GZTO (GaZnSnO)-based, GZO (GaZnO)-based, GO (GaO)-based, IO (InO)-based, ITZO (InSnZnO)-based, FIZO (FeInZnO)-based, and TO (SnO)-based oxide semiconductor materials. may include. The active layer (ACT) may have a single-layer structure or a multi-layer structure including two or more oxide semiconductor layers.

The gate insulating layer (GI) on the semiconductor layer (ACT) may have a single-layer or multi-layer structure including at least one inorganic insulating material of silicon oxide (SiOx) and silicon nitride (SiNx). The gate insulating layer GI may be disposed only between the gate electrode G and the semiconductor layer ACT, or may be disposed on the buffer layer BF to cover the semiconductor layer ACT.

The gate electrode (G) on the gate insulating layer (GI) includes a metal material and may overlap the channel region of the semiconductor layer (ACT).

The interlayer insulating layer (ILD) covering the gate electrode (G) may have a single-layer or multi-layer structure including at least one inorganic insulating material of silicon oxide (SiOx) and silicon nitride (SiNx).

The source electrode (S) and the drain electrode (D) on the interlayer insulating layer (ILD) include a metal material, and the interlayer insulating layer (ILD) and the gate insulating layer (GI) or the first electrode penetrating the interlayer insulating layer (ILD) and the second contact holes H1 and H2, respectively, to the conductive region of the semiconductor layer ACT.

The light blocking layer LS of the TFT MT2 shown in FIG. 6 is connected to the source electrode S through the third contact hole H3 penetrating the plurality of insulating layers BF, GI, and ILD. It may have a gate and source contact structure.

The light blocking layer LS of the TFT MT3 shown in FIG. 7 is connected to the carry terminal CR through the third contact hole H3 penetrating the plurality of insulating layers BF, GI, and ILD. It may have a gate and carry contact structure.

The passivation layer (PAS) covering the source and drain electrodes (D) on the interlayer dielectric layer (ILD) includes at least one inorganic insulating material of silicon oxide (SiOx) and silicon nitride (SiNx) or an organic insulating material. It may have a single-layer or multi-layer structure.

FIG. 8 is an equivalent circuit diagram illustrating the stage circuit configuration of a gate driver according to an embodiment, and FIG. 9 is a driving waveform diagram of the stage shown in FIG. 8.

Referring to FIG. 8, in the gate driver according to one embodiment, each stage (ST(N), N is a natural number) includes a first input line 21, a second input line 26, and a third input line 32. ), clock line 28, first power line 34, second power line 36, and output line 30.

A gate driver according to one embodiment may be expressed as a scan driver.

The first input line 21 of each stage (ST(N)) receives the output (Gout(N-2)) of the N-2th stage (previous stage) as the first input signal, and the second input line ( 26) can receive the output (Gout(N-1)) of the N-1th stage (previous stage) as a second input signal. When each stage (ST(N)) is the first or second stage, the first input line 21 receives the first start signal as the first input signal, and the second input line 26 receives the second start signal. It can be supplied as a second input signal.

The third input line 32 of each stage (ST(N)) can receive the output (Gout(N+2)) of the N+2th stage (post-stage) as a third input signal. When each stage (ST(N)) is the last or (last-1) stage, the third input line 32 can receive a reset signal as the third input signal.

The clock line 28 of each stage (ST(N)) may be supplied with a clock signal (CLK(N)). The clock signal CLK(N) may be one of a plurality of clock signals with different phases. Each clock signal (CLK(N)) may be supplied in the form of a pulse in which the on level (Von) of a specific horizontal period and the off level (Voff) of a specific horizontal period alternate as shown in FIG. 9. The off level (Voff) of each clock signal (CLK(N)) may be expressed as a low level or a first level and may be the same voltage level as the second low-potential power supply voltage (VSS). The on level (Von) of each clock signal (CLK(N)) may be expressed as a high level or a second level.

The first power line 34 of each stage (ST(N)) may be supplied with a first low-potential power supply voltage (VSS), and the second power line 36 may be supplied with a second low-potential power supply voltage (VGL). can be supplied. The first low potential power supply voltage (VSS) may be expressed as a first gate low voltage or a first gate off voltage. The second low-potential power supply voltage (VGL) may be expressed as a second gate low voltage or a second gate-off voltage. The first low-potential power supply voltage (VSS) may be lower than the second low-potential power supply voltage (VSS) (VSS<VGL).

Each stage (ST(N)) has an output buffer unit 108 that outputs a scan signal (Gout(N)), and a first node charging unit (Q2) that controls the first node (Q2 node) of the output buffer unit 108. A first node control unit (Q2 control unit) including a charging unit (102) and a first node discharge unit (Q2 discharge unit (104)), and a second node control unit that controls the QB node (second node) of the output buffer unit (108). (QB control unit, 106). The first and second node control units may be expressed as a control unit.

The Q2 charging unit 102 includes a first charging transistor (T1) that charges the first node (Q2), and a second charging transistor (T1A) that controls the third node (Q1 node) connected to the first charging transistor (T1). and a discharge transistor (T1B) and a boosting capacitor (C1) connected between the gate electrode and the source electrode of the first charge transistor (T1).

The first charging transistor T1 may have a gate electrode connected to the Q1 node, a source electrode connected to the Q2 node, and a drain electrode connected to the second input line 26. The second charging transistor T1A may have a gate electrode and a drain electrode connected to the first input line 22 in a diode structure, and a source electrode may be connected to the Q1 node. The first discharge transistor T1B may have a gate electrode connected to the output line 30, a source electrode connected to the first power line 34, and a drain electrode connected to the Q1 node.

The Q2 discharge unit 104 may include a discharge transistor T3 that discharges the Q2 node. The discharge transistor T3 may have a gate electrode connected to the third input line 32, a source electrode connected to the first power line 34, and a drain electrode connected to the Q2 node.

The QB control unit 106 may include a discharge transistor T5 that discharges the QB node. The discharge transistor T5 may have a gate electrode connected to the Q2 node, a source electrode connected to the first power line 34, and a drain electrode connected to the QB node.

The output buffer 108 is connected between the pull-up transistor (T6) and the pull-down transistor (T7) that output the scan output (Goun(N)), and the gate electrode and source electrode of the pull-up transistor (T6). may include a boosting capacitor (CB). The pull-up transistor T6 may have a gate electrode connected to the Q2 node, a source electrode connected to the output line 30, and a drain electrode connected to the clock line 28. The pull-down transistor T7 may have a gate electrode connected to the QB node, a source electrode connected to the second power line 36, and a drain electrode connected to the output line 30.

In the first period (t1), the second charge transistor (T1A) precharges the Q1 node by the on level (Von) of the output (Gout (N-2)) of the N-2th stage, so that the first charge transistor ( T1) can be turned on.

In the second period (t2), the second charge transistor (T1A) is turned off by the off level (Voff) of the output (Gout (N-2)) of the N-2th stage, and the first charge transistor (T1) ) can be maintained in the turn-on state. The first charge transistor (T1) turns on the pull-up transistor (T6) by precharging the Q2 node using the on level (Von) of the output (Gout (N-1)) of the N-1th stage. You can. At this time, the on level (Von) of the Q1 node is boosted by the coupling of the boosting capacitor (C1), thereby enhancing precharging of the Q2 node through the first charge transistor (T1). The discharge transistor (T5) of the QB control unit 106 is turned on by the on level (Von) of the Q2 node to discharge the QB node to an off level using the first low-potential power supply voltage (VSS), thereby discharging the pull-down transistor ( T7) can be turned off.

In the third period (t3), the first charge transistor (T1) is turned off to float the Q2 node at the on level (Von) and maintain the pull-up transistor (T6) in the turned-on state. . The pull-up transistor T6 can output the on level (Von) of the scan output (Gout(N)) using the on level (Von) of the clock signal (CLK(N)). At this time, the on level (Von) of the Q2 node is boosted by the coupling of the boosting capacitor (CB), thereby reducing the rising time of the scan output (Gout (N)) through the pull-up transistor (T6). The discharge transistor (T1B) is turned on by the on level (Von) of the scan output (Gout (N)), discharging the Q1 node to the off level (Voff) using the second low-potential power supply voltage (VSS), thereby discharging the first The charging transistor T1 can be stably turned off and leakage current of the first charging transistor T1 can be prevented.

In the fourth period after the third period t3, the pull-up transistor T6 uses the off level Voff of the clock signal CLK(N) to set the off level of the scan output Gout(N) ( Voff) can be output. In the fifth period after the fourth period, the discharge transistor T3 of the Q2 discharge unit 104 is turned on by the on level (Von) of the output (Gout (N+2)) of the N+2th stage. The Q2 node can be discharged to an off level (Voff) using the second low-potential power supply voltage (VSS).

Referring to FIG. 8, in the stage ST(N) according to an embodiment, the Q2 discharge unit 104 and the QB control unit 106, excluding the transistors T1, T1A, and T1B of the Q2 charging unit 102. and the transistors (T3, T5, T6, T7) of the output buffer 108 all have the lower gate and source contact structures of the double gate TFT (MT2) shown in FIG. 6 as described above, thereby reducing leakage current. It can be prevented.

The transistors (T1, T1A, T1B) of the Q2 charging unit 102 apply the double gate TFT (MT1) of the lower gate floating structure shown in FIG. 5 as described above, but the boosting capacitor (C1) and the charging transistor ( By boosting the Q1 node using T1A), the precharging of the Q2 node can be strengthened and leakage current can be prevented to ensure the stability of the scan output.

Accordingly, the gate driver according to one embodiment can improve reliability and reduce power consumption by preventing leakage current and ensuring stability of scan output.

FIG. 10 is an equivalent circuit diagram illustrating the stage circuit configuration of a gate driver according to an embodiment, and FIG. 11 is a driving waveform diagram of the stage shown in FIG. 10.

Compared to the stage (ST(N)) shown in FIG. 8, the stage (ST(N)) shown in FIG. 10 changes the signals supplied to the Q2 charging unit 112 to reduce the rising and polling times of the Q1 node. The output buffer 118 may further include a carry pull-up transistor (T6c) and a carry pull-down transistor (T7c) for carry output (CRY(N)) to provide scan output (Gout(N)) and The rising and falling times of the carry output (CRY(N)) can be reduced. In FIG. 10 , descriptions of components overlapping with those of FIG. 8 may be omitted or simply mentioned.

Referring to FIG. 10, the first input line 23 of each stage (ST(N)) receives the carry output (CRY(N-2)) of the N-2th stage as the first input signal, and the second input line 23 receives the carry output (CRY(N-2)) of the N-2th stage as the first input signal. The input line 27 can receive the carry output (CRY(N-1)) of the N-1th stage as a second input signal. The third input line 32 can receive the carry output (CRY(N+2)) of the N+2th stage as a third input signal.

The clock line 28 of each stage (ST(N)) can receive a clock signal (CLK(N)), and the carry clock line 35 can receive a carry clock signal (CRCLK(N)). . The clock signal CLK(N) may be one of a plurality of clock signals having different phases, and the carry clock signal CRCLK(N) may be one of a plurality of carry clock signals having different phases. The clock signal (CLK(N)) and carry clock signal (CRCLK(N)) have a pulse form in which the on level (Von) of a specific horizontal period and the off level (Voff, Voff') of a specific horizontal period alternate as shown in FIG. 11. can be supplied. The off level (Voff') of the carry clock signal (CRCLK(N)) may be lower than the off level (Voff) of the clock signal (CLK(N)).

The first power line 34 of each stage (ST(N)) may be supplied with a first low-potential power supply voltage (VSS), and the second power line 36 may be supplied with a second low-potential power supply voltage (VGL). can be supplied, and the third power line 25 can be supplied with a high potential power supply voltage (VDD). The high potential supply voltage (VDD) can be expressed as a gate high voltage or gate on voltage.

Referring to FIG. 10, in each stage (ST(N)), the Q2 charging unit 112 includes a charging transistor (T1) and a boosting capacitor (CQ1) connected to the Q2 node, and charging and discharging transistors (T1A) connected to the Q1 node. , T1B). The Q2 discharge unit 114 may include a discharge transistor T3 connected to the Q2 node. The QB control unit 116 may include a discharge transistor T5 connected to the QB node. The output buffer unit 118 includes a pull-up transistor (T6) and a pull-down transistor (T7) connected to the output line 30, a carry pull-up transistor (T6c) connected to the carry output line 40, and It may include a carry pull-down transistor (T7c). The output buffer unit 118 may include a boosting capacitor (CB) connected between the gate electrode and the source electrode of the pull-up transistor (T6). The output buffer unit 118 may include a carry boosting capacitor (CQ) connected between the gate electrode and the source electrode of the carry pull-up transistor (T6c) or may omit it.

10 and 11, the second charge transistor T1A is turned on by the carry output (CRY(N-2)) of the N-2th stage, and the Q1 node is connected to the high potential power supply voltage (VDD). Precharging can be done with on level (Von) using . During the period (t2) during which the first charge transistor (T1) precharges the Q2 node to the on level (Von) using the on level (Von) of the carry output (CRY(N-1)) of the N-1th stage. , the on level (Von) of the Q1 node is boosted by the coupling of the boosting capacitor (CQ1), thereby enhancing precharging of the Q2 node through the first charge transistor (T1).

During the period (t3) during which the Q2 node is activated in a floating state after precharging, the pull-up transistor (T6) uses the on level (Von) of the clock signal (CLK(N)) to produce scan output (Gout(N)). The on level (Von) can be output, and the carry pull-up transistor (T6c) uses the on level (Von) of the carry clock signal (CRCLK(N)) to output the on level of the carry output (CRY(N)). (Von) can be output. At this time, the on level (Von) of the Q2 node is boosted by the coupling of the boosting capacitors (CB, CQ), thereby increasing the scan output (Gout (N)) through the pull-up transistor (T6) and the carry pull-up transistor (T6c). ) and the rising time of the carry output (CRY(N)) can be reduced. The discharge transistor (T1B) is turned on by the on level (Von) of the carry output (CRY(N)), discharging the Q1 node to the off level (Voff) using the second low-potential power supply voltage (VSS), thereby discharging the first The charging transistor T1 can be stably turned off and leakage current of the first charging transistor T1 can be prevented.

While the Q2 node remains activated in the floating state after the t3 period, the pull-up transistor (T6) uses the off level (Voff) of the clock signal (CLK(N)) to output the scan output (Gout (N)). The off level (Voff) can be output, and the carry pull-up transistor (T6c) uses the off level (Voff') of the carry clock signal (CRCLK(N)) to level the carry output (CRout(N)). (Voff') can be output. While the discharge transistor (T3) of the Q2 discharge unit 114 is turned on by the carry output (CRout(N+2)) of the N+2th stage, the Q2 node is applied to the second low-potential power supply voltage (VSS). It can be used to discharge to an off level (Voff).

Referring to FIG. 10, in the stage ST(N) according to an embodiment, the Q2 discharge unit ( 114) and the transistors (T3, T5, T6c, T7, T7c) of the QB control unit 116 and the output buffer 118 are all, as described above, the lower gate and the lower gate of the double gate TFT (MT2) shown in FIG. By having a source contact structure, leakage current can be prevented.

As described above, the pull-up transistor T6 can prevent leakage current by having the bottom gate and carry contact structure of the double gate TFT MT3 shown in FIG. 7. The light blocking layer of the pull-up transistor T6 is connected to the carry output line 40 to receive the carry output CRY(N).

The transistors (T1, T1A, T1B) of the Q2 charging unit 112 apply the double gate TFT (MT1) of the lower gate floating structure shown in FIG. 5 as described above, but the boosting capacitor (C1) and the charging transistor ( By boosting the Q1 node using T1A), the precharging of the Q2 node can be strengthened and leakage current can be prevented to ensure the stability of the scan output.

Accordingly, the gate driver according to one embodiment can improve reliability and reduce power consumption by preventing leakage current and ensuring stability of scan output.

Figure 12 is an equivalent circuit diagram illustrating the stage circuit configuration of a gate driver according to an embodiment.

Compared to the stage ST(N) shown in FIG. 11, the stage ST(N) shown in FIG. 12 is located between the second input line 27 and the charging transistor T1 in the Q2 charging unit 122. By additionally including the added charge transistor T1C and an offset transistor T3q connected to an intermediate node between the charge transistors T1C and T1, leakage current of the charge transistor T1 can be further prevented. In FIG. 12, descriptions of components overlapping with those of FIG. 11 will be omitted or briefly mentioned. The stage ST(N) shown in FIG. 12 can be driven by the driving waveform shown in FIG. 11.

Referring to FIG. 12, between the second input line 27 to which the carry output (CRY(N-1)) of the N-1th stage is supplied from the Q2 charging unit 122 of each stage (ST(N)) and the Q2 node. The charging transistor pair (T1C, T1) may be connected in series and is controlled by the Q1 node to be turned on during the precharging and boosting period (t1, t2). You can.

The offset transistor (T3q) is turned on during the period (t2, t3) when the Q2 node is active for precharging and boosting, thereby offseting the high-potential supply voltage (VDD) to the intermediate node between the pair of charging transistors (T1C, T1). It can be supplied by voltage. Accordingly, during the period (t1, t2) when the Q2 node is activated, leakage current through the turned-off charging transistor pair (T1, T1C) can be further prevented.

Referring to FIG. 12, in the stage (ST(N)) according to an embodiment, the Q2 room except the transistors (T1, T1A, T1B, T1C) and the pull-up transistor (T6) of the Q2 charging unit 122. The transistors (T3, T5, T6c, T7, T7c) and the offset transistor (T3q) of the front 114 and the QB control unit 116 and the output buffer 118 are all double gates shown in FIG. 6 as described above. By having a lower gate and source contact structure of the TFT (MT2), leakage current can be prevented.

As described above, the pull-up transistor T6 can prevent leakage current by having the bottom gate and carry contact structure of the double gate TFT MT3 shown in FIG. 7.

The transistors (T1, T1A, T1B, and T1C) of the Q2 charging unit 122 apply the double gate TFT (MT1) of the lower gate floating structure shown in FIG. 5 as described above, but the boosting capacitor (C1) and the charging By boosting the Q1 node using a transistor (T1A), precharging of the Q2 node can be strengthened and leakage current can be prevented to ensure the stability of the scan output.

Accordingly, the gate driver according to one embodiment can improve reliability and reduce power consumption by preventing leakage current and ensuring stability of scan output.

Figure 13 is an equivalent circuit diagram illustrating the stage circuit configuration of a gate driver according to an embodiment.

Compared to the stage ST(N) shown in FIG. 12, the stage ST(N) shown in FIG. 13 is located between the discharge transistor T3 and the first power line 34 in the Q2 discharge unit 134. It further includes an inverter 136 including a discharge transistor (T3C) added, a pair of discharge transistors (T3A, T3B) added between the Q2 node and the first power line 34, and a discharge transistor (T5). As a result, the Q2 node and QB node can be driven more stably. In FIG. 13, descriptions of components overlapping with those of FIG. 12 will be omitted or briefly mentioned. The stage ST(N) shown in FIG. 13 can be driven by the driving waveform shown in FIG. 11.

Referring to FIG. 13, a first pair of discharge transistors (T3, T3C) may be connected in series between the Q2 node and the first power line 34 in the Q2 discharge unit 134 of each stage (ST(N)). there is. The first discharge transistor pair (T3, T3C) is controlled by the N+2th carry output (CRY(N+2)) of the third input line 32 to set the Q2 node to the first low-potential power supply voltage (VSS). It can be used to discharge to an off level (Voff).

The second discharge transistor pair (T3A, T3B) connected in series between the Q2 node and the first power line 34 in the Q2 discharge unit 134 may be connected in parallel with the first discharge transistor pair (T3, T3C). . The second discharge transistor pair (T3A, T3B) is controlled by the QB node to discharge the Q2 node to the off level (Voff) using the first low-potential power supply voltage (VSS) while the QB node is activated.

The intermediate node (N2) between the first discharge transistor pair (T3, T3C) and the intermediate node (N2) between the two discharge transistor pairs (T3A, T3B) are at high potential while the Q2 node is activated through the offset transistor (T3q). The power supply voltage (VDD) can be supplied as an offset voltage. Accordingly, leakage current through the first discharge transistor pair (T3, T3C) and the second discharge transistor pair (T3A, T3B) can be prevented.

The inverter 136 can control the QB node in contrast to the Q2 node. Inverter 136 may deactivate the QB node when the Q2 node is activated and activate the QB node when the Q2 node is deactivated.

The inverter 136 includes first to third transistors (T4A, T4B, T4C) that charge and discharge the QB node in response to the control of the Q2 node, and a fourth transistor (T4A, T4B, T4C) that discharges the QB node in response to the control of the Q2 node. T5), and may further include a capacitor C connected between the gate electrode and the source electrode of the transistor T4A. The inverter 136 may further include a fifth transistor 5A that discharges the QB node in response to the N-2th carry output (CRY(N-2)) supplied to the first input line 23.

The second transistor T4B of the inverter 136 is connected to the third power line 25 in a diode structure and can supply a high potential power supply voltage VDD to the intermediate node N3. The third transistor (T4C) of the inverter 136 responds to the control of the Q2 node, and while the Q2 node is activated, the intermediate node (N3) is connected to the fourth power line 42 to which the third low-potential power voltage (VSS1) is supplied. ) can be connected. The first transistor T4A of the inverter 136 may charge the QB node using the high potential power supply voltage VDD while the intermediate node N3 is activated. The fourth transistor T5 of the inverter 136 may discharge the QB node using the first low-potential power supply voltage VSS in response to the control of the Q2 node. The inverter 136 may discharge the QB node using the first low-potential power supply voltage (VSS) in response to the N-2th carry output (CRY(N-2)) of the fifth transistor (5A).

Referring to FIG. 13, in the stage (ST(N)) according to an embodiment, the Q2 room excluding the transistors (T1, T1A, T1B, T1C) of the Q2 charging unit 132 and the pull-up transistor (T6). The transistors (T3, T3C, T3A, T3B, T4A, T4B, T4C, T5, T5A, T6c, T7, T7c) and the offset transistor (T3q) of the front 134, inverter 136, and output buffer 138 are In all, as described above, by having the lower gate and source contact structures of the double gate TFT (MT2) shown in FIG. 6, leakage current can be prevented.

As described above, the pull-up transistor T6 can prevent leakage current by having the bottom gate and carry contact structure of the double gate TFT MT3 shown in FIG. 7.

The transistors (T1, T1A, T1B, and T1C) of the Q2 charging unit 132 apply the double gate TFT (MT1) of the lower gate floating structure shown in FIG. 5 as described above, but the boosting capacitor (C1) and the charging By boosting the Q1 node using a transistor (T1A), precharging of the Q2 node can be strengthened and leakage current can be prevented to ensure the stability of the scan output.

Accordingly, the gate driver according to one embodiment can improve reliability and reduce power consumption by preventing leakage current and ensuring stability of scan output.

As described above, the gate driver according to some embodiments includes a plurality of stages that each output a plurality of scan signals, and each of the plurality of stages is controlled by the first control node and the second control node. In response, it includes an output buffer for outputting a scan signal through an output line, a first control unit for controlling the first control node, and a second control unit for controlling the second control node, wherein the first control unit controls the first control node. It includes a charging unit for precharging and a discharging unit for discharging the first control node, wherein the charging unit is controlled by a first charging transistor controlled by a third control node to precharge the first control node, and is controlled by a first input signal. It is controlled by a second charging transistor for precharging the third control node before the precharging period of the first control node, a boosting capacitor connected between the gate electrode and the source electrode of the first charging transistor, and the output of the output buffer. 1 may include a discharge transistor that discharges the control node to a first gate-off voltage.

In a gate driver according to some embodiments, the output buffer is controlled by a first control node, and includes a first pull-up transistor that outputs a clock signal supplied to the clock line as a scan signal of the output line, and a first control node It may include a first pull-down transistor that is controlled by a second control node that performs an opposite operation to discharge the output line to a second gate-off voltage.

In a gate driver according to some embodiments, the first charge transistor is configured to charge the first control node using the scan output of the first front-end stage during a period when the third control node is boosted by the boosting capacitor and the scan output of the first front-end stage. Precharging, the second charge transistor is controlled by the scan output of the second front stage supplied as the first input signal, and precharges the third control node using the scan output of the second front stage, and the discharge transistor is controlled by the scan output of the output buffer to discharge the first control node to the first gate-off voltage.

In the gate driver according to some embodiments, each of the transistors constituting the charging part of the first control unit is a first double gate type transistor having a structure in which the first lower gate electrode is floating, and the output buffer and the room of the first control unit are All and each of the transistors constituting the second control unit may be a second double gate type transistor having a lower gate and source contact structure in which the second lower gate electrode and the second source electrode are in contact.

In a gate driver according to some embodiments, the output buffer is controlled by a first control node, a second pull-up transistor to output the carry clock signal supplied to the carry clock line as a carry signal of the carry output line, and a second pull-up transistor It may further include a second pull-down transistor controlled by the control node to discharge the carry output line to the first gate-off voltage.

In a gate driver according to some embodiments, the first charge transistor is configured to charge the first control node using the carry output of the first front-end stage during a period when the third control node is boosted by the boosting capacitor and the carry output of the first front-end stage. The second charge transistor is controlled by the carry output of the second front stage supplied with the first input signal to precharge the third control node using the gate-on voltage, and the discharge transistor is controlled by the carry output of the second front stage supplied with the first input signal. Controlled by the carry output, the first control node can be discharged to the first gate-off voltage.

In the gate driver according to some embodiments, the charging part of the first control unit is controlled by a third control node, and the third input line connected between the first charging transistor and the second input line to which the carry output of the first front stage is supplied. A charging transistor may additionally be included.

In the gate driver according to some embodiments, the first control unit is controlled by the first control node and may further include an offset transistor that supplies an offset voltage to an intermediate node between the third charging transistor and the first charging transistor. .

In a gate driver according to some embodiments, the discharge unit of the first control unit is controlled by the scan output of the rear stage and may include a first discharge transistor that discharges the first control node to a first gate-off voltage.

In the gate driver according to some embodiments, the discharge unit of the first control unit is controlled by the scan output of the rear stage, and the first control node is connected in series between the first control node and the first power line to which the first gate-off voltage is supplied. and a second discharge transistor, and third and fourth discharge transistors controlled by the second control node and connected in series between the first control node and the first power line, and between the first and second discharge transistors. The intermediate node of and the intermediate node between the third and fourth discharge transistors may receive an offset voltage from the offset transistor.

In a gate driver according to some embodiments, the second control unit is controlled by control of the first control node, deactivates the second control node when the first control node is activated, and deactivates the second control node when the first control node is deactivated. It may include an inverter that activates the control node.

In the gate driver according to some embodiments, the second control unit is controlled by the carry output of the front stage and may further include a discharge transistor that discharges the second control node to the first gate-off voltage.

In the gate driver according to some embodiments, each of the transistors constituting the charging part of the first control unit is a first double gate type transistor having a structure in which the first lower gate electrode is floating, and excluding the first pull-up transistor Each of the transistors constituting the output buffer, the discharge unit of the first control unit, and the second control unit is a second double gate type transistor having a lower gate and source contact structure in which the second lower gate electrode and the second source electrode are in contact. , and the first pull-up transistor may be a third double gate type transistor having a structure in which the third lower gate electrode and the carry output line are in contact.

A display device according to some embodiments includes a display panel including a display area that displays an image through subpixels and a bezel area surrounding the display area, and gate lines disposed in the bezel area and connected to the subpixels, respectively. It may include a gate driver according to some embodiments that supplies a plurality of scan signals respectively.

A display device according to some embodiments includes a display panel including a display area that displays an image through subpixels and a bezel area surrounding the display area, a first type of gate disposed in the bezel area and connected to the subpixels. A gate driver according to some embodiments that supplies a plurality of scan signals to each of the lines, and a light emission control device that supplies a light emission control signal to each of the second type gate lines disposed in the bezel area and connected to the subpixels. May include drivers.

As such, in the gate driver and the display device using the same according to some embodiments, most of the TFTs in each stage have the lower gate and source contact structures of double gate TFTs, thereby preventing leakage current and ensuring the stability of the gate signal. The reliability of the gate driver can be improved and power consumption can be reduced.

In the gate driver and the display device using the same according to some embodiments, the pull-up TFT in each stage has the lower gate and carry contact structure of the double gate TFT, thereby preventing leakage current and ensuring the stability of the gate signal, so the gate driver Reliability can be improved and power consumption can be reduced.

A gate driver and a display device using the same according to some embodiments use a double gate TFT with a lower gate floating structure as the precharging TFT in each stage and additionally include a boosting capacitor and a TFT to strengthen the precharging role of the control node. Since the stability of the gate signal can be secured, the reliability of the gate driver can be improved.

A light emission control driver according to an embodiment and a display device including the same may be applied to various electronic devices. For example, a light emission control driver according to an embodiment and a display device including the same may be used in a mobile device, a video phone, a smart watch, a watch phone, a wearable device, or a foldable device ( foldable device, rollable device, bendable device, flexible device, curved device, electronic notebook, e-book, PMP (portable multimedia player), PDA ( personal digital assistant, MP3 player, mobile medical device, desktop PC, laptop PC, netbook computer, workstation, navigation, vehicle navigation, vehicle display, television, It can be applied to wallpaper display devices, signage devices, game devices, laptops, monitors, cameras, camcorders, and home appliances.

The features, structures, effects, etc. described in the various examples of the present specification described above are included in at least one example of the present specification and are not necessarily limited to only one example. Furthermore, the features, structures, effects, etc. illustrated in at least one example of the present specification can be combined or modified and implemented in other examples by those skilled in the art in the field to which the technical idea of the present specification pertains. Therefore, contents related to such combinations and modifications should be construed as being included in the technical scope or scope of rights of this specification.

The present specification described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which this specification pertains that various substitutions, modifications, and changes are possible without departing from the technical spirit of the present specification. It will be clear to those who have the knowledge of. Therefore, the scope of the present specification is indicated by the claims described below, and all changes or modified forms derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present specification.

100: Display panel GD: Gate driver
SD: Scan driver EMD: Emission control driver
DD: Data Driver DIC: Data Driver IC
COF: Circuit film BZ1~BZ4: Bezel area
TCON: Timing Controller LS: Level Shifter
1000: Display device DA: Display area
102, 112, 122, 132: first node (Q2) charging unit
104, 114, 134: first node (Q2) discharge unit
106, 116: QB control unit 108, 118, 138: output buffer
136: inverter

Claims (15)

It includes a plurality of stages that each output a plurality of scan signals,
Each of the plurality of stages is,
an output buffer that outputs the scan signal through an output line in response to control of a first control node and control of a second control node;
a first control unit controlling the first control node; and
It includes a second control unit that controls the second control node,
The first control unit includes a charging unit for precharging the first control node and a discharge unit for discharging the first control node,
The charging part,
a first charging transistor controlled by a third control node to precharge the first control node;
a second charging transistor controlled by a first input signal to precharge the third control node before the precharging period of the first control node;
a boosting capacitor connected between the gate electrode and the source electrode of the first charging transistor; and
A gate driver including a discharge transistor controlled by the output of the output buffer to discharge the first control node to a first gate-off voltage. In claim 1,
The output buffer is
a first pull-up transistor controlled by the first control node to output a clock signal supplied to a clock line as a scan signal of the output line; and
A gate driver comprising a first pull-down transistor controlled by the second control node operating in a manner opposite to that of the first control node to discharge the output line to a second gate-off voltage. In claim 2,
The first charging transistor precharges the first control node using the scan output of the first front-end stage during a period when the third control node is boosted by the boosting capacitor and the scan output of the first front-end stage, and ,
The second charging transistor is controlled by the scan output of the second front stage supplied with the first input signal to precharge the third control node using the scan output of the second front stage,
A gate driver wherein the discharge transistor is controlled by a scan output of the output buffer to discharge the first control node to the first gate-off voltage. In claim 2,
Each of the transistors constituting the charging unit of the first control unit,
It is a first double gate type transistor having a structure in which the first lower gate electrode is floating,
Each of the transistors constituting the output buffer, the discharge unit of the first control unit, and the second control unit,
A gate driver that is a second double gate type transistor having a lower gate and source contact structure in which a second lower gate electrode and a second source electrode are in contact. In claim 2,
The output buffer is
a second pull-up transistor controlled by the first control node to output the carry clock signal supplied to the carry clock line as a carry signal of the carry output line; and
A gate driver further comprising a second pull-down transistor controlled by the second control node to discharge the carry output line to the first gate-off voltage. In claim 5,
The first charging transistor precharges the first control node using the carry output of the first front-end stage during a period when the third control node is boosted by the boosting capacitor and the carry output of the first front-end stage, and ,
The second charging transistor is controlled by the carry output of the second front stage supplied with the first input signal to precharge the third control node using the gate-on voltage,
A gate driver wherein the discharge transistor is controlled by a carry output of the output buffer to discharge the first control node to the first gate-off voltage. In claim 5,
The charging unit of the first control unit
The gate driver is controlled by the third control node and further includes a third charging transistor connected between a second input line to which a carry output of the first front stage is supplied and the first charging transistor. In claim 5,
The first control unit
A gate driver controlled by the first control node and further comprising an offset transistor that supplies an offset voltage to an intermediate node between the third charging transistor and the first charging transistor. In claim 5,
The discharge unit of the first control unit
A gate driver controlled by a scan output of a rear stage and including a first discharge transistor that discharges the first control node to the first gate-off voltage. In claim 8,
The discharge unit of the first control unit
First and second discharge transistors controlled by the scan output of a rear stage and connected in series between the first control node and a first power line supplied with the first gate-off voltage; and
Controlled by the second control node and comprising third and fourth discharge transistors connected in series between the first control node and the first power line,
A gate driver in which an intermediate node between the first and second discharge transistors and an intermediate node between the third and fourth discharge transistors receive the offset voltage from the offset transistor. In claim 6,
The second control unit
An inverter controlled by the control of the first control node, deactivating the second control node when the first control node is activated, and activating the second control node when the first control node is deactivated. gate driver. In claim 11,
The second control unit
A gate driver controlled by a carry output of a front-end stage, and further comprising a discharge transistor that discharges the second control node to the first gate-off voltage. In claim 5,
Each of the transistors constituting the charging unit of the first control unit,
It is a first double gate type transistor having a structure in which the first lower gate electrode is floating,
Each of the transistors constituting the output buffer, the discharge unit of the first control unit, and the second control unit, excluding the first pull-up transistor,
A second double gate type transistor having a lower gate and source contact structure in which a second lower gate electrode and a second source electrode are in contact,
The first pull-up transistor is
A gate driver that is a third double gate type transistor having a structure in which a third lower gate electrode and the carry output line are in contact. A display panel including a display area that displays an image through subpixels and a bezel area surrounding the display area; and
A display device comprising the gate driver according to any one of claims 1 to 13, which is disposed in the bezel area and supplies the plurality of scan signals to each of the gate lines connected to the subpixels. A display panel including a display area that displays an image through subpixels and a bezel area surrounding the display area;
a gate driver according to any one of claims 1 to 13, which is disposed in the bezel area and supplies the plurality of scan signals to each of first type gate lines connected to the subpixels; and
A display device comprising an emission control driver disposed in the bezel area and supplying an emission control signal to each of the second type gate lines connected to the subpixels.

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