KR20240082643A - Circuit board for semiconductor and manufacturing method of the same - Google Patents

Abstract

The semiconductor circuit board of the present invention includes an insulating layer; and a circuit pattern layer patterned and disposed on the insulating layer, and the roughness (Ra) of the surface of the circuit pattern layer formed by polishing the circuit pattern layer with an electrolyte composition. includes having a range of 0.01 ㎛ or more and less than 0.32 ㎛.

Description

Circuit board for semiconductor and manufacturing method thereof {Circuit board for semiconductor and manufacturing method of the same}

The present invention relates to a semiconductor circuit board and a manufacturing method thereof.

Entering the information age, the electronic products market has grown significantly, and the electronic circuit market is also growing rapidly. As technology develops, the demand for high-performance, highly integrated circuits increases in the market, and as smart devices spread around the world after the smartphone revolution, it is inevitable that products will become lighter, thinner, and simpler.

In order to create products that meet these market demands, it is essential to implement fine pitch of electronic circuits such as PCBs.

As a method of implementing existing circuits, the photolithography process is widely used, in which a photosensitive resin is exposed to light and then a pattern is formed through development, etching, and peeling processes.

The photolithography process is a method of manufacturing a copper circuit board by forming a pattern to be implemented using photosensitive resin on a substrate on which a copper plating layer is formed, followed by exposure and etching. However, the pitch that can be achieved with this general photolithography process is at least 25 ㎛, making it difficult to form fine patterns.

Due to these process difficulties, recently, the SAP (Semi Additive Process) method or the MSAP (Modified Semi Additive Process) method has been mainly used as a method to realize a fine pitch. The typical SAP method uses methods such as sputtering, chemical vapor deposition, electroless plating, and copper foil pressing to form a pattern using a lithography method using photosensitive resin on a substrate material on which a thin metal seed layer of chrome, nickel, copper, etc. is laminated. do. After plating a conductive material such as copper into the pattern groove formed in this way, the photosensitive resin is removed. After the circuit was formed by copper plating, the metal seed layer from which the photosensitive resin was removed was etched using a chemical or electrical method.

For example, chemical copper has selectivity depending on Cu grain size and Cu type, so Cu roughness was formed after etching, and electric copper had a problem in that parts with smaller grains flew off first, making it more uneven.

In addition, when the circuit surface becomes more uneven, the surface area of the circuit surface becomes relatively larger and the path for transmitting signals also increases, causing a problem of increased signal loss.

The technical problem to be solved by the present invention is to etch the metal seed layer (Cu seed layer) through electrolytic polishing, regardless of grain size or Cu type. The object of the present invention is to provide a semiconductor circuit board capable of forming low roughness by selectively etching the roughness generated during electrolytic polishing, and a method of manufacturing the same.

The technical problems to be achieved in the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below. You will be able to.

A semiconductor circuit board of the present invention for achieving the above technical problem includes an insulating layer; and a circuit pattern layer patterned and disposed on the insulating layer, and the circuit pattern is formed by polishing the circuit pattern layer with an electrolyte composition. The roughness (Ra) of the layer surface includes those having a range of 0.01 μm or more and less than 0.32 μm.

In addition, a cathode is connected to a jig located inside an electrolytic polishing tank containing the electrolyte composition, and the semiconductor circuit board on which the circuit pattern layer is laminated is connected to an anode located inside the jig to electrolytically polish the circuit pattern layer. may include

In addition, the electrolyte composition includes 40 to 85% by weight of phosphoric acid (H ₃ PO ₄ ), 1 to 5% by weight of ethylene glycol, 5 to 35% by weight of purified water (DI water, Deionized water), and sulfuric acid (H ₂ It may include SO ₄ ) in a ratio of 1 to 5% by weight, and copper sulfate (CuSO4) in a ratio of 1 to 15% by weight.

Additionally, the cathode may include at least one of platinum (Pt), titanium (Ti), palladium (Pd), and silver (Ag).

Additionally, the circuit pattern layer may include at least one of gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). .

A method of manufacturing a semiconductor circuit board according to an embodiment of the present invention includes forming an insulating layer, laminating a seed layer on the insulating layer, laminating a dry film on the seed layer, and partially partially applying the dry film. exposure and development to form at least one pattern, filling the at least one pattern formed in the dry film with a conductive material, and removing the dry film to leave the conductive material filled in the at least one pattern. Forming a pattern layer, electropolishing the circuit pattern layer with an electrolyte composition to form a roughness (Ra) of the surface of the circuit pattern layer in a range of 0.01 μm or more and less than 0.32 μm.

In addition, the electrolyte composition includes 40 to 85% by weight of phosphoric acid (H ₃ PO ₄ ), 1 to 5% by weight of ethylene glycol, 5 to 35% by weight of purified water (DI water, Deionized water), and sulfuric acid (H ₂ It may include 1 to 5% by weight of SO ₄ ) and 1 to 15% by weight of copper sulfate (CuSO4).

The above aspects of the present invention are only some of the preferred embodiments of the present invention, and various embodiments reflecting the technical features of the present invention can be understood by those skilled in the art. It can be derived and understood based on

The present invention described above has the following effects.

The semiconductor circuit board of the present invention and its manufacturing method include providing a jig inside an electrolytic polishing tank containing an electrolyte composition, placing the substrate inside the jig, and then connecting the cathode to the jig and the anode to the substrate to obtain voltage and By applying current, the seed layer is etched through electrolytic polishing, and the roughness generated during electropolishing is selectively etched regardless of grain size or Cu type, resulting in a circuit with very low roughness. can be formed.

In addition, in the semiconductor circuit board and its manufacturing method of the present invention, when the roughness (Ra) of the circuit is low, the surface area of the circuit surface is relatively small, which reduces the path through which signals are transmitted, thereby reducing signal loss.

The effects that can be obtained from the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

1 is a diagram for explaining a semiconductor circuit board of the present invention.
2 to 8 are diagrams for explaining a method of manufacturing a semiconductor circuit board of the present invention.
9 is a diagram of an electrolytic polishing device capable of performing electrolytic polishing.
Figure 10 is a diagram showing the change in signal loss according to illuminance according to an embodiment of the present invention.

Since the present invention can make various changes and have various embodiments, specific embodiments will be illustrated and described in the drawings. However, this is not intended to limit the present invention to specific embodiments, and should be understood to include all changes, equivalents, and substitutes included in the spirit and technical scope of the present invention.

Terms containing ordinal numbers, such as first, second, etc., may be used to describe various components, but the components are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, the second component may be referred to as the first component without departing from the scope of the present invention, and similarly, the first component may also be referred to as the second component. The term and/or includes any of a plurality of related stated items or a combination of a plurality of related stated items.

When a component is said to be "connected" or "connected" to another component, it is understood that it may be directly connected to or connected to the other component, but that other components may exist in between. It should be. On the other hand, when it is mentioned that a component is “directly connected” or “directly connected” to another component, it should be understood that there are no other components in between.

In the description of the embodiments, each layer (film), region, pattern or structure is “on” or “under” the substrate, each layer (film), region, pad or pattern. The description of being formed includes all being formed directly or through another layer. The standards for top/top or bottom/bottom of each floor are explained based on the drawing. In addition, the thickness or size of each layer (film), region, pattern, or structure in the drawings may be changed for clarity and convenience of explanation, and therefore does not entirely reflect the actual size.

The terms used in this application are only used to describe specific embodiments and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, terms such as “comprise” or “have” are intended to designate the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, but are not intended to indicate the presence of one or more other features. It should be understood that it does not exclude in advance the possibility of the existence or addition of elements, numbers, steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the technical field to which the present invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and should not be interpreted in an ideal or excessively formal sense unless explicitly defined in the present application. No.

Hereinafter, embodiments will be described in detail with reference to the attached drawings, but identical or corresponding components will be assigned the same reference numbers regardless of reference numerals, and duplicate descriptions thereof will be omitted.

In addition, the semiconductor circuit board and its manufacturing method of the present invention related to the embodiment include providing a jig inside an electrolytic polishing tank containing an electrolyte composition, placing a substrate inside the jig, and then placing a cathode on the jig to the substrate. By connecting the anode and applying voltage and current to electrolytically polish the seed layer and circuit pattern of the semiconductor circuit board, a semiconductor circuit board with very low roughness can be formed.

Hereinafter, a method of forming a fine circuit according to this embodiment will be described in detail with reference to the attached drawings.

1 is a diagram for explaining a semiconductor circuit board of the present invention. 2 to 8 are diagrams for explaining a method of manufacturing a semiconductor circuit board of the present invention.

Referring to FIG. 1, a semiconductor circuit board 100 may include an insulating layer 110, a seed layer 120, and a circuit pattern layer 150.

The semiconductor circuit board 100 may have a multilayer structure. And, Figure 1 shows the outermost structure of the multi-layer semiconductor circuit board 100. For example, the insulating layer 110 may refer to an insulating layer disposed on the outermost side, for example, the uppermost side or the lowermost side, of the multi-layered semiconductor circuit board 100. However, the embodiment is not limited to this, and the insulating layer 110 may be an inner insulating layer between the uppermost layer and the lowermost layer of the multilayer semiconductor circuit board 100.

The insulating layer 110 may have a low dielectric constant. For example, the insulating layer 110 may have a dielectric constant of 3.0Dk or less. For example, the insulating layer 110 may have a dielectric constant of 2.7 Dk or less. For example, the insulating layer 110 may have a dielectric constant of 2.5 Dk or less.

To this end, the insulating layer 110 may be made of resin that does not contain glass fibers. For example, the insulating layer 110 may be part of copper foil bonding resin (RCC). The copper foil adhesive resin may include a film-type resin composition and a copper foil layer disposed on the resin composition. The insulating layer 110 may be a resin composition of copper foil adhesive resin. The insulating layer 110 may have a dielectric constant of 2.5 Dk or less by adjusting the content of resin and filler. Accordingly, the insulating layer 110 of the embodiment may be applied to a printed circuit board for high frequency use (for example, a printed circuit board for 5G).

The insulating layer 110 may have a thickness ranging from 10 μm to 15 μm. If the thickness of the insulating layer 110 is less than 10㎛, the inner circuit pattern (not shown) disposed in the insulating layer 110 may not be stably protected. When the thickness of the insulating layer 110 is greater than 15㎛, the overall thickness of the semiconductor circuit board 100 may increase as the thickness of the insulating layer 110 increases.

Additionally, the insulating layer 110 may generally be made of PPG (prepreg). PPG may have a structure in which glass fibers are impregnated within a resin.

The circuit pattern layer 150 may be disposed on one side of the insulating layer 110. The circuit pattern layer 150 is a wire that transmits electrical signals and may be formed of a metal material with high electrical conductivity. For example, the circuit pattern layer 150 is at least one selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). It can be formed from a metal material.

In addition, the circuit pattern layer 150 is made of gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which have excellent bonding properties. It may be formed of a paste containing at least one metal material or a solder paste.

Preferably, the circuit pattern layer 150 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

The circuit pattern layer 130 is formed using the typical manufacturing processes of the semiconductor circuit board 100, such as the additive process, subtractive process, MSAP (Modified Semi Additive Process), and SAP (Semi Additive Process). ), and ETS (Embedded Trace Substrate) method, etc., and detailed description is omitted here.

2 to 8, the manufacturing method of the semiconductor circuit board of the present invention is as follows.

As shown in FIG. 2, the seed layer 120 may be formed on the insulating layer 110. The seed layer 120 may be formed through processes such as sputtering, chemical vapor deposition, electroless plating, electroplating, coating, dipping, flexographic printing, gravure printing, and gravure offset. It is not limited to this, and may be formed through a common process for forming a metal thin film. For example, the seed layer 120 may be referred to as a copper (Cu) layer or a seed layer.

As shown in FIG. 3, the dry film 130 can be laminated on the seed layer 120. For example, the dry film 130 can be formed by applying a photosensitive resin on the seed layer 120.

As shown in FIGS. 4 and 5 , the dry film 130 is partially exposed and developed through a photolithography process, thereby forming at least one pattern. That is, the dry film 130 can be partially exposed and developed through a photolithography process to form a predetermined pattern 140 or a predetermined hole through which the seed layer 120 is selectively exposed.

The dry film 130 can selectively expose a portion of the seed layer 120 where a circuit is to be formed through a predetermined pattern or a predetermined hole.

For example, the dry film 130 may use a negative type photo resist (PR) as a photosensitive resin. It is not limited to this, and the dry film 130 may use a positive type photo resist if necessary.

As shown in FIG. 6, the circuit pattern layer 150 may be formed by filling a conductive material into a predetermined hole 140 or a predetermined pattern formed in the dry film 130. Conductive materials may include metallic materials with very high electrical conductivity. For example, the conductive material may be copper (Cu).

The circuit pattern layer 150 may be electrically connected to the seed layer 120 exposed through the dry film 130. The circuit pattern layer 150 may be formed of substantially the same conductive material as the seed layer 120.

As shown in FIG. 7 , the dry film 130 may be peeled off after the circuit pattern layer 150 is filled in a predetermined hole 140 or a predetermined pattern. A circuit pattern layer 150 formed as a pattern may be formed on the seed layer 120 in an area where a predetermined hole or a predetermined pattern is formed, and only the seed layer 120 may remain in other areas.

Thereafter, as shown in FIG. 8, the seed layer 120 and the circuit pattern layer 150 formed on the insulating layer 110 are phosphoric acid (H3PO4), ethylene glycol, and purified water (DI water, Deionized). It can be polished with an electrolyte composition consisting of water), sulfuric acid (H2SO4), and copper sulfate (CuSO4).

That is, the electrolyte composition is removed by polishing the surface of the circuit pattern layer 150 and the surface of the seed layer 120 on which the circuit pattern layer 150 is not formed, thereby removing the seed layer 120 and forming the circuit pattern layer 150. There can only be left.

The above-described electrolyte composition can be applied to the electrolytic polishing device 200, which will be described later, to polish the seed layer 120 and the circuit pattern layer 150.

Figure 9 is a diagram of an electrolytic polishing device capable of performing the polishing step of the present invention.

Referring to FIG. 9, the electrolytic polishing apparatus 100 is a semiconductor circuit in which a seed layer 120 and a circuit pattern layer 150 are stacked on an electrolytic polishing tank 210, a jig 220, and an insulating layer 110. It may include a substrate 100, a cathode 240, and an anode 250.

The electrolytic polishing tank 210 may serve as a container that contains an electrolyte composition (polishing electrolyte), a jig 220, a substrate, etc. therein. The electrolytic polishing tank 210 may be made of one or more materials selected from polyvinylpyrrolidone (PVP), polyvinyl chloride (PVC), and polypropylene (PP).

The jig 220 is a container that holds a semiconductor circuit board 100 in which a seed layer 120 and a circuit pattern layer 150 are stacked on an insulating layer 110, and the cathode 240 is used during electrolytic polishing. By connecting, it can function as a cathode. For example, the jig 220 may be made of any one or at least one of platinum (Pt), titanium (Ti), palladium (Pd), silver (Ag), copper, aluminum, and stainless steel (SUS).

The semiconductor circuit board 100 can be connected to the anode 250 during electrolytic polishing. The semiconductor circuit board 100 can function as an anode by being connected to the anode 250.

That is, when voltage and current are applied to the semiconductor circuit board 100, which functions as an anode, using a DC power supply, the seed layer 120 and the circuit pattern layer 150 are dissolved in the electrolyte solution, resulting in electrolytic polishing. can be performed.

That is, the electrolytic polishing device 200 is an electrolytic polishing tank 210 containing an electrolyte composition consisting of phosphoric acid (H3PO4), ethylene glycol (Ethylene glycol), purified water (DI water, Deionized water), sulfuric acid (H2SO4), and copper sulfate (CuSO4). ) By electrically connecting the cathode 240 and the anode 250 to each of the jig 220 provided inside and the semiconductor circuit board 100 provided inside the jig 220, voltage and current are applied to the seed. The layer 120 and the circuit pattern layer 150 may be melted and electropolished.

Specifically, the electrolytic polishing device 200 is provided with a jig 220 inside an electrolytic polishing tank 210 containing an electrolyte composition, and the semiconductor circuit board 100 is placed inside the jig 220. After that, the cathode 240 is connected to the jig 220 and the anode 250 is connected to the semiconductor circuit board 100 to apply voltage and current, thereby forming the seed layer 120 on the insulating layer 110. ) and the circuit pattern layer 150 can be melted and electrolytically polished.

For example, the semiconductor circuit board 100 applies direct current or pulse voltage and current, and applies a voltage of 6 to 18V or 10 to 15V and a current of 200 to 300A or 220 to 250A at 60 ° C. to 80 ° C. or 60 ° C. to 60 ° C. It can be performed by applying it at a temperature of 70°C for 2 to 5 minutes or 2 to 4 minutes. At this time, the applied current density may be 0.1 to 5 A/cm or 0.1 to 4 A/cm. It is not limited to this, and may be approved slightly differently depending on the surrounding environment.

As described above, the present invention provides a jig (220) inside an electrolytic polishing tank (210) containing an electrolyte composition, and places the semiconductor circuit board (100) inside the jig (220). After that, the cathode 240 is connected to the jig 220 and the anode 250 is connected to the semiconductor circuit board 100 to apply voltage and current, thereby forming the seed layer 120 and the circuit pattern layer 150 through electrolytic polishing. ) can lower the illumination intensity. An explanation of this will be provided later.

In addition, the electrolyte composition includes 40 to 85% by weight of phosphoric acid (H3PO4), 1 to 5% by weight of ethylene glycol, 5 to 35% by weight of purified water (DI water, deionized water), and 1 to 5% by weight of sulfuric acid (H2SO4). , and copper sulfate (CuSO4) may be in a ratio of 1 to 15% by weight.

As described above, when the semiconductor circuit board 100 is electrolytically polished using the electrolyte composition, a semiconductor circuit board with a low surface roughness of the circuit pattern layer 150 can be formed.

The circuit pattern layer 150 electrolytically polished by the electrolytic polishing method according to the present invention may exhibit the physical properties shown in Table 1.

Transmission Loss Illuminance measurement results Ra( μm ) Example 1 0.01 Example 2 0.03 Example 3 0.1 Comparison example 0.32

The roughness (Ra), which is the center line average surface roughness of the surface of the circuit pattern layer 150 electrolytically polished according to an embodiment of the present invention, may be 0.01 μm to 0.32 μm. A detailed description of this will be given in FIG. 10.

Figure 10 is a diagram for explaining the change in signal loss according to illuminance.

In the graph shown in FIG. 10, the X-axis represents frequency, and the Y-axis represents transmission loss.

The roughness (Ra) of the circuit pattern layer 150 may be in the range of 0.01 μm or more and less than 0.32 μm.

This should increase the adhesion of the circuit pattern layer 150 to other layers and not affect the flow of signals through the circuit pattern layer 150. Accordingly, the roughness (Ra) of the circuit pattern layer 150 in the embodiment may be in the range of 0.01 μm or more and less than 0.32 μm.

Here, when the roughness (Ra) of the circuit pattern layer 150 is less than 0.01㎛, the bonding force between the circuit pattern layer 150 and other layers decreases, and thus the bonding force between the circuit pattern layer 150 and other layers decreases. Peel strength may be low.

For example, when the roughness (Ra) of the circuit pattern layer 150 is less than 0.01㎛, the peeling strength from other layers is low, which may cause reliability problems in which other layers separate from the circuit pattern layer 150. You can.

Additionally, when the roughness (Ra) of the circuit pattern layer 150 is greater than 0.32 ㎛, loss may occur in the signal flowing through the circuit pattern layer 150. That is, when the roughness (Ra) of the circuit pattern layer 150 is greater than 0.32 ㎛, the surface roughness of the circuit pattern layer 150 increases, resulting in transmission loss due to the skin effect. can be increased.

That is, when the roughness (Ra) of the circuit pattern layer 150 is greater than 0.32㎛, the surface area of the circuit surface is relatively large, so the path through which the signal is transmitted increases, and signal loss may increase.

Here, the skin effect may be a phenomenon in which signals are transmitted only to the surface of the circuit at high frequencies. In consideration of the skin effect, in the present invention, it is preferable that the roughness (Ra) of the circuit pattern layer 150 is formed lower than 0.3㎛.

As described above, in the present invention, considering peel strength and skin effect, the roughness (Ra) of the circuit pattern layer 150 may be in the range of 0.01 μm or more and less than 0.32 μm.

Preferably, in the present invention, considering peel strength and skin effect, the roughness (Ra) of the circuit pattern layer 150 may be in the range of 0.02 μm or more and less than 0.2 μm.

More preferably, in the present invention, considering peel strength and skin effect, the roughness (Ra) of the circuit pattern layer 150 may be in the range of 0.03 μm or more and less than 0.1 μm.

Most preferably, in consideration of peel strength and skin effect, the roughness (Ra) of the circuit pattern layer 150 may be in the range of 0.04 μm or more and less than 0.074 μm.

Although the above description focuses on the embodiments, this is only an example and does not limit the present invention, and those skilled in the art will understand that the examples are as follows without departing from the essential characteristics of the present embodiments. You will see that various variations and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. And these variations and differences in application should be construed as being included in the scope of the present invention as defined in the appended claims.

100: semiconductor circuit board, 110: insulating layer
120: seed layer, 130: dry film
140: predetermined hole, 150: circuit pattern layer
200: electrolytic polishing device, 210: electrolytic polishing tank
220: jig, 240: cathode
250: anode

Claims (7)

insulating layer; and
It includes a circuit pattern layer patterned and disposed on the insulating layer,
The roughness (Ra) of the surface of the circuit pattern layer formed by polishing the circuit pattern layer with an electrolyte composition is,
Having a range of 0.01㎛ or more and less than 0.32㎛,
Circuit board for semiconductors. According to claim 1,
For semiconductors, a cathode is connected to a jig located inside an electrolytic polishing tank containing the electrolyte composition, and the semiconductor circuit board on which the circuit pattern layer is laminated is connected to an anode located inside the jig to electrolytically polish the circuit pattern layer. circuit board. According to claim 1,
The electrolyte composition is,
Phosphoric acid (H ₃ PO ₄ ) 40 to 85% by weight, ethylene glycol (Ethylene glycol) 1 to 5% by weight, purified water (DI water, Deionized water) 5 to 35% by weight, sulfuric acid (H ₂ SO ₄ ) 1 to 5% by weight %, and copper sulfate (CuSO4) in a ratio of 1 to 15% by weight. According to clause 2,
The cathode is,
A semiconductor circuit board containing at least one of platinum (Pt), titanium (Ti), palladium (Pd), and silver (Ag). According to claim 1,
The circuit pattern layer is,
A semiconductor circuit board containing at least one of gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). In a method of manufacturing a semiconductor circuit board,
insulating layer,
Forming a seed layer on the insulating layer,
Forming a dry film on the seed layer,
Partially exposing and developing the dry film to form at least one pattern,
Filling the at least one pattern formed in the dry film with a conductive material,
removing the dry film to leave the conductive material filled in the at least one pattern to form a circuit pattern layer;
Electropolishing the circuit pattern layer with an electrolyte composition,
A method of manufacturing a semiconductor circuit board comprising forming a roughness (Ra), which is the center line average surface roughness of the surface of the circuit pattern layer, in a range of 0.01 μm or more and less than 0.32 μm. According to clause 6,
The electrolyte composition is,
Phosphoric acid (H ₃ PO ₄ ) 40 to 85% by weight, ethylene glycol (Ethylene glycol) 1 to 5% by weight, purified water (DI water, Deionized water) 5 to 35% by weight, sulfuric acid (H ₂ SO ₄ ) 1 to 5% by weight %, and copper sulfate (CuSO4) in a ratio of 1 to 15% by weight.