KR20240057407A - 다이-기판 기계적 스트레스를 감소시키기 위해 패키지 기판의 금속 구조물(들)에 보이드-한정된 섹션들을 갖는 반도체 다이 모듈 패키지들, 및 관련 방법들 - Google Patents

다이-기판 기계적 스트레스를 감소시키기 위해 패키지 기판의 금속 구조물(들)에 보이드-한정된 섹션들을 갖는 반도체 다이 모듈 패키지들, 및 관련 방법들 Download PDF

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Publication number
KR20240057407A
KR20240057407A KR1020247006857A KR20247006857A KR20240057407A KR 20240057407 A KR20240057407 A KR 20240057407A KR 1020247006857 A KR1020247006857 A KR 1020247006857A KR 20247006857 A KR20247006857 A KR 20247006857A KR 20240057407 A KR20240057407 A KR 20240057407A
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KR
South Korea
Prior art keywords
metal
void
voids
metal structure
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
KR1020247006857A
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English (en)
Korean (ko)
Inventor
안드레아스 데틀레프센
제로엔 비엘렌
Original Assignee
퀄컴 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20240057407A publication Critical patent/KR20240057407A/ko
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/255—Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates
    • H01L23/3735—
    • H01L21/4857—
    • H01L21/4882—
    • H01L23/367—
    • H01L23/49568—
    • H01L23/49822—
    • H01L23/49838—
    • H01L23/5383—
    • H01L23/562—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/01—Manufacture or treatment
    • H10W40/03—Manufacture or treatment of arrangements for cooling
    • H10W40/037—Assembling together parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/461—Leadframes specially adapted for cooling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/66—Conductive materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Structure Of Printed Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
KR1020247006857A 2021-09-09 2022-07-01 다이-기판 기계적 스트레스를 감소시키기 위해 패키지 기판의 금속 구조물(들)에 보이드-한정된 섹션들을 갖는 반도체 다이 모듈 패키지들, 및 관련 방법들 Pending KR20240057407A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/470,961 US20230076844A1 (en) 2021-09-09 2021-09-09 Semiconductor die module packages with void-defined sections in a metal structure(s) in a package substrate to reduce die-substrate mechanical stress, and related methods
US17/470,961 2021-09-09
PCT/US2022/073351 WO2023039312A1 (en) 2021-09-09 2022-07-01 Semiconductor die module packages with void-defined sections in a metal structure(s) in a package substrate to reduce die-substrate mechanical stress, and related methods

Publications (1)

Publication Number Publication Date
KR20240057407A true KR20240057407A (ko) 2024-05-02

Family

ID=83050029

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020247006857A Pending KR20240057407A (ko) 2021-09-09 2022-07-01 다이-기판 기계적 스트레스를 감소시키기 위해 패키지 기판의 금속 구조물(들)에 보이드-한정된 섹션들을 갖는 반도체 다이 모듈 패키지들, 및 관련 방법들

Country Status (7)

Country Link
US (1) US20230076844A1 (https=)
EP (1) EP4399744A1 (https=)
JP (1) JP2024533137A (https=)
KR (1) KR20240057407A (https=)
CN (1) CN117836937A (https=)
TW (1) TW202312416A (https=)
WO (1) WO2023039312A1 (https=)

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6175158B1 (en) * 1998-09-08 2001-01-16 Lucent Technologies Inc. Interposer for recessed flip-chip package
JP2003168848A (ja) * 2001-11-30 2003-06-13 Nec Kansai Ltd 配線基板
JP2009500830A (ja) * 2005-06-30 2009-01-08 サンディスク コーポレイション 封止された集積回路パッケージにおける歪みを減らす方法
US20100263914A1 (en) * 2009-04-16 2010-10-21 Qualcomm Incorporated Floating Metal Elements in a Package Substrate
US9659884B2 (en) * 2015-08-14 2017-05-23 Powertech Technology Inc. Carrier substrate
US9978699B1 (en) * 2017-04-07 2018-05-22 Dr Technology Consulting Company, Ltd. Three-dimensional complementary-conducting-strip structure
JP7357436B2 (ja) * 2017-04-10 2023-10-06 日東電工株式会社 撮像素子実装基板、その製造方法、および、実装基板集合体
JP7407498B2 (ja) * 2017-09-15 2024-01-04 日東電工株式会社 配線回路基板およびその製造方法

Also Published As

Publication number Publication date
CN117836937A (zh) 2024-04-05
WO2023039312A1 (en) 2023-03-16
JP2024533137A (ja) 2024-09-12
EP4399744A1 (en) 2024-07-17
US20230076844A1 (en) 2023-03-09
TW202312416A (zh) 2023-03-16

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