KR20230137329A - 기판의 표면과 정렬된 표면 상호연결부들을 포함하는기판을 갖는 패키지 - Google Patents

기판의 표면과 정렬된 표면 상호연결부들을 포함하는기판을 갖는 패키지 Download PDF

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Publication number
KR20230137329A
KR20230137329A KR1020237025272A KR20237025272A KR20230137329A KR 20230137329 A KR20230137329 A KR 20230137329A KR 1020237025272 A KR1020237025272 A KR 1020237025272A KR 20237025272 A KR20237025272 A KR 20237025272A KR 20230137329 A KR20230137329 A KR 20230137329A
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KR
South Korea
Prior art keywords
substrate
interconnections
interconnects
package
integrated device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
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KR1020237025272A
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English (en)
Korean (ko)
Inventor
홍 복 위
마커스 수
아니켓 파틸
Original Assignee
퀄컴 인코포레이티드
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Publication of KR20230137329A publication Critical patent/KR20230137329A/ko
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H01L23/5383—
    • H01L21/4857—
    • H01L23/13—
    • H01L23/49811—
    • H01L23/5386—
    • H01L24/14—
    • H01L25/0655—
    • H01L25/16—
    • H01L25/18—
    • H01L25/50—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/6565—Shapes or dispositions of interconnections recessed into the surface of the package substrates, interposers, or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H01L2224/1403—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/227—Multiple bumps having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231—Shapes
    • H10W72/237—Multiple bump connectors having different shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H10W72/248—Top-view layouts, e.g. mirror arrays

Landscapes

  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Combinations Of Printed Boards (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
KR1020237025272A 2021-02-01 2021-12-22 기판의 표면과 정렬된 표면 상호연결부들을 포함하는기판을 갖는 패키지 Pending KR20230137329A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/164,729 2021-02-01
US17/164,729 US11682607B2 (en) 2021-02-01 2021-02-01 Package having a substrate comprising surface interconnects aligned with a surface of the substrate
PCT/US2021/064920 WO2022164560A1 (en) 2021-02-01 2021-12-22 Package having a substrate comprising surface interconnects aligned with a surface of the substrate

Publications (1)

Publication Number Publication Date
KR20230137329A true KR20230137329A (ko) 2023-10-04

Family

ID=80050968

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020237025272A Pending KR20230137329A (ko) 2021-02-01 2021-12-22 기판의 표면과 정렬된 표면 상호연결부들을 포함하는기판을 갖는 패키지

Country Status (8)

Country Link
US (1) US11682607B2 (https=)
EP (1) EP4285407A1 (https=)
JP (1) JP7824965B2 (https=)
KR (1) KR20230137329A (https=)
CN (1) CN116745902A (https=)
BR (1) BR112023014695A2 (https=)
TW (1) TWI911361B (https=)
WO (1) WO2022164560A1 (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7728756B2 (ja) 2019-10-29 2025-08-25 エイエムエス－オスラム インターナショナル ゲーエムベーハー オプトエレクトロニクス装置
WO2021110332A1 (en) * 2019-12-06 2021-06-10 Osram Opto Semiconductors Gmbh Window or surface of a vehicle comprising at least one optoelectronic component
DE112020005977T5 (de) 2019-12-06 2022-09-22 Osram Opto Semiconductors Gmbh Vorrichtung umfassend einen träger mit optoelektronischen elementen und verfahren zur herstellung der vorrichtung
CN114786943A (zh) 2019-12-06 2022-07-22 奥斯兰姆奥普托半导体股份有限两合公司 光电装置
US12040317B2 (en) 2019-12-06 2024-07-16 Osram Opto Semiconductors Gmbh Optoelectronic device
CN114787996A (zh) 2019-12-06 2022-07-22 奥斯兰姆奥普托半导体股份有限两合公司 光电装置
US11682607B2 (en) * 2021-02-01 2023-06-20 Qualcomm Incorporated Package having a substrate comprising surface interconnects aligned with a surface of the substrate
US12549154B2 (en) 2021-09-24 2026-02-10 Rf360 Singapore Pte. Ltd. Package comprising an acoustic device and a cap substrate comprising an inductor
US12341488B2 (en) * 2022-09-20 2025-06-24 Qualcomm Incorporated Package comprising an acoustic device and a polymer cap layer
US20240136293A1 (en) * 2022-10-25 2024-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8021976B2 (en) * 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
US7099293B2 (en) * 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
JP3800215B2 (ja) 2003-09-29 2006-07-26 株式会社トッパンＮｅｃサーキットソリューションズ 印刷配線板、半導体装置、及びそれらの製造方法
JP4769022B2 (ja) 2005-06-07 2011-09-07 京セラＳｌｃテクノロジー株式会社 配線基板およびその製造方法
US7569422B2 (en) * 2006-08-11 2009-08-04 Megica Corporation Chip package and method for fabricating the same
JP5101169B2 (ja) 2007-05-30 2012-12-19 新光電気工業株式会社 配線基板とその製造方法
US8193555B2 (en) * 2009-02-11 2012-06-05 Megica Corporation Image and light sensor chip packages
US8837872B2 (en) * 2010-12-30 2014-09-16 Qualcomm Incorporated Waveguide structures for signal and/or power transmission in a semiconductor device
US9177899B2 (en) 2012-07-31 2015-11-03 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
US9461008B2 (en) * 2012-08-16 2016-10-04 Qualcomm Incorporated Solder on trace technology for interconnect attachment
US9508637B2 (en) * 2014-01-06 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Protrusion bump pads for bond-on-trace processing
US10971476B2 (en) * 2014-02-18 2021-04-06 Qualcomm Incorporated Bottom package with metal post interconnections
US9679841B2 (en) 2014-05-13 2017-06-13 Qualcomm Incorporated Substrate and method of forming the same
US9343369B2 (en) * 2014-05-19 2016-05-17 Qualcomm Incorporated Three dimensional (3D) integrated circuits (ICs) (3DICs) and related systems
US10157823B2 (en) 2014-10-31 2018-12-18 Qualcomm Incorporated High density fan out package structure
US9425174B1 (en) 2014-11-18 2016-08-23 Altera Corporation Integrated circuit package with solderless interconnection structure
US11139224B2 (en) * 2019-12-05 2021-10-05 Qualcomm Incorporated Package comprising a substrate having a via wall configured as a shield
US20210175178A1 (en) * 2019-12-05 2021-06-10 Qualcomm Incorporated Package comprising a double-sided redistribution portion
US12040317B2 (en) * 2019-12-06 2024-07-16 Osram Opto Semiconductors Gmbh Optoelectronic device
US20210210452A1 (en) * 2020-01-02 2021-07-08 Qualcomm Incorporated Integrated passive device (ipd) coupled to front side of integrated device
US11444019B2 (en) * 2020-04-06 2022-09-13 Qualcomm Incorporated Package comprising a substrate with interconnect routing over solder resist layer and an integrated device coupled to the substrate and method for manufacturing the package
US11502049B2 (en) * 2020-05-06 2022-11-15 Qualcomm Incorporated Package comprising multi-level vertically stacked redistribution portions
US11682607B2 (en) * 2021-02-01 2023-06-20 Qualcomm Incorporated Package having a substrate comprising surface interconnects aligned with a surface of the substrate
US11823983B2 (en) * 2021-03-23 2023-11-21 Qualcomm Incorporated Package with a substrate comprising pad-on-pad interconnects
US12469811B2 (en) * 2021-03-26 2025-11-11 Qualcomm Incorporated Package comprising wire bonds coupled to integrated devices
US11791276B2 (en) * 2021-04-08 2023-10-17 Qualcomm Incorporated Package comprising passive component between substrates for improved power distribution network (PDN) performance

Also Published As

Publication number Publication date
TW202232694A (zh) 2022-08-16
BR112023014695A2 (pt) 2023-12-12
CN116745902A (zh) 2023-09-12
US11682607B2 (en) 2023-06-20
JP2024505487A (ja) 2024-02-06
TWI911361B (zh) 2026-01-11
JP7824965B2 (ja) 2026-03-05
US20220246496A1 (en) 2022-08-04
EP4285407A1 (en) 2023-12-06
WO2022164560A1 (en) 2022-08-04

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