KR20230051867A - a method of manufacturing semiconductor package - Google Patents

Abstract

A method for manufacturing a semiconductor package, according to the present invention, comprises: placing a semiconductor chip having a first thickness on a target substrate; placing a second semiconductor chip having a second thickness and a thickness compensation structure having a third thickness on a first surface of a carrier substrate with the first surface and a second surface facing each other; placing the carrier substrate on the target substrate to make the thickness compensation structure and the first semiconductor chip vertically overlapped to be in contact with each other; irradiating laser from the second surface of the carrier substrate to the first surface on the carrier substrate, wherein a height from the target substrate to a top surface of the second semiconductor chip is identical to a sum of a height, from the target substrate to a top surface of the first semiconductor chip, and a third thickness; and removing the carrier substrate and the thickness compensation structure. The second thickness is thicker than the first thickness. According to the present invention, the method can bond semiconductor chips or semiconductor packages with different thicknesses by a wafer or a panel level.

Description

Manufacturing method of semiconductor package {a method of manufacturing semiconductor package}

The present invention relates to a method for manufacturing a semiconductor package.

BACKGROUND A technology for bonding a semiconductor chip, package, sensor, or passive element (hereinafter referred to as a chip or package) to a wafer or panel substrate is continuously being developed.

A common method of bonding to a wafer or panel substrate is to bond with heat and pressure using a ceramic heater. This method is bonded at the individual chip or package level, so when the bonding process is performed on the wafer or panel substrate, the wafer or panel substrate is bonded. Overall, the process time required for the bonding process is long, resulting in a drop in productivity. As the process time drops, the flux applied for the bonding process on the wafer or panel substrate, NCP (Non-Conductive Paste), NCF (Non-Conductive Paste) The physical properties of the film) change, resulting in a problem that the process is impossible or the defect rate in the bonding process increases rapidly.

An object to be solved by the present invention is to provide a method for manufacturing a semiconductor package that electrically and mechanically simultaneously bonds chips or packages having different thicknesses to a wafer or panel substrate.

In the method of simultaneously bonding chips or packages having different thicknesses to a wafer or panel substrate according to one aspect of the present invention, semiconductor chips having a first thickness are disposed on a target substrate, first surfaces and second surfaces facing each other are disposed. Disposing a second semiconductor chip having a second thickness and a thickness compensation structure having a third thickness on the first surface of a carrier substrate having two surfaces, wherein the thickness compensation structure and the first semiconductor chip are vertically overlapped. Disposing the carrier substrate on the target substrate so that it is in contact with the target substrate, and the height from the target substrate to the upper surface of the second semiconductor chip is the sum of the height from the target substrate to the upper surface of the first semiconductor chip and the third thickness. Same as, radiating a laser from the second surface of the carrier substrate toward the first surface on the carrier substrate and removing the carrier substrate and the thickness compensation structure, wherein the second thickness is A method of manufacturing a semiconductor package having a thickness larger than the first thickness.

According to the configuration of the present invention, semiconductor chips or semiconductor packages having different thicknesses can be simultaneously bonded at the wafer or panel level.

1 to 6 are diagrams illustrating a method of manufacturing a semiconductor package according to example embodiments.
7 and 8 are diagrams illustrating a method of manufacturing a semiconductor package according to some embodiments.

In order to fully understand the configuration and effects of the present invention, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention is not limited to the embodiments disclosed below, but may be implemented in various forms and various modifications and changes may be applied. However, it is provided to complete the disclosure of the present invention through the description of the present embodiment, and to completely inform those skilled in the art of the scope of the invention to which the present invention belongs. In the accompanying drawings, for convenience of explanation, the size of the components is shown larger than the actual size, and the ratio of each component may be exaggerated or reduced.

Terms used in this specification are for describing embodiments and are not intended to limit the present invention. In addition, terms used in this specification may be interpreted as meanings commonly known to those skilled in the art unless otherwise defined.

Hereinafter, a wafer or panel level simultaneous bonding process according to an embodiment of the present invention will be described in detail with reference to the drawings.

1 to 6 are diagrams illustrating a method of manufacturing a semiconductor package according to example embodiments.

Referring to FIG. 1 , a target substrate 10 may be provided. The target substrate 10 may be a wafer or a printed circuit board (PCB). First pads 12a and second pads 12b may be provided on the target substrate 10 .

An adhesive layer 11 may be provided on the target substrate 10 to cover the first pads 12a and the second pads 12b. The adhesive layer 11 may include at least one of flux, non-conductive film (NCF), and non-conductive paste (NCP).

At least one first semiconductor chip 20 may be disposed on the adhesive layer 11 . The first semiconductor chip 20 may include a first semiconductor substrate 21 , first metal posts 22 , and first connection terminals 23 . Each of the first metal posts 22 may include, for example, copper. The first metal posts 22 may be provided on the active surface of the first semiconductor chip 20 . According to some embodiments, first metal pads may be provided between the first metal posts 22 and the first semiconductor substrate 21 (not shown).

First connection terminals 23 may be provided on each of the first metal posts 22 . The first connection terminals 23 may be, for example, solder bumps. According to some embodiments, the first metal posts 22 may be omitted, and each of the first connection terminals 23 may contact the first metal pads respectively (not shown).

The first semiconductor chip 20 may be disposed such that the first metal posts 22 vertically overlap the first pads 12a. A high-temperature heat treatment process such as melting the adhesive layer 11 and the first connection terminal 23 may not be included in the process of disposing the adhesive layer 11 and the first semiconductor chip 20 .

The first semiconductor chip 20 may have a first thickness T1. The first thickness T1 means a vertical distance from the lowermost portion of the first connection terminal 23 to the upper surface of the first semiconductor substrate 21 . When a plurality of first semiconductor chips 20 are provided, the thicknesses T1 of each of the first semiconductor chips 20 may be substantially the same as each other.

Referring to FIG. 2 , a carrier substrate 30 including facing first and second surfaces 30a and 30b may be provided. The carrier substrate 30 may include a transparent material. The carrier substrate 30 may include, for example, glass, transparent polyimide, transparent PET, glass, quartz, sapphire, or the like. A transparent adhesive layer 31 may be provided on the first surface 30a of the carrier substrate 30 . The transparent adhesive layer 31 may include, for example, polydimethylsiloxane (PDMS).

Both the carrier 30 and the transparent adhesive layer 31 may have transparency of 80% or more in light of a wavelength of 200 nm to 2 um.

The second semiconductor chip 24 and at least one thickness compensation structure 32 may be attached to the transparent adhesive layer 31 .

The second semiconductor chip 24 may include a second semiconductor substrate 25 , second metal posts 26 , and second connection terminals 27 . Each of the second metal posts 26 may include, for example, copper. The second metal posts 26 may be provided on the active surface of the second semiconductor chip 24 . According to some embodiments, second metal pads may be provided between the second metal posts 26 and the second semiconductor substrate 25 (not shown).

Second connection terminals 27 may be provided on each of the second metal posts 26 . The second connection terminals 27 may be, for example, solder bumps. According to some embodiments, the second metal posts 26 are omitted, and each of the second connection terminals 27 may contact the second metal pads respectively (not shown).

The second semiconductor chip 24 may have a second thickness T2 , and the thickness compensation structure 32 may have a third thickness T3 . The second thickness T2 may be a vertical distance from the lowermost portion of the second connection terminal 27 to the upper surface of the second semiconductor substrate 25 . The third thickness T3 may be a vertical distance from the lower surface of the thickness compensation structure 32 to the upper surface.

The second thickness T2 of the second semiconductor chip 24 may be greater than the first thickness T1 of the first semiconductor chip 21 and the third thickness T3 of the thickness compensation structure 32 .

The thickness compensation structure 32 may include a material having the same laser absorption rate as that of the first semiconductor chip 20 . Laser absorption rate refers to the degree of absorption by the irradiated material. For example, the thickness compensation structure 32 and the first semiconductor chip 20 may have substantially the same laser absorption coefficient.

Referring to FIG. 3 , a transparent pressure plate 40 may be attached to the second surface 30b of the carrier substrate 30 . Pressure may be applied to bring the carrier substrate 30 closer to the target substrate 10 through the transparent pressure plate 40 . As a result, the connection terminals 23 and 27 may contact the pads 12 and the thickness compensation structure 32 may contact the upper surface of the first semiconductor substrate 21 . Pressure may also be applied to the first semiconductor chip 20 through the thickness compensation structure 32 . The first height H1 of the upper surface of the second semiconductor substrate 25 is the sum of the second height H2 of the upper surface of the first semiconductor substrate 21 and the third thickness T3 of the thickness compensation structure 32 and may be substantially the same. The first height H1 means a vertical distance from the top surface 10a of the target substrate 10 to the top surface of the second semiconductor substrate 25 . The second height H2 means a vertical distance from the top surface 10a of the target substrate 10 to the top surface of the first semiconductor substrate 21 .

Referring to FIG. 4 , a surface emitting laser device 50 may be provided over the transparent platen 40 . The laser L1 may be radiated toward the second surface 30b of the carrier substrate 30 using the surface-emitting laser device 50 .

The laser L1 may pass through the transparent pressure plate 40 , the carrier substrate 30 , and the transparent adhesive layer 31 . The laser L1 is absorbed by the first semiconductor chip 20, the second semiconductor chip 24, and the thickness compensation structure 32, and the temperatures of the first semiconductor chip 20 and the second semiconductor chip 24 increase. can rise That is, when the temperature of the second semiconductor chip 24 increases, the temperature of the first semiconductor chip 20 may simultaneously increase through the thickness compensation structure 32 .

As a result, the temperatures of the first metal posts 22 and the second metal posts 26 increase, and at the same time, the first connection terminals 23 and the second connection terminals 27 are melted. . During the melting process, the oxide film on the surface of each of the first connection terminals 23 and the second connection terminals 27 may be removed by the adhesive layer 11 . The first connection terminals 23 may be electrically and mechanically coupled to the first pads 12a. At the same time, the second connection terminals 27 may be electrically and mechanically coupled to the second pads 12b.

Referring to FIG. 5 , the carrier substrate 30 , the transparent adhesive layer 31 and the thickness compensation structure 32 may be separated.

A sawing process of the target substrate 10 may be performed along the sawing line SL, and a semiconductor package 1 as shown in FIG. 6 may be formed.

According to some embodiments, the molding member may cover the top surface 10a of the target substrate 10, the top surface and side surface of the first semiconductor chip 10, and the top surface and side surface of the second semiconductor chip 10 before the sawing process. there is. The molding member may include an epoxy molding compound (EMC).

In the case of the existing technology, when attaching semiconductor chips having different thicknesses to a target substrate, each semiconductor chip was sequentially bonded to the target substrate using heat and pressure. In this case, there is a problem in that productivity decreases due to the long process time, and as the process time increases, the physical properties of the bonding layer change or the defective rate of the bonding process increases rapidly. According to the concept of the present invention, by using the thickness compensation structure, semiconductor chips having different thicknesses can be simultaneously bonded to a large area in a short time through a single heat treatment process (eg, surface-emitting laser process).

According to some embodiments, a first sub-semiconductor package may be provided instead of the first semiconductor chip 20 of FIG. 1 . A second semiconductor package may be provided instead of the second semiconductor chip 24 of FIG. 2 . Subsequently, the processes of FIGS. 3 to 5 may be performed in substantially the same way. The thickness of the second sub-semiconductor package may be greater than that of the first sub-semiconductor package, and the thickness of the thickness compensating structure 32 may compensate for a thickness difference between the first sub-semiconductor package and the second sub-semiconductor package. The laser absorption rate of the thickness compensation structure 32 may be substantially the same as that of the first sub-semiconductor package.

7 is a diagram illustrating a method of manufacturing a semiconductor package according to some embodiments.

Referring to FIG. 7 , third pads 12c may be provided on the target substrate 10 . An adhesive layer 11 may be provided on the target substrate 10 to cover the third pads 12c.

A carrier substrate 30 and a transparent adhesive layer 31 may be provided. Third semiconductor chips 60 may be attached to the transparent adhesive layer 31 . Each of the third semiconductor chips 60 may include a third semiconductor substrate 61 , third metal posts 62 , and third connection terminals 63 .

The third semiconductor chips 60 may be substantially identical to each other. That is, the thickness of each of the third semiconductor substrates 61 may be substantially the same. Subsequently, the semiconductor package of FIG. 8 may be formed through the processes of FIGS. 3 to 6 .

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention may be implemented in other specific forms without changing its technical spirit or essential features. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

10: target substrate
11: adhesive layer
12: Pad
20: first semiconductor chip
21: first semiconductor substrate
22: first metal post
23: first connection terminal
24: second semiconductor chip
25: second semiconductor substrate
26: second metal post
27: second connection terminal
30: carrier
31: transparent adhesive layer
32: thickness compensation structure
40: transparent pressure plate
50: Surface Emitting Laser device
60: third semiconductor chip
61: third semiconductor substrate
62: third metal post
63: third connection terminal

Claims (1)

disposing a semiconductor chip having a first thickness on a target substrate;
disposing a second semiconductor chip having a second thickness and a thickness compensation structure having a third thickness on the first surface of a carrier substrate having first and second surfaces facing each other;
Disposing the carrier substrate on the target substrate so that the thickness compensation structure and the first semiconductor chip are vertically overlapped and contacted, and a height from the target substrate to an upper surface of the second semiconductor chip is from the target substrate to the first semiconductor chip. 1 equal to the sum of the height to the upper surface of the semiconductor chip and the third thickness;
irradiating a laser from the second surface of the carrier substrate toward the first surface on the carrier substrate; and
And removing the carrier substrate and the thickness compensation structure,
The second thickness is a method of manufacturing a semiconductor package greater than the first thickness.

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