JP2013045987A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which inhibits a bonding wire connected with a lower layer chip from contacting with an upper layer chip without causing the increase of the device size and the material cost.SOLUTION: Bonding wires 16-2 are connected to one surface of a first semiconductor device 13, and an adhesion member 14 is provided on one surface of a second semiconductor chip 15. The other surface of the second semiconductor chip is held by using a collet and the collet is cooled while holding the second semiconductor chip. After the collet is cooled, the collet is moved and the adhesive member 14 is placed in close contact with the one surface of the first semiconductor chip 13. Then, the first semiconductor chip 13 and the second semiconductor chip 15 are bonded to each other through the adhesive member 14.

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a second chip is stacked on a first chip to which a bonding wire is connected.

  The related semiconductor device manufacturing method is to apply an insulating film adhesive layer to the upper semiconductor chip, gradually bring the upper semiconductor chip closer to the surface of the lower semiconductor chip, and insulate the bonding wires on the surface of the lower semiconductor chip. The upper and lower semiconductor chips are bonded while being present in the adhesive film-like adhesive layer (for example, see Patent Document 1).

Japanese Patent Laying-Open No. 2004-72009 (0021, FIG. 3)

  When an insulating film adhesive layer is used and the upper and lower semiconductor chips are bonded while the bonding wire is embedded in the layer, the distance between the two chips becomes too small and the bonding wire comes into contact with the back surface of the upper semiconductor chip. There is a risk of short circuit.

  Patent Document 1 describes a method of using two types of adhesive layers having different viscosities and further providing another layer between them in order to prevent contact between the bonding wire and the upper semiconductor chip. Yes.

  However, increasing the number and types of adhesive layers causes problems that the apparatus is increased in size and the material cost is increased.

  In a method for manufacturing a semiconductor device according to an aspect of the present invention, a bonding wire is connected to one surface of a first semiconductor chip, an adhesive member is formed on one surface of a second semiconductor chip, and a collet is used. Holding the other surface of the second semiconductor chip, cooling the collet while holding the second semiconductor chip, cooling the collet, moving the collet, and It is characterized in that the first semiconductor chip and the second semiconductor chip are adhered to each other through the adhesive member, in close contact with one surface of the first semiconductor chip.

  According to the present invention, after the collet is cooled, the second semiconductor chip is bonded to the first semiconductor chip using the adhesive member formed on one surface of the second semiconductor chip. Contact between the bonding wire connected to the first semiconductor chip and the second semiconductor chip can be suppressed without increasing the thickness of the member or increasing the material cost.

It is sectional drawing which shows schematic structure of an example of the semiconductor device to which this invention is applied. (A)-(f) is a figure for demonstrating the manufacturing process of the 2nd semiconductor chip contained in the semiconductor device of FIG. (A)-(f) is process drawing for manufacturing the semiconductor device based on the 1st Embodiment of this invention. It is process drawing for demonstrating in detail the die-bonding process demonstrated with reference to FIG.3 (b). It is sectional drawing which shows the modification of the collet used for the die bonding process of FIG.

  Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings.

  In the method for manufacturing a semiconductor device according to the first embodiment of the present invention, a bonding wire is connected to one surface of the first semiconductor chip, an adhesive member is formed on one surface of the second semiconductor chip, The collet is used to hold the other surface of the second semiconductor chip, the collet is cooled while holding the second semiconductor chip, the collet is cooled, the collet is moved, and the adhesive member is moved to the first member. The first semiconductor chip and the second semiconductor chip are adhered to one surface of the semiconductor chip via an adhesive member.

  Here, the cooling of the collet is performed such that the temperature is equal to or lower than the first predetermined temperature. The cooling of the collet is performed using, for example, air ejected from a nozzle. The collet may have a vent hole that allows air ejected from the nozzle to pass therethrough and increases the cooling efficiency of the collet.

  On the other hand, the first semiconductor chip is heated to a temperature equal to or higher than the second predetermined temperature, and decreases the viscosity of the adhesive member that approaches and contacts.

  The adhesive member has a low viscosity on the first semiconductor chip side and a high viscosity on the second semiconductor chip side. As a result, the bonding wire connected to the first semiconductor chip easily enters the adhesive member, but is difficult to reach the second semiconductor chip. Thus, contact between the wire bonding and the second semiconductor chip is suppressed. In addition, there is no need to increase the thickness or number of layers of the adhesive member, and there is no increase in raw material costs.

  FIG. 1 is a cross-sectional configuration diagram illustrating an example of a semiconductor device manufactured by the method of manufacturing a semiconductor device according to the first embodiment of the present invention.

  The illustrated semiconductor device 10 is an MCP (Multi Chip Package) type semiconductor device. The semiconductor device 10 includes a wiring board 11, a first semiconductor chip (lower chip) 13 bonded to a surface of the wiring board 11 with a first adhesive member (for example, DAF: Die Attach Film) 12, A second semiconductor chip (upper chip) 15 bonded to one surface of the semiconductor chip 13 by a second adhesive member (for example, FOW: Film On Wire) 14, and first and second semiconductor chips 13 and 15; The plurality of first and second bonding wires 16-1 and 16-2 and the first and second semiconductor chips 13 and 15 that are electrically connected to the wiring board 11 are bonded to the bonding wires 16-1 and 16-. 2 and a sealing body (insulating resin) 17 for sealing on the wiring substrate 11 and a plurality of solder balls 18 mounted on the other surface of the wiring substrate 11.

  The wiring board 11 may be a substantially rectangular plate-like glass epoxy board. The wiring board 11 includes an insulating base 111, wiring layers 112 and 113 formed on one and other surfaces thereof, a via 114 that penetrates the insulating base 111 and electrically connects the wiring layers 112 and 113, and Insulating films (solder resist) 115 and 116 are formed on one surface and the other surface of the insulating base so as to cover the wiring layers 112 and 113.

  The wiring layer 112 includes connection pads 117 to which the bonding wires 16-1 and 16-2 are connected. The wiring layer 113 includes a land 118 on which the solder ball 18 is mounted.

  A predetermined circuit is formed in each of the first semiconductor chip 13 and the second semiconductor chip 15. These semiconductor chips 13 and 15 are mounted on the wiring substrate 11 in a so-called face-up state in which the circuit formation surface faces the information shown in the figure. The semiconductor chips 13 and 15 may be any circuit formed.

  Each of the first adhesive member 12 and the second adhesive member 14 is an insulating adhesive film having an epoxy resin as a main component. However, in order to allow the second semiconductor chip 15 to be bonded to the first semiconductor chip 13 in a state where the first semiconductor chip 13 is mounted on the wiring substrate 11, the second adhesive member 14 is the first one. The melting point is lower than that of the adhesive member 12.

  The bonding wires 16-1 and 16-2 are conductive metal wirings such as Au and Cu. The electrode pads on the circuit formation surfaces of the first and second semiconductor chips 13 and 15 mounted on the wiring board 11 in a face-up state are electrically connected to the connection pads of the wiring board 11.

  The sealing body 17 seals the first and second semiconductor chips 13 and 15 together with the bonding wires 16-1 and 16-2 on the wiring substrate 11 to protect the semiconductor chips. The sealing resin also has an epoxy resin as a main component.

  1 will be described with reference to FIGS. 2A to 2F and FIGS. 3A to 3F.

  First, as shown in FIG. 2A, a plurality of predetermined circuits, for example, a plurality of memory circuits, respectively corresponding to the plurality of second semiconductor chips 15 are formed on one surface side of the semiconductor wafer 20. FIG. 2A shows a dicing line 21 that partitions a plurality of second semiconductor chips 15 and a plurality of electrode pads 22 that are external connection terminals of a predetermined circuit formed.

  Next, in order to perform a wafer BG (Back Grinding) process, a BG tape 23 (FIG. 2B) is attached to one surface side of the semiconductor wafer 20. Subsequently, the other side of the semiconductor wafer 20 is ground using a BG grindstone (not shown), and the thickness of the semiconductor wafer 20 is reduced as shown in FIG. By this BG process, the semiconductor wafer 20 is thinned to, for example, about 100 μm.

  Next, as illustrated in FIG. 2C, an adhesive layer 24 that becomes the second adhesive member 14, for example, a FOW (Film On Wire) film, is formed on the entire other surface side of the semiconductor wafer 20.

  Subsequently, as shown in FIG. 2D, a dicing tape 25 is attached to the adhesive layer 24 side. Further, the BG tape 23 attached to one surface side of the semiconductor wafer 20 is removed. In this way, the semiconductor wafer 20 whose back side is held on the dicing tape 25 via the adhesive layer 24 is prepared.

  Next, a dicing process is performed. In the dicing process, the semiconductor wafer 20 is held on a stage of a dicing apparatus (not shown), and the dicing apparatus recognizes a dicing line on one surface of the semiconductor wafer 20. The dicing apparatus uses a dicing blade that rotates at high speed to cut the semiconductor wafer 20 from one surface side of the semiconductor wafer 20 along the recognized dicing line. The cutting depth of the dicing blade is adjusted to a depth at which a part of the dicing tape is cut. Thereby, as shown in FIG. 2E, the semiconductor wafer 20 is cut integrally with the adhesive layer 24.

  After the dicing process is completed, the dicing tape 25 is irradiated with UV light by an unillustrated ultraviolet (UV) irradiation mechanism to reduce the adhesive strength of the dicing tape 25. Then, the individually cut semiconductor chips 15 are picked up from the dicing tape 25 by a pickup device (not shown). In this way, a plurality of second semiconductor chips 15 having the second adhesive member 14 provided on the back surface as shown in FIG.

  While manufacturing the 2nd semiconductor chip 15 as mentioned above, the wiring mother board cut and divided | segmented into the some wiring board 11 and the some 1st semiconductor chip 13 are prepared. The wiring mother board and the first semiconductor chip 13 are manufactured using a known method.

  Next, an assembly process of the semiconductor device 10 will be described with reference to FIGS.

  First, as shown in FIG. 3A, a plurality of first semiconductor chips 13 are mounted on one surface of the wiring mother board 30. A plurality of product formation regions that are cut and separated along the dicing line 31 are defined on the wiring mother board 30, and the first semiconductor chip 13 is mounted in each region. The first semiconductor chip 13 is bonded and fixed to the wiring motherboard 30 using the first adhesive member 12. Subsequently, using a bonding apparatus (not shown), the electrode pads of the first semiconductor chip 13 mounted on the wiring mother board 30 and the corresponding connection pads 117 of the wiring mother board 30 are connected by the first bonding wires 16-1. Connect electrically.

  Note that, as the first semiconductor chip 13, similarly to the second semiconductor chip 15, a semiconductor chip having a FOW film formed on the back surface may be used. In that case, the FOW film is used as it is as the first adhesive member 12.

  Next, as shown in FIG. 3B, the second semiconductor chip 15 is stacked and mounted on the first semiconductor chip 11 mounted on the wiring motherboard 30. The second adhesive member 14 formed on the other surface side of the second semiconductor chip 15 is brought into close contact with one surface of the first semiconductor chip 13, and the first bonding wire 16-1 is connected to the second adhesive member. 14 is built in. This process will be described in detail later with reference to FIG.

  Next, as shown in FIG. 3C, the electrode pads of the second semiconductor chip 15 and the corresponding connection pads 117 of the wiring mother board 30 are electrically connected by the second bonding wires 16-2.

  Next, as shown in FIG. 3D, a sealing resin layer 32 is formed on one surface side of the wiring mother board 30 by batch molding. Thereby, the first semiconductor chip 13 and the second semiconductor chip 15 are sealed by the sealing resin layer 32 together with the first and second bonding wires 16-1 and 16-2. The sealing resin layer 32 is later cut to become the sealing body 17.

  Next, as shown in FIG. 3E, solder balls 18 are mounted on the plurality of lands 118 exposed on the other surface side of the wiring mother board 30, respectively. The solder ball 18 is electrically connected to the first semiconductor chip 13 or the second semiconductor chip 15 via a wiring pattern formed on the wiring mother board 30 and bonding wires 16-1 and 16-2. The solder ball 18 is used as an external terminal of the semiconductor device 10.

  The mounting of the plurality of solder balls 18 can be performed using, for example, an adsorption mechanism (not shown) including a plurality of adsorption holes arranged in correspondence with the plurality of lands 118. In this case, the plurality of solder balls 18 are sucked and held by the suction mechanism, and flux is transferred and formed on the plurality of held solder balls 18 and mounted on the plurality of lands 118 of the wiring mother board 30 at a time. Thereafter, the plurality of solder balls 18 and the plurality of lands 118 are connected and fixed by reflow processing.

  Next, the wiring mother board 30 and the sealing resin layer 32 are cut along the dicing line 31 using a dicing blade (not shown). As a result, as shown in FIG. 3F, a plurality of semiconductor devices 10 are obtained.

  Next, a process of stacking the second semiconductor chip 15 on the first semiconductor device 13 (die bonding process) will be described with reference to FIGS.

  As shown in FIG. 4A, the second semiconductor chip 15 is positioned above the first semiconductor chip 13 mounted on one surface of the wiring motherboard 30 and connected to the bonding wires 16-1.

  Here, the wiring mother board 30 is mounted and held on the bonding stage 41. The bonding stage 41 is provided with a heater 42, and the wiring mother board 30 is heated to a predetermined bonding temperature (second predetermined temperature), for example, 150 ° C. This temperature is maintained even after the end of the wire bonding process, and the temperature of the bonding wire 16-1 is also maintained at substantially the same temperature.

  On the other hand, the second semiconductor chip 15 is held by a collet 43. In other words, the collet 43 holds one surface side of the second semiconductor chip 15 by vacuum suction. Further, a collet cooler 44 is provided near the collet 43, and relatively low-temperature air 45 is ejected toward the collet 43. The collet 43 is cooled by the air 45 from the collet cooler 44 and is maintained at a predetermined temperature (first predetermined temperature) or lower, for example, 60 ° C. or lower. Note that the second adhesive member 14 formed on the other surface side of the second semiconductor chip 15 has a relatively high viscosity because the collet 43 is cooled. Note that the cooling temperature of the collet 43 may be determined according to the viscosity required for the second adhesive member 14.

  Next, as shown in FIG. 4B, the collet 43 is lowered so that the second semiconductor chip 15 is moved toward the first semiconductor chip 13. The second adhesive member 14 is heated by radiant heat from the wiring mother board 30 and the first semiconductor chip 13, and the viscosity gradually decreases from the side facing the first semiconductor chip 13. As a result, a high viscosity portion 46 on the second semiconductor chip 15 side and a low viscosity portion 47 on the first semiconductor chip 13 side are formed in the second adhesive member 14. In particular, at the portion where the bonding wire 16-1 comes into contact, the viscosity of the second adhesive member 14 is reduced, and the bonding wire 16-1 enters the second adhesive member 14 as the collet descends.

  When the collet 52 is further lowered, the second adhesive member 14 comes into contact with the first semiconductor chip 13. Further, the collet 43 is pushed down with an appropriate pressing force, and the second adhesive member 14 is pressed and brought into close contact with the first semiconductor chip 13. As described above, the high-viscosity portion 46 exists on the first semiconductor chip 13 side of the second adhesive member 14. The high viscosity portion 46 functions as a stopper that suppresses the entry of the bonding wire 16-1. As a result, the contact of the bonding wire 16-1 with the other surface of the first semiconductor chip 13 is suppressed.

  As described above, the second semiconductor chip 15 is stacked on the first semiconductor chip 13 so that the space between the first semiconductor chip 13 and the second semiconductor chip 15 is filled with the second adhesive member 14. Is done.

  Note that the temperature of the collet 43 may rise during the above-described die bonding process. However, even if the temperature of the collet 43 rises, the above-described process can be repeated without any problem by cooling the collet cooler 44 to a predetermined temperature or lower before the die bonding process is performed.

  Further, in order to enhance the cooling effect of the collet 43, a heat radiating means may be provided. For example, the collet 51 shown in FIG. 5 includes a hole 52 as a heat dissipating means. By providing the hole 51, the surface area of the collet 51 is larger than that of the collet 43, and the heat dissipation efficiency is increased. Moreover, the temperature of the collet 51 can be more efficiently lowered by allowing the air 45 ejected from the collet cooler 44 to pass through the hole 52. Thereby, compared with the case where the collet 43 which does not have the hole part 52 is used, the contact with the 1st bonding wire 16-1 and the 2nd semiconductor chip 15 can be suppressed more stably.

  As described above, in the present embodiment, the second semiconductor chip 15 is mounted on the first semiconductor chip 13 with the collet 43 cooled and the adhesive member 14 having a relatively high viscosity. By doing so, without increasing the thickness of the adhesive member 14 or combining with another layer, that is, without increasing the size of the semiconductor device and increasing the material cost, Contact with the second semiconductor chip 15 can be suppressed.

  As mentioned above, although this invention was demonstrated based on some embodiment, it cannot be overemphasized that this invention is not limited to the said embodiment, and can be variously changed in the range which does not deviate from the summary.

  For example, in the above-described embodiment, the second semiconductor chip is die-bonded after being cooled by spraying air on the collet. However, the second semiconductor chip is mounted while air is sprayed on the collet. You may comprise so that die bonding may be carried out. As a result, the cooling time of the collet after die bonding of the second semiconductor chip and before the next die bonding process can be shortened, and the manufacturing efficiency can be improved.

  In the above embodiment, the case where the second semiconductor chip is stacked on the first semiconductor chip in which the electrode pad is arranged in the peripheral portion has been described. However, in the present invention, the electrode pad is formed in the central portion. The present invention can also be applied to the manufacture of a semiconductor device in which the second semiconductor chip is stacked on the first semiconductor chip.

  In the above embodiment, the case where the collet is cooled by spraying air on the collet by the collet cooler has been described. However, any configuration may be used as long as the collet can be cooled, for example, the collet itself. A cooling mechanism may be provided.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Wiring board 12 1st adhesive member 13 1st semiconductor chip 14 2nd adhesive member 15 2nd semiconductor chip 16-1 1st bonding wire 16-2 2nd bonding wire 17 Sealing body DESCRIPTION OF SYMBOLS 18 Solder ball 111 Insulating base material 112,113 Wiring layer 114 Via 115,116 Insulating film 117 Connection pad 118 Land 20 Semiconductor wafer 21 Dicing line 22 Electrode pad 23 BG tape 24 Adhesive material layer 25 Dicing tape 30 Wiring mother board 31 Dicing line 32 Sealing resin layer 41 Bonding stage 42 Heater 43 Collet 44 Collet cooler 45 Air 46 High viscosity part 47 Low viscosity part 51 Collet 52 Hole

Claims (5)

Connecting a bonding wire to one side of the first semiconductor chip;
An adhesive member is provided on one surface of the second semiconductor chip,
Holding the other surface of the second semiconductor chip using a collet;
Cooling the collet while holding the second semiconductor chip;
After cooling the collet, the collet is moved to bring the adhesive member into close contact with one surface of the first semiconductor chip, and the first semiconductor chip and the second semiconductor chip are interposed via the adhesive member. Glue
A method for manufacturing a semiconductor device.   The method of manufacturing a semiconductor device according to claim 1, wherein the cooling of the collet is performed so that the temperature is equal to or lower than a first predetermined temperature.   The method of manufacturing a semiconductor device according to claim 1, wherein the cooling of the collet is performed using air ejected from a nozzle.   4. The semiconductor according to claim 1, wherein the first semiconductor chip is heated to a second predetermined temperature or more before the adhesive member is pressed against one surface of the first semiconductor chip. 5. Device manufacturing method.   5. The method of manufacturing a semiconductor device according to claim 1, wherein a collet having at least one through-hole through which the air passes is used as the collet.

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