KR20230033965A - 3d flash memory with extended memory window - Google Patents

Abstract

Disclosed is a three-dimensional flash memory with an extended memory window, which can implement multi-level cells. According to one embodiment of the present invention, the three-dimensional flash memory may comprise: word lines which are formed to horizontally extend and are disposed to be spaced apart from each other in a vertical direction; and vertical channel structures which penetrate the word lines and are formed to extend in the vertical direction. Each of the vertical channel structures includes a vertical channel pattern formed to extend in the vertical direction, and a tunneling oxide-charge trap nitride-blocking oxide formed to cover the vertical channel pattern. At least one of a tunneling oxide layer or blocking oxide layer of the ONO is formed of a ferroelectric material. The ONO and the vertical channel pattern are composed of memory cells corresponding to the word lines.

Description

3D flash memory with extended memory window {3D FLASH MEMORY WITH EXTENDED MEMORY WINDOW}

The following embodiments relate to a three-dimensional flash memory, and more specifically, a technology for a three-dimensional flash memory with an extended memory window.

A flash memory device is an electrically erasable programmable read only memory (EEPROM) by electrically controlling the input and output of data by Fowler-Nordheimtunneling or hot electron injection. , can be commonly used in computers, digital cameras, MP3 players, game systems, memory sticks, and the like.

In such a flash memory device, a three-dimensional structure in which memory cell transistors are arranged in a vertical direction to form a cell string has been proposed to increase the degree of integration in order to meet the excellent performance and low price demanded by consumers.

However, since the 3D flash memory is also subject to limitations of limited physical size and degree of integration, research and development on technology for realizing multi-valued data to be stored has recently been conducted.

However, since the existing data multi-level implementation technology has a limitation in implementing only a 4-bit level with a 7V-level memory window, a technique for extending the memory window to implement 5 bits or more needs to be proposed.

Embodiments use both a charge trap nitride layer of ONO (Tunneling Oxide-Charge trap Nitride-Blocking Oxide) and a layer formed of a ferroelectric material as a data storage element to expand a memory window and implement multi-value. We propose a 3D flash memory to use.

However, the technical problems to be solved by the present invention are not limited to the above problems, and can be variously expanded without departing from the technical spirit and scope of the present invention.

According to one embodiment, a three-dimensional flash memory may include word lines extending in a horizontal direction and spaced apart in a vertical direction; and vertical channel structures penetrating the word lines and extending in the vertical direction, each of the vertical channel structures extending in the vertical direction and forming a tunneling oxide (ONO) formed surrounding the vertical channel pattern. -Charge trap Nitride-Blocking Oxide), at least one of a tunneling oxide layer and a blocking oxide layer of the ONO is formed of a ferroelectric material, and the ONO and the vertical channel pattern correspond to the word line. Constituting - may include.

According to one aspect, the 3D flash memory uses a charge trap nitride layer of the ONO as a primary data storage element, and at least one of the tunneling oxide layer and the blocking oxide layer formed of the ferroelectric material is used. It may be characterized in that it is used as a secondary data storage element.

According to another aspect, the 3D flash memory may include a primary programming operation of generating FN tunneling by applying a program voltage of a positive value to a target memory cell to be programmed among the plurality of memory cells, and the target memory A secondary program for raising the threshold voltage of the target memory cell by applying a negative program voltage to the cell to generate a polarization phenomenon in a region corresponding to the target memory cell among at least one layer formed of the ferroelectric material. It may be characterized by performing a two-step program operation including an operation.

According to another aspect, the 3D flash memory may apply the program voltage of the positive value to the target memory cell to generate a positive value in a region corresponding to the target memory cell among at least one layer formed of the ferroelectric material. The threshold voltage of the target memory cell is lowered to a negative region by placing charges of at an interface with the charge trapping nitride layer, and a program voltage of a negative value is applied to the target memory cell to at least one formed of the ferroelectric material. It may be characterized in that a threshold voltage of the target memory cell is raised to a positive region by locating negative charges at an interface with the charge trap nitride layer in a region corresponding to the target memory cell of one layer.

According to another aspect, the 3D flash memory includes a primary erase operation of injecting holes into the charge trap nitride layer based on a GIDL method in the plurality of memory cells and the plurality of word lines among the plurality of word lines. In a second program operation, a positive erase voltage is applied to a word line corresponding to the target memory cell whose threshold voltage is raised to polarize a region corresponding to the target memory cell among at least one layer formed of the ferroelectric material. It may be characterized in that a two-step erase operation including a second erase operation in which a threshold voltage of the target memory cell is lowered by generating a phenomenon is performed.

Embodiments use both a charge trap nitride layer of ONO (Tunneling Oxide-Charge trap Nitride-Blocking Oxide) and a layer formed of a ferroelectric material as a data storage element, thereby expanding a memory window and enabling multi-leveling. It is possible to propose a 3D flash memory to implement.

However, the effects of the present invention are not limited to the above effects, and can be variously extended without departing from the technical spirit and scope of the present invention.

1 is a simplified circuit diagram illustrating an array of three-dimensional flash memories according to one embodiment.
2 is a plan view illustrating the structure of a 3D flash memory according to an exemplary embodiment.
FIG. 3 is a cross-sectional view showing the structure of a 3D flash memory according to an exemplary embodiment, and corresponds to a cross-section of FIG. 2 taken along line A-A'.
FIG. 4 is an enlarged cross-sectional view of an area 300 in the 3D flash memory shown in FIG. 3 .
5A to 5C are diagrams for explaining a two-step programming operation of a 3D flash memory according to an exemplary embodiment.
6A and 6B are diagrams for explaining a two-step erase operation of a 3D flash memory according to an exemplary embodiment.
7 is a perspective view schematically illustrating an electronic system including a 3D flash memory according to embodiments.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited by the examples. Also, like reference numerals in each figure denote like members.

In addition, terms used in this specification (terminology) are terms used to appropriately express preferred embodiments of the present invention, which may vary according to the intention of a viewer or operator or customs in the field to which the present invention belongs. Therefore, definitions of these terms will have to be made based on the content throughout this specification. For example, in this specification, singular forms also include plural forms unless specifically stated otherwise in a phrase. Also, as used herein, "comprises" and/or "comprising" means that a referenced component, step, operation, and/or element is one or more other components, steps, operations, and/or elements. The presence or addition of elements is not excluded. In addition, although terms such as first and second are used in this specification to describe various regions, directions, shapes, etc., these regions, directions, and shapes should not be limited by these terms. These terms are only used to distinguish one area, direction or shape from another area, direction or shape. Accordingly, a portion referred to as a first portion in one embodiment may be referred to as a second portion in another embodiment.

Also, it should be understood that the various embodiments of the present invention are different from each other but are not necessarily mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in one embodiment in another embodiment without departing from the spirit and scope of the present invention. In addition, it should be understood that the location, arrangement, or configuration of individual components in the scope of each embodiment presented may be changed without departing from the spirit and scope of the present invention.

Hereinafter, a 3D flash memory according to embodiments, an operating method thereof, and an electronic system including the same will be described in detail with reference to the drawings.

1 is a simplified circuit diagram illustrating an array of three-dimensional flash memories according to one embodiment.

Referring to FIG. 1 , a three-dimensional flash memory array according to an embodiment includes a common source line CSL, a plurality of bit lines BL0, BL1, and BL2, and the common source line CSL and bit lines BL0. , BL1, and BL2) may include a plurality of cell strings CSTR.

The bit lines BL0 , BL1 , and BL2 may be two-dimensionally arranged while being spaced apart from each other along the first direction D1 while extending in the second direction D2 . Here, each of the first direction D1 , the second direction D2 , and the third direction D3 are orthogonal to each other and may form a rectangular coordinate system defined by X, Y, and Z axes.

A plurality of cell strings CSTR may be connected in parallel to each of the bit lines BL0 , BL1 , and BL2 . The cell strings CSTR may be connected in common to the common source line CSL while being provided between the bit lines BL0 , BL1 , and BL2 and one common source line CSL. In this case, a plurality of common source lines CSL may be provided, and the plurality of common source lines CSL are spaced apart from each other along the second direction D2 while extending in the first direction D1 and have a two-dimensional can be arranged sequentially. The same voltage may be electrically applied to the plurality of common source lines CSL, but different voltages may be applied as each of the plurality of common source lines CSL is electrically independently controlled without being limited or limited thereto. there is.

The cell strings CSTR may be spaced apart from each other along the second direction D2 for each bit line while extending in the third direction D3 and may be arranged. According to an embodiment, each of the cell strings CSTR includes a ground select transistor GST connected to the common source line CSL and first and second strings connected in series to bit lines BL0, BL1, and BL2. Select transistors SST1 and SST2, memory cell transistors MCT connected in series while being disposed between the ground select transistor GST and the first and second string select transistors SST1 and SST2, and an erase control transistor ECT ) can be configured. Also, each of the memory cell transistors MCT may include a data storage element.

For example, each of the cell strings CSTR may include first and second string select transistors SST1 and SST2 connected in series, and the second string select transistor SST2 may include bit lines BL0 and BL1 , BL2). However, without being limited thereto, each of the cell strings CSTR may include one string select transistor. As another example, the ground select transistor GST in each of the cell strings CSTR may be composed of a plurality of MOS transistors connected in series similarly to the first and second string select transistors SST1 and SST2. .

One cell string CSTR may include a plurality of memory cell transistors MCT having different distances from the common source lines CSL. That is, the memory cell transistors MCT may be connected in series while being disposed along the third direction D3 between the first string select transistor SST1 and the ground select transistor GST. The erase control transistor ECT may be connected between the ground select transistor GST and the common source lines CSL. Each of the cell strings CSTR is formed between the first string select transistor SST1 and the uppermost one of the memory cell transistors MCT and between the ground select transistor GST and the lowermost one of the memory cell transistors MCT. Dummy cell transistors DMC connected to each other may be further included.

According to an embodiment, the first string select transistor SST1 may be controlled by the first string select lines SSL1-1, SSL1-2, and SSL1-3, and the second string select transistor SST2 may be It can be controlled by 2 string select lines (SSL2-1, SSL2-2, SSL2-3). The memory cell transistors MCT may be respectively controlled by a plurality of word lines WL0 - WLn, and the dummy cell transistors DMC may be respectively controlled by a dummy word line DWL. The ground select transistor GST may be controlled by the ground select lines GSL0 , GSL1 , and GSL2 , and the erase control transistor ECT may be controlled by the erase control line ECL. A plurality of erasure control transistors ECT may be provided. Common source lines CSL may be commonly connected to sources of erase control transistors ECT.

Gate electrodes of the memory cell transistors MCT, which are provided at substantially the same distance from the common source lines CSL, may be connected in common to one of the word lines WL0 - WLn and DWL to be in an equipotential state. . However, without being limited thereto, even if the gate electrodes of the memory cell transistors MCT are provided at substantially the same level from the common source lines CSL, the gate electrodes provided in different rows or columns may be independently controlled. there is.

Ground select lines (GSL0, GSL1, GSL2), first string select lines (SSL1-1, SSL1-2, SSL1-3) and second string select lines (SSL2-1, SSL2-2, SSL2-3) ) may extend along the first direction D1, be spaced apart from each other in the second direction D2, and be two-dimensionally arranged. ground selection lines GSL0, GSL1, and GSL2 provided at substantially the same level from the common source lines CSL, first string selection lines SSL1-1, SSL1-2, SSL1-3, and a second string The selection lines SSL2-1, SSL2-2, and SSL2-3 may be electrically separated from each other. Also, erase control transistors ECT of different cell strings CSTR may be controlled by a common erase control line ECL. The erase control transistors ECT may generate gate induced drain leakage (GIDL) during an erase operation of the memory cell array. In some embodiments, an erase voltage may be applied to the bit lines BL0 , BL1 , and BL2 and/or the common source lines CSL during an erase operation of the memory cell array, and the string select transistor SST and/or Alternatively, gate induced leakage current may be generated in the erasure control transistors ECT.

The above-described string selection line SSL may be expressed as an upper selection line USL, and the ground selection line GSL may be expressed as a lower selection line.

2 is a plan view illustrating the structure of a 3D flash memory according to an exemplary embodiment. FIG. 3 is a cross-sectional view showing the structure of a 3D flash memory according to an exemplary embodiment, and corresponds to a cross-section of FIG. 2 taken along line A-A'. 4 is an enlarged cross-sectional view of an area 300 of the 3D flash memory shown in FIG. 3, and FIGS. 5A to 5C are diagrams for explaining a two-step program operation of the 3D flash memory according to an exemplary embodiment. FIGS. 6A and 5C 6b is a diagram for explaining a two-step erase operation of a 3D flash memory according to an exemplary embodiment.

Referring to FIGS. 2 to 6B , the substrate SUB may be a semiconductor substrate such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a monocrystalline epitaxial layer grown on a monocrystalline silicon substrate. . The substrate SUB may be doped with first conductivity-type impurities (eg, P-type impurities).

Stacked structures ST may be disposed on the substrate SUB. The stacked structures ST may be two-dimensionally disposed along the second direction D2 while extending in the first direction D1. In addition, the stacked structures ST may be spaced apart from each other in the second direction D2.

Each of the stacked structures ST includes gate electrodes EL1 , EL2 , and EL3 alternately stacked in a vertical direction perpendicular to the upper surface of the substrate SUB (eg, in the third direction D3 ), and interlayer insulating films ILD. can include The stacked structures ST may have substantially flat upper surfaces. That is, top surfaces of the stacked structures ST may be parallel to the top surface of the substrate SUB. Hereinafter, the vertical direction means the third direction D3 or a direction opposite to the third direction D3.

Referring back to FIG. 1 , each of the gate electrodes EL1 , EL2 , and EL3 includes an erase control line ECL, ground select lines GSL0 , GSL1 , and GSL2 sequentially stacked on the substrate SUB, and a word line. (WL0-WLn, DWL), one of the first string selection lines (SSL1-1, SSL1-2, SSL1-3) and the second string selection lines (SSL2-1, SSL2-2, SSL2-3) can be

Each of the gate electrodes EL1 , EL2 , and EL3 may have substantially the same thickness in the third direction D3 while extending in the first direction D1 . Hereinafter, the thickness means the thickness in the third direction D3. Each of the gate electrodes EL1 , EL2 , and EL3 may be formed of a conductive material. For example, each of the gate electrodes EL1 , EL2 , EL3 may be a doped semiconductor (ex, doped silicon, etc.), a metal (ex, W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), It may include at least one selected from Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.) or conductive metal nitride (ex, titanium nitride, tantalum nitride, etc.). Each of the gate electrodes EL1 , EL2 , and EL3 may include at least one of all metal materials that can be formed by ALD in addition to the metal material described above.

More specifically, the gate electrodes EL1 , EL2 , and EL3 include a lowermost first gate electrode EL1 , an uppermost third gate electrode EL3 , and the first and third gate electrodes EL1 and EL3 . A plurality of second gate electrodes EL2 may be included therebetween. Although each of the first gate electrode EL1 and the third gate electrode EL3 is shown and described in the singular number, this is exemplary and not limited thereto, and the first gate electrode EL1 and the third gate electrode EL3 may be used as necessary. may be provided in plural. The first gate electrode EL1 may correspond to one of the ground selection lines GSL0 , GSL1 , and GLS2 shown in FIG. 1 . The second gate electrode EL2 may correspond to one of the word lines WL0 - WLn and DWL shown in FIG. 1 . The third gate electrode EL3 includes any one of the first string select lines SSL1-1, SSL1-2 and SSL1-3 of FIG. 1 shown in FIG. 1 or the second string select lines SSL2-1 and SSL2-1. SSL2-2, SSL2-3) may correspond to any one.

Although not shown, an end of each of the stacked structures ST may have a stepwise structure along the first direction D1. More specifically, the lengths of the gate electrodes EL1 , EL2 , and EL3 of the stack structures ST in the first direction D1 may decrease as the distance from the substrate SUB increases. The third gate electrode EL3 may have the smallest length in the first direction D1 and the largest distance from the substrate SUB in the third direction D3. The first gate electrode EL1 may have the longest length in the first direction D1 and the shortest distance from the substrate SUB in the third direction D3. Due to the stepped structure, the thickness of each of the stacked structures ST may decrease as the distance from the outermost one of the vertical channel structures VS described later increases, and the gate electrodes EL1, Sidewalls of EL2 and EL3 may be spaced apart at regular intervals along the first direction D1 when viewed in plan.

Each of the interlayer insulating layers ILD may have different thicknesses. For example, the lowermost and uppermost interlayer insulating layers ILD may have a smaller thickness than other interlayer insulating layers ILD. However, this is illustrative and not limited thereto, and the thickness of each of the interlayer insulating layers ILD may be different from each other according to the characteristics of the semiconductor device or all may be set to be the same. The interlayer insulating layers ILD may be formed of an insulating material to insulate between the gate electrodes EL1 , EL2 , and EL3 . For example, the interlayer insulating layers ILD may be formed of silicon oxide.

Although it has been described that interlayer insulating layers ILD are included in each of the stacked structures ST, air gaps may be included in each of the stacked structures ST instead of the interlayer insulating layers ILD. In this case, the air gaps may be alternately disposed with the gate electrodes EL1 , EL2 , and EL3 as in the interlayer insulating layer ILD to enable insulation between the gate electrodes EL1 , EL2 , and EL3 .

A plurality of channel holes CH penetrating portions of the stacked structures ST and the substrate SUB may be provided. Vertical channel structures VS may be provided in the channel holes CH. The vertical channel structures VS are the plurality of cell strings CSTR shown in FIG. 1 , and may extend in the third direction D3 while being connected to the substrate SUB. The connection of the vertical channel structures VS with the substrate SUB may be achieved by partially burying a portion of each of the vertical channel structures VS in the substrate SUB, but is not limited thereto, and the vertical channel structures VS are not limited thereto. The lower surface of (VS) may be made by contacting the upper surface of the substrate (SUB). When portions of each of the vertical channel structures VS are buried in the substrate SUB, lower surfaces of the vertical channel structures VS may be positioned at a lower level than the upper surface of the substrate SUB.

A plurality of columns of vertical channel structures VS passing through any one of the stacked structures ST may be provided. For example, as shown in FIG. 2 , columns of two vertical channel structures VS may pass through one of the stacked structures ST. However, without being limited thereto, three or more columns of vertical channel structures VS may pass through one of the stacked structures ST. In a pair of adjacent columns, the vertical channel structures VS corresponding to one column may be shifted in the first direction D1 from the vertical channel structures VS corresponding to the other adjacent column. there is. When viewed from a plan view, the vertical channel structures VS may be arranged in a zigzag shape along the first direction D1. However, without being limited thereto, the vertical channel structures VS may form an array arranged side by side in rows and columns.

Each of the vertical channel structures VS may extend from the substrate SUB in the third direction D3. In the drawing, each of the vertical channel structures VS is shown as having a column shape having the same width at the top and bottom, but is not limited thereto, and is not limited thereto. It may have a shape in which the width to (D2) is increased. This is due to the limitation that, when the channel holes CH are etched, the widths in the first direction D1 and the second direction D2 decrease toward the opposite direction of the third direction D3. The upper surface of each of the vertical channel structures VS may have a circular shape, an elliptical shape, a rectangular shape, or a bar shape.

Each of the vertical channel structures VS may include a tunneling oxide-charge trap nitride-blocking oxide (ONO), a vertical channel pattern VCP, a vertical semiconductor pattern VSP, and a conductive pad PAD. In each of the vertical channel structures VS, the ONO may have a pipe shape or macaroni shape with an open bottom, and the vertical channel pattern VCP may have a pipe shape or macaroni shape with a closed bottom. . The vertical semiconductor pattern VSP may fill a space surrounded by the vertical channel pattern VCP and the conductive pad PAD.

The ONO may cover inner walls of each of the channel holes CH, inwardly contact the vertical channel pattern VCP, and outwardly contact sidewalls of the gate electrodes EL1 , EL2 , and EL3 . Accordingly, the regions corresponding to the second gate electrodes EL2 of the ONO, together with the regions corresponding to the second gate electrodes EL2 of the vertical channel pattern VCP, through the second gate electrodes EL2. Memory cells in which a memory operation (program operation, read operation, or erase operation) is performed by an applied voltage may be configured. The memory cells correspond to the memory cell transistors MCT shown in FIG. 1 .

At this time, at least one of the tunneling oxide layer and the blocking oxide layer of the ONO may be formed of a ferroelectric material as shown in FIG. 4 . For example, the tunneling oxide layer is formed of a ferroelectric material as in CASE 1 of FIG. 4, the blocking oxide layer is formed of a ferroelectric material as in CASE 2, or both the tunneling oxide layer and the blocking oxide layer are ferroelectric materials as in CASE 3. can be formed as In this case, the rest of the tunneling oxide layer or the blocking oxide layer, which is not formed of a ferroelectric material, may be formed of the same material as the conventional tunneling oxide layer or the conventional blocking oxide layer.

Hereinafter, the ferroelectric material is HfO _x having an orthorhombic crystal structure, HfO _x doped with at least one of Al, Zr or Si, PZT (Pb(Zr, Ti)O ₃ ), PTO (PbTiO ₃ ) , SBT (SrBi ₂ Ti ₂ O ₃ ), BLT (Bi(La, Ti)O ₃ ), PLZT (Pb(La, Zr)TiO ₃ ), BST (Bi(Sr, Ti)O ₃ ), barium titanate ( At least one of barium titanate, BaTiO ₃ ), P(VDF-TrFE), PVDF, AlO _x , ZnO _x , TiO _x , TaO _x or InO _x may be included. The ferroelectric material may include various materials having hysteresis characteristics without being limited or limited to the examples described.

Accordingly, the charge trap nitride layer of ONO may be used as a primary data storage element that traps charges or holes by a voltage applied through the second gate electrode EL2, and the tunneling oxide layer of ONO or At least one layer formed of a ferroelectric material among the blocking oxide layers may be used as a secondary data storage element that maintains a state of charges (eg, a polarization state of charges) by a voltage applied through the second gate electrode EL2. there is.

That is, the 3D flash memory simultaneously uses both the charge trapping nitride layer of ONO and at least one layer formed of a ferroelectric material among the tunneling oxide layer and blocking oxide layer of ONO as data storage elements, thereby changing trapped charges or holes. And, it can represent a multi-valued data value by changing the state of charges. A detailed description of this will be described below.

A vertical channel pattern (VCP) may cover an inner wall of the ONO. The vertical channel pattern VCP may include a first portion VCP1 and a second portion VCP2 on the first portion VCP1.

The first portion VCP1 of the vertical channel pattern VCP may be provided under each of the channel holes CH and may contact the substrate SUB. The first portion VCP1 of the vertical channel pattern VCP may be used to block, suppress, or minimize leakage current in each of the vertical channel structures VS and/or to form an epitaxial pattern. A thickness of the first portion VCP1 of the vertical channel pattern VCP may be greater than, for example, a thickness of the first gate electrode EL1. A sidewall of the first portion VCP1 of the vertical channel pattern VCP may be surrounded by ONO. A top surface of the first portion VCP1 of the vertical channel pattern VCP may be positioned at a higher level than a top surface of the first gate electrode EL1. More specifically, the top surface of the first part VCP1 of the vertical channel pattern VCP may be positioned between the top surface of the first gate electrode EL1 and the bottom surface of the lowermost one of the second gate electrodes EL2. A lower surface of the first portion VCP1 of the vertical channel pattern VCP may be positioned at a lower level than an uppermost surface of the substrate SUB (ie, a lower surface of a lowermost one of the interlayer insulating layers ILD). A portion of the first portion VCP1 of the vertical channel pattern VCP may overlap the first gate electrode EL1 in a horizontal direction. Hereinafter, the horizontal direction refers to an arbitrary direction extending on a plane parallel to the first and second directions D1 and D2.

The second portion VCP2 of the vertical channel pattern VCP may extend in the third direction D3 from the upper surface of the first portion VCP1. The second portion VCP2 of the vertical channel pattern VCP may be provided between the ONO and the vertical semiconductor pattern VSP, and may correspond to the second gate electrodes EL2. Accordingly, as described above, the second part VCP2 of the vertical channel pattern VCP may constitute memory cells together with regions corresponding to the second gate electrodes EL2 of the ONO.

A top surface of the second part VCP2 of the vertical channel pattern VCP may be substantially coplanar with a top surface of the vertical semiconductor pattern VSP. A top surface of the second part VCP2 of the vertical channel pattern VCP may be positioned at a level higher than a top surface of an uppermost one of the second gate electrodes EL2 . More specifically, the upper surface of the second portion VCP2 of the vertical channel pattern VCP may be positioned between the upper and lower surfaces of the third gate electrode EL3 .

The vertical channel pattern VCP may be formed of monocrystalline silicon or polysilicon to form a channel or to be boosted by an applied voltage. However, without being limited thereto, the vertical channel pattern VCP may be formed of an oxide semiconductor material capable of blocking, suppressing, or minimizing leakage current. For example, the vertical channel pattern VCP may be formed of an oxide semiconductor material including at least one of In, Zn, and Ga having excellent leakage current characteristics, or a Group 4 semiconductor material. The vertical channel pattern VCP may be formed of, for example, a ZnOx-based material including AZO, ZTO, IZO, ITO, IGZO, or Ag-ZnO. Accordingly, the vertical channel pattern VCP may block, suppress, or minimize leakage current to the gate electrodes EL1 , EL2 , and EL3 or the substrate SUB, and at least one of the gate electrodes EL1 , EL2 , and EL3 Any one transistor characteristic (eg, threshold voltage distribution and program/read speed) may be improved, and consequently, electrical characteristics of the 3D flash memory may be improved.

The vertical semiconductor pattern VSP may be surrounded by the second portion VCP2 of the vertical channel pattern VCP. An upper surface of the vertical semiconductor pattern VSP may contact the conductive pad PAD, and a lower surface of the vertical semiconductor pattern VSP may contact the first portion VCP1 of the vertical channel pattern VCP. The vertical semiconductor pattern VSP may be spaced apart from the substrate SUB in the third direction D3. In other words, the vertical semiconductor pattern VSP may be electrically floated from the substrate SUB.

The vertical semiconductor pattern VSP may be formed of a material that helps diffusion of charges or holes in the vertical channel pattern VCP. More specifically, the vertical semiconductor pattern VSP may be formed of a material having excellent charge and hole mobility. For example, the vertical semiconductor pattern VSP may be formed of a semiconductor material doped with impurities, an intrinsic semiconductor material not doped with impurities, or a polycrystalline semiconductor material. For a more specific example, the vertical semiconductor pattern VSP may be formed of polysilicon doped with impurities of the same first conductivity type as the substrate SUB (eg, P-type impurities). That is, the vertical semiconductor pattern VSP can improve the electrical characteristics of the 3D flash memory to increase the speed of memory operation.

Referring back to FIG. 1 , the vertical channel structures VS include an erase control transistor ECT, first and second string select transistors SST1 and SST2 , a ground select transistor GST, and memory cell transistors MCT. ) may correspond to channels of

Conductive pads PAD may be provided on top surfaces of the second portion VCP2 of the vertical channel pattern VCP and on top surfaces of the vertical semiconductor pattern VSP. The conductive pad PAD may be connected to an upper portion of the vertical channel pattern VCP and an upper portion of the vertical semiconductor pattern VSP. A sidewall of the conductive pad PAD may be surrounded by ONO. A top surface of the conductive pad PAD may be substantially coplanar with a top surface of each of the stack structures ST (ie, a top surface of an uppermost one of the interlayer insulating layers ILD). A lower surface of the conductive pad PAD may be positioned at a lower level than an upper surface of the third gate electrode EL3 . More specifically, the lower surface of the conductive pad PAD may be positioned between the upper and lower surfaces of the third gate electrode EL3 . That is, at least a portion of the conductive pad PAD may overlap the third gate electrode EL3 in a horizontal direction.

The conductive pad PAD may be formed of a semiconductor doped with impurities or a conductive material. For example, the conductive pad PAD is doped with an impurity different from that of the vertical semiconductor pattern VSP (more precisely, an impurity of a second conductivity type (eg, N-type) different from the first conductivity type (eg, P-type)). It may be formed of a semiconductor material.

The conductive pad PAD may reduce contact resistance between the bit line BL and the vertical channel pattern VCP (or vertical semiconductor pattern VSP), which will be described later.

Although the vertical channel structures VS have been described as having a structure including the conductive pad PAD, it is not limited thereto and may have a structure in which the conductive pad PAD is omitted. In this case, as the conductive pad PAD is omitted from the vertical channel structures VS, the upper surfaces of each of the vertical channel pattern VCP and the vertical semiconductor pattern VSP are the upper surfaces of each of the stacked structures ST (ie, Each of the vertical channel pattern VCP and the vertical semiconductor pattern VSP may extend in the third direction D3 so as to be substantially coplanar with the top surface of the uppermost one of the interlayer insulating layers ILD. Also, in this case, the bit line contact plug BLPG, which will be described later, directly contacts the vertical channel pattern VCP instead of being indirectly electrically connected to the vertical channel pattern VCP through the conductive pad PAD. can be electrically connected.

Also, although it has been described that the vertical channel structures VS include the vertical semiconductor pattern VSP, the vertical semiconductor pattern VSP may be omitted without being limited or limited thereto.

In addition, although the vertical channel pattern VCP has been described as having a structure including the first part VCP1 and the second part VCP2, it is not limited thereto and may have a structure excluding the first part VCP1. can For example, the vertical channel pattern VCP may be provided between the vertical semiconductor pattern VSP and ONO extending to the substrate SUB and may extend to the substrate SUB to contact the substrate SUB. In this case, the lower surface of the vertical channel pattern VCP may be positioned at a lower level than the uppermost surface of the substrate SUB (the lower surface of the lowermost one of the interlayer insulating films ILD), and the upper surface of the vertical channel pattern VCP may be located at a level lower than that of the upper surface of the substrate SUB. A top surface of the pattern VSP may be substantially coplanar.

An isolation trench TR extending in the first direction D1 may be provided between the stacked structures ST adjacent to each other. The common source region CSR may be provided inside the substrate SUB exposed by the isolation trench TR. The common source region CSR may extend in the first direction D1 within the substrate SUB. The common source region CSR may be formed of a semiconductor material doped with impurities of the second conductivity type (eg, N-type impurities). The common source region CSR may correspond to the common source line CSL of FIG. 1 .

A common source plug CSP may be provided in the isolation trench TR. The common source plug CSP may be connected to the common source region CSR. A top surface of the common source plug CSP may be substantially coplanar with a top surface of each of the stacked structures ST (ie, a top surface of an uppermost one of the interlayer insulating layers ILD). The common source plug CSP may have a plate shape extending in the first and third directions D1 and D3. In this case, the common source plug CSP may have a shape in which a width in the second direction D2 increases toward the third direction D3.

Insulation spacers SP may be interposed between the common source plug CSP and the stacked structures ST. Insulation spacers SP may be provided to face each other between adjacent stacked structures ST. For example, the insulating spacers SP may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

A capping insulating layer CAP may be provided on the stacked structures ST, the vertical channel structures VS, and the common source plug CSP. The capping insulating layer CAP may cover the top surface of the uppermost one of the interlayer insulating layers ILD, the top surface of the conductive pad PAD, and the top surface of the common source plug CSP. The capping insulating layer CAP may be formed of an insulating material different from that of the interlayer insulating layers ILD. A bit line contact plug BLPG electrically connected to the conductive pad PAD may be provided inside the capping insulating layer CAP. The bit line contact plug BLPG may have a shape in which widths in the first and second directions D1 and D2 increase in the third direction D3.

A bit line BL may be provided on the capping insulating layer CAP and the bit line contact plug BLPG. The bit line BL corresponds to any one of the plurality of bit lines BL0 , BL1 , and BL2 shown in FIG. 1 , and may be formed of a conductive material to extend along the second direction D2 . The conductive material constituting the bit line BL may be the same material as the conductive material forming each of the gate electrodes EL1 , EL2 , and EL3 described above.

The bit line BL may be electrically connected to the vertical channel structures VS through the bit line contact plug BLPG. Here, that the bit line BL is connected to the vertical channel structures VS may mean that it is connected to the vertical channel pattern VCP included in the vertical channel structures VS.

The three-dimensional flash memory having such a structure includes a voltage applied to each of the cell strings CSTR, a voltage applied to the string selection line SSL, a voltage applied to each of the word lines WL0-WLn, and a ground selection line. A program operation, a read operation, and an erase operation may be performed based on the voltage applied to the GSL and the voltage applied to the common source line CSL. For example, the 3D flash memory includes a voltage applied to each of the cell strings CSTR, a voltage applied to the string select line SSL, a voltage applied to each of the word lines WL0 to WLn, and a ground select line GSL. ) and a voltage applied to the common source line CSL, a channel may be formed in the vertical channel pattern VCP to perform a program operation.

In particular, as described above, the three-dimensional flash memory uses the feature of simultaneously using both the charge trapping nitride layer of ONO and at least one layer formed of a ferroelectric material among the tunneling oxide layer or blocking oxide layer of ONO as a data storage element. Thus, it is possible to perform a program operation that expands the memory window and implements multi-value.

More specifically, in a 3D flash memory, a first programming operation in which FN tunneling occurs by applying a positive program voltage to a target memory cell to be programmed among a plurality of memory cells and a negative value to the target memory cell A two-step program operation including a secondary program operation of increasing the threshold voltage of the target memory cell by generating a polarization phenomenon in a region corresponding to the target memory cell among at least one layer formed of a ferroelectric material by applying a program voltage of It can be characterized by performing.

For example, a 3D flash memory includes at least one layer formed of a ferroelectric material by applying a positive program voltage (eg, 20V) to a target memory cell as shown in FIG. 5A to generate FN tunneling. (hereinafter, the blocking oxide layer will be described as being formed of a ferroelectric material), the threshold voltage of the target memory cell is set in a negative region by placing positive charges at the interface with the charge trap nitride layer in the region corresponding to the target memory cell. It is possible to perform the first program operation to descend to . Subsequently, as shown in FIG. 5B, the 3D flash memory applies a negative program voltage (eg, -10V) to the target memory cell to form a region corresponding to the target memory cell among at least one layer formed of a ferroelectric material. A secondary program operation may be performed in which a threshold voltage of a target memory cell is raised to a positive region by placing negative charges at an interface with the charge trap nitride layer within the memory cell.

Therefore, by the two-step program described, the memory window can be expanded from the conventional 7V level as shown in FIG. 5C to the 9 to 10V level as shown in FIG. can

Regarding the erase operation, the 3D flash memory is characterized by performing a two-step erase operation similarly to the program operation. More specifically, the 3D flash memory has a threshold voltage in a first erase operation of injecting holes into a charge trap nitride layer based on the GIDL method into a plurality of memory cells and a second program operation among a plurality of word lines. By applying a positive erase voltage to the word line corresponding to the raised target memory cell, a polarization phenomenon is generated in a region corresponding to the target memory cell among at least one layer formed of a ferroelectric material, thereby lowering the threshold voltage of the target memory cell. A two-step erase operation including a second erase operation may be performed.

For example, a 3D flash memory, as shown in FIG. 6A, performs a primary erase operation in which holes are injected into a charge trap nitride layer based on the GIDL method in a plurality of memory cells, and then, as shown in FIG. 6B As described above, a positive erase voltage is applied to a word line corresponding to a target memory cell whose threshold voltage is raised in a secondary program operation among a plurality of word lines, and a corresponding memory cell among at least one layer formed of a ferroelectric material is applied. A secondary erase operation may be performed in which a threshold voltage of a target memory cell is lowered (the threshold voltage raised in a secondary program operation is reduced) by placing positive charges in the region at an interface with the charge trap nitride layer.

7 is a perspective view schematically illustrating an electronic system including a 3D flash memory according to embodiments.

Referring to FIG. 7 , an electronic system 700 including a 3D flash memory according to embodiments includes a main board 701, a controller 702 mounted on the main board 701, and one or more semiconductor packages 703. ) and DRAM 704.

The semiconductor package 703 and the DRAM 704 may be connected to the controller 702 through wiring patterns 705 provided on the main substrate 701 .

The main board 701 may include a connector 706 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 706 may vary depending on the communication interface between the electronic system 700 and an external host.

The electronic system 700 may use any of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCIExpress), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS), for example. Depending on one, you can communicate with external hosts. The electronic system 700 may be operated by power supplied from an external host through, for example, a connector 706 . The electronic system 700 may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from an external host to the controller 702 and the semiconductor package 703 .

The controller 702 can write data to the semiconductor package 703 or read data from the semiconductor package 703 and can improve the operating speed of the electronic system 700 .

The DRAM 704 may be a buffer memory for mitigating a speed difference between the semiconductor package 703, which is a data storage space, and an external host. The DRAM 704 included in the electronic system 700 may also operate as a kind of cache memory, and may provide a space for temporarily storing data in a control operation for the semiconductor package 703 . When the electronic system 700 includes the DRAM 704 , the controller 702 may further include a DRAM controller for controlling the DRAM 704 in addition to the NAND controller for controlling the semiconductor package 703 .

The semiconductor package 703 may include first and second semiconductor packages 703a and 703b spaced apart from each other. Each of the first and second semiconductor packages 703a and 703b may be a semiconductor package including a plurality of semiconductor chips 720 . Each of the first and second semiconductor packages 703a and 703b includes a package substrate 710 , semiconductor chips 720 on the package substrate 710 , and adhesive layers 730 disposed on lower surfaces of each of the semiconductor chips 720 . ), connection structures 740 electrically connecting the semiconductor chips 720 and the package substrate 710 and a molding layer 750 covering the semiconductor chips 720 and the connection structures 740 on the package substrate 710 can include

The package substrate 710 may be a printed circuit board including package upper pads 711 . Each of the semiconductor chips 720 may include input/output pads 721 . Each of the semiconductor chips 720 may include the aforementioned 3D flash memory (a 3D flash memory that extends the aforementioned memory window). More specifically, each of the semiconductor chips 720 may include gate stack structures 722 and memory channel structures 723 . The gate stack structures 722 may correspond to the above-described stack structures ST, and the memory channel structures 723 may correspond to the above-described vertical channel structures VS.

The connection structures 740 may be, for example, bonding wires electrically connecting the input/output pads 721 and the package upper pads 711 . Accordingly, in each of the first and second semiconductor packages 703a and 703b, the semiconductor chips 720 may be electrically connected to each other using a bonding wire method, and the package upper pads 711 of the package substrate 710 and can be electrically connected. According to example embodiments, in each of the first and second semiconductor packages 703a and 703b, the semiconductor chips 720 are connected to the through electrode (Through Silicon Via) instead of the bonding wire type connection structures 740. may be electrically connected to each other.

Unlike shown, the controller 702 and the semiconductor chips 720 may be included in one package. The controller 702 and the semiconductor chips 720 may be mounted on a separate interposer substrate different from the main substrate 701, and the controller 702 and the semiconductor chips 720 may be connected to each other by wiring provided on the interposer substrate. there is.

As described above, although the embodiments have been described with limited examples and drawings, those skilled in the art can make various modifications and variations from the above description. For example, the described techniques may be performed in an order different from the method described, and/or components of the described system, structure, device, circuit, etc. may be combined or combined in a different form than the method described, or other components may be used. Or even if it is replaced or substituted by equivalents, appropriate results can be achieved.

Therefore, other implementations, other embodiments, and equivalents of the claims are within the scope of the following claims.

Claims (5)

word lines extending in a horizontal direction and spaced apart in a vertical direction; and
Vertical channel structures penetrating the word lines and extending in the vertical direction—each of the vertical channel structures extending in the vertical direction and forming a tunneling oxide (ONO) formed surrounding the vertical channel pattern charge trap nitride-blocking oxide), at least one of a tunneling oxide layer and a blocking oxide layer of the ONO is formed of a ferroelectric material, and the ONO and the vertical channel pattern form memory cells corresponding to the word line. made up-
A three-dimensional flash memory comprising a. According to claim 1,
The three-dimensional flash memory,
The charge trap nitride layer of the ONO is used as a primary data storage element, and at least one layer formed of the ferroelectric material among the tunneling oxide layer or the blocking oxide layer is used as a secondary data storage element. 3D flash memory. According to claim 2,
The three-dimensional flash memory,
A first programming operation of generating FN tunneling by applying a program voltage of a positive value to a target memory cell, which is a target of the program operation among the plurality of memory cells, and applying a program voltage of a negative value to the target memory cell to perform the program operation. performing a two-step program operation including a second program operation of raising a threshold voltage of the target memory cell by generating a polarization phenomenon in a region corresponding to the target memory cell among at least one layer formed of a ferroelectric material; Characterized by a three-dimensional flash memory. According to claim 3,
The three-dimensional flash memory,
By applying the positive program voltage to the target memory cell, positive charges are located at the interface with the charge trap nitride layer in a region corresponding to the target memory cell among at least one layer formed of the ferroelectric material. to lower the threshold voltage of the target memory cell to a negative region;
A program voltage of a negative value is applied to the target memory cell to place negative charges at an interface with the charge trap nitride layer in a region corresponding to the target memory cell among at least one layer formed of the ferroelectric material. The three-dimensional flash memory, characterized in that raising the threshold voltage of the target memory cell to a positive region. According to claim 3,
The three-dimensional flash memory,
The object in which the threshold voltage is raised in the first erase operation of injecting holes into the charge trap nitride layer of the plurality of memory cells based on the GIDL method and the second program operation among the plurality of word lines A positive erase voltage is applied to a word line corresponding to a memory cell to generate a polarization phenomenon in a region corresponding to the target memory cell among at least one layer formed of the ferroelectric material, thereby lowering the threshold voltage of the target memory cell. A three-dimensional flash memory characterized in that it performs a two-step erase operation including a second erase operation.

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