KR20210087550A - Metal interconnect structure by subtractive process - Google Patents

Abstract

A metal interconnect structure of an integrated circuit may be fabricated by forming two successive metallization layers followed by forming one or more vias. The one or more vias are fully aligned with the first metallization layer and the second metallization layer. A hardmask material or other insulating material remains on top of the first metallization layer and the second metallization layer during fabrication of the metal interconnect structure. Some of the hardmask material or other insulating material is etched and subsequently backfilled with an electrically conductive material to form one or more vias, the one or more vias contained within a space that does not overlap the surrounding dielectric material.

Description

Metal interconnect structure by subtractive process

An interconnect structure incorporated in an integrated circuit (IC) includes one or more levels of metal lines to connect the electronic devices of the IC to each other and to external connections. The levels of metal lines may be insulated from each other by one or more intervening layers of dielectric material. The interconnect structures may be formed by an additive patterning technique or a subtractive patterning technique. The additive patterning technique may include a damascene or dual damascene process, which may be used to fabricate interconnect structures using metals such as copper and cobalt. The trenches and/or holes are etched into the dielectric material, metal is deposited into the trenches and/or holes, and the excess is removed using chemical-mechanical planarization (CMP). However, in a removable patterning technique, a blanket layer of metal is deposited and etched to form trenches and/or holes in the metal, and a dielectric material is deposited into the trenches and/or holes.

The background provided herein is for the purpose of generally presenting the context of the present disclosure. The achievements of the inventors named herein to the extent described in this background, as well as aspects of the description that may not otherwise be certified as prior art at the time of filing, are expressly or implied prior to the present disclosure. is not recognized as

quoted by reference

The PCT application form is filed concurrently with this specification as part of this application. Each application claiming priority or interest as identified in the PCT application form to which this application was concurrently filed is hereby incorporated by reference in its entirety for all purposes.

A method of making a metal interconnect structure is provided herein. The method includes forming a first layer of patterned metal lines on a substrate by subtractive patterning; and forming a second layer of patterned metal lines over the first layer of patterned metal lines by removable patterning. The method includes forming a second layer of patterned metal lines, followed by at least one providing electrical interconnection between a first layer of patterned metal lines and a second layer of patterned metal lines to form a metal interconnect structure. The method further includes forming vias.

In some implementations, forming the one or more vias comprises: forming one or more via openings into a first layer of patterned metal lines through at least a second layer of patterned metal lines; and filling the one or more via openings with an electrically conductive material. In some implementations, the method includes forming a first plurality of insulating features on a first layer of patterned metal lines; and after forming the plurality of first insulating features, forming a first dielectric material in spaces between adjacent metal lines of the first layer. The method includes forming a plurality of second insulating features on a second layer of patterned metal lines; and after forming the plurality of second insulating features, forming a second dielectric material in spaces between adjacent metal lines of the second layer. In some implementations, forming the one or more vias includes etching through one or more second insulating features; etching through the second layer of patterned metal lines; etching through the one or more first insulating features to form one or more via openings to expose the first layer of patterned metal lines; and depositing an electrically conductive material in the one or more via openings to form one or more vias on the exposed first layer of patterned metal lines. In some implementations, the method includes forming a via mask over the plurality of second insulating features and the second dielectric material; and patterning one or more holes in the via mask, wherein the one or more holes each have a diameter or width greater than a critical dimension (CD) of the second layer of patterned metal lines and/or the first layer of patterned metal lines. , further comprising patterning the holes. Each of the one or more holes may have a diameter or width that is up to about 100% greater than the CD of the second layer of patterned metal lines and/or the first layer of patterned metal lines. In some implementations, depositing the electrically conductive material includes filling the first insulating features and the second layer of patterned metal lines with the previously etched electrically conductive material. In some implementations, each of the first layer of patterned metal lines, the second layer of patterned metal lines, and the electrically conductive material is molybdenum (Mo), ruthenium (Ru), aluminum (Al), or tungsten (W) includes In some implementations, the one or more vias are fully aligned with the first layer of patterned metal lines and the second layer of patterned metal lines. In some implementations, forming the first layer of patterned metal lines includes depositing a first metal over a substrate; depositing a first mask layer over the first metal; etching the first mask layer to form a first plurality of insulating features over the first metal; and etching the first metal to form a first layer of patterned metal lines defined by the plurality of first insulating features. In some implementations, forming the second layer of patterned metal lines includes depositing a second metal over the first layer of patterned metal lines; depositing a second mask layer over the second metal; etching the second mask layer to form a second plurality of insulating features over the second metal; and etching the second metal to form patterned metal lines of the second metal defined by the plurality of second insulating features.

Another aspect involves a metal interconnect structure for an integrated circuit. The metal interconnect structure includes a first layer of patterned metal lines; a plurality of first insulating features on at least some of the patterned metal lines of the first layer of patterned metal lines; a second layer of patterned metal lines over the first layer of patterned metal lines; a plurality of second insulating features on at least a portion of the second layer of patterned metal lines; and one or more vias providing electrical interconnection between the first layer of patterned metal lines and the second layer of patterned metal lines, wherein the one or more vias are the first layer of patterned metal lines and the patterned metal line. fully aligned with their second layer.

In some implementations, one or more vias extend through the first insulating features to contact a first layer of patterned metal lines with a second layer of patterned metal lines. In some implementations, a first dielectric material surrounding a first layer of patterned metal lines and a plurality of first insulating features; and a second dielectric material surrounding the second layer of patterned metal lines and the plurality of second insulating features. In some implementations, the metal interconnect structure further includes a third dielectric material over the recessed via metal fill of the one or more vias. In some implementations, each of the first dielectric material and the second dielectric material comprises a low-k dielectric material, and each of the plurality of first insulating features and the plurality of second insulating features has a different etch than the low-k dielectric material. have selectivity. In some implementations, the one or more vias include an electrically conductive material, wherein each of the first layer of patterned metal lines, the second layer of patterned metal lines, and the electrically conductive material comprises Mo, Ru, Al or W include

These and other aspects are further described below with reference to the drawings.

1A-1O show schematic illustrations of an exemplary process for forming a metal interconnect structure by removable patterning.
2A shows a cross-sectional schematic view of an exemplary partially fabricated metal interconnect structure from line AA of FIG. 1F.
2B shows a cross-sectional schematic illustration of an exemplary partially fabricated metal interconnect structure from line BB of FIG. 1H with via openings aligned with underlying metal lines.
2BB shows a cross-sectional schematic illustration of an exemplary partially fabricated metal interconnect structure from line CC of FIG. 1H with via openings misaligned with underlying metal lines.
FIG. 2C shows a cross-sectional schematic illustration of an exemplary partially fabricated metal interconnect structure from line CC of FIG. 1J with vias aligned with underlying metal lines; FIG.
FIG. 2CB shows a cross-sectional schematic illustration of an exemplary partially fabricated metal interconnect structure from line CC of FIG. 1J with vias misaligned with underlying metal lines; FIG.
FIG. 2DA shows a cross-sectional schematic illustration of an exemplary metal interconnect structure from line DD of FIG. 1N with vias aligned with overlying metal lines;
FIG. 2DB shows a cross-sectional schematic illustration of an exemplary metal interconnect structure from line DD of FIG. 1N with vias misaligned with overlying metal lines;
3 shows a flow diagram of an exemplary method of fabricating a metal interconnect structure of an integrated circuit in accordance with some implementations.
4A-4N show schematic illustrations of an example process for forming a metal interconnect structure with fully aligned vias by removable patterning in accordance with some implementations.
5A shows a cross-sectional schematic illustration of an exemplary partially fabricated metal interconnect structure from line AA of FIG. 4J in accordance with some implementations.
5B shows a cross-sectional schematic illustration of an exemplary partially fabricated metal interconnect structure from line BB of FIG. 4J in accordance with some implementations.
5C shows a cross-sectional schematic illustration of an exemplary metal interconnect structure from line CC of FIG. 4N in accordance with some implementations.
5D shows a cross-sectional schematic illustration of an exemplary metal interconnect structure from line DD of FIG. 4N in accordance with some implementations.

In this disclosure, the terms "semiconductor wafer", "wafer", "substrate", "wafer substrate", and "partially fabricated integrated circuit" are used interchangeably. Those skilled in the art will understand that the term "partially fabricated integrated circuit" may refer to a silicon wafer during any of the many stages of integrated circuit fabrication thereon. A wafer or substrate used in the semiconductor device industry typically has a diameter of 200 mm, or 300 mm, or 450 mm. The detailed description below assumes that the present disclosure is implemented on a wafer. However, the present disclosure is not so limited. The workpiece may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that may benefit from the present disclosure include various articles such as printed circuit boards, and the like.

introduction

BACKGROUND OF THE INVENTION Advances in integrated circuit technology involve scaling to increasingly smaller features in integrated circuits. Integrated circuits generally include electrically conductive microelectronic structures or vias that connect electrically conductive structures or layers. Electrically conductive structures include line features (eg, metal lines or metallization layers) that traverse a distance across the chip, and interconnect features (eg, vias) that connect line features of different levels. may include Line features and interconnect features may be insulated by dielectric materials.

Damascene and dual damascene fabrication techniques have been employed to create vias and metal lines in metal interconnect structures. Damascene and dual damascene techniques are additional patterning techniques that we rely on when fabricating metal interconnect structures, such as copper interconnect structures. However, as feature sizes of integrated circuits continue to shrink, additive patterning techniques may not be sufficient for certain technology nodes. Subtractive patterning techniques may be suitable in cases where additive patterning techniques are insufficient.

Generally speaking, the removal patterning technique deposits a blanket layer of metal, applies a mask to the blanket layer of metal, and etches the blanket layer of metal to pattern the metal lines or features defined by the mask. In contrast, additive patterning techniques deposit a blanket layer of dielectric material, apply a mask to the blanket layer of dielectric material, etch openings or recesses into the blanket layer of dielectric material defined by the mask, and the opening Fill the fields or recesses with metal. Typical metals used in additive patterning techniques include copper (Cu) or cobalt (Co). Copper has a high electrical conductivity (next to silver), which makes it highly desirable as an interconnection metal. However, metals such as copper and cobalt are difficult to etch and are therefore not good candidates for the removal patterning techniques commonly used in integrated circuit fabrication.

Conventional removable patterning techniques have employed metals such as aluminum (Al) when making metal lines and metal interconnect structures. Line widths produced by the removal patterning techniques were generally on the order of a few micrometers to several hundred nanometers. Copper damascene techniques were introduced many years ago to fabricate copper lines and copper interconnect structures, and line widths produced by damascene techniques were typically on the order of tens to hundreds of nanometers. However, line widths of about 30 nm or less or about 20 nm or less are difficult to reliably achieve using copper damascene techniques. For example, copper interconnect structures typically require diffusion barrier layers and/or liner layers to limit copper diffusion into surrounding dielectric materials, which layers can occupy more space and consequently more It can make small line widths more difficult to achieve. Metals other than copper that can withstand thinner diffusion barrier layers and/or liner layers may be used in the removable patterning, or none at all. This may enable smaller dimensions and/or technology nodes in integrated circuit fabrication.

Removable Patterning

1A-1O show schematic illustrations of an exemplary process for forming a metal interconnect structure by removable patterning. 1A , a first metal layer 101 (Mx) is deposited over the substrate 100 . The first metal layer 101 of FIG. 1A is a blanket layer that has not yet been patterned. The first metal layer 101 uses any suitable deposition process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or electrodeposition. may be deposited. Electrodeposition may include, for example, electroplating or electroless plating. In some implementations, the first metal layer 101 can include metals that can be etched, including but not limited to molybdenum (Mo), ruthenium (Ru), tungsten (W), or aluminum ( Al) may be included. In some implementations, a liner layer may be disposed between the first metal layer 101 and the substrate 100 . Examples of liner layers include, but are not limited to, titanium nitride (TiN). Other examples include tantalum nitride (TaN), tungsten nitride (WN), and tungsten carbon nitride (WCN). The thickness of the liner layer may be about 5 nm or less or about 3 nm or less. In some implementations, a dielectric layer 102 may be disposed between the liner layer and the substrate 100 . The liner layer functions to separate the first metal layer 101 from the dielectric layer 102 .

To pattern the first metal layer 101 , a first hardmask layer 103 may be deposited over the first metal layer 101 . Examples of suitable hardmask materials include silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, amorphous silicon, polysilicon, or carbon (e.g., amorphous carbon, metal-doped amorphous carbon, diamond-like carbon, polycrystalline diamond). The first hardmask layer 103 may be patterned using a photoresist 104 and a resist underlayer 105 that undergoes extreme ultraviolet (EUV) lithography. Additional layers may be formed between the photoresist and the first hardmask layer, and additional layers may be useful in photolithography processes. For example, an amorphous carbon layer 106 (a-C) and an anti-reflective layer 107 (ARL) may be disposed between the photoresist 104 and the first hardmask layer 103 . The anti-reflective layer 107 may function to prevent radiation from reflecting from the underlying layers and interfering with the exposure process in subsequent photolithography processes.

In FIG. 1B , a plurality of first hardmask features 108 are formed by patterning the first hardmask layer 103 . The plurality of first hardmask features 108 may be defined by patterning the photoresist 104 using photolithography (eg, EUV lithography). Moreover, in some implementations, the feature sizes of the first hardmask features may be reduced by a self-aligned double patterning (SADP) process. As an example, narrower hardmask features may be formed by pitch doubling, and the pitch of the first plurality of hardmask features 108 may be lowered from 80 nm to 40 nm using a SADP process. have.

In FIG. 1C , additional mask layers may be selectively deposited and patterned over the plurality of first hardmask features 108 . Additional mask layers may be patterned to etch an underlying plurality of first hardmask features 108 into a desired arrangement of first hardmask features to pattern the first metal layer 101 . Consequently, the first metal layer 101 may be patterned and “cut” according to the desired arrangement of the first hardmask features 108 . In some implementations, additional mask layers may include photoresist 109 , under-resist layer 110 , and spin-on carbon 111 (SoC). However, instead of using additional mask layers to etch the underlying plurality of first hardmask features 108 , the etching of the first hardmask features 108 etches the first metal layer 101 . It will be understood that it may be applied later. That is, the first metal layer 101 is “cut” by additional mask layers instead of the first plurality of hardmask features 108 undergoing “cutting”.

In FIG. 1D , a plurality of first hardmask features 108 are patterned by additional mask layers. The additional mask layers form the first plurality of hardmask features 108 in the desired arrangement of features by a “cut” etch process. Additional mask layers are subsequently removed.

In FIG. 1E , a first metal layer 101 is patterned to form a first layer 112 of patterned metal lines. The first layer 112 of patterned metal lines is defined by a plurality of first hardmask features 108 during the metal line etching process. The metal line etch process may selectively etch through the metal to form the first layer 112 of patterned metal lines without etching the underlying dielectric layer 102 . A suitable etchant may be used to etch the metal without etching or substantially without etching the dielectric material of the underlying dielectric layer 102 . As used herein, “substantially without etching” is an etching process in which the etch rate of the target material (eg, dielectric) is at least 5 times lower than the etch rate of the target material (eg, metal) to be etched. can refer to For example, the ablated plasma etch may remove the blanket layer of metal at a substantially higher etch rate than the underlying dielectric layer 102 . After the first layer of patterned metal lines 112 is formed, the plurality of hardmask features 108 may be removed. In some implementations, a diffusion barrier layer and/or a liner layer may be deposited on the first layer 112 of patterned metal lines. A diffusion barrier layer and/or liner layer separates the first layer 112 of patterned metal lines from the surrounding dielectric material.

In FIG. 1F , a first dielectric material 113 is deposited over the first layer 112 of patterned metal lines and fills spaces between adjacent first metal lines. A first dielectric material 113 may surround the first layer 112 of patterned metal lines. After etching the blanket layer of metal to form the first layer 112 of patterned metal lines, the first dielectric material 113 may include gaps, recesses, openings, previously filled by the blanket layer of metal, Or fill the spaces. In some implementations, after the first dielectric material 113 is deposited, the first dielectric material 113 may be planarized by a planarization process, such as chemical mechanical polishing (CMP) and/or blanket etchback. . In some implementations, the first dielectric material 113 is a dielectric material with a low dielectric constant (low-k dielectric). The low-k dielectric may have a dielectric constant of about 5.0 or less, which may be less than or equal to the dielectric constant of silicon oxide (about 4.2). The low-k dielectric materials may include an organic-containing low-k material such as fluorine-doped or carbon-doped silicon oxide or organosilicate glass (OSG). In some implementations, air gaps may be formed in the first dielectric material 113 between adjacent patterned metal lines, wherein the air gaps are the dielectric constant of the first dielectric material 113 between adjacent patterned metal lines. It may also function to further reduce . These air gaps 114 may be observed in FIG. 2A in a cross-sectional schematic illustration of a partially fabricated metal interconnect structure taken from line A-A in FIG. 1F. As shown in FIG. 2A , a first dielectric material 113 fills the spaces between adjacent patterned metal lines. Air gaps 114 are formed in the first dielectric material 113 in the space between adjacent patterned metal lines, and the patterned metal lines are separated from the air gaps 114 by the remaining first dielectric material 113 . do.

1G , a via mask 115 may be formed over the first dielectric material 113 . In some implementations, the via mask 115 may include one or more mask layers, wherein the one or more mask layers include a photoresist 116 , a resist underlayer 117 , and spin-on carbon 118 (SoC). includes To form vias that connect to the first layer 112 of patterned metal lines, via openings will be patterned and formed in the first dielectric material 113 as defined by the via mask 115 . A photolithography process may be applied to the photoresist 116 to pattern the photoresist 116 of the via mask 115 . One or more holes 119 may be formed in the via mask 115 to define via openings in the first dielectric material 113 . One or more holes 119 in via mask 115 are intended to align with first layer 112 of patterned metal lines.

In FIG. 1H , via openings 120 are formed in the first dielectric material 113 by etching. Via openings 120 are defined by one or more holes 119 of via mask 115 . The via openings 120 are intended to align with one or more patterned metal lines of the first layer 112 . However, as discussed below, alignment errors may occur during the photolithography process that may cause the via openings 120 to become out of alignment with one or more patterned metal lines of the first layer 112 . The via mask 115 may be removed after forming the via openings 120 . Via openings 120 perfectly aligned with the one or more patterned metal lines of the first layer 112 may be observed in FIG. 2B , while the one or more patterned metal lines of the first layer 112 and Unaligned via openings 120 may be observed in FIG. 2BB .

Along with shrinking feature sizes, scaling conventional lithography processes to provide smaller feature sizes can be difficult. This is due, at least in part, to alignment or overlay errors between features of the metal interconnect structure. Because the mask is not perfectly aligned with the underlying structure, alignment or overlay errors always occur during the photolithography process. For example, during light exposure steps using a reticle in a photolithography process, there may be misalignment by several nanometers in the patterning masks for vias and trenches. As a result, vias intended to connect with patterned metal lines may be misaligned. While overlay errors can be minimized by reworking the photolithography process, some overlay errors are unavoidable.

As shown in FIG. 2B , when the via openings 120 patterned from one or more mask layers are perfectly aligned with the first layer 112 of patterned metal lines, the via openings 120 are formed from the patterned metal. It is not offset from the first layer 112 of lines. Via openings 120 are not formed in the space between adjacent patterned metal lines of the first layer 112 , but are formed directly over the first layer 112 of the patterned metal lines. However, alignment or overlay errors may cause one or more mask layers to be offset in the x-direction or y-direction even by a few nanometers. As shown in FIG. 2BB , the via openings 120 are patterned from one or more mask layers and are misaligned with the first layer 112 of patterned metal lines. The misalignment causes some of the via openings 120 to form in the spaces between the first layer 112 of adjacent patterned metal lines. The misalignment results in a loss of contact area between the via and the first layer of patterned metal lines 112 and the via overlaps portions of dielectric material surrounding the first layer 112 of patterned metal lines. Moreover, misalignment may result in a risk of breaking of nearby air gaps 114 which may cause short circuits or current leakage.

In FIG. 1I , a second metal layer 121 (Mx+1) is deposited over the first dielectric material 113 , the second metal layer 121 filling the via openings 120 to form one or more vias. do. The second metal layer 121 provides a blanket layer of metal over the first dielectric material 113 . In some implementations, a liner layer is disposed between the second metal layer 121 and the first dielectric material 113 . A liner layer may also be disposed between the vias and the first layer 112 of one or more patterned metal lines. The second metal layer 121 may provide an overburden of metal over the first dielectric material 113 or may be deposited to a target thickness for the second metal layer 121 . Deposition of the second metal layer 121 may create surface roughness or surface topography issues that may be attributable to the metal filling the via openings 120 and blanketing the first dielectric material 113 . In some implementations, a planarization process may be used to planarize the second metal layer 121 to produce a relatively smooth and flat metal sheet. In some implementations, the second metal layer 121 is deposited by a suitable deposition technique such as PVD, CVD, PECVD, ALD, or electrodeposition. In some implementations, the second metal layer 121 includes Mo, Ru, Al, or W. In some implementations, the via openings 120 may be filled by a metal deposition process separate from the metal deposition process for depositing metal on the first dielectric material 113 . For example, via openings 120 may be filled with one of the metals listed above using a suitable deposition process. This may be followed by a separate process for depositing a blanket layer of one of the metals listed above connected to the vias on the first dielectric material 113 . In some implementations, a planarization process may be performed to a desired thickness of the second metal layer 121 .

In FIG. 1J , a second hardmask layer 122 is deposited over the second metal layer 121 . Examples of suitable hardmask materials include silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, amorphous silicon, polysilicon, or carbon (e.g., amorphous carbon, metal-doped amorphous carbon, diamond-like carbon, polycrystalline diamond). The second hardmask layer 122 may be patterned using a photoresist 123 and a resist underlayer 124 that has undergone EUV lithography. Additional layers may be formed between the photoresist 123 and the second hardmask layer 122 , and additional layers may be useful in photolithography processes. For example, an amorphous carbon layer 125 (a-C) and an anti-reflective layer 126 (ARL) may be disposed between the photoresist 123 and the second hardmask layer 122 .

2ca and 2cb show cross-sectional schematic illustrations of a partially fabricated metal interconnect structure taken from line C-C in FIG. 1j ; 2ca and 2cb , the second metal layer 121 is provided with via openings 120 to form vias 127 that provide electrical interconnection with the first layer 112 of patterned metal lines. ) is filled. The vias 127 are perfectly aligned with the first layer 112 of patterned metal lines in FIG. 2C . However, due to alignment or overlay errors, the vias 127 are not aligned with the first layer 112 of patterned metal lines as shown in FIG. 2CB . Due to alignment and overlay errors, vias 127 partially “land” on the top surface of first layer 112 of one or more patterned metal lines, causing vias 127 to partially “land” adjacent vias 127 . Shift closer to the first layer of patterned metal lines 112 and into the surrounding dielectric material. This results in a reduced distance between the conductive features and means that there is less insulating space between the via 127 and the first layer 112 of the neighboring patterned metal line. The reduced distance can result in insufficient shorting margin and reduced Time-Dependent Dielectric Breakdown (TDDB), or even complete shorting. TDDB is a failure mode in which an insulating layer (such as first dielectric material 113 ) breaks down with time and no longer serves as a suitable electrical insulator in normal electric fields. TDDB is subject to the electric field between metal lines because regions exposed to higher electric fields are more susceptible to TDDB failure. Higher voltages and/or reduced insulator thickness will result in higher electric fields. TDDB also depends on the spacing between adjacent metal lines because the spacing can be reduced to the point where the insulating layer cannot withstand electric fields, thus creating unintended conductance between adjacent metal lines. The end result is a short circuit or reduced reliability when the insulating layer cannot support the operating electric field. “Unlanded” vias can cause significant reliability problems due to TDDB degradation. Moreover, “unlanded” vias can cause breakdown of the underlying air gaps 114 deposited with electrically conductive materials, which can cause a short.

1K , a plurality of second hardmask features 128 are formed by patterning the second hardmask layer 122 . The second plurality of hardmask features 128 may be defined by patterning the photoresist 123 using photolithography (eg, EUV lithography). Moreover, in some implementations, the feature sizes of the second hardmask features 128 may be reduced by a self-aligned double patterning (SADP) process. As an example, narrower hardmask features may be formed by pitch doubling, and the pitch within the plurality of second hardmask features 128 may be lowered from 40 nm to 20 nm using a SADP process.

In FIG. 1L , additional mask layers may be selectively deposited and patterned over the plurality of second hardmask features 128 . Additional mask layers may be patterned to etch an underlying plurality of second hardmask features 128 into a desired arrangement of second hardmask features 128 to pattern the second metal layer 121 . may be Consequently, the second metal layer 121 may be patterned and “cut” according to the desired arrangement of the second hardmask features 128 . In some implementations, additional mask layers may include photoresist 129 , under-resist layer 130 , and spin-on carbon 131 (SoC). However, instead of using additional mask layers to etch the underlying plurality of second hardmask features 128 , the etching of the second hardmask features 128 etches the second metal layer 121 . It will be understood that it may be applied later. That is, the second metal layer 121 is “cut” by additional mask layers instead of the second plurality of hardmask features 128 undergoing “cutting”.

In FIG. 1M , a plurality of second hardmask features 128 are patterned with additional mask layers. The additional mask layers form a second plurality of hardmask features 128 in the desired arrangement of features by a “cut” etch process. Additional mask layers are subsequently removed.

In FIG. 1N , the second metal layer 121 is patterned to form a second layer 132 of patterned metal lines. The patterned metal lines are defined by a plurality of second hardmask features 128 during the metal line etching process. The metal line etch process may selectively etch through the metal to form the second layer 132 of patterned metal lines without etching the first dielectric material 113 . A suitable etchant may be used to remove the metal without etching or substantially without etching the first dielectric material 113 . For example, the ablated plasma etch may remove the blanket layer of metal at a substantially higher etch rate than the underlying first dielectric material 113 . After the second layer of patterned metal lines 132 is formed, the plurality of second hardmask features 128 may be removed. In some implementations, a diffusion barrier layer and/or liner layer may be deposited on the second layer 132 of the patterned metal lines. A diffusion barrier layer and/or liner layer separates the second layer 132 of patterned metal lines from the surrounding dielectric material.

Vias 127 provide electrical interconnection between the second layer of patterned metal lines 132 and the first layer of patterned metal lines 112 to form a metal interconnect structure. As previously discussed, when patterning the one or more holes 119 in the via mask 115 , there is a risk of misalignment with the first layer 112 of the patterned metal lines. Not only is there a risk of misalignment of the patterned metal lines with the first layer 112 (Mx), but there is also a risk of misalignment of the patterned metal lines with the second layer 132 (Mx+1). When patterning the second layer 132 of patterned metal lines, there is a risk of misalignment between the vias 127 and the second layer 132 of the patterned metal lines. FIG. 2DA shows a cross-sectional schematic illustration of a metal interconnect structure from line D-D of FIG. 1N , with vias 127 aligned with the second layer 132 of patterned metal lines. There is no loss of contact area between the vias 127 and the second layer 132 of patterned metal lines in FIG. 2da . FIG. 2DB shows a cross-sectional schematic illustration of a metal interconnect structure from line D-D of FIG. 1N in which vias 127 are misaligned with the second layer 132 of patterned metal lines. As a result of the misalignment there is a loss of contact area between the vias 127 and the second layer of metal lines 132 patterned in FIG. 2db. This causes a loss of via area. Electrical resistance is directly proportional to the resistivity and length of the material, and inversely proportional to the cross-sectional area of the material. Loss of via area results in higher via resistance, which results in reduced performance and reduced reliability.

In FIG. 1O , a dielectric material 133 is deposited over the second layer 132 of patterned metal lines in essentially the same manner as for Mx and fills the spaces between adjacent second metal lines. This dielectric material 133 , referred to below as a second dielectric material, may surround the second layer 132 of patterned metal lines. After etching the blanket layer of metal to form the second layer 132 of the patterned metal lines, the second dielectric material 133 is formed of gaps, recesses, openings, previously filled by the blanket layer of metal, Or fill the spaces. In some implementations, after the second dielectric material 133 is deposited, it may be planarized by a planarization process such as CMP and/or blanket etch-back. In some implementations, the second dielectric material 133 is a low-k dielectric material. In some implementations, the second dielectric material 133 shares the same composition as the first dielectric material 113 . In some implementations, air gaps may be formed in the second dielectric material between adjacent second metal lines, the air gaps further reducing the dielectric constant of the second dielectric material 133 between adjacent second metal lines. It may function to make After the second dielectric material 133 is deposited, the metal interconnect structure is fabricated. A metal interconnect structure formed by removable patterning techniques has a first layer of patterned metal lines (112) and a second layer of patterned metal lines over the first layer of patterned metal lines (112), wherein one The above vias 127 provide electrical interconnection between the first layer 112 of patterned metal lines and the second layer 132 of patterned metal lines. It will be appreciated that additional metal lines (eg, Mx+2, Mx+3, etc.) may be deposited and patterned to build on the metal interconnect structure. Additional metal lines may be formed in the same or similar manner as the second layer 132 of patterned metal lines and the first layer 112 of patterned metal lines.

Self-aligned vias in removable patterning

The present disclosure relates to the fabrication of a metal interconnect structure in which one or more vias are formed following the formation of two successive metallization layers. The one or more vias are formed by filling the one or more via openings with an electrically conductive material after patterning the first metal layer and after patterning the second metal layer. The metal interconnect structure is fabricated by removable patterning techniques. One or more vias are aligned with each of two successive metallization layers. Alignment between one or more vias and successive metallization layers is achieved by forming two successive metallization layers and then leaving some hardmask material or other insulating isolation material on top of the patterned metal lines. Some of the remaining insulating isolation material is removed when etching through one of the successive metallization layers to form one or more via openings. Due to differences in etch selectivity between the surrounding dielectric material and the insulating isolation material and differences in etch selectivity between the surrounding dielectric material and the continuous metallization layer, the formation of one or more vias is contained within a space not formed with the surrounding dielectric material do. In some implementations, the one or more vias are fully aligned with two successive metallization layers to provide improved contact area, reduced electrical resistivity, reduced risk of TBBD failure, and reduced risk of short circuits.

3 shows a flow diagram of an example method of fabricating a metal interconnect structure of an integrated circuit in accordance with some implementations. The operations of process 300 may be performed in different orders and/or with different, fewer, or additional operations.

At block 310 of process 300 , a first layer (Mx) of patterned metal lines on a substrate is formed by removable patterning. In some implementations, the substrate may be a semiconductor wafer, built on a semiconductor wafer, or be part of a semiconductor wafer. The substrate may include a dielectric layer on which a first layer of patterned metal lines is formed. In some implementations, a diffusion barrier layer and/or liner layer may be deposited on the dielectric layer to separate the first layer of patterned metal lines from the dielectric layer. The first layer of patterned metal lines represents a first metallization layer of the metal interconnect structure. As used herein, a layer of patterned metal lines may also be referred to as a metallization layer, a metal layer, metal lines, metal features, or line features. The first layer or first metallization layer of patterned metal lines may also be referred to as the bottom layer or bottom metallization layer of patterned metal lines.

Formation of the first layer of patterned metal lines by removable patterning may involve one or more operations at block 310 of process 300 . In some implementations, forming the first layer of patterned metal lines comprises depositing a first metal layer over the substrate, depositing a first insulating layer over the first metal layer, a plurality of over the first metal layer etching the first insulating layer to form first insulating features; and etching the first metal layer to form a first layer of patterned metal lines defined by the plurality of first insulating features. . In some implementations, the first insulating layer may be a first hardmask layer and the first insulating features may be first hardmask features. The first metal layer can include any suitable metal that can be etched and patterned using removable patterning techniques. For example, the first metal layer may include Mo, Ru, Al, or W. In some implementations, the first metal layer is deposited using any suitable deposition technique, such as PVD, CVD, PECVD, ALD, or electrodeposition. Electrodeposition may include, for example, electroplating or electroless plating. In some implementations, the critical dimension (CD) of the first layer (Mx) of patterned metal lines is about 50 nm or less, about 20 nm or less, about 15 nm or less, or about 10 nm or less. In some implementations, the pitch of the first layer (Mx) of patterned metal lines may be about 100 nm or less, about 40 nm or less, about 30 nm or less, or about 20 nm or less.

In some implementations, process 300 further includes forming a first plurality of insulating features on the first metal layer. The plurality of first insulating features may define patterned metal lines in the first metal layer. Process 300 further includes forming a first dielectric material in spaces between adjacent metal lines. A first dielectric material may surround the plurality of first insulating features and the first layer of patterned metal lines. A first plurality of insulating features is maintained to cover top surfaces of the first layer of patterned metal lines after formation of the first dielectric material. This may serve to include subsequent etching processes when forming one or more vias.

4A-4D show schematic illustrations of an exemplary process for forming a first layer of patterned metal lines over a substrate by removable patterning. Forming the first layer of patterned metal lines in block 310 of process 300 may involve different, fewer, or additional operations than shown in FIGS. 4A-4D . In FIG. 4A , a first metal layer 401 (Mx) is deposited over the substrate 400 . The first metal layer 401 of FIG. 4A is a blanket layer of metal that has not yet been patterned. In some implementations, a liner layer may be disposed between the first layer of metal 401 and the substrate 400 . Examples of liner layers include, but are not limited to, titanium nitride (TiN). Other examples include tantalum nitride (TaN), tungsten nitride (WN), and tungsten carbon nitride (WCN). The thickness of the liner layer may be about 5 nm or less or about 3 nm or less. In some implementations, a dielectric layer 402 may be disposed between the liner layer and the substrate 400 . The liner layer functions to separate the first layer 401 of metal from the dielectric layer 402 .

To pattern the first metal layer 401 , a first hardmask layer 403 may be deposited over the first metal layer 401 . Examples of suitable hardmask materials include silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, amorphous silicon, polysilicon, or carbon (e.g., amorphous carbon, metal-doped amorphous carbon, diamond-like carbon, polycrystalline diamond). The first hardmask layer 403 uses a photoresist 404 and a resist underlayer 405 as described in FIG. 1A , optionally an amorphous carbon layer 406 and a photoresist as described in FIG. 1A . It may be patterned using an anti-reflective layer 407 disposed between 404 and the first hardmask layer 403 .

In FIG. 4B , a plurality of first hardmask features 408 are formed by patterning the first hardmask layer 403 . Patterning the first hardmask layer 403 may be accomplished by patterning the photoresist 404 using photolithography (eg, EUV lithography). In some implementations, smaller feature sizes may be formed by pitch doubling as described in FIG. 1B . In some implementations, additional masking operations may be performed to “cut” the first hardmask features 408 into the desired arrangement of first hardmask features 408 as described in FIGS. 1C and 1D . may be Eventually, the first metal layer 401 will be patterned as defined by the first hardmask features 408 following additional masking and cutting operations.

In FIG. 4C , a first metal layer 401 is patterned to form a first layer 409 of patterned metal lines. A first layer 409 of patterned metal lines is defined by a plurality of first hardmask features 408 during a metal line etching process. The metal line etch process may selectively etch through the metal to form the first layer 409 of patterned metal lines without etching or substantially etching the underlying dielectric layer 402 . For example, an ablated plasma etch may remove the blanket layer of metal at a substantially higher etch rate than the underlying dielectric layer 402 . Instead of removing the first plurality of hardmask features 408 from the first layer 409 of patterned metal lines of FIG. 4C , the first plurality of hardmask features 408 are retained. In some implementations, a liner layer and/or diffusion barrier layer may be deposited on the plurality of first hardmask features 408 and on the first layer 409 of patterned metal lines. A liner layer and/or diffusion barrier layer separates the first layer of patterned metal lines 409 and the dielectric material surrounding the plurality of first hardmask features 408 .

In FIG. 4D , a first dielectric material 410 is deposited around a first layer 409 of patterned metal lines and a plurality of first hardmask features 408 and fills the spaces between adjacent patterned metal lines. do. A first dielectric material 410 can surround a first layer of patterned metal lines 409 and first hardmask features 408 . In some implementations, a first dielectric material 410 is deposited over the plurality of first hardmask features 408 . After etching the blanket layer of metal to form the first layer of patterned metal lines, first dielectric material 410 is applied to gaps, recesses, openings, or spaces that were previously filled by the blanket layer of metal. fill them up In some implementations, after the first dielectric material 410 is deposited, the first dielectric material 410 and the plurality of first hardmask features 408 are planarized by a planarization process such as CMP and/or blanket etchback. could be The planarization process may expose top surfaces of the first hardmask features 408 covering the first layer 409 of patterned metal lines. The top surfaces of the first hardmask features 408 and the first dielectric material 410 are coplanar. In some implementations, the first dielectric material 410 is a low-k dielectric material. Low-k dielectric materials may include organic-containing low-k materials such as fluorine-doped or carbon-doped silicon oxide or OSG. In some implementations, air gaps may be formed in the first dielectric material 410 between adjacent patterned metal lines, wherein the air gaps are the dielectric constant of the first dielectric material 410 between adjacent patterned metal lines. It may also function to further reduce . Air gaps are formed in the first dielectric material 410 in the space between adjacent patterned metal lines, and the patterned metal lines are separated from the air gaps by the remaining first dielectric material 410 .

Referring again to FIG. 3 , at block 320 of process 300 , a second layer of patterned metal lines is formed over the first layer of patterned metal lines by removable patterning. In some implementations, a diffusion barrier layer and/or liner layer may be deposited on the exposed surfaces of the first dielectric material and the plurality of first insulating features. The second layer of patterned metal lines represents a second metallization layer of the metal interconnect structure.

Formation of the second layer of patterned metal lines by removable patterning may involve one or more operations at block 320 of process 300 . In some implementations, forming the second layer of patterned metal lines comprises depositing a second metal layer over the first dielectric material and over the first layer of patterned metal lines, a second insulation over the second metal layer depositing a layer, etching the second insulating layer to form a second plurality of insulating features over the second metal layer, and forming a second layer of patterned metal lines defined by the plurality of second insulating features. and etching the second metal layer to form. In some implementations, the second insulating layer may be a second hardmask layer and the second insulating features may be second hardmask features. The second metal layer can include any suitable metal that can be etched and patterned using removable patterning techniques. For example, the second metal layer may include Mo, Ru, Al, or W. In some implementations, the second metal layer is the same material as the first metal layer. In some implementations, the second metal layer is deposited using any suitable deposition technique, such as PVD, CVD, PECVD, ALD, or electrodeposition. Electrodeposition may include, for example, electroplating or electroless plating. In some implementations, the critical dimension of the second layer of patterned metal lines (Mx+1) is about 50 nm or less, about 20 nm or less, about 15 nm or less, or about 10 nm or less. In some implementations, the pitch of the second layer of patterned metal lines (Mx+1) is about 100 nm or less, about 40 nm or less, about 30 nm or less, or about 20 nm or less.

In some implementations, process 300 further includes forming a second plurality of insulating features on the second metal layer. A second plurality of insulating features may define a second layer of patterned metal lines within the second metal layer. Process 300 further includes forming a second dielectric material in spaces between adjacent metal lines. A second dielectric material may surround a second plurality of insulating features and a second layer of patterned metal lines. A second plurality of insulating features is maintained to cover top surfaces of the second layer of patterned metal lines after formation of the second dielectric material. This may serve to include subsequent etching processes when forming one or more vias.

4E-4H show schematic illustrations of an exemplary process for forming a second layer of patterned metal lines over a first layer of patterned metal lines by removable patterning. Forming the second layer of patterned metal lines at block 320 of process 300 may involve different, fewer, or additional operations than shown in FIGS. 4E-4H . In FIG. 4E , a second metal layer 411 (Mx+1) is over the first layer 409 of patterned metal lines and over the first dielectric material 410 and a plurality of first hardmask features 408 . ) is deposited on The second metal layer 411 of FIG. 4E provides a blanket layer of metal over the first dielectric material 410 and the plurality of first hardmask features 408 . In some implementations, a liner layer is disposed between the second metal layer 411 and the first dielectric material 410 and between the second metal layer 411 and the plurality of first hardmask features 408 . When patterning the second metal layer 411 , a second hardmask layer 412 may be deposited over the second layer of metal 411 , wherein the second hardmask layer 412 is the one described in FIG. 1J . Using photoresist 413 and resist underlayer 414 as described above, optionally between amorphous carbon layer 415 and photoresist 413 and second hardmask layer 412 as described in FIG. 1J . It may be patterned using the disposed anti-reflective layer 416 .

In FIG. 4F , a plurality of second hardmask features 417 are formed by patterning the second hardmask layer 412 . Patterning the second hardmask layer 412 may be accomplished by patterning the photoresist 413 using photolithography (eg, EUV lithography). In some implementations, smaller feature sizes may be formed by pitch doubling as described in FIG. 1K . In some implementations, additional masking operations may be performed to “cut” the second hardmask features 417 into the desired arrangement of second hardmask features 417 as described in FIGS. 1L and 1M . may be Eventually, the second metal layer 411 will be patterned as defined by the second hardmask features 417 following additional masking and cutting operations.

In FIG. 4G , the second metal layer 411 is patterned to form a second layer 418 of patterned metal lines. The second layer 418 of patterned metal lines is defined by a plurality of second hardmask features 417 during the metal line etch process. The metal line etching process is performed to form a second layer 418 of patterned metal lines without etching or substantially etching the first dielectric material 410 and the plurality of first hardmask features 408 . The metal layer 411 may be selectively etched through. For example, the ablated plasma etch may remove the blanket layer of metal at a substantially higher etch rate than the first dielectric material 410 and the plurality of first hardmask features 408 . As used herein, “substantially higher etch rate” may refer to an etch rate that is at least five times greater for a target material to be etched than other materials. Instead of removing the plurality of second hardmask features 417 from the second layer of patterned metal lines 418 of FIG. 4G , the second plurality of hardmask features 417 are maintained. In some implementations, a liner layer and/or diffusion barrier layer may be deposited on the plurality of second hardmask features 417 and on the second layer 418 of patterned metal lines. A liner layer and/or diffusion barrier layer separates the second layer of patterned metal lines 418 and the dielectric material surrounding the plurality of second hardmask features 417 .

In FIG. 4H , a second dielectric material 419 is deposited around a second layer 418 of patterned metal lines and a plurality of second hardmask features 417 and fills the spaces between adjacent patterned metal lines. do. A second dielectric material 419 can surround a second layer of patterned metal lines 418 and second hardmask features 417 . In some implementations, a second dielectric material 419 is deposited over the plurality of second hardmask features 417 . After etching the blanket layer of metal to form the second layer 418 of patterned metal lines, the second dielectric material 419 is formed of gaps, recesses, openings, which were previously filled by the blanket layer of metal, Or fill the spaces. In some implementations, after the second dielectric material 419 is deposited, the second dielectric material 419 and the plurality of second hardmask features 417 are planarized by a planarization process such as CMP and/or blanket etchback. could be The planarization process may expose top surfaces of the second hardmask features 417 covering the second layer 418 of patterned metal lines. The top surfaces of the second hardmask features 417 and the second dielectric material 419 are coplanar. In some implementations, the second dielectric material 419 is a low-k dielectric material. In some implementations, air gaps may be formed in a second dielectric material 419 between adjacent patterned metal lines, the patterned metal lines being separated from the air gaps by a remaining second dielectric material 419 . .

Referring back to FIG. 3 , at block 330 of process 300 , one providing electrical interconnection between a first layer of patterned metal lines and a second layer of patterned metal lines to form a metal interconnect structure More than one via is formed. The one or more vias are formed subsequent to formation of the first layer of patterned metal lines and the second layer of patterned metal lines. In addition, the one or more vias are formed following the removable patterning of the first metal layer and filling of spaces around the first layer of metal lines patterned with the first dielectric material, and the removable patterning of the second metal layer and the second Subsequent to filling of spaces around the second layer of metal lines patterned with dielectric material are formed. That is, after two metallization layers are defined, one or more vias are patterned.

The formation of one or more vias may involve one or more operations at block 330 of process 300 . The one or more vias may be formed by forming one or more via openings with a first layer of patterned metal lines through at least a second layer of patterned metal lines and filling the one or more via openings with an electrically conductive material. Forming the one or more via openings may include etching through one or more second insulating features, etching through a second layer of patterned metal lines, and etching through one or more first insulating features. can Etching through three or more layers of materials without or substantially without etching the surrounding materials can present many challenges. In some implementations, etching through the one or more second insulating features occurs without etching or substantially etching the second dielectric material. In some implementations, etching through the second layer of patterned metal lines occurs without etching or substantially etching the second dielectric material. In some implementations, etching through the one or more first insulating features occurs without or substantially without etching the first dielectric material. As used herein, “substantially without etching” means an etch in which the etch rate of the target material (eg, dielectric) is at least 5 times lower than the etch rate of the target material (eg, hardmask) to be etched It can refer to processes. That is, the target material to be etched has an etch selectivity of at least about 5:1 over other materials. Etching through three or more layers of materials may use the same etching process using the same etchant, or may use different etching processes using different etchants. In some implementations, filling the one or more via openings with an electrically conductive material includes backfilling in which the second layer of patterned metal lines and one or more first insulating features are etched. This backfilling forms one or more vias to provide electrical connection with the remaining second layer of patterned metal lines.

Forming the one or more via openings with the first layer of patterned metal lines may be limited by first insulating features and second insulating features such that the one or more via openings are not offset or misaligned. Specifically, the first insulating features and the second insulating features serve to limit the etching process such that via openings are not formed into the surrounding dielectric materials. After formation of the first layer of patterned metal lines and the second layer of patterned metal lines, the first layer of patterned metal lines and the second layer of patterned metal lines without retaining the first insulating features and the second insulating features Alignment or overlay errors can occur that create unwanted electrical connections (eg, unwanted shorts) between the two layers.

The material difference between the first and second insulating features and the surrounding dielectric materials drives an etch contrast such that via formation is included such that one or more vias are formed in the first layer of the patterned metal lines and the first layer of the patterned metal line. Let it self-align with the second floor. Conventional manufacturing processes for providing vias between metallization layers generally use the same dielectric material as the spatial offset between the metallization layers, while the first insulating features and the second insulating features of the present disclosure have different etch choices. It provides a material difference with the surrounding dielectric material having a degree.

The vertical walls of the surrounding dielectric material serve as etch boundaries limiting the via etch such that the via formation aligns with the first layer of patterned metal lines and the second layer of patterned metal lines. The via etch does not extend to the surrounding dielectric material or adjacent vias. By limiting via formation, this ensures self-alignment of the one or more vias with the first layer of patterned metal lines and the second layer of patterned metal lines. When the one or more vias are aligned with at least the first layer of patterned metal lines, the one or more vias directly contact the top surfaces of the first layer of patterned metal lines without overlap. Thus, the one or more vias do not overlap the first dielectric material and solve the TDDB degradation and short circuit problems caused by the misaligned vias. When the one or more vias are aligned with at least the second layer of patterned metal lines, the one or more vias are filled with an electrically conductive material in which the second layer of the one or more patterned metal lines was previously etched and does not overlap the second dielectric material do. This addresses the reduced contact area, higher via resistance, and reduced reliability issues caused by misaligned vias. Accordingly, the self-aligned via patterning scheme may provide one or more vias that will be fully aligned with the second layer of patterned metal lines and the first layer of patterned metal lines.

In some implementations, process 300 includes depositing a via mask over the second plurality of insulating features and the second dielectric material, and patterning one or more holes in the via mask to define one or more via openings. include more Each of the one or more holes has a diameter or width that is greater than a critical dimension of the second layer of patterned metal lines and/or the first layer of patterned metal lines. In some implementations, each of the one or more holes has a diameter or width that is up to about 100% greater than the critical dimension of the second layer of patterned metal lines and/or the first layer of patterned metal lines. The diameter or width of the one or more holes in the via mask is over-sized to be greater than the diameter or width of the one or more vias actually formed. In this way, any misalignment between the one or more holes and the underlying layers to be etched leaves no target material to be etched. By over-sizing the holes, this also ensures that the underlying layers to be etched are actually etched independent of any alignment errors. It has in part second insulating features selective to the second dielectric material during etching, having a second layer of patterned metal lines selective to the second dielectric material during etching, and to the first dielectric material during etching. due to having optional first insulating features. However, it will be appreciated that the diameter or width of one or more holes is not large enough to risk extending into adjacent metal lines. Thus, the diameter or width of one or more holes in the via mask is slightly over-sized to account for misalignment tolerance, but not over-sized enough to be etched into other metal lines.

4I-4L show schematic illustrations of an exemplary process for forming one or more vias to provide electrical interconnection between a first layer of patterned metal lines and a second layer of patterned metal lines. Forming one or more vias at block 330 of process 300 may involve different, fewer, or additional operations than those shown in FIGS. 4I-4L . In FIG. 4I , a via mask 420 is formed over the plurality of second hardmask features 417 and the second dielectric material 419 . The via mask 420 may have one or more holes 421 for patterning one or more via openings through at least the second layer 418 of patterned metal lines. Via mask 420 may include one or more layers for patterning, one or more layers including photoresist 422 , resist underlayer 423 , spin-on carbon 424 (SoC), and mask layer 425 . ) (eg, a hardmask layer). A photolithography process may be applied to photoresist 422 to pattern mask layer 425 , where one or more holes may be formed in mask layer 425 . Portions of the mask layer 425 may be etched to form one or more holes for defining one or more via openings. One or more holes in mask layer 425 are aligned with second hardmask features 417 , second layer of patterned metal lines 418 , and first hardmask features 408 in which one or more vias will be formed. intended to do In some implementations, a diameter of the one or more holes is greater than a critical dimension of the second layer of patterned metal lines 418 and/or of the first layer of patterned metal lines 409 . In some implementations, the critical dimension of the first layer of patterned metal lines 409 or the second layer of patterned metal lines 418 may be about 50 nm or less, about 20 nm or less, or about 10 nm or less. In some implementations, the diameter is from about 1% to about 100% greater, or from about 5% to about 100% greater than the critical dimension of the second layer of patterned metal lines and/or the first layer of patterned metal lines 409 . % greater, or from about 10% to about 50% greater. The diameter of the one or more holes is larger than the actual one or more via openings formed through the second layer 418 of patterned metal lines, where the difference in size accounts for some tolerance of misalignment without etching adjacent metal lines. In some implementations, the mask layer 425 of the via mask 420 is a layer of the second hardmask features 417 , the second layer of patterned metal lines 418 , and the first hardmask features 408 . material different from the material.

In FIG. 4J , one or more via openings 426 are formed by etching through at least a second layer of patterned metal lines 418 with a first layer of patterned metal lines 409 . The one or more via openings 426 are defined by one or more holes 421 in the via mask 420 . The one or more via openings 426 are intended to align with the second layer 418 of one or more patterned metal lines and the first layer 409 of one or more patterned metal lines. Tolerance of misalignment allows for electrically insulating material (eg, first hardmask features and second hardmask features) on top surfaces of patterned metal lines that have different etch selectivity than surrounding dielectric materials. It can also be explained by leaving In this way, the electrically isolated material serves to limit the etch processes such that one or more via openings 426 are not formed with the surrounding dielectric materials. The tolerance of the misalignment also causes the holes in the via mask 420 to be slightly over-sized and etched to the second hardmask features 417 over the surrounding dielectric material, the second layer of patterned metal lines 418, and optional for the first hardmask features 408 . In this way, the over-sized holes of the via mask 420 reduce the risk of losing targeted materials to be etched, so forming the one or more via openings 426 leaves no targeted materials.

Forming the one or more via openings 426 includes etching through the one or more second hardmask features 417 , etching through the second layer 418 of patterned metal lines, and the one or more second hardmask features 417 . and etching through the first hardmask features (408). Etching is stopped on the first layer 409 of patterned metal lines. A first layer 409 of patterned metal lines is exposed after etching. Etching through the one or more second hardmask features 417 is optional with respect to the second dielectric material 419 , and etching through the second layer 418 of patterned metal lines 418 comprises a second dielectric material. Optional for 419 , and etching through one or more first hardmask features 408 is optional for first dielectric material 410 . of via openings 426 through one or more second hardmask features 417 , through a second layer of patterned metal lines 418 , and through one or more first hardmask features 408 . Formation may be observed in FIGS. 5A and 5B taken along line AA and line BB of FIG. 4J , respectively.

In FIG. 4K , an electrically conductive material 427 is deposited in the one or more via openings 426 to fill the one or more via openings 426 . One or more vias 428 are formed by filling one or more via openings 426 pre-filled with one or more first hardmask features 408 and a second layer of patterned metal lines 418 . In some implementations, the electrically conductive material 427 is the same material as the first layer 409 of patterned metal lines and the second layer 418 of patterned metal lines. For example, the electrically conductive material 427 includes Mo, Ru, Al, or W. In some implementations, the electrically conductive material 427 is a different material than the first layer 409 of patterned metal lines and the second layer 418 of patterned metal lines. In some implementations, the electrically conductive material 427 is deposited by a suitable deposition technique such as PVD, CVD, PECVD, ALD, or electrodeposition to at least substantially fill the one or more via openings 426 . In some implementations, a diffusion barrier layer and/or liner layer may be deposited in the one or more via openings 426 prior to filling the one or more via openings 426 with an electrically conductive material 427 . A diffusion barrier layer and/or liner layer may separate one or more vias 428 from surrounding dielectric materials.

The one or more vias 428 are formed by backfilling with an electrically conductive material 427 in which the second layer 418 of patterned metal lines and one or more first hardmask features 408 have been etched. An electrically conductive material 427 contacts the exposed first layer of patterned metal lines 409 and provides electrical interconnection with the second layer 418 of patterned metal lines by backfill. In some implementations, electrically conductive material 427 fills one or more via openings 426 , fills one or more holes in mask layer 425 , and is electrically conductive over one or more via openings 426 . It is deposited to provide a blanket layer of material 427 . This provides an overburden of electrically conductive material 427 over one or more via openings 426 .

In FIG. 4L , the remaining portion of electrically conductive material 427 in which one or more first hardmask features 408 and a second layer of patterned metal lines 418 have pre-filled one or more via openings 426 . A portion of the electrically conductive material 427 is removed so that they are filled. This removal of the portion of the electrically conductive material 427 is in the one or more holes of the mask layer 425 , over the one or more via openings 426 , and the second hardmask features 417 are one or more vias. and etching the electrically conductive material 427 that previously filled the openings 426 . This removes the overburden of the electrically conductive material 427 and leaves the electrically conductive material 427 up to the bottom level of the second hardmask features 417 . Accordingly, one or more recesses may be formed through the one or more holes to the bottom level of the second hardmask features 417 , thereby displacing at least the recessed metal fill 429 into the second hardmask features 417 . ) as the lower level of In FIG. 4L a metal interconnect structure having two successive metallization layers connected by one or more fully aligned vias 428 is fabricated.

Referring again to FIG. 3 , process 300 can further include covering the exposed portions of the electrically conductive material with a third dielectric material. In some implementations, a third dielectric material may be deposited over the recessed via metal fill and the second insulating features. The third dielectric material may be etched or polished to be coplanar with the second insulating features. In some implementations, the third dielectric material can be the same material as the second insulating features.

In some implementations, process 300 can further include forming a third layer of patterned metal lines (Mx+2) over the second layer of patterned metal lines by removable patterning. The third layer of patterned metal lines may represent a third metallization layer of the metal interconnect structure. In some implementations, one or more additional vias may be formed to provide electrical interconnection between the second layer of patterned metal lines and the third layer of patterned metal lines. Additional metallization layers and vias may continue to be fabricated in the metal interconnect structure, wherein the additional metallization layers may be formed in the same or similar manner as the first metallization layer and the second metallization layer, and additional The specific vias may be formed in the same or similar manner as one or more vias that provide electrical interconnection between the first layer of patterned metal lines and the second layer of patterned metal lines.

4M and 4N show schematic illustrations of an exemplary process for capping a recessed via metal fill with a third dielectric material. Capping the recessed via metal fill may involve different, fewer, or additional operations than shown in FIGS. 4M and 4N . In FIG. 4M , a third dielectric material 430 is deposited over the plurality of second hardmask features 417 and the recessed via metal fill 429 . A third dielectric material 430 may be deposited in the one or more recesses formed after removing portions of the electrically conductive material 427 filling the one or more via openings 426 . In some implementations, the third dielectric material 430 is the same material as the second hardmask features 417 . In some implementations, a third dielectric material 430 is deposited over the mask layer 425 . The third dielectric material 430 may be the same material or the same type of material as the mask layer 425 . A third dielectric material 430 is deposited to cover the exposed portions of the electrically conductive material 427 .

In FIG. 4N , a planarization process is performed to remove the third dielectric material 430 up to the second hardmask features 417 . The planarization process may include CMP and/or blanket etchback such that the third dielectric material 430 is coplanar with the second hardmask features 417 . In addition, the mask layer 425 over the plurality of second hardmask features 417 may be removed along with some removal of the third dielectric material 430 . The third dielectric material 430 and the second hardmask features 417 serve to cap or otherwise cover the second layer of the patterned metal lines 418 . Additional layers of patterned metal lines and additional vias are in the same or similar manner as the first layer of patterned metal lines 409 , the second layer of patterned metal lines 418 , and one or more vias 428 . may be formed subsequently. After capping the recessed via metal fill 429 , a metal interconnect structure can be observed in FIGS. 5C and 5D taken along lines C-C and D-D in FIG. 4N , respectively. The metal interconnect structure of FIGS. 5C and 5D has fully aligned vias 428 that provide electrical interconnection between a first layer 409 of patterned metal lines and a second layer 418 of patterned metal lines. shows

A metal interconnect structure is formed after formation of the one or more vias 428 when providing electrical interconnection between the first layer of patterned metal lines 409 and the second layer of patterned metal lines 418 . Exemplary metal interconnect structures of integrated circuits are illustrated in FIGS. 5C and 5D . The metal interconnect structure includes a first layer of patterned metal lines 409 , a plurality of first insulating features 431 on at least some of the first layer 409 of patterned metal lines, a first of the patterned metal lines. a second layer of patterned metal lines 418 over the layer 409 , and a plurality of second insulating features 432 on at least some of the second layer of patterned metal lines 418 . The metal interconnect structure further includes one or more vias 428 that provide electrical interconnection between the first layer 409 of patterned metal lines and the second layer 418 of patterned metal lines, and one or more The vias 428 are fully aligned with the first layer 409 of patterned metal lines and the second layer 418 of patterned metal lines. A first dielectric material 410 surrounds a first layer 409 of patterned metal lines and a plurality of first insulating features 431 . A second dielectric material 419 surrounds the second layer of patterned metal lines 418 and second insulating features 432 . The one or more vias 428 directly contact the first layer 409 of patterned metal lines where the one or more vias 428 do not overlap the first dielectric material 410 or the second dielectric material 419 . completely aligned to One or more vias 428 are formed after patterning the first layer 409 of metal lines and the second layer 418 of metal lines.

In some implementations, the metal interconnect structure further includes a third dielectric material 430 over the recessed via metal fill 429 , and the top surfaces of the second layer 418 of patterned metal lines are second insulating. Via metal fill 429 covered and recessed by features 432 is covered by a third dielectric material 430 . In some implementations, the third dielectric material 430 is the same material as the second insulating features 432 . In some implementations, each of the first dielectric material 410 and the second dielectric material 419 is a low-k dielectric material. The first insulating features 431 and the second insulating features 432 have different etch selectivity than the low-k dielectric material. In some implementations, the first layer of patterned metal lines 409 and the second layer of patterned metal lines 418 include Mo, Ru, Al, or W. In some implementations, the one or more vias 428 include Mo, Ru, Al, or W, wherein the material of the one or more vias 428 includes the first layer 409 of patterned metal lines and the patterning. the same or different from the material of the second layer 418 of the metal lines.

The process described herein may be used in conjunction with lithographic patterning tools or processes, for example, for the manufacture or fabrication of semiconductor devices, displays, LEDs, optoelectronic panels, and the like. Typically, though not necessarily, these tools/processes will be used or performed together in a common manufacturing facility. Lithographic patterning of a film typically involves the following operations, each of which is enabled using a number of possible tools: (1) a workpiece using a spin-on tool or a spray-on tool. , that is, applying a photoresist on the substrate; (2) curing the photoresist using a hot plate or furnace or UV curing tool; (3) exposing the photoresist to visible or UV or x-ray light using a tool such as a wafer stepper; (4) developing the resist to pattern the resist by selectively removing the resist using a tool such as a wet bench; (5) transferring the resist pattern into an underlying film or workpiece by using a dry or plasma assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper.

conclusion

In the foregoing description, numerous specific details have been set forth in order to provide a thorough understanding of the presented implementations. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the disclosed implementations. While the disclosed implementations have been described in conjunction with specific implementations, it will be understood that this is not intended to limit the disclosed implementations.

Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the present embodiments. Accordingly, the present embodiments are to be regarded as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.

Claims (20)

A method of manufacturing a metal interconnect structure comprising:
forming a first layer of patterned metal lines on a substrate by subtractive patterning;
forming a second layer of patterned metal lines over the first layer of patterned metal lines by the removable patterning; and
one providing electrical interconnection between the first layer of patterned metal lines and the second layer of patterned metal lines to form a metal interconnect structure after forming the second layer of patterned metal lines A method of fabricating a metal interconnect structure comprising forming one or more vias. The method of claim 1,
Forming the one or more vias comprises:
forming one or more via openings into the first layer of patterned metal lines at least through the second layer of patterned metal lines; and
and filling the one or more via openings with an electrically conductive material. The method of claim 1,
forming a first plurality of insulating features on the first layer of patterned metal lines; and
and after forming the plurality of first insulating features, forming a first dielectric material in spaces between adjacent metal lines of the first layer. 4. The method of claim 3,
forming a second plurality of insulating features on the second layer of patterned metal lines; and
and after forming the plurality of second insulating features, forming a second dielectric material in spaces between adjacent metal lines of the second layer. 5. The method of claim 4,
Forming the one or more vias comprises:
etching through one or more second insulating features;
etching through the second layer of patterned metal lines;
etching through one or more first insulating features to form one or more via openings to expose the first layer of patterned metal lines; and
and depositing an electrically conductive material in the one or more via openings to form the one or more vias on the exposed first layer of patterned metal lines. 6. The method of claim 5,
forming a via mask over the plurality of second insulating features and the second dielectric material; and
patterning one or more holes in the via mask, each of the one or more holes having a diameter greater than a critical dimension (CD) of the second layer of patterned metal lines and/or the first layer of patterned metal lines, or and patterning the holes having a width. 7. The method of claim 6,
wherein each of the one or more holes has a diameter or width at most about 100% greater than the CD of the second layer of patterned metal lines and/or the first layer of patterned metal lines. 7. The method of claim 6,
and depositing the electrically conductive material comprises filling the first insulating features and the second layer of patterned metal lines with the electrically conductive material previously etched. 6. The method of claim 5,
Etching through the one or more second insulating features is optional with respect to the second dielectric material surrounding the one or more second insulating features, and etching through the second layer of patterned metal lines comprises: selective with respect to the second dielectric material surrounding the second layer of patterned metal lines, and wherein etching through the one or more first insulating features comprises the first dielectric surrounding the one or more first insulating features. A method of fabricating a metal interconnect structure that is selective to the material 6. The method of claim 5,
wherein each of the first layer of patterned metal lines, the second layer of patterned metal lines, and the electrically conductive material comprises Mo, Ru, Al, or W. 5. The method of claim 4,
each of the first dielectric material and the second dielectric material comprises a low-k dielectric material, and each of the plurality of first insulating features and the plurality of second insulating features comprises the low-k dielectric material. k having a different etch selectivity than the dielectric material. 12. The method according to any one of claims 1 to 11,
and the one or more vias are fully aligned with the first layer of patterned metal lines and the second layer of patterned metal lines. 12. The method according to any one of claims 1 to 11,
The CD of the first layer of patterned metal lines and the second layer of patterned metal lines is about 20 nm or less. 12. The method according to any one of claims 1 to 11,
Forming a first layer of the patterned metal lines comprises:
depositing a first metal over the substrate;
depositing a first mask layer over the first metal;
etching the first mask layer to form a first plurality of insulating features over the first metal; and
etching the first metal to form a first layer of the patterned metal lines defined by the plurality of first insulating features;
Forming a second layer of the patterned metal lines comprises:
depositing a second metal over the first layer of patterned metal lines;
depositing a second mask layer over the second metal;
etching the second mask layer to form a second plurality of insulating features over the second metal; and
and etching the second metal to form patterned metal lines of the second metal defined by the plurality of second insulating features. A metal interconnect structure for an integrated circuit comprising:
a first layer of patterned metal lines;
a plurality of first insulating features on at least some of the patterned metal lines of the first layer of patterned metal lines;
a second layer of patterned metal lines over the first layer of patterned metal lines;
a plurality of second insulating features on at least a portion of the second layer of patterned metal lines; and
one or more vias providing electrical interconnection between the first layer of patterned metal lines and the second layer of patterned metal lines, the one or more vias comprising the first layer of patterned metal lines and the patterned metal lines and the one or more vias fully aligned with the second layer of metal lines. 16. The method of claim 15,
and the one or more vias extend through the first insulating features to contact the first layer of patterned metal lines with the second layer of patterned metal lines. 16. The method of claim 15,
a first dielectric material surrounding the first layer of patterned metal lines and the plurality of first insulating features; and
and a second dielectric material surrounding the second layer of patterned metal lines and the plurality of second insulating features. 18. The method of claim 17,
and a third dielectric material over the recessed via metal fill of the one or more vias. 18. The method of claim 17,
each of the first dielectric material and the second dielectric material comprises a low-k dielectric material, and each of the plurality of first insulating features and the plurality of second insulating features is different from the low-k dielectric material. A metal interconnect structure having etch selectivity. 20. The method according to any one of claims 15 to 19,
the one or more vias comprise an electrically conductive material, each of the first layer of patterned metal lines, the second layer of patterned metal lines, and the electrically conductive material comprising Mo, Ru, Al or W which is a metal interconnect structure.

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