WO2020112388A1

WO2020112388A1 - Metal interconnect structure by subtractive process

Info

Publication number: WO2020112388A1
Application number: PCT/US2019/061718
Authority: WO
Inventors: Thomas Weller Mountsier
Original assignee: Lam Research Corporation
Priority date: 2018-11-30
Filing date: 2019-11-15
Publication date: 2020-06-04
Also published as: CN113169117A; KR20210087550A; TW202036791A

Abstract

A metal interconnect structure of an integrated circuit may be fabricated by forming one or more vias subsequent to formation of two contiguous metallization layers. The one or more vias are fully aligned with a first metallization layer and a second metallization layer. Hardmask material or other insulating material is left on top of the first metallization layer and the second metallization layer during fabrication of the metal interconnect structure. Some of the hardmask material or other insulating material is etched and subsequently backfilled with electrically conductive material to form the one or more vias, where the one or more vias are contained within a space that does not overlap with surrounding dielectric material.

Description

METAL INTERCONNECT STRUCTURE BY SUBTRACTIVE

PROCESS

INCORPORATION BY REFERENCE

[0001] A PCT Request Form is filed concurrently with this specification as part of the present application. Each application that the present application claims benefit of or priority to as identified in the concurrently filed PCT Request Form is incorporated by reference herein in its entirety and for all purposes.

BACKGROUND

[0002] An interconnect structure incorporated in an integrated circuit (IC) includes one or more levels of metal lines to connect electronic devices of the IC to one another and to external connections. The levels of metal lines may be insulated front each other by one or more intervening layers of dielectric material. The interconnect structures may be formed by- additive patterning techniques or subtractive patterning techniques. An additive patterning technique may include a damascene or dual damascene process, which may be used to fabricate interconnect structures with metals such as copper and cobalt. Trenches and/or holes are etched into the dielectric material, metal is deposited into the trenches and/or holes, and the excess is removed using chemical-mechanical planarization (CMP). In a subtractive patterning technique, however, a blanket layer of metal is deposited and etched to form trenches and/or holes in the metal, and dielectric material is deposited into the trenches and/or holes.

[0003] The background provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent that it is described in this background, as -well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

SUMMARY

[0004] Provided herein is a method of manufacturing a metal interconnect structure. The method includes forming a first layer of patterned metal lines on a substrate by subtractive patterning and forming a second layer of patterned metal lines over the first layer of paterned metal lines by subtractive patterning. The method further includes forming, after forming the second layer of patterned metal lines, one or more vias providing electrical interconnection between the first layer of patterned metal lines and the second layer of patterned metal lines to form the metal interconnect structure.

[0005] In some implementations, forming the one or more vias includes forming one or more via openings through at least the second layer of patterned metal lines to the first layer of patterned metal lines and filling the one or more via openings with an electrically conductive material. In some implementations, the method further includes forming a plurality of first insulating features on the first layer of patterned metal lines and forming, after forming the plurality of first insulating features, a first dielectric material in spaces between adjacent metal lines of the first layer. The method further includes forming a plurality of second insulating features on the second layer of patterned metal lines and forming, after forming the plurality of second insulating features, a second dielectric material in spaces between adjacent metal lines of the second layer. In some implementations, forming the one or more vias includes etching through one or more second insulating features, etching through the second layer of patterned metal lines, etching through one or more first insulating features to form one or more via openings to expose the first layer of patterned metal lines, and depositing electrically conductive material in the one or more via openings to form the one or more vias on the exposed first layer of patterned metal lines. In some implementations, the method further includes forming a via mask over the plurality of second insulating features and the second dielectric material and patterning one or more holes in the via mask, where the one or more holes each has a diameter or width greater than a critical dimension (CD) of the second layer of patterned metal lines and/or the first layer of patterned metal lines. The one or more holes each can have a diameter or width up to about 100% greater than the CD of the second layer of patterned metal lines and/or the first layer of patterned metal lines. In some implementations, depositing the electrically conductive material includes filling with the electrically conductive material where the first insulating features and the second layer of patterned metal lines w^ere previously etched. In some implementations, each of the first layer of patterned metal lines, the second layer of patterned metal lines, and the electrically conductive material comprises molybdenum (Mo), ruthenium (Ru), aluminum (Al), or tungsten (W). In some implementations, the one or more vias are fully aligned with the first layer of patterned metal lines and the second layer of patterned metal lines. In some implementations, forming the first layer of patterned metal lines includes depositing a first metal over the substrate, depositing a first mask layer over the first metal, etching a first mask layer to form a plurality of first insulating features over the first metal, and etching the first metal to form the first layer of patterned metal lines defined by the plurality of first insulating features. In some implementations, forming the second layer of patterned metal lines includes depositing a second metal over the first layer of patterned metal lines, depositing a second mask layer over the second metal, etching the second mask layer to form a plurality of second insulating features over the second metal, and etching the second metal to form the second metal of patterned metal lines defined by the plurality of second insulating features.

[0006] Another aspect involves a metal interconnect structure for an integrated circuit. The metal interconnect structure includes a first layer of patterned metal lines, a plurality of first insulating features on at least some of the patterned metal lines of the first layer of the patterned metal lines, a second layer of patterned metal lines over the first layer of patterned metal lines, a plurality of second insulating features on at least some of the patterned metal lines of the second layer, and one or more vias providing electrical interconnection between the first layer of patterned metal lines and the second layer of patterned metal lines, where the one or more vias are fully aligned with the first layer of patterned metal lines and the second layer of patterned metal lines.

[0007] In some implementations, the one or more vias extend through the first insulating features to contact the first layer of patterned metal lines with the second layer of patterned metal lines. In some implementations, the metal interconnect structure further includes a first dielectric material surrounding the first layer of patterned metal lines and the plurality of first insulating features, and a second dielectric material surrounding the second layer of patterned metal lines and the plurality of second insulating features. In some implementations, the metal interconnect structure further includes a third dielectric material over a recessed via metal fill of the one or more vias. In some implementations, each of the first dielectric material and the second dielectric material includes a low-k dielectric material, where each of the plurality of first insulating features and the plurality of second insulating features has a different etch selectivity than the low-k dielectric material. In some implementations, the one or more vias include an electrically conductive material, where each of the first layer of patterned metal lines, the second layer of patterned metal lines, and the electrically conductive material includes Mo, Ru, Al, or W.

[0008] These and other aspects are described further below with reference to the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures lA-10 show schematic illustrations of an example process of forming a metal interconnect structure by subtractive patterning.

[0010] Figure 2 A shows a cross-sectional schematic illustration of an example partially fabricated metal interconnect structure from line A- A of Figure IF.

[0011] Figure 2B-1 shows a cross-sectional schematic illustration of an example partially fabricated metal interconnect structure from line B-B of Figure 1H where via openings are aligned with underlying metal lines.

[0012] Figure 2B-2 show's a cross-sectional schematic illustration of an example partially fabricated metal interconnect structure from line C-C of Figure 1H where via openings are misaligned with underlying metal lines.

[0013] Figure 2C-1 shows a cross-sectional schematic illustration of an example partially fabricated metal interconnect structure from line C-C of Figure 1J where vias are aligned with underlying metal lines.

[0014] Figure 2C-2 show's a cross-sectional schematic illustration of an example partially fabricated metal interconnect structure from line C-C of Figure IJ where vias are misaligned with underlying metal lines.

[0015] Figure 2D-1 show's a cross-sectional schematic illustration of an example metal interconnect structure from line D-D of Figure IN where vias are aligned with overlying metal lines

[0016] Figure 2D-2 shows a cross-sectional schematic illustration of an example metal interconnect structure from line D-D of Figure IN where vias are misaligned with overlying metal lines.

[0017] Figure 3 shows a flow' diagram of an example method of manufacturing a metal interconnect structure in an integrated circuit according to some implementations.

[0018] Figures 4A-4N show' schematic illustrations of an example process of forming a metal interconnect structure with fully aligned vias by subtractive patterning according to some implementations.

[0019] Figure 5 A shows a cross-sectional schematic illustration of an example partially fabricated metal interconnect structure from line A-A of Figure 4J according to some implementations.

[0020] Figure 5B shows a cross-sectional schematic illustration of an example partially fabricated metal interconnect structure from line B-B of Figure 4] according to some implementations.

[0021] Figure 5C show's a cross-sectional schematic illustration of an example metal interconnect structure from line C-C of Figure 4N according to some implementations.

[0022] Figure 5D shows a cross-sectional schematic illustration of an example metal interconnect structure from line D-D of Figure 4N according to some implementations.

DETAILED DESCRIPTION

[0023] In the present disclosure, the terms“semiconductor wafer,”“wafer,”“substrate,” “wafer substrate,” and“partially fabricated integrated circuit” are used interchangeably. One of ordinary skill in the art would understand that the term“partially fabricated integrated circuit” can refer to a silicon wafer during any of many stages of integrated circuit fabrication thereon. A wafer or substrate used in the semiconductor device industry_' typically has a diameter of 200 mm, or 300 mm, or 450 mm. The following detailed description assumes the present disclosure is implemented on a wafer. However, the present disclosure is not so limited. The work piece may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other work pieces that may take advantage of the present disclosure include various articles such as printed circuit boards and the like.

Introduction

[0024] Advances in integrated circuit technology have involved scaling to smaller and smaller features in integrated circuits. Integrated circuits commonly include electrically conductive microelectronic structures or vias that connect electrically conductive structures or layers. The electrically conductive structures may include line features (e.g , metal lines or metallization layers) that traverse a distance across a chip, and interconnect features (e.g., vias) that connect the line features in different levels. The line features and interconnect features may be insulated by dielectric materials.

[0025] Damascene and dual damascene fabrication techniques have been employed to produce vias and metal lines in metal interconnect structures. Damascene and dual damascene techniques are additive patterning techniques that have been relied upon in fabricating metal interconnect structures such as copper interconnect structures. However, as feature sizes in integrated circuits continue to shrink, additive patterning techniques may not be sufficient for certain technology nodes. Subtractive patterning techniques may be suitable where additive patterning techniques are deficient.

[0026] Generally speaking, a subtractive patterning technique deposits a blanket layer of metal, applies a mask to the blanket layer of metal, and etches the blanket layer of metal to pattern metal lines or features defined by the mask. In contrast, an additive patterning technique deposits a blanket layer of dielectric material, applies a mask to the blanket layer of dielectric material, etches openings or recesses into the blanket layer of the dielectric material defined by the mask, and fills the openings or recesses with metal. Typical metals used in additive patterning techniques include copper (Cu) or cobalt (Co). Copper has high electrical conductivity (second to silver), which makes it very desirable as an interconnect metal. However, metals such as copper and cobalt are challenging to etch and thus are not good candidates for the subtractive patterning techniques commonly used in integrated circuit fabrication.

[0027] Typical subtractive patterning techniques employed metals such as aluminum (Al) in manufacturing metal lines and metal interconnect structures. Line widths manufactured by subtractive patterning techniques were generally on the order of a few microns to hundreds of nanometers. Copper damascene techniques were introduced many years ago for manufacturing copper lines and copper interconnect structures, where line widths manufactured by damascene techniques were generally on the order of tens and hundreds of nanometers. However, line widths equal to or less than about 30 nm or equal to or less than about 20 nm have been difficult to reliably achieve using copper damascene techniques. For example, copper interconnect structures normally require diffusion barrier layers and/or liner layers to limit diffusion of copper into surrounding dielectric materials, and such layers can occupy more space and consequently make smaller line widths more difficult to achieve. Metals other than copper may be used in subtractive patterning that can tolerate thinner diffusion barrier layers and/or liner layers, or none at all. This can enable smaller dimensions and/or technology nodes in integrated circuit fabrication.

[0028] Figures 1A--1Q show schematic illustrations of an example process of forming a metal interconnect structure by subtractive patterning. In Figure 1A, a first layer of metal 101 (Mx) is deposited over a substrate 100. The first layer of metal 101 in Figure 1A is a blanket layer that has not yet been patterned. The first layer of metal 101 may be deposited using any suitable deposition process such as physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or electrodeposition. Electrodeposition can include, for example, electroplating or electroless plating. In some implementations, the first layer of metal 101 can include metals that can be etched, where such metals can include but are not limited to molybdenum (Mo), ruthenium (Ru), tungsten (W), or aluminum (Al). In some implementations, a liner layer may be disposed between the first layer of metal 101 and substrate 100. An example of a liner layer includes but is not limited to titanium nitride (TiN). Other examples include tantalum nitride (TaN), tungsten nitride (WN), and tungsten carbon nitride (WCN). A thickness of the liner layer can be equal to or less than about 5 nm or equal to or less than about 3 nm. In some implementations, a dielectric layer 102 may be disposed between the liner layer and the substrate 100. The liner layer serves to separate the first layer of metal 101 from the dielectric layer 102.

[0029] To pattern the first layer of metal 101, a first hardmask layer 103 may be deposited over the first layer of metal 101. Examples of suitable hardmask materials may include silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, amorphous silicon, polysilicon, or carbon (e.g , amorphous carbon, metal-doped amorphous carbon, diamond-like carbon, polycrystalline diamond). The first hardmask layer 103 may be paterned using a photoresist 104 and resist underlayer 105 subject to extreme ultraviolet (EUV) lithography. Additional layers may be formed between the photoresist and the first hardmask layer, where the additional layers may be useful in photolithography processes. For example, an amorphous carbon layer 106 (a-C) and an anti -reflective layer 107 (ARE) may be disposed between the photoresist 104 and the first hardmask layer 103. The anti- reflective layer 107 may serve to prevent radiation in subsequent photolithographic processes from reflecting off layers below and interfering with the exposure process.

[0030] In Figure IB, a plurality of first hardmask features 108 are formed by patterning the first hardmask layer 103. The plurality of first hardmask features 108 may be defined by- patterning the photoresist 104 using photolithography (e.g., EUV lithography). Moreover, in some implementations, feature sizes of the first hardmask features may be reduced by a self- aligned double patterning (SADP) process. By way of an example, narrower hardmask features can be formed by pitch doubling, where the pitch in the plurality of first hardmask features 108 can be lowered from 80 ran to 40 nrn using a SADP process.

[0031] In Figure 1C, additional mask layers may be optionally deposited and patterned over the plurality of first hardmask features 108. The additional mask layers may be patterned for etching the underlying plurality of first hardmask features 108 into a desired arrangement of first hardmask features for patterning the first layer of metal 101. In turn, the first layer of metal 101 may be patterned and“cut” according to the desired arrangement of first hardmask features 108. In some implementations, additional mask layers may include a photoresist 109, a resist underlayer 110, and spin-on carbon 1 11 (SoC). It will be appreciated, however, that instead of using the additional mask layers for etching the underlying plurality of first hardmask features 108, the etching of the first hardmask features 108 may be applied after etching the first layer of metal 101. In other words, the first layer of metal 101 is“cut” by the additional mask layers rather than having the plurality of first hardmask features 108 undergo a“cut.”

[0032] In Figure ID, the plurality of first hardmask features 108 are patterned by the additional mask layers. The additional mask layers form the plurality of first hardmask features 108 into a desired arrangement of features by a“cut” etch process. The additional mask layers are subsequently removed.

[0033] In Figure IE, the first layer of metal 101 is patterned to form the first layer of patterned metal lines 112. The first layer of patterned metal lines 112 are defined by the plurality of first hardmask features 108 during a metal line etch process. The metal line etch process may selectively etch through the metal to form the first layer of patterned metal lines 112 without etching the underlying dielectric layer 102. A suitable etchant may be used to etch metal without etching or without substantially etching dielectric material of the underlying dielectric layer 102. As used herein,“without substantially etching” can refer to etch processes where an etch rate of a subject material (e.g., dielectric) is at least 5 times less than an etch rate of a target material to be etched (e.g., metal). For example, a subtractive plasma etch may remove the blanket layer of metal at a substantially higher etch rate than the underlying dielectric layer 102. After the first layer of patterned metal lines 112 is formed, the plurality of hardmask features 108 may be removed. In some implementations, a diffusion barrier layer and/or liner layer may be deposited on the first layer of patterned metal lines 112. The diffusion barrier layer and/or liner layer separates the first layer of patterned metal lines 112 from surrounding dielectric material.

[0034] In Figure IF, first dielectric material 113 is deposited over the first layer of patterned metal lines 112 and fills in spaces between adjacent first metal lines. The first dielectric material 113 can surround the first layer of patterned metal lines 112. After etching the blanket layer of metal to form the first layer of patterned metal lines 112, the first dielectric material 1 13 fills in gaps, recesses, openings, or spaces that were previously filled by the blanket layer of metal. In some implementations, after the first dielectric material 113 is deposited, the first dielectric material 113 may be planarized by a planarization process such as chemical mechanical polishing (CMP) and/or blanket etchback. In some implementations, the first dielectric material 1 13 is a dielectric material having a low dielectric constant (low-k dielectric). A low-k dielectric can have a dielectric constant equal to or less than about 5.0, which may be equal to or less than a dielectric constant of silicon oxide (about 4.2). Low-k dielectric materials may include a fluorine-doped or carbon-doped silicon oxide or an organic-containing low-k material such as an organosilicate glass (OSG) In some implementations, air gaps may be formed in the first dielectric material 113 between adjacent patterned metal lines, where the air gaps may serve to further reduce the dielectric constant of the first dielectric material 113 between adjacent patterned metal lines. Such air gaps 114 may be observed in Figure 2A in a cross-sectional schematic illustration of the partially fabricated metal interconnect structure taken from line A-A of Figure IF. As shown in Figure 2A, the first dielectric material 113 fills spaces in between adjacent patterned metal lines. Air gaps 114 are formed in the first dielectric material 113 in the spaces between adjacent patterned metal lines, where the patterned metal lines are separated from the air gaps 114 by remaining first dielectric material 113.

[0035] In Figure 1G, a via mask 1 15 may be formed over the first dielectric material 113. In some implementations, the via mask 1 15 may include one or more mask layers, where the one or more mask layers include a photoresist 1 16, a resist underlayer 117, and spin-on carbon 118 (SoC). To form vias that connect to the first layer of paterned metal lines 112, via openings will be patterned and formed in the first dielectric material 1 13 as defined by the via mask 115. A photolithography process may be applied to the photoresist 116 to patern the photoresist 1 16 of the via mask 115. One or more holes 1 19 may be formed in the via mask 1 15 for defining the via openings in the first dielectric material 113. The one or more holes 1 19 in the via mask 115 are intended to align with the first layer of patterned metal lines 112. [0036] In Figure 1H, via openings 120 are formed in the first dielectric material 113 by etching. The via openings 120 are defined by the one or more holes 119 of the via mask 1 15. The via openings 120 are intended to align with one or more patterned metal lines of the first layer 112. However, as discussed below', alignment errors may arise during the photolithography process that may cause the via openings 120 to not be aligned with the one or more paterned metal lines of the first layer 112. The via mask 115 may be removed after forming the via openings 120 Via openings 120 that are perfectly aligned with one or more paterned metal lines of the first layer 112 may be observed in Figure 2B-1, whereas via openings 120 that are not aligned with one or more patterned metal lines of the first layer 1 12 may be observed in Figure 2B-2.

[0037] With shrinking feature sizes, the scaling of conventional photolithography processes to provide smaller feature sizes can be difficult. This is due at least in part to alignment or overlay errors between features in a metal interconnect structure. Alignment or overlay errors invariably result during a photolithography process as a mask is not perfectly aligned with an underlying structure. For example, during light exposure stages using a reticle in a photolithography process, there can be misalignment by a few nanometers in patterning masks for vias and trenches. As a result, a via intended to connect with patterned metal lines may be misaligned. Although overlay errors can be minimized by reworking the photolithography process, some amount of overlay error is unavoidable.

[0038] As shown in Figure 2B-1, when via openings 120 patterned from the one or more mask layers are perfectly aligned with the first layer of patterned metal lines 112, the via openings 120 are not offset from the first layer of patterned metal lines 112. The via openings 120 are formed directly over the first layer of patterned metal lines 1 12 without being formed in a space between adjacent patterned metal lines of the first layer 112. However, alignment or overlay errors may cause one or more mask layers to be offset in an x-direction or y-direction even by a few nanometers. As shown in Figure 2B-2, via openings 120 are patterned from the one or more mask layers and are misaligned with the first layer of patterned metal lines 1 12 The misalignment causes a portion of the via openings 120 to be formed in spaces between adjacent paterned metal lines of the first layer 112. The misalignment results in loss of contact area between the patterned metal line of the first layer 112 and the via, and the via overlaps with portions of dielectric material surrounding the first layer of patterned metal lines 112. Furthermore, the misalignment can risk breach of nearby air gaps 114 that can lead to a short-circuit or current leak. [0039] In Figure II, a second layer of metal 121 (Mx+1) is deposited over the first dielectric material 113, where the second layer of metal 121 fills the via openings 120 to form one or more vias. The second layer of metal 121 provides a blanket layer of metal over the first dielectric material 1 13. In some implementations, a liner layer is disposed between the second layer of metal 121 and the first dielectric material 113. The liner layer may also be disposed between the one or more patterned metal lines of the first layer 112 and the vias. The second layer of metal 121 may provide an overburden of metal over the first dielectric material 113 or it may be deposited to the target thickness for the second layer of metal 121. Deposition of the second layer of metal 121 may result in surface topography issues or surface roughness that may be attributable to metal filling the via openings 120 and blanketing the first dielectric material 113. In some implementations, a planarization process may be used to planarize the second layer of metal 121 to create a relatively smooth, flat sheet of metal. In some implementations, the second layer of metal 121 is deposited by a suitable deposition technique such as PVD, CVD, PECVD, ALD, or electrodeposition. In some implementations, the second layer of metal 121 includes Mo, Ru, Ai, or W. In some implementations, the via openings 120 may be filled by a separate metal deposition process than the metal deposition process for depositing metal on the first dielectric material 113. For example, the via openings 120 may be filled with one of the metals listed above using a suitable deposition process. This can be followed by a separate process for depositing a blanket layer of one of the metals listed above on the first dielectric material 113 and connected to the vias. In some implementations, a planarization process may be performed to a desired thi ckness of the second layer of metal 121.

[0040] In Figure 1J, a second hardma.sk layer 122 is deposited over the second layer of metal 121. Examples of suitable hardmask materials include silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, amorphous silicon, polysilicon, or carbon (e g., amorphous carbon, metal-doped amorphous carbon, diamond-like carbon, polycrystalline diamond). The second hardmask layer 122 may be patterned using a photoresist 123 and resist underlayer 124 subject to EUV lithography. Additional layers may be formed between the photoresist 123 and the second hardmask layer 122, where the additional layers may be useful in photolithography processes. For example, an amorphous carbon 125 (a-C) and an anti -reflective layer 126 (ARE) may be disposed between the photoresist 123 and the second hardmask layer 122,

[0041] Figures 2C-1 and 2C-2 show cross-sectional schematic illustrations of the partially fabricated metal interconnect structure taken from line C-C of Figure 1J. As shown in Figures 2C-1 and 2C-2, the second layer of metal 121 fills the via openings 120 to form vias 127 providing electrical interconnection with the first layer of patterned metal lines 112. The vias 127 are perfectly aligned with the first layer of patterned metal lines 112 in Figure 2C-1. However, due to alignment or overlay errors, vias 127 are not aligned with the first layer of patterned metal lines 112 as shown in Figure 2C-2. Due to alignment and overlay errors, vias 127 partially“land” on a top surface of one or more patterned metal lines of the first layer 112, thereby shifting the vias 127 closer to neighboring patterned metal lines of the first layer 112 and into surrounding dielectric material. This leads to a reduced distance between conductive features, meaning that there is less insulating space between a via 127 and a neighboring patterned metal line of the first layer 1 12. The reduced distance can lead to an insufficient shorting margin and decreased time-dependent dielectric breakdown (TBBD), or even a complete short-circuit. TDDB is a failure mode whereby an insulating layer (such as the first dielectric material 113) breaks down over time and no longer serves as an adequate electrical insulator in typical electric fields. TDDB is dependent on the electric field between metal lines as regions exposed to higher electrical fields are more susceptible to TDDB failure. High voltages and/or reduced insulator thickness will lead to higher electrical fields. TDDB is also dependent on the spacing between adjacent metal lines as the spacing can be reduced to the point where the insulating layer is incapable of withstanding the electric fields, thereby resulting in unintended conductance between adjacent metal lines. The end result is shorting or decreased reliability when the insulating layer is incapable of supporting the operating electric field. “Unlanded” vias can lead to significant reliability issues because of TDDB degradation. Furthermore,“unlanded” vias can result in breach of underlying air gaps 1 14 that get deposited with electrically conductive materials, which can lead to a short- circuit.

[0042] In Figure IK, a plurality of second hardmask features 128 are formed by patterning the second hardmask layer 122 The plurality of second hardmask features 128 may be defined by patterning the photoresist 123 using photolithography (e.g., EUV lithography). Moreover, in some implementations, feature sizes of the second hardmask features 128 may^¬ be reduced by a self-aligned double patterning (SADP) process. By way of an example, narrower hardmask features can be formed by pitch doubling, where the pitch in the plurality of second hardmask features 128 can be lowered from 40 ntn to 20 nm using a SADP process. [0043] In Figure 1L, additional mask layers may be optionally deposited and patterned over the plurality of second hardmask features 128. The additional mask layers may be patterned for etching the underlying plurality of second hardmask features 128 into a desired arrangement of second hardmask features 128 for patterning the second layer of metal 121. In turn, the second layer of metal 121 may be patterned and“cut” according to the desired arrangement of second hardmask features 128. In some implementations, additional mask layers may include a photoresist 129, a resist underlayer 130, and spin-on carbon 131 (SoC). It will be appreciated, however, that instead of using the additional mask layers for etching the underlying plurality of second hardmask features 128, the etching of the second hardmask features 128 may be applied after etching the second layer of metal 121. In other words, the second layer of metal 121 is“cut” by the additional mask layers rather than having the plurality of second hardmask features 128 undergo a“cut.”

[0044] In Figure 1M, the plurality of second hardmask features 128 are patterned by the additional mask layers. The additional mask layers form the plurality of second hardmask features 128 into a desired arrangement of features by a“cut” etch process. The additional mask layers are subsequently removed.

[0045] In Figure IN, the second layer of metal 121 is patterned to form the second layer of patterned metal lines 132. The patterned metal lines are defined by the plurality of second hardmask features 128 during a metal line etch process. The metal line etch process may selectively etch through the metal to form the second layer of patterned metal lines 132 without etching the first dielectric material 113. A suitable etchant may be used to remove metal without etching or without substantially etching the first dielectric material 113. For example, a subtractive plasma etch may remove the blanket layer of metal at a substantially higher etch rate than the underlying first dielectric material 113. After the second layer of patterned metal lines 132 is formed, the plurality of second hardmask features 128 may be removed. In some implementations, a diffusion barrier layer and/or liner layer may be deposited on the second layer of patterned metal lines 132. The diffusion barrier layer and/or liner layer separates the second layer of patterned metal lines 132 from surrounding dielectric material.

[0046] Vias 127 provide electrical interconnection between the second layer of patterned metal lines 132 and the first layer of patterned metal lines 1 12 to form a metal interconnect structure. As discussed earlier, when patterning one or more holes 119 in the via mask 115, there is a risk of misalignment with the first layer of patterned metal lines 112. Not only is there the risk of misalignment with the first layer of patterned metal lines 112 (Mx), but there is also the risk of misalignment with the second layer of patterned metal lines 132 (Mx+1). When patterning the second layer of patterned metal lines 132, there is a risk of misalignment between the vias 127 and the second layer of patterned metal lines 132. Figure 2D-1 shows a cross-sectional schematic illustration of a metal interconnect structure from line D-D of Figure IN where vias 127 are aligned with the second layer of patterned metal lines 132, There is no loss of contact area between the vias 127 and the second layer of paterned metal lines 132 in Figure 2D-1. Figure 2D-2 shows a cross-sectional schematic illustration of a metal interconnect structure from line D-D of Figure IN where vias 127 are misaligned with the second layer of patterned metal lines 132. There is a loss of contact area between the vias 127 and the second layer of patterned metal lines 132 in Figure 2D-2 as a result of the misalignment. This leads to a loss of via area. Electrical resistance is directly proportional to a resistivity of a material and its length, and inversely proportional to a cross-sectional area of the material. The loss of via area results in higher via resistance, which leads to reduced performance and reduced reliability.

[0047] In Figure 10, dielectric material 133 is deposited over the second layer of patterned metal lines 132 and fills in spaces between adjacent second metal lines, in essentially the same manner as for Mx. This dielectric material 133, which is hereinafter referred to as a second dielectric material, can surround the second layer of paterned metal lines 132. After etching the blanket layer of metal to form the second layer of patterned metal lines 132, the second dielectric material 133 fills in gaps, recesses, openings, or spaces that were previously filled by the blanket layer of metal. In some implementations, after the second dielectric material 133 is deposited, it may be planarized by a planarization process such as CMP and/or blanket etchback. In some implementations, the second dielectric material 133 is a iow-k dielectric material. In some implementations, the second dielectric material 133 shares the same composition as the first dielectric material 113. In some implementations, air gaps may be formed in the second dielectric material between adjacent second metal lines, where the air gaps may serve to further reduce the dielectric constant of the second dielectric material 133 between adjacent second metal lines. After the second dielectric material 133 is deposited, a metal interconnect structure is fabricated. The metal interconnect structure formed by subtractive patterning techniques has a first layer of patterned metal lines 1 12 and a second layer of patterned metal lines 132 over the first layer of patterned metal lines 112, where one or more vias 127 provide electrical interconnection betw-een the first layer of patterned metal lines 112 and the second layer of patterned metal lines 132 It will be appreciated that additional metal lines (e.g., Mx+2, Mx+3, etc.) may deposited and patterned to build on the metal interconnect structure. The additional metal lines may be formed in the same or similar fashion as the second layer of patterned metal lines 132 and the first layer of patterned metal lines 112.

Self-Aligned Vi as in Subtractive Patterning

[0048] The present disclosure relates to fabrication of a metal interconnect structure where one or more vias are formed subsequent to formation of two contiguous metallization layers. The one or more vias are formed by filling one or more via openings with electrically conductive material after patterning a first layer of metal and after patterning second layer of metal. The metal interconnect structure is fabricated by subtractive patterning techniques. The one or more vias are aligned with each of the two contiguous metallization layers. Alignment between the one or more vias and the contiguous metallization layers is achieved by leaving some hardmask material or other insulating separation material on top of patterned metal lines after forming the two contiguous metallization layers. Some of the remaining insulating separation material is removed when etching through one of the contiguous metallization layers to form the one or more via openings. Due to differences in etch selectivity between surrounding dielectric material and the insulating separation material, and differences in etch selectivity between the surrounding dielectric material and a contiguous metallization layer, formation of one or more vias are contained within a space that does not form into the surrounding dielectric material. In some implementations, the one or more vias are fully aligned with the two contiguous metallization layers to provide improved contact area, reduced electrical resistivity, reduced risk of TBBD failure, and reduced risk of shorting.

[0049] Figure 3 shows a flow diagram of an example method of manufacturing a metal interconnect structure in an integrated circuit according to some implementations. The operations in a process 300 may be performed in different orders and/or with different, fewer, or additional operations.

[0050] At block 310 of the process 300, a first layer of patterned metal lines (Mx) on a substrate is formed by subtractive patterning. In some implementations, the substrate is a semiconductor wafer, built on a semiconductor wafer, or part of a semiconductor wafer. The substrate may include a dielectric layer upon which the first layer of patterned metal lines is formed. In some implementations, a diffusion barrier layer and/or liner layer may be deposited on the dielectric layer to separate the first layer of patterned metal lines from the dielectric layer. The first layer of patterned metal lines represents a first metallization layer in a metal interconnect structure. As used herein, a layer of patterned metal lines may also be referred to as a metallization layer, metal layer, metal lines, metal features, or line features. The first layer of patterned metal lines or the first metallization layer may also be referred to as a botom layer of patterned metal lines or a bottom metallization layer.

[0051] Formation of the first layer of patterned metal lines by subtractive patterning can involve one or more operations at block 310 of the process 300. In some implementations, forming the first layer of patterned metal lines includes depositing a first metal layer over the substrate, depositing a first insulating layer over the first metal layer, etching the first insulating layer to form a plurality of first insulating features over the first metal layer, and etching the first metal layer to form the first layer of patterned metal lines defined by the plurality of first insulating features. In some implementations, the first insulating layer may^¬ be a first hardmask layer and the first insulating features may be first hardmask features. The first metal layer can include any suitable metal that can be etched and patterned using subtractive patterning techniques. For example, the first metal layer can include Mo, Ru, Al, or W. In some implementations, the first metal layer is deposited using any suitable deposition technique such as PVD, CVD, PECVD, ALD, or electrodeposition. Electrodeposition can include, for example, electroplating or electroless plating. In some implementations, a critical dimension (CD) of the paterned metal lines of the first layer (Mx) is equal to or less than about 50 nm, equal to or less than about 20 nm, equal to or less than about 15 n n, or equal to or less than about 10 nm. In some implementations, a pitch of the patterned metal lines of the first layer (Mx) is equal to or less than about 100 nm, equal to or less than about 40 n n, equal to or less than about 30 nrn, or equal to or less than about 20 nm.

[0052] In some implementations, the process 300 further includes forming a plurality of first insulating features on the first metal layer. The plurality of first insulating features may define the patterned metal lines in the first metal layer. The process 300 further includes forming a first dielectric material in spaces between adjacent metal lines. The first dielectric material may surround the plurality of first insulating features and the first layer of patterned metal lines. The plurality of first insulating features are retained after formation of the first dielectric material to cover top surfaces of the first layer of patterned metal lines. This can serve to contain subsequent etch processes when forming one or more vias.

[0053] Figures 4A-4D show schematic illustrations of an example process of forming a first layer of patterned metal lines over a substrate by subtractive patterning. Forming the first layer of patterned metal lines at block 310 of the process 300 may involve different, fewer, or additional operations than what is shown in Figures 4A-4D. In Figure 4A, a first layer of metal 401 (Mx) is deposited over a substrate 400. The first layer of metal 401 in Figure 4 A is a blanket layer of metal that has not yet been patterned. In some implementations, a liner layer may be disposed between the first layer of metal 401 and substrate 400. An example of a liner layer includes but is not limited to titanium nitride (TiN). Other examples include tantalum nitride (TaN), tungsten nitride (WN), and tungsten carbon nitride (WCN). A thickness of the liner layer can be equal to or less than about 5 nm or equal to or less than about 3 nm. In some implementations, a dielectric layer 402 may be disposed between the liner layer and the substrate 400. The liner layer serves to separate the first layer of metal 401 from the dielectric layer 402.

[0054] To pattern the first layer of metal 401, a first hardmask layer 403 may be deposited over the first layer of metal 401. Examples of suitable hardmask materials may include silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, amorphous silicon, polysilicon, or carbon (e.g., amorphous carbon, metal-doped amorphous carbon, diamond-like carbon, polycrystalline diamond). The first hardmask layer 403 may be patterned using a photoresist 404 and resist underlayer 405 as described in Figure 1A, and optionally with an amorphous carbon layer 406 and an anti -reflective layer 407 disposed between the photoresist 404 and the first hardmask layer 403 as described in Figure 1 A.

[0055] In Figure 413, a plurality of first hardmask features 408 are formed by paterning the first hardmask layer 403. Patterning the first hardmask layer 403 may be achieved by patterning the photoresist 404 using photolithography (e.g., EUV lithography). In some implementations, smaller feature sizes can be formed by pitch doubling as described in Figure IB. In some implementations, additional masking operations may be performed to “cut” the first hardmask features 408 into a desired arrangement of first hardmask features 408 as described in Figures 1C and ID. In turn, the first layer of metal 401 will be patterned as defined by the first hardmask features 408 following the additional masking and cutting operations. [0056] In Figure 4C, the first layer of metal 401 is patterned to form the first layer of patterned metal lines 409. The first layer of patterned metal lines 409 is defined by the plurality of first hardmask features 408 during a metal line etch process. The metal line etch process may selectively etch through the metal to form the first layer of patterned metal lines

409 without etching or without substantially etching the underlying dielectric layer 402. For example, a subtractive plasma etch may remove the blanket layer of metal at a substantially higher etch rate than the underlying dielectric layer 402. Instead of removing the plurality of first hardmask features 408 from the first layer of patterned metal lines 409 in Figure 4C, the plurality of first hardmask features 408 are retained. In some implementations, a liner layer and/or diffusion barrier layer may be deposited on the plurality of first hardmask features 408 and on the first layer of patterned metal lines 409. The liner layer and/or diffusion barrier layer separates the first layer of patterned metal lines 409 and plurality of first hardmask features 408 fro surrounding dielectric material.

[0057] In Figure 4D, first dielectric material 410 is deposited around the first layer of patterned metal lines 409 and the plurality of first hardmask features 408 and fills in spaces between adjacent patterned metal lines. The first dielectric material 410 can surround the first layer of patterned metal lines 409 and the first hardmask features 408. In some implementations, the first dielectric material 410 is deposited over the plurality of first hardmask features 408. After etching the blanket layer of metal to form the first layer of patterned metal lines 409, the first dielectric material 410 fills in gaps, recesses, openings, or spaces that were previously filled by the blanket layer of metal. In some implementations, after the first dielectric material 410 is deposited, the first dielectric material 410 and the plurality of first hardmask features 408 may be planarized by a planarization process such as CMP and/or blanket etchback. The planarization process may expose top surfaces of the first hardmask features 408 covering the first layer of patterned metal lines 409. The top surfaces of the first hardmask features 408 and the first dielectric material 410 are coplanar. In some implementations, the first dielectric material 410 is a low-k dielectric material. Low-k dielectric materials may include a fluorine-doped or carbon-doped silicon oxide or an organic-containing low-k material such as OSG. In some implementations, air gaps may be formed in the first dielectric material 410 between adjacent patterned metal lines, where the air gaps may serve to further reduce the dielectric constant of the first dielectric material 410 between adjacent patterned metal lines. Air gaps are formed in the first dielectric material

410 in the spaces between adjacent paterned metal lines, where the patterned metal lines are separated from the air gaps by remaining first dielectric material 410.

[0058] Returning to Figure 3, at block 320 of the process 300, a second layer of patterned metal lines are formed over the first layer of patterned metal lines by subtractive patterning. In some implementations, a diffusion barrier layer and/or liner layer may be deposited on exposed surfaces of the first dielectric material and the plurality of first insulating features. The second layer of patterned metal lines represents a second metallization layer in the metal i nterconnect structure .

[0059] Formation of the second layer of patterned metal lines by subtractive patterning can involve one or more operations at block 320 of the process 300. In some implementations, forming the second layer of patterned metal lines includes depositing a second metal layer over the first dielectric material and over the first layer of patterned metal lines, depositing a second insulating layer over the second metal layer, etching the second insulating layer to form a plurality of second insulating features over the second metal layer, and etching the second metal layer to for the second layer of patterned metal lines defined by the plurality of second insulating features. In some implementations, the second insulating layer may be a second hardmask layer and the second insulating features may be second hardmask features. The second metal layer can include any suitable metal that can be etched and patterned using subtractive patterning techniques. For example, the second metal layer can include Mo, Ru, Al, or W. In some implementations, the second metal layer is the same material as the first metal layer. In some implementations, the second metal layer is deposited using any suitable deposition technique such as PVD, CVD, PECVD, ALD, or electrodeposition. Electrodeposition can include, for example, electroplating or electroless plating. In some implementations, a critical dimension of the patterned metal lines of the second layer (Mx+1) is equal to or less than about 50 nm, equal to or less than about 20 nm, equal to or less than about 15 nm, or equal to or less than about 10 nm. In some implementations, a pitch of the patterned metal lines of the second layer (Mx+1) is equal to or less than about 100 nm, equal to or less than about 40 nm, equal to or less than about 30 nm, or equal to or less than about 20 nm.

[0060] In some implementations, the process 300 further includes forming a plurality of second insulating features on the second metal layer. The plurality of second insulating features may define the second layer of patterned metal lines in the second metal layer. The process 300 further includes forming a second dielectric material in spaces between adjacent metal lines. The second dielectric material may surround the plurality of second insulating features and the second layer of patterned metal lines. The plurality of second insulating features are retained after formation of the second dielectric material to cover top surfaces of the second layer of patterned metal lines. This can serve to contain subsequent etch processes when forming one or more vias.

[0061] Figures 4E---4H show schematic illustrations of an example process of forming a second layer of patterned metal lines over the first layer of patterned metal lines by subtractive patterning. Forming the second layer of patterned metal lines at block 320 of the process 300 may involve different, fewer, or additional operations than what is shown in Figures 4E-4H. In Figure 4E, a second layer of metal 411 (Mx+1) is deposited over the first layer of patterned metal lines 409, and over the first dielectric material 410 and over the plurality of first hardmask features 408. The second layer of metal 411 in Figure 4E provides a blanket layer of metal over the first dielectric material 410 and the plurality of first hardmask features 408 In some implementations, a liner layer is disposed between the second layer of metal 411 and the first dielectric material 410 and between the second layer of metal 411 and the plurality of first hardmask features 408. In patterning the second layer of metal 411, a second hardmask layer 412 may be deposited over the second layer of metal 411, where the second hardmask layer 412 may be patterned using a photoresist 413 and resist underlayer 414 as described in Figure 1J, and optionally with an amorphous carbon layer 415 and an anti -reflective layer 416 disposed between the photoresist 413 and the second hardmask layer 412 as described in Figure 1 J.

[0062] In Figure 4F, a plurality of second hardmask features 417 are formed by patterning the second hardmask layer 412. Patterning the second hardmask layer 412 may be achieved by patterning the photoresist 413 using photolithography (e.g., EUV lithography). In some implementations, smaller feature sizes can be formed by pitch doubling as described in Figure IK. In some implementations, additional masking operations may be performed to “cut” the second hardmask features 417 into a desired arrangement of second hardmask features 417 as described in Figures 1L and 1M. In turn, the second layer of metal 411 will be patterned as defined by the second hardmask features 417 following the additional masking and cutting operations.

[0063] In Figure 4G, the second layer of metal 411 is patterned to form the second layer of patterned metal lines 418. The second layer of patterned metal lines 418 is defined by the plurality of second hardmask features 417 during a metal line etch process. The metal line etch process may selectively etch through the second layer of metal 411 to form the second layer of patterned metal lines 418 without etching or without substantially etching the first dielectric material 410 and the plurality of first hardmask features 408. For example, a subtractive plasma etch may remove the blanket layer of metal at a substantially higher etch rate than the first dielectric material 410 and the plurality of first hardmask features 408. As used herein,“a substantially higher etch rate” can refer to an etch rate that is at least 5 times greater for the target material to be etched than other materials. Instead of removing the plurality of second hardmask features 417 from the second layer of patterned metal lines 418 in Figure 4G, the plurality of second hardmask features 417 are retained. In some implementations, a liner layer and/or diffusion hairier layer may be deposited on the plurality of second hardmask features 417 and on the second layer of patterned metal lines 418. The liner layer and/or diffusion barrier layer separates the second layer of patterned metal lines 418 and plurality of second hardmask features 417 from surrounding dielectric material.

[0064] In Figure 4H, second dielectric material 419 is deposited around the second layer of patterned metal lines 418 and the plurality of second hardmask features 417 and fills in spaces between adjacent patterned metal lines. The second dielectric material 419 can surround the second layer of patterned metal lines 418 and the second hardmask features 417. In some implementations, the second dielectric material 419 is deposited over the plurality of second hardmask features 417. After etching the blanket layer of metal to form the second layer of patterned metal lines 418, the second dielectric material 419 fills in gaps, recesses, openings, or spaces that were previously filled by the blanket layer of metal. In some implementations, after the second dielectric material 419 is deposited, the second dielectric material 419 and the plurality of second hardmask features 417 may be planarized by a planarization process such as CMP and/or blanket etchback. The planarization process may- expose top surfaces of the second hardmask features 417 covering the second layer of patterned metal lines 418. The top surfaces of the second hardmask features 417 and the second dielectric material 419 are coplanar. In some implementations, the second dielectric material 419 is a low-k dielectric material. In some implementations, air gaps may be formed in the second dielectric material 419 between adjacent patterned metal lines, where the patterned metal lines are separated from the air gaps by remaining second dielectric material 419.

[0065] Returning to Figure 3, at block 330 of the process 300, one or more vias are formed providing electrical interconnection between the first layer of patterned metal lines and the second layer of patterned metal lines to form a metal interconnect structure. The one or more vias are formed subsequent to formation of the first layer of patterned metal lines and the second layer of patterned metal lines. In addition, the one or more vias are formed subsequent to subtractive patterning of the first layer of metal and filling in spaces around the first layer of patterned metal lines with first dielectric material, and subsequent to subtractive patterning of the second layer of metal and filling in spaces around the second layer of patterned metal lines with second dielectric material. In other words, patterning the one or more vias occurs after two metallization layers are defined

[0066] Formation of the one or more vias can involve one or more operations at block 330 of the process 300. The one or more vias may be formed by forming one or more via openings through at least the second layer of patterned metal lines to the first layer of patterned metal lines and filling the one or more via openings with an electrically conductive material. Forming the one or more via openings can include etching through one or more second insulating features, etching through the second layer of patterned metal lines, and etching through one or more first insulating features. Etching through three or more layers of materials without etching or without substantially etching surrounding materials can present many challenges. In some implementations, etching through one or more second insulating features occurs without etching or without substantially etching the second dielectric material. In some implementations, etching through the second layer of patterned metal lines occurs without etching or without substantially etching the second dielectric material. In some implementations, etching through the one or more first insulating features occurs without etching or without substantially etching the first dielectric material. As used herein, “without substantially etching” can refer to etch processes where an etch rate of a subject material (e.g., dielectric) is at least 5 times less than an etch rate of a target material to be etched (e.g., hardmask). In other words, the target material to be etched has an etch selectivity equal to or greater than about 5:1 against other materials. Etching through the three or more layers of materials may use the same etch process with the same etchant, or may use different etch processes with different etchants. In some implementations, filling the one or more via openings with the electrically conductive material includes backfilling where the second layer of patterned metal lines and where the one or more first insulating features were etched away. Such backfilling forms the one or more vias to provide electrical connection with the remaining second layer of patterned metal lines. [0067] Forming the one or more via openings to the first layer of patterned metal lines can be constrained by the first insulating features and the second insulating features so that the one or more via openings are not offset or misaligned. Specifically, the first insulating features and the second insulating features serve to constrain the etch process so that via openings are not formed into the surrounding dielectric materials. Without retaining the first insulating features and the second insulating features after formation of the first layer of patterned metal lines and the second layer of patterned metal lines, alignment or overlay errors can occur that create unwanted electrical connections (e.g., unwanted shorts) between the first layer of patterned metal lines and the second layer of patterned metal lines.

[0068] The material difference between the first and second insulating features and the surrounding dielectric materials drives an etch contrast so via formation is contained, thereby allowing for one or more vias to be self-aligned with the first layer of patterned metal lines and with the second layer of patterned metal lines. Conventional fabrication processes for providing vias between metallization layers generally use the same dielectric material as a spatial offset between the metallization layers, whereas the first and second insulating features of the present disclosure provide a material difference with the surrounding dielectric material having a different etch selectivity.

[0069] Vertical walls of surrounding dielectric material serve as etch boundaries that constrain a via etch so that via formation is aligned with the first layer of patterned metal lines and the second layer of patterned metal lines. The via etch does not extend into surrounding dielectric material or adjacent vias. By constraining via formation, this ensures self-alignment of the one or more vias with the first layer of patterned metal lines and the second layer of patterned metal lines. When the one or more vias are aligned with at least the first layer of patterned metal lines, the one or more vias directly contact top surfaces of the first layer of patterned metal lines with no overlap. Thus, the one or more vias do not overlap with the first dielectric material and address TDDB degradation and shorting concerns caused by misaligned vias. When the one or more vias are aligned with at least the second layer of patterned metal lines, the one or more vias are filled with electrically conductive material where the one or more patterned metal lines of the second layer were previously etched and having no overlap with the second dielectric material. This addresses the reduced contact area, higher via resistance, and reduced reliability concerns caused by misaligned vias. Therefore, the self-aligned via patterning scheme may provide the one or more vias to be fully aligned with the second layer of patterned metal lines and the first layer of patterned metal lines.

[0070] In some implementations, the process 300 further includes depositing a via mask over the second plurality of insulating features and the second dielectric material, and patterning one or more holes in the via mask for defining the one or more via openings. Each of the one or more holes has a diameter or width greater than a critical dimension of the second layer of patterned metal lines and/or the first layer of patterned metal lines. In some implementations, each of the one or more holes has a diameter or width up to about 100% greater than a critical dimension of the second layer of patterned metal lines and/or the first layer of patterned metal lines. The diameter or width of the one or more holes in the via mask is over-sized so as to be greater than a diameter or width of the one or more vias actually formed. That way, any misalignment between the one or more holes and underlying layers to be etched does not result in leaving behind target material to be etched. By having over-sized holes, this also ensures that the underlying layers to be etched are actually etched regardless of any alignment errors. This is due in part to having the second insulating features selective against the second dielectric material during etching, having the second layer of patterned metal lines selective against the second dielectric material during etching, and having the first insulating features selective against the first dielectric material during etching. However, it will be appreciated that the diameter or width of the one or more holes is not so large that it risks extending into adjacent metal lines. Thus, the diameter or width of the one or more holes in the via mask is slightly over-sized to account for tolerance in misalignment, but not so over-sized that it etches into other metal lines.

[0071] Figures 4I-4L show schematic illustrations of an example process of forming one or more vias to provide electrical interconnection between the first layer of patterned metal lines and the second layer of patterned metal lines. Forming the one or more vias at block 330 of the process 300 may involve different, fewer, or additional operations than what is shown in Figures 4I-4L In Figure 41, a via mask 420 is formed over the plurality of second hardmask features 417 and the second dielectric material 419. The via mask 420 may have one or more holes 421 for patterning one or more via openings through at least the second layer of patterned metal lines 418. The via mask 420 may include one or more layers for patterning, where the one or more layers may include a photoresist 422, a resist underlayer 423, spin-on carbon 424 (SoC), and a mask layer 425 (e.g., hardmask layer). A photolithography process may be applied to the photoresist 422 to pattern the mask layer 425, where one or more holes may be formed in the mask layer 425. Portions of the mask layer 425 may be etched to form the one or more holes for defining the one or more via openings. The one or more holes in the mask layer 425 are intended to align with the second hardmask features 417, the second layer of patterned metal lines 418, and the first hardmask features 408 in which one or more vias will be formed. In some implementati ons, a diameter of the one or more holes is greater than a critical dimension of the second layer of patterned metal lines 418 and/or the first layer of patterned metal lines 409. In some implementations, a critical dimension of the first layer of patterned metal lines 409 or the second layer of patterned metal lines 418 may be equal to or less than about 50 nm, equal to or less than about 20 nm, or equal to or less than about 10 nm. In some implementations, the diameter is between about 1% and about 100% greater, between about 5% and about 100% greater, or between about 10% and about 50% greater than the critical dimension of the second layer of patterned metal lines 418 and/or the first layer of patterned metal lines 409. The diameter of the one or more holes is greater than the actual one or more via openings formed through the second layer of patterned metal lines 418, where the difference in size accounts for some tolerance in misalignment without etching adjacent metal lines. In some implementations, the mask layer 425 of the via mask 420 includes a material that is different than materials of the second hardmask features 417, second layer of patterned metal lines 418, and the first hardmask features 408.

[0072] In Figure 4J, one or more via openings 426 are formed through at least the second layer of patterned metal lines 418 to the first layer of patterned metal lines 409 by etching. The one or more via openings 426 are defined by the one or more holes 421 in the via mask 420. The one or more via openings 426 are intended to be aligned with one or more paterned metal lines of the second layer 418 and one or more paterned metal lines of the first layer 409. Tolerance in misalignment may be accounted for by leaving electrically insulating material (e.g., first and second hardmask features) on top surfaces of paterned metal lines that have different etch selectivity than surrounding dielectric materials. That way, the electrically insulating material serves to constrain etch processes so that the one or more via openings 426 are not formed into the surrounding dielectric materials. Tolerance in misalignment may also be accounted for by having slightly over-sized holes in the via mask 420 and by ensuring that the etching is selective to the second hardmask features 417, the second layer of patterned metal lines 418, and the first hardmask features 408 over surrounding dielectric materials. That way, over-sized holes in the via mask 420 reduce the risk of etch processes missing targeted materials to be etched, and so forming the one or more via openings 426 does not leave any of the targeted materials behind. [0073] Forming the one or more via openings 426 includes etching through one or more second hardmask features 417, etching through the second layer of patterned metal lines 418, and etching through one or more first hardmask features 408. Etching stops on the first layer of patterned metal lines 409. The first layer of patterned metal lines 409 is exposed after etching. Etching through the one or more second hardmask features 417 is selective against the second dielectric material 419, etching through the second layer of patterned metal lines 418 is selective against the second dielectric material 419, and etching through the one or more first hardmask features 408 is selective against the first dielectric material 410. Formation of via openings 426 through one or more second hardmask features 417, through the second layer of patterned metal lines 418, and through one or more first hardmask features 408 may be observed in Figures 5A and 5B taken along line A-A and line B-B, respectively, of Figure 4J.

[0074] In Figure 4K, electrically conductive material 427 is deposited in the one or more via openings 426 to fill the one or more via openings 426. One or more vias 428 are formed by filling the one or more via openings 426 where the one or more first hardmask features 408 and the second layer of patterned metal lines 418 were previously filled. In some implementations, the electrically conductive material 427 is the same material as the first layer of patterned metal lines 409 and the second layer of patterned metal lines 418. For example, the electrically conductive material 427 includes Mo, Ru, Al, or W. In some implementations, the electrically conductive material 427 is a different material than the first layer of patterned metal lines 409 and the second layer of patterned metal lines 418. In some implementations, the electrically conductive material 427 is deposited by a suitable deposition technique such as PVD, CVD, PECVD, ALD, or electrodeposition for at least substantially filling the one or more via openings 426. In some implementations, a diffusion barrier layer and/or liner layer may be deposited in the one or more via openings 426 before filling the one or more via openings 426 with the electrically conductive material 427. The diffusion barrier layer and/or liner layer may separate the one or more vias 428 from surrounding dielectric materials.

[0075] The one or more vias 428 are formed by backfilling with electrically conductive material 427 where the second layer of patterned metal lines 418 and the one or more first hardmask features 408 were etched away. The electrically conductive material 427 contacts the exposed first layer of patterned metal lines 409 and provides electrical interconnection with the second layer of patterned metal lines 418 by backfilling. In some implementations, the electrically conductive material 427 is deposited to fill the one or more via openings 426, to fill the one or more holes in the mask layer 425, and to provide a blanket layer of the electrically conductive material 427 over the one or more via openings 426. This provides an overburden of the electrically conductive material 427 over the one or more via openings 426.

[0076] In Figure 4L, a portion of the electrically conductive material 427 is removed so that remaining portions of the electrically conductive materi al 427 fill where the one or more first hardmask features 408 and the second layer of patterned metal lines 418 previously filled the one or more via openings 426. Such a removal of the portion of the electrically conductive material 427 includes etching the electrically conductive material 427 that is over the one or more via openings 426, that is in the one or more holes in the mask layer 425, and that is where the one or more second hardmask features 417 previously filled the one or more via openings 426. This removes the overburden of the electrically conductive material 427 and leaves electrically conductive material 427 up to a bottom level of the second hardmask features 417. Thus, one or more recesses may be formed through the one or more holes to the bottom level of the second hardmask features 417, thereby providing at least a recessed metal fill 429 to the bottom level of the second hardmask features 417. A metal interconnect structure is fabricated having two contiguous metallization layers connected by one or more fully aligned vias 428 at Figure 4L.

[0077] Returning to Figure 3, the process 300 can further include covering exposed portions of the electrically conductive material with a third dielectric material. In some implementations, the third dielectric material may be deposited over recessed via metal fill and the second insulating features. The third dielectric material may be etched or polished to be coplanar with the second insulating features. In some implementations, the third dielectric material can be the same material as the second insulating features.

[0078] In some implementations, the process 300 can further include forming a third layer of patterned metal lines (Mx+2) over the second layer of patterned metal lines by subtractive patterning. The third layer of patterned metal lines may represent a third metallization layer in the metal interconnect structure. In some implementations, one or more additional vias may be formed providing electrical interconnection between the second layer of patterned metal lines and the third layer of patterned metal lines. Additional metallization layers and vias may continue to be fabricated in the metal interconnect structure, where the additional metallization layers may be formed in the same or similar manner as the first metallization layer and the second metallization layer, and the additional vias may be formed in the same or similar manner as the one or more vias providing electrical interconnection between the first layer of patterned metal lines and the second layer of patterned metal lines.

[0079] Figures 4M-4N show schematic illustrations of an example process of capping the recessed via metal fill with a third dielectric material. Capping the recessed via metal fill may involve different, fewer, or additional operations than what is shown in Figures 4M-4N. In Figure 4M, a third dielectric material 430 is deposited over the plurality of second hardmask features 417 and the recessed via metal fill 429. The third dielectric material 430 may be deposited in one or more recesses formed after removing portions of the electrically conductive material 427 filling the one or more via openings 426. In some implementations, the third dielectric material 430 is the same material as the second hardmask features 417 In some implementations, the third dielectric material 430 is deposited over the mask layer 425. The third dielectric material 430 may be the same material or same type of material as the mask layer 425. The third dielectric material 430 is deposited to cover exposed portions of the electrically conductive material 427.

[0080] In Figure 4N, a planarization process is performed to remove the third dielectric material 430 up to the second hardmask features 417. The planarization process can include CMP and/or blanket etchback so that the third dielectric material 430 is coplanar with the second hardmask features 417. Furthermore, the mask layer 425 over the plurality of second hardmask features 417 may be removed with the removal of some of the third dielectric material 430. The third dielectric material 430 and the second hardmask features 417 serve to cap or otherwise cover the second layer of patterned metal lines 418. Additional layers of patterned metal lines and additional vias may be subsequently formed in the same or similar manner the first layer of patterned metal lines 409, the second layer of patterned metal lines 418, and the one or more vias 428. After capping the recessed via metal fill 429, a metal interconnect structure can be observed in Figures 5C and 5D taken along lines C-C and D-D, respectively, in Figure 4N. The metal interconnect structure in Figures 5C and 5D show fully aligned vias 428 providing electrical interconnection between the first layer of patterned metal lines 409 and the second layer of patterned metal lines 418.

[0081] A metal interconnect structure is formed after the formation of the one or more vias 428 in providing electrical interconnection between the first layer of patterned metal lines 409 and the second layer of patterned metal lines 418. An example metal interconnect structure of an integrated circuit is illustrated in Figures 5C and 5D. A metal interconnect structure can include the first layer of patterned metal lines 409, a plurality of first insulating features 431 on at least some of the patterned metal lines of the first layer 409, a second layer of patterned metal lines 418 over the first layer of patterned metal lines 409, and a plurality of second insulating features 432 on at least some of the patterned metal lines of the second layer 418 The metal interconnect structure further includes one or more vias 428 providing electrical interconnection between the first layer of patterned metal lines 409 and the second layer of patterned metal lines 418, where the one or more vias 428 are fully aligned with the first layer of patterned metal lines 409 and the second layer of patterned metal lines 418. A first dielectric material 410 surrounds the first layer of patterned metal lines 409 and the plurality of first insulating features 431. A second dielectric material 419 surrounds the second layer of patterned metal lines 418 and the second insulating features 432. The one or more vias 428 are fully aligned so that the one or more vias 428 directly contact the first layer of patterned metal lines 409 having no overlap with the first dielectric material 410 or the second dielectric material 419. The one or more vias 428 are formed after patterning the first layer of metal lines 409 and the second layer of metal lines 418.

[0082] In some implementations, the metal interconnect structure further includes a third dielectric material 430 over the recessed via metal fill 429, where top surfaces of the second layer of patterned metal lines 418 are covered by the second insulating features 432 and the recessed via metal fill 429 is covered by the third dielectric material 430. In some implementations, the third dielectric material 430 is the same material as the second insulating features 432. In some implementations, each of the first dielectric material 410 and the second dielectric material 419 is a low-k dielectric material. The first insulating features 431 and the second insulating features 432 have a different etch selectivity than the low-k dielectric material. In some implementations, the first layer of patterned metal lines 409 and the second layer of patterned metal lines 418 include Mo, Ru, Al, or W. In some implementations, the one or more vias 428 include Mo, Ru, Al, or W, where a material of the one or more vias 428 is the same or different than a material of the first layer of the patterned metal lines 409 and the second layer of patterned metal lines 418.

[0083] The process described herein may be used in conjunction with lithographic patterning tools or processes, for example, for the fabrication or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels and the like. Typically, though not necessarily, such tools/processes will be used or conducted together in a common fabrication facility. Lithographic patterning of a film typically includes some or all of the following operations, each operation enabled with a number of possible tools: (1) application of photoresist on a workpiece, i.e., substrate, using a spin-on or spray-on tool; (2) curing of photoresist using a hot plate or furnace or IJV curing tool, (3) exposing the photoresist to visible or UV or x-ray light with a tool such as a wafer stepper; (4) developing the resist so as to selectively remove resist and thereby pattern it using a tool such as a wet bench, (5) transferring the resist pattern into an underlying film or workpiece by using a dry or plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper.

Conclusion

[0084] In the foregoing description, numerous specific details are set forth to provide a thorough understanding of the presented implementations. The disclosed implementations may be practiced without some or all of these specifi c details. In other instances, well-known process operations have not been described in detail to not unnecessarily obscure the disclosed implementations. While the disclosed implementations are described in conjunction with the specific implementations, it will be understood that it is not intended to limit the disclosed implementations.

[0085] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the present embodiments. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.

Claims

CLAIMS What is claimed is:

1. A method of manufacturing a metal interconnect structure, the method comprising: forming a first layer of paterned metal lines on a substrate by subtractive paterning, forming a second layer of patterned metal lines over the first layer of paterned metal lines by subtractive patterning; and forming, after forming the second layer of paterned metal lines, one or more vias providing electrical interconnection between the first layer of patterned metal lines and the second layer of patterned metal lines to form the metal interconnect structure.

2. The method of claim 1, wherein forming the one or more vias comprises: forming one or more via openings through at least the second layer of patterned metal lines to the first layer of patterned metal lines; and filling the one or more via openings with an electrically conductive material .

3. The method of claim 1, further comprising: forming a plurality of first insulating features on the first layer of patterned metal lines, and forming, after forming the plurality of first insulating features, a first dielectric material in spaces between adjacent metal lines of the first layer.

4. The method of claim 3, further comprising: forming a plurality of second insulating features on the second layer of patterned metal lines; and forming, after forming the plurality of second insulating features, a second dielectric material in spaces between adjacent metal lines of the second layer.

5. The method of claim 4, wherein forming the one or more vias comprises: etching through one or more second insulating features; etching through the second layer of patterned metal lines; etching through one or more first insulating features to form one or more via openings to expose the first layer of patterned metal lines; and depositing electrically conductive material in the one or more via openings to form the one or more vias on the exposed first layer of patterned metal lines.

6. The method of claim 5, further comprising: forming a via mask over the plurality of second insulating features and the second dielectric material; and patterning one or more holes in the via mask, wherein the one or more holes each has a diameter or width greater than a critical dimension (CD) of the second layer of patterned metal lines and/or the first layer of patterned metal lines.

7. The method of claim 6, wherein the one or more holes each has a diameter or width up to about 100% greater than the CD of the second layer of patterned metal lines and/or the first layer of patterned metal lines.

8. The method of claim 6, wherein depositing the electrically conductive material comprises filling with the electrically conductive material where the first insulating features and the second layer of patterned metal lines were previously etched.

9. The method of claim 5, wherein etching through the one or more second insulating features is selective against the second dielectric material surrounding the one or more second insulating features, and wherein etching through the second layer of patterned metal lines is selective against the second dielectric material surrounding the second layer of patterned metal lines, and wherein etching through the one or more first insulating features is selective against the first dielectric material surrounding the one or more first insulating features.

10. The method of claim 5, wherein each of the first layer of patterned metal lines, the second layer of patterned metal lines, and the electrically conductive material comprises Mo, Ru, Al, or W

1 1. The method of claim 4, wherein each of the first dielectri c material and the second dielectric material includes a low-k dielectric material, and wiierein each of the plurality of first insulating features and the plurality of second insulating features has a different etch selectivity than the low-k dielectric material.

12. The method of any one of claims 1-1 1, wherein the one or more vias are fully

aligned with the first layer of patterned metal lines and the second layer of patterned metal lines

13. The method of any one of claims 1 -1 1, wherein a CD of the first layer of patterned metal lines and the second layer of patterned metal lines is equal to or less than about 20 ran.

14. The method of any one of claims 1-11, wherein forming the first layer of patterned metal lines comprises: depositing a first metal over the substrate; depositing a first mask layer over the first metal; etching a first mask layer to form a plurality of first insulating features over the first metal; and etching the first metal to form the first layer of patterned metal lines defined by the plurality of first insulating features; wherein forming the second layer of patterned metal lines compri ses: depositing a second metal over the first layer of patterned metal lines; depositing a second mask layer over the second metal; etching the second mask layer to form a plurality of second insulating features over the second metal; and etching the second metal to form the second metal of patterned metal lines defined by the plurality of second insulating features.

15. A metal interconnect structure for an integrated circuit, the metal interconnect

structure comprising: a first layer of patterned metal lines; a plurality of first insulating features on at least some of the patterned metal lines of the first layer of the patterned metal lines; a second layer of patterned metal lines over the first layer of patterned metal lines; a plurality of second insulating features on at least some of the patterned metal lines of the second layer; and one or more vias providing electrical interconnection between the first layer of patterned metal lines and the second layer of patterned metal lines, wherein the one or more vias are fully aligned with the first layer of patterned metal lines and the second layer of patterned metal lines.

16. The metal interconnect structure of claim 15, wherein the one or more vias extend through the first insulating features to contact the first layer of patterned metal lines with the second layer of patterned metal lines.

17. The metal interconnect structure of claim 15, further comprising: a first dielectric material surrounding the first layer of patterned metal lines and the plurality of first insulating features; and a second dielectric material surrounding the second layer of patterned metal lines and the plurality of second insulating features.

18. The metal interconnect structure of claim 17, further comprising: a third dielectric material over a recessed via metal fill of the one or more vias.

19. The metal interconnect structure of claim 17, wherein each of the fi rst dielectric material and the second dielectric material includes a low-k dielectric material, and wherein each of the plurality of first insulating features and the plurality of second insulating features has a different etch selectivity than the low-k dielectric material.

20. The metal interconnect structure of any one of claims 15-19, wherein the one or more vias include an electrically conductive material, wherein each of the first layer of patterned metal lines, the second layer of patterned metal lines, and the electrically conductive material includes Mo, Ru, Al, or W.