KR20200129671A - 패키지 온 패키지 및 이를 포함하는 패키지 연결 시스템 - Google Patents

패키지 온 패키지 및 이를 포함하는 패키지 연결 시스템 Download PDF

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KR20200129671A
KR20200129671A KR1020190054427A KR20190054427A KR20200129671A KR 20200129671 A KR20200129671 A KR 20200129671A KR 1020190054427 A KR1020190054427 A KR 1020190054427A KR 20190054427 A KR20190054427 A KR 20190054427A KR 20200129671 A KR20200129671 A KR 20200129671A
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South Korea
Prior art keywords
package
semiconductor chip
disposed
semiconductor
wiring layer
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KR1020190054427A
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English (en)
Korean (ko)
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이영관
허영식
소원욱
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삼성전기주식회사
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Application filed by 삼성전기주식회사 filed Critical 삼성전기주식회사
Priority to KR1020190054427A priority Critical patent/KR20200129671A/ko
Priority to TW108126756A priority patent/TW202042371A/zh
Priority to US16/531,625 priority patent/US10840225B1/en
Priority to CN201911074537.1A priority patent/CN111916429A/zh
Publication of KR20200129671A publication Critical patent/KR20200129671A/ko

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KR1020190054427A 2019-05-09 2019-05-09 패키지 온 패키지 및 이를 포함하는 패키지 연결 시스템 KR20200129671A (ko)

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TW108126756A TW202042371A (zh) 2019-05-09 2019-07-29 堆疊式封裝以及包括其的封裝連接系統
US16/531,625 US10840225B1 (en) 2019-05-09 2019-08-05 Package-on-package and package connection system comprising the same
CN201911074537.1A CN111916429A (zh) 2019-05-09 2019-11-06 层叠封装件及包括该层叠封装件的封装件连接系统

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US10199337B2 (en) 2015-05-11 2019-02-05 Samsung Electro-Mechanics Co., Ltd. Electronic component package and method of manufacturing the same
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US10672744B2 (en) * 2016-10-07 2020-06-02 Xcelsis Corporation 3D compute circuit with high density Z-axis interconnects
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