KR20200086241A - Liquid crystal display device - Google Patents

Abstract

A liquid crystal display device according to one embodiment of the present invention includes: a display panel receiving a plurality of gate signals and a plurality of data voltages, and displaying an image based on a plurality of frames; a timing controller which generates a data control signal and a plurality of vertical start signals corresponding to the frames; a gate driver which outputs a plurality of gate signals in response to a vertical start signal according to each frame; and a data driver generating the data voltages in response to the data control signal, wherein the timing controller controls the frames to have different frequencies by setting activation times of the vertical start signals corresponding to the frames.

Description

Liquid crystal display device{LIQUID CRYSTAL DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, to a liquid crystal display device based on time division driving.

The liquid crystal display device is one of the most widely used flat panel display devices. The liquid crystal display device includes two substrates on which an electric field generating electrode such as a pixel electrode and a common electrode is formed, and a liquid crystal layer interposed therebetween. The alignment of the liquid crystal molecules included in the liquid crystal layer may be determined in response to a voltage difference between the pixel electrode and the common electrode. The liquid crystal display device can display an image by controlling polarization of incident light transmitted from the outside to the liquid crystal layer.

In particular, the liquid crystal display device based on the vertical alignment (Vertical Alignment, VA) mode is in the spotlight because of its high contrast ratio and easy implementation of a wide reference viewing angle. Here, the reference viewing angle means a viewing angle having a contrast ratio of 1:10 or an inverted luminance limit angle between gradations.

In a liquid crystal display device based on VA mode, as a means for realizing a wide viewing angle, there are a method of forming an incision in the field generating electrode and a method of forming a projection on the field generating electrode. The reference viewing angle can be widened by dispersing the inclined direction of the liquid crystal molecules in various directions using an incision or a projection.

However, the liquid crystal display based on VA mode has a problem in that side visibility is inferior to that of front visibility. For example, in the case of a patterned vertically aligned (PVA) type liquid crystal display equipped with an incision, a luminance difference between high gray levels disappears toward the side, resulting in a case where the picture looks clumped.

An object of the present invention is to provide a liquid crystal display device with improved visibility.

A liquid crystal display according to an embodiment of the present invention for achieving the above object is provided with a plurality of gate signals and a plurality of data voltages, a display panel for displaying an image based on a plurality of frames, a data control signal and A timing controller generating a plurality of vertical start signals corresponding to the frames, a gate driver outputting a plurality of gate signals in response to a vertical start signal according to each frame, and generating the data voltages in response to the data control signal Including a data driver, the timing controller controls the frames to have different frequencies by setting different activation times of the vertical start signals corresponding to the frames.

In one embodiment of the present invention, the plurality of frames includes a first sub-frame and a second sub-frame.

In one embodiment of the present invention, the display panel includes a plurality of pixels displaying the image by receiving the corresponding data voltages in response to the gate signals, wherein the pixels include the first subframe and the One image is displayed in response to the second sub-frame.

In one embodiment of the present invention, the data driver outputs a plurality of data voltages corresponding to the first sub-frame to the pixels, and a plurality of data voltages corresponding to the second sub-frame to the pixels. Output.

In one embodiment of the present invention, the gray level of the data voltages corresponding to the first sub-frame is set higher than that of the data voltages corresponding to the second sub-frame.

In one embodiment of the present invention, the activation period of the vertical start signal corresponding to the second sub frame is set longer than the activation period of the vertical start signal corresponding to the first sub frame.

In one embodiment of the present invention, the activation period of the gate signals output in response to the vertical start signal of the second sub frame is longer than the activation period of the gate signals output in response to the vertical start signal of the first sub frame. Is set.

A liquid crystal display according to another embodiment of the present invention for achieving the above object is provided with a plurality of gate signals and a plurality of data voltages, a display panel for displaying an image based on a plurality of frames, a data control signal and A timing controller generating a plurality of vertical start signals corresponding to the frames, a gate driver outputting a plurality of gate signals in response to a vertical start signal according to each frame, and generating the data voltages in response to the data control signal It includes a data driver, a backlight unit for supplying light to the display panel, the timing controller controls the frames to have different frequencies by differently setting the activation time of the vertical start signals corresponding to the frames, The backlight unit supplies light at different cycles for each of the frames.

In another embodiment of the present invention, the timing controller further generates a backlight control signal, but the backlight unit supplies light as a different cycle for each frame in response to the backlight control signal.

In another embodiment of the present invention, the plurality of frames includes a first sub-frame and a second sub-frame.

In another embodiment of the present invention, the display panel includes a plurality of pixels displaying the image by receiving the corresponding data voltages in response to the gate signals, wherein the pixels include the first subframe and the One image is displayed in response to the second sub-frame.

In another embodiment of the present invention, the data driver outputs a plurality of data voltages corresponding to the first sub-frame to the pixels, and a plurality of data voltages corresponding to the second sub-frame to the pixels. Output.

In another embodiment of the present invention, based on the light period output from the backlight unit, the gradation value of the data voltages corresponding to the first sub-frames and the data voltages corresponding to the second sub-frames Further comprising a gradation control unit for adjusting the.

In another embodiment of the present invention, the gray level of the data voltages corresponding to the first sub-frame is set higher than that of the data voltages corresponding to the second sub-frame.

In another embodiment of the present invention, the backlight unit continuously supplies light during the first sub-frame, and supplies light at a predetermined time period during the second sub-frame.

In another embodiment of the present invention, the backlight unit supplies light at a predetermined time period during the first sub-frame and the second sub-frame.

In another embodiment of the present invention, the activation period of the vertical start signal corresponding to the second sub frame is set longer than the activation period of the vertical start signal corresponding to the first sub frame.

In another embodiment of the present invention, the activation period of gate signals output in response to the vertical start signal of the second sub frame is longer than the activation period of gate signals output in response to the vertical start signal of the first sub frame. Is set.

The display device according to an exemplary embodiment of the present invention operates based on time-division driving, thereby improving visibility of the liquid crystal display device.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.
2 is a circuit diagram of pixels disposed on the display panel shown in FIG. 1.
3 is a graph showing response characteristics of typical liquid crystal molecules based on time division driving.
4 is a timing diagram showing an operation of a gate driver based on time division driving according to an embodiment of the present invention.
5 is a graph showing response characteristics of liquid crystal molecules based on the operation of the gate driver illustrated in FIG. 3.
6 is a block diagram of a liquid crystal display according to another exemplary embodiment of the present invention.
7 is a timing diagram showing the operation of a gate driver and a backlight unit based on time division driving according to an embodiment of the present invention.
8 is a timing diagram showing operations of a gate driver and a backlight unit based on time division driving according to another embodiment of the present invention.

The present invention may be variously modified and may have various forms, and specific embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosure form, and it should be understood that all modifications, equivalents, and substitutes included in the spirit and scope of the present invention are included.

In describing each drawing, similar reference numerals are used for similar components. In the accompanying drawings, the dimensions of the structures are shown to be enlarged than the actual for clarity of the present invention. Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from other components. For example, the first component may be referred to as a second component without departing from the scope of the present invention, and similarly, the second component may be referred to as a first component. Singular expressions include plural expressions unless the context clearly indicates otherwise.

In this application, the terms "include" or "have" are intended to indicate the presence of features, numbers, steps, actions, components, parts or combinations thereof described herein, one or more other features. It should be understood that the existence or addition possibilities of fields or numbers, steps, actions, components, parts or combinations thereof are not excluded in advance.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the liquid crystal display device 10 includes a timing controller 110, a gate driver 120, a data driver 130, and a display panel 140.

The timing controller 110 receives a plurality of image signals RGB and a plurality of control signals CS from the outside of the liquid crystal display 10. The timing controller 110 converts the data format of the image signals RGB to meet the interface specification with the data driver 130. The image signals RGB' in which the data format is converted are provided to the data driver 130.

In addition, the timing controller 110 generates the data control signal D-CS and the gate control signal G-CS in response to the control signals CS. For example, the data control signal D-CS may include an output start signal and a horizontal start signal. The gate control signal G-CS may include a vertical start signal and a vertical clock bar signal. The timing controller 110 provides the data control signal D-CS to the data driver 130 and the gate control signal G-CS to the gate driver 120.

In an embodiment, the liquid crystal display 10 according to the present invention may output an image based on a field sequential type. In detail, unlike the conventional liquid crystal display device that displays one image based on one frame, the liquid crystal display device 10 according to the present invention can display one image based on two frames. On the other hand, the liquid crystal display 10 according to the present invention is described as displaying one image based on two frames, but is not limited thereto. That is, one image may be displayed based on a plurality of frames according to frequency setting.

The timing controller 110 may generate a gate control signal G-CS and a data control signal D-CS based on a plurality of frames according to the frequency setting.

The gate driver 120 sequentially outputs a gate signal in response to the gate control signal G-CS provided from the timing controller 110. The plurality of pixels PX11 to PXnm included in the display panel 140 may be scanned row by row and sequentially by gate signals.

The data driver 130 converts the image signals RGB' converted from the data format into a plurality of data voltages in response to the data control signal D-CS provided from the timing controller 110. The data driver 130 outputs data voltages to the display panel 140.

The display panel 140 includes a plurality of gate lines GL1 to GLn, a plurality of data lines DL1 to DLm, and a plurality of pixels PX11 to PXnm.

The gate lines GL1 to GLn extend in the row direction and are disposed to intersect the data lines DL1 to DLm extending in the column direction. The gate lines GL1 to GLn are electrically connected to the gate driver 120 to receive gate signals. The data lines DL1 to DLm are electrically connected to the data driver 130 to receive data voltages. Each of the pixels PX11 to PXnm is connected to a corresponding gate line GLn and a corresponding data line DLm.

2 is a circuit diagram of pixels disposed on the display panel shown in FIG. 1.

Referring to FIG. 2, one pixel PX among the pixels PX11 to PXnm (see FIG. 1) disposed on the display panel 140 (see FIG. 1) is disclosed. In addition, one gate line GLi of the plurality of gate lines GL1 to GLn connected to the pixel PX and one data line DLj of the plurality of data lines DL1 to DLm are illustrated. . Here, n and m are integers greater than zero. i is an integer greater than 0 and less than or equal to n. j is an integer greater than 0 and less than or equal to m.

The pixel PX connected to the gate line GLi and the data line DLj includes a thin film transistor Tr and a liquid crystal capacitor Clc connected to the thin film transistor Tr. The thin film transistor Tr includes a gate electrode connected to the gate line GLi, a source electrode connected to the data line DLj, and a drain electrode connected to the liquid crystal capacitor Clc.

In addition, the liquid crystal capacitor Clc includes a pixel electrode PE electrically connected to a drain electrode of the thin film transistor Tr, a common electrode CE facing the pixel electrode PE, and a pixel electrode PE and a common electrode ( CE) is formed by a liquid crystal layer (not shown) disposed between. The liquid crystal capacitor Clc may be charged with a difference voltage between the data voltage supplied to the pixel electrode PE and the common voltage supplied to the common electrode CE.

3 is a graph showing response characteristics of typical liquid crystal molecules based on time division driving.

Referring to FIG. 3, the horizontal axis represents each frame t according to the frequency setting, and the vertical axis represents the voltage level V of the pixel electrode PE (see FIG. 2 ). In addition, the graph illustrated in FIG. 3 shows response characteristics of liquid crystal molecules during the first and second subframes Frame1 and Frame2 based on one of a plurality of pixels. Here, the first and second sub-frames Frame1 and Frame2 may be defined as a unit frame that is a time unit in which one image is provided.

In general, a liquid crystal display device has a problem in that side visibility is inferior to front visibility according to liquid crystal characteristics. In order to improve the side visibility, a liquid crystal display device may be operated based on a time division driving method. For such time-division driving, the liquid crystal display may display an image of a desired gradation based on the first and second sub-frames Frame1 and Frame2. In detail, an image of a desired grayscale may be displayed based on an average of grayscales corresponding to the data voltages of the first subframe Frame1 and grayscales corresponding to the data voltages of the second subframe Frame2. Here, each of the first and second sub-frames Frame1 and Frame2 may be set to 120 Hz, but is not limited thereto.

Also, the gray level corresponding to the data voltage of the first sub frame Frame1 may be higher than the gray level corresponding to the data voltage of the second sub frame Frame1. For example, in order to display 150 gray during the first and second sub-frames (Frame1, Frame2), a data voltage corresponding to 250 gray during the first sub-frame (Frame1) may be set, and the second sub-frame During (Frame2), a data voltage corresponding to 50 gray may be set. In addition, in the description of the present invention in the future, it is described that the data voltage of the first sub-frame Frame1 is higher than the data voltage of the second sub-frame Frame1. However, the present invention is not limited to this.

3, the first sub-frame Frame1 includes first and second times t1 and t2.

At the first time t1, the pixel electrode PE and the common electrode CE by the data voltage applied to the pixel electrode PE (see FIG. 2) and the common voltage applied to the common electrode CE (see FIG. 2). ) Between the electric field is formed. The liquid crystal molecules of the liquid crystal layer are rearranged by the electric field formed between the pixel electrode PE and the common electrode CE. That is, the first time t1 is a case in which the voltage level of the pixel electrode PE does not reach the data voltage level corresponding to the desired gradation, and is a period in which liquid crystal molecules of the liquid crystal layer are changed. Here, the data voltage level corresponding to the desired gradation of the first frame frame1 may be a high voltage level (HV).

The second time t2 is a period in which an image corresponding to a desired gradation is displayed when the voltage level of the pixel electrode PE reaches a data voltage level corresponding to a desired gradation, that is, a high voltage level HV. Can.

The second sub-frame Frame2 includes third and fourth times t3 and t4.

At the third time t3, an electric field is formed between the pixel electrode PE and the common electrode CE by the data voltage applied to the pixel electrode PE and the common voltage applied to the common electrode CE. The liquid crystal molecules of the liquid crystal layer are rearranged by the electric field formed between the pixel electrode PE and the common electrode CE. That is, the third time t3 is a case in which the voltage level of the pixel electrode PE does not reach the data voltage level corresponding to the desired gradation, and is a section in which liquid crystal molecules of the liquid crystal layer are changed. Here, the data voltage level corresponding to the desired gray level of the second frame Frame2 may be a low voltage level LV.

The fourth time t4 is a period in which an image corresponding to a desired gradation is displayed when the voltage level of the pixel electrode PE reaches a data voltage level corresponding to a desired gradation, that is, a low voltage level LV. Can.

As described above, an image of a desired gradation may be displayed based on the second and fourth times t2 and t4. However, in general, the response characteristics of the liquid crystal molecules have a problem in that the response speed is slower when the low voltage level is reached than the high voltage level. For the above-described reason, the fourth time t4 may be shorter than the second time t2. Due to this, a wash out defect caused by light mixing of adjacent pixels may occur.

According to an embodiment of the present invention, the liquid crystal display 10 may have different frequencies of the first and second sub-frames Frame1 and Frame2. That is, in order to increase the period of the fourth time t4 when the low level voltage is reached, the frequency of the second sub frame Frame2 may be longer than the frequency of the first sub frame Frame1. This operation will be described later.

4 is a timing diagram showing an operation of a gate driver based on time division driving according to an embodiment of the present invention.

1 and 4, the timing controller 110 provides a gate control signal G-CS to the gate driver 120. The gate control signal G-CS may include a vertical start signal STV that controls the operation of the gate signals output from the gate driver 120. The gate driver 120 may sequentially output a plurality of gate signals according to each frame in response to the vertical start signal STV.

On the other hand, in an embodiment, the timing controller 110 according to the present invention controls the vertical start signal STV so that the frequencies of the first and second sub-frames Frame1 and Frame2 are set differently. As described in FIG. 3, the first and second subframes Frame1 and Frame2 may be defined as a unit frame that is a time unit in which one image is provided. On the other hand, in the description of the present invention, the gray level of the data voltages corresponding to the first sub-frame (Frame1) may be set higher than that of the data voltages corresponding to the second sub-frame (Frame2).

First, in the first sub-frame (Frame1), the gate driver 120 responds to the vertical start signal (STV) provided from the timing controller 110, the first gate signal (G1) during the first activation period (H11) Provided to the first gate line GL1. The first pixel PX11 transmits the corresponding first data voltage to the pixel electrode PE (see FIG. 2) in response to the first gate signal G1. Here, the first data voltage may be a high voltage level described in FIG. 3.

Further, although the vertical start signal STV has been described as being transitioned to a high level at the same time as the first gate signal G1, it is not limited thereto. That is, the vertical start signal STV may transition to a high level in a period before the first gate signal G1 is activated.

Thereafter, as the first gate signal G1 transitions to the low level, the gate driver 120 outputs the second gate signal G2 to the second gate line (not shown) during the second activation period H12. do. That is, as the first gate signal G1 transitions to the low level, the second gate signal G2 that is the next gate signal may transition to the high level.

By repeating the above-described operation, during the first sub-frame Frame1, the first to n-th gate signals G1 to Gn may be sequentially output in response to the vertical start signal STV.

Meanwhile, after the first to n-th gate signals G1 to Gn according to the first sub-frame Frame1 are output, before the second sub-frame Frame2, which is the next frame, starts, a blank time (Blank) This may exist. In an embodiment, the timing controller 110 according to the present invention may increase the second subframe Frame2 by reducing the blank time. Here, the blank time shown in FIG. 4 may be a blank time reduced by a predetermined time compared to the existing blank time.

In detail, the timing controller 110 may increase the frequency of the second subframe Frame2 by the predetermined time than the frequency of the first subframe Frame1 based on the blank time reduced by the predetermined time. That is, the vertical start signal STV of the second sub-frame Frame2 may be activated as quickly as the predetermined time. Accordingly, a period in which the first to n-th gate signals G1 to Gn according to the second sub-frame Frame2 are activated may be increased.

In the second sub-frame (Frame2), the gate driver 120 in response to the vertical start signal (STV) provided from the timing controller 110, the first gate signal (G1) during the first activation period (H21) first Provided to the gate line GL1. The first pixel PX11 transmits a corresponding first data voltage to the pixel electrode PE in response to the first gate signal G1 according to the second sub-frame Frame2. Here, the first data voltage may be the low voltage level described in FIG. 2.

As described above, as the frequency of the second sub-frame Frame2 is set longer than the frequency of the first sub-frame Frame1, the first activation period of the first gate signal G1 of the second sub-frame Frame2 (H21) may be increased. Due to this, the fourth time t4 for reaching the low voltage level shown in FIG. 3 can be increased.

5 is a graph showing response characteristics of liquid crystal molecules based on the operation of the gate driver illustrated in FIG. 4.

Referring to FIG. 5, the horizontal axis represents time according to the frequency setting, and the vertical axis represents the voltage level of the pixel electrode. In addition, like the graph shown in FIG. 3, the graph shown in FIG. 5 is based on any one of a plurality of pixels to determine the response characteristics of the liquid crystal molecules during the first and second subframes (Frame1, Frame2). Show.

As illustrated in FIG. 5, frequencies of the first sub-frame Frame1 and the second sub-frame Frame2 may be set differently. In detail, the fourth time t4 of the second sub-frame Frame2 may be increased in response to a blank time (see Blank (see FIG. 3)) reduced by a predetermined time. As the fourth time t4 increases by the predetermined time, the low voltage level period may increase.

As described above, by increasing the low voltage level period, the average grayscale between the first and second subframes Frame1 and Frame2 may be output as a normal grayscale. Accordingly, the overall visibility of the liquid crystal display device 10 (see FIG. 1) may be improved. In particular, based on the above-described frequency setting, side visibility of the liquid crystal display 10 can be improved more efficiently.

6 is a block diagram of a liquid crystal display according to another exemplary embodiment of the present invention.

Referring to FIG. 6, the liquid crystal display device 20 includes a timing controller 210, a gate driver 220, a data driver 230, a display panel 240, a backlight unit 250, and a gradation controller 260. Includes. The liquid crystal display device 20 according to the present invention is a backlight unit 250 and a gradation control unit 260 added as compared to the liquid crystal display device 10 shown in FIG. 1, and other components except the timing controller 210 Their behavior may be the same. Therefore, the description of the operation of the remaining components will be omitted.

First, like the liquid crystal display device 10 described in FIG. 1, the liquid crystal display device 20 according to the present invention may output an image based on a field sequential type. That is, the liquid crystal display device 20 may display one image based on two frames. Meanwhile, the liquid crystal display device 20 according to the present invention is described as displaying one image based on two frames, but is not limited thereto. That is, one image may be displayed based on a plurality of frames according to frequency setting.

In detail, the plurality of pixels PX11 to PXnm disposed on the display panel 240 may display one image according to the average gradation between the first and second subframes (Frame1, Frame2, and FIG. 7 ). have. That is, the pixels PX11 to PXnm according to the present invention may display one image based on the first and second subframes Frame1 and Frame2. Meanwhile, frequencies of the first and second subframes Frame1 and Frame2 may be set differently. For example, as the time between the first and second sub-frames Frame1 and Frame2 is reduced, the frequency of the second sub-frame Frame2 may be increased than the frequency of the first sub-frame Frame1. This will be omitted because it is the same as the operation method described in FIG. 4.

The timing controller 210 generates a data control signal D-CS, a gate control signal G-CS, and a backlight control signal B-CS in response to the control signals CS. The timing controller 210 provides a data control signal (D-CS) to the data driver 230, a gate control signal (G-CS) to the gate driver 220, and a backlight control signal (B-CS). ) To the backlight unit 250.

The backlight unit 250 is disposed on the rear surface of the display panel 240 to supply light to the display panel 240. In particular, the backlight unit 250 may supply light to the display panel 240 in response to the backlight control signal B-CS provided from the timing controller 210.

In an embodiment, the backlight unit 250 may continuously supply light during the first subframe Frame1 in response to the backlight control signal B-CS, and light at a predetermined period during the second subframe Frame2. Can supply

In an embodiment, the backlight unit 250 may supply light to each of the first and second sub-frames Frame1 and Frame2 in a predetermined cycle in response to the backlight control signal B-CS. The backlight unit 250 supplies light at a predetermined cycle will be described in detail with reference to FIG. 7.

Although the gradation control unit 260 is not illustrated, the gradation values of the pixels PX11 to PXnm corresponding to each frame may be received from the display panel 240 based on the operation of the backlight unit 250. Here, the gradation control unit 260 may measure gradation values of pixels PX11 to PXnm corresponding to the first and second subframes Frame1 and Frame2 in advance.

The gradation control unit 260 may set gradation values of pixels PX11 to PXnm corresponding to the first and second subframes Frame1 and Frame2 based on the measured gradation value. The gradation control unit 260 transmits the gradation values of the set pixels PX11 to PXnm to the timing controller 210. The timing controller 210 sets a data control signal D-CS to be provided to the data driver 230 in response to the gradation value transmitted from the gradation controller 260. Subsequently, the data driver 230 responds to the data control signal D-CS set from the timing controller 210, and the pixels PX11 to PXnm according to the first and second subframes Frame1 and Frame2. Data voltages to be supplied to the system are generated.

7 is a timing diagram showing the operation of a gate driver and a backlight unit based on time division driving according to an embodiment of the present invention.

In the description of the present invention, the operation of the gate driver illustrated in FIG. 7 may be the same as the operation of the gate driver illustrated in FIG. 4. Therefore, the description thereof will be omitted.

6 and 7, in the first sub-frame (Frame1), the backlight unit 250 continuously supplies light to the display panel 240 in response to the backlight control signal B-CS. For example, the backlight unit 250 maintains a turn-on state during the first sub-frame Frame1 to provide light to the display panel 240.

On the other hand, in the second sub-frame (Frame2), the backlight unit 250 supplies light to the display panel 240 at regular intervals in response to the backlight control signal B-CS. For example, the backlight unit 250 may be periodically turned on and off during the second sub frame Frame2. That is, the backlight unit 250 supplies light to the turn-on section and does not supply light to the turned-off section.

The timing controller 210 may set the backlight control signal B-CS based on a plurality of image signals RGB received from the outside.

For example, in the second sub-frame Frame2, the backlight unit 250 is defined as a predetermined time from the starting point of the first activation period H21 among the first activation period H21 of the first gate signal G1. Turns off the light for the first time td1. That is, the backlight unit 250 does not supply light to the pixels PX11 to PXnm for the first time td1 of the first activation period H21. In this case, the first time td1 when no light is supplied may be the same as the extended time of the second subframe Frame2 compared to the first subframe Frame1, but is not limited thereto. In addition, since the first time td1 is defined as a predetermined time from the start point of the first activation period H21, the data voltage level of the first time td1 does not reach the low voltage level (LV, see FIG. 5 ). It may be part of a failed section.

Due to this, the liquid crystal display device 20 may have an effect in which the frequency times of the first subframe Frame1 and the second subframe Frame2 are set to be the same.

However, since light is not supplied to the pixels PX11 to PXnm for the first time td1 among the first activation period H21 of the second sub-frame Frame2, the gradation value corresponding to the first time td1 The first activation period H11 of the first sub-frame Frame1 may be compensated. For example, during the first time td1 when the backlight unit 250 is turned off, the pixels PX11 to PXnm may display a black image.

In detail, as the black gradation is displayed for the first time td1 of the second frame Frame2, the average luminance of the first frame1 and the second frame2 may decrease. In order to compensate for the deteriorated luminance value, the gradation value of the first frame (Frame1) may be compensated. Here, the compensated gradation value is a value corresponding to a luminance value that decreases with black gradation. Therefore, the gradation value of the first frame Frame1 may be increased by the gradation value corresponding to the luminance value deteriorated by the black gradation.

Meanwhile, the gradation control unit 260 may measure the gradation value compensated for the first activation period H11 of the first sub-frame Frame1. The gradation control unit 260 transmits the gradation value compensated for the first activation period H11 of the first subframe Frame1 to the timing controller 210. The timing controller 210 may set the data control signal D-CS to output the data voltage based on the compensated gradation value during the first activation period H11 of the first subframe Frame1.

Accordingly, the data driver 230 may output the data voltage to the display panel 240 based on the compensated gradation value during the first activation period H11 of the first subframe Frame1.

In addition, although the first time td1 during which the light is not supplied among the second sub-frames Frame1 is described to be the same as the extended time of the second sub-frames Frame2, it is not limited thereto. Also, the time during which light is not supplied to the first to nth activation periods of the second subframe Frame2 may be different.

8 is a timing diagram showing operations of a gate driver and a backlight unit based on time division driving according to another embodiment of the present invention.

6 and 8, compared to the timing diagram illustrated in FIG. 7, the rest of the operation except for the section of the first subframe Frame1 may be the same. Therefore, the operation description of the second sub-frame (Frane2) section will be omitted.

In detail, in the first and second sub-frames (Frame1, Frame2), the backlight unit 250 supplies light to the display panel 240 at regular intervals in response to the backlight control signal B-CS. The backlight unit 250 may be periodically turned on and off during the first sub frame Frame1. That is, the backlight unit 250 supplies light to the turn-on section and does not supply light to the turned-off section.

For example, in the first sub-frame Frame1, the backlight unit 250 emits light for a predetermined time from the starting point of the first activation period H11 among the first activation period H11 of the first gate signal G1. Turn off. That is, the backlight unit 250 does not supply light to the pixels PX11 to PXnm for a predetermined time during the first activation period H11. In addition, since the predetermined time is defined as a predetermined time from the start point of the first activation section H11, the predetermined time may be a part of a section in which the data voltage level has not reached the high voltage level (HV, see FIG. 5).

Similarly, in the second sub-frame Frame2, the backlight unit 250 turns on light for a predetermined time from the start point of the first activation period H21 among the first activation period H21 of the first gate signal G1. Off. That is, the backlight unit 250 does not supply light to the pixels PX11 to PXnm for a predetermined time during the first activation period H21. In addition, since the predetermined time is defined as a predetermined time from the start point of the first activation period H21, the predetermined time may be a part of a period in which the data voltage level has not reached the low voltage level (LV, see FIG. 5).

In addition, as light is not supplied for a predetermined time among the first activation periods H11 of the first subframe Frame1, the grayscale value corresponding to the predetermined time is the first activation period H21 of the second subframe Frame2. ). Similarly, as light is not supplied for a predetermined time among the first activation periods H21 of the second subframe Frame2, a gray level value corresponding to a predetermined time is the first activation period H11 of the first subframe Frame1 ).

That is, in the first and second sub-frames (Frame1, Frame2), a ratio of a section in which the data voltage level reaches a high or low voltage level may be increased. For example, as the gradation value according to the first activation period H11 of the first subframe Frame1 increases, the data voltage level may increase. As a result, a period in which the voltage level of the pixel electrode PE reaches the data voltage level corresponding to the corresponding gray level, that is, the high voltage level (HV, see FIG. 5) may be faster.

As described above, the backlight unit 250 may improve the liquid crystal response characteristics of the pixels by adjusting the light provided to the display panel 240 during the first and second sub-frames Frame1 and Frame2. Therefore, an image of a corresponding gray level can be displayed from the pixels, thereby improving the overall visibility of the liquid crystal display device.

As described above, embodiments have been disclosed in the drawings and the specification. Although specific terms are used herein, they are used only for the purpose of describing the present invention, and are not used to limit the scope of the present invention described in the meaning or the claims. Therefore, those of ordinary skill in the art will understand that various modifications and other equivalent embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

110: timing controller 210: timing controller
120: gate driver 220: gate driver
130: data driving unit 230: data driving unit
140: display panel 240: display panel
250: backlight unit
260: gradation setting unit

Claims (10)

A display panel that displays an image based on a plurality of frames and receives a plurality of gate signals and a plurality of data voltages corresponding to each of the frames;
A timing controller outputting a data control signal and a plurality of vertical start signals respectively corresponding to the frames;
A gate driver outputting the gate signals in response to the vertical start signal according to each of the frames; And
And a data driver outputting the data voltages according to each of the frames in response to the data control signal.
The timing controller corresponds to a first vertical start signal and the second frame corresponding to the first frame among the vertical start signals, such that at least two first and second frames of the frames have different frequencies. To control the activation time of the second vertical start signal differently,
And an activation period of the gate signals output in response to the first vertical start signal and an activation period of the gate signals output in response to the second vertical start signal. According to claim 1,
The display panel includes a plurality of pixels receiving the gate signals and the data voltages according to each of the frames,
The pixels display a single image in response to the first frame and the second frame. According to claim 2,
The data driver outputs first data voltages corresponding to the first frame to the pixels, and outputs second data voltages corresponding to the second frame to the pixels,
The gradation of the first data voltages is set higher than the gradation of the second data voltages. The method of claim 3,
And a gradation control unit configured to adjust a gradation value of the first data voltages corresponding to the first frame and the second data voltages corresponding to the second frames. According to claim 1,
The display device of which the activation period of the second vertical start signal is set longer than the activation period of the first vertical start signal. According to claim 1,
The display device of which the activation period of the gate signals according to the second vertical start signal is set longer than the activation period of the gate signals according to the first vertical start signal. A display panel that displays an image based on a plurality of frames and receives a plurality of gate signals and a plurality of data voltages corresponding to each of the frames;
A timing controller outputting a data control signal and a plurality of vertical start signals respectively corresponding to the frames;
A gate driver outputting the gate signals in response to the vertical start signal according to each of the frames;
A data driver outputting the data voltages according to each of the frames in response to the data control signal; And
It includes a light source for outputting light to the display panel,
The timing controller corresponds to a first vertical start signal and the second frame corresponding to the first frame among the vertical start signals, such that at least two first and second frames of the frames have different frequencies. To control the activation time of the second vertical start signal differently,
The light source is a display device that continuously supplies light to the display panel during the first frame and supplies light to the display panel during a period of time during the second frame. The method of claim 7,
The display device of which the activation period of the second vertical start signal is set longer than the activation period of the first vertical start signal. The method of claim 7,
The display device of which the activation period of the gate signals according to the second vertical start signal is set longer than the activation period of the gate signals according to the first vertical start signal. The method of claim 7,
And a gradation control unit that adjusts a gradation value of the data voltages corresponding to the first frame and the data voltages corresponding to the second frame based on the light period output from the light source.

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