KR102323772B1 - Liquid crystal display device - Google Patents

Abstract

A liquid crystal display device according to an embodiment of the present invention receives a plurality of gate signals and a plurality of data voltages, and a display panel that displays an image based on a plurality of frames, a data control signal, and a data control signal corresponding to the frames. A timing controller for generating a plurality of vertical start signals, a gate driver for outputting a plurality of gate signals in response to a vertical start signal for each frame, and a data driver for generating the data voltages in response to the data control signal, The timing controller controls the frames to have different frequencies by differently setting activation times of the vertical start signals corresponding to the frames.

Description

Liquid crystal display device {LIQUID CRYSTAL DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, to a liquid crystal display device based on time division driving.

A liquid crystal display is one of the most widely used flat panel displays. The liquid crystal display includes two substrates on which field generating electrodes such as a pixel electrode and a common electrode are formed, and a liquid crystal layer interposed therebetween. The alignment of liquid crystal molecules included in the liquid crystal layer may be determined in response to a voltage difference between the pixel electrode and the common electrode. The liquid crystal display may display an image by controlling the polarization of incident light transmitted through the liquid crystal layer from the outside.

In particular, a liquid crystal display based on a vertical alignment (hereinafter, referred to as VA) mode has a high contrast ratio and is easy to implement a wide reference viewing angle, and thus has been in the spotlight. Here, the reference viewing angle means a viewing angle having a contrast ratio of 1:10 or a luminance inversion limit angle between gray levels.

In the liquid crystal display based on the VA mode, as means for realizing a wide viewing angle, there are a method of forming a cutout in the electric field generating electrode and a method of forming a protrusion on the electric field generating electrode. By dispersing the inclination directions of liquid crystal molecules in various directions using cutouts or protrusions, the reference viewing angle can be widened.

However, the liquid crystal display based on the VA mode has a problem in that the side visibility is inferior compared to the front visibility. For example, in the case of a patterned vertically aligned (PVA) type liquid crystal display device having a cutout, the difference in luminance between the higher grayscales disappears toward the side, so that the picture looks distorted.

An object of the present invention is to provide a liquid crystal display device having improved visibility.

A liquid crystal display device according to an embodiment of the present invention for achieving the above object is a display panel that receives a plurality of gate signals and a plurality of data voltages, and displays an image based on a plurality of sub-frames, and a data control signal and a timing controller generating a plurality of vertical start signals corresponding to the sub-frames, a gate driver outputting a plurality of gate signals in response to a vertical start signal corresponding to each sub-frame, and the data voltage in response to the data control signal and a data driver to generate the data, wherein the timing controller sets activation times of the vertical start signals corresponding to the sub-frames to be different from each other, thereby controlling the sub-frames to have different frequencies.

In an embodiment of the present invention, the plurality of subframes include a first subframe and a second subframe.

In an embodiment of the present invention, the display panel includes a plurality of pixels receiving the data voltages corresponding to the gate signals to display the image, wherein the pixels include the first sub-frame and the One image is displayed in response to the second sub-frame.

In an embodiment of the present invention, the data driver outputs a plurality of data voltages corresponding to the first sub-frame to the pixels, and applies a plurality of data voltages corresponding to the second sub-frame to the pixels. print out

In an embodiment of the present invention, the grayscale of the data voltages corresponding to the first sub-frame is set to be higher than that of the data voltages corresponding to the second sub-frame.

In an embodiment of the present invention, the activation period of the vertical start signal corresponding to the second subframe is set longer than the activation period of the vertical start signal corresponding to the first subframe.

In an embodiment of the present invention, the activation period of the gate signals output in response to the vertical start signal of the second sub-frame is longer than the activation period of the gate signals output in response to the vertical start signal of the first sub-frame. is set

A liquid crystal display device according to another embodiment of the present invention for achieving the above object is a display panel that receives a plurality of gate signals and a plurality of data voltages, and displays an image based on a plurality of sub-frames, and a data control signal and a timing controller generating a plurality of vertical start signals corresponding to the frames, a gate driver outputting a plurality of gate signals in response to a vertical start signal corresponding to each sub-frame, and controlling the data voltages in response to the data control signal. a data driver generating a data driver and a backlight unit supplying light to the display panel, wherein the timing controller sets activation times of the vertical start signals corresponding to the sub-frames to be different from each other so that the sub-frames have different frequencies. and the backlight unit supplies light with a different cycle for each of the sub-frames.

In another embodiment of the present invention, the timing controller further generates a backlight control signal, and the backlight unit supplies light at a different cycle for each of the subframes in response to the backlight control signal.

In another embodiment of the present invention, the plurality of sub-frames include a first sub-frame and a second sub-frame.

In another embodiment of the present invention, the display panel includes a plurality of pixels receiving the data voltages corresponding to the gate signals to display the image, wherein the pixels include the first sub-frame and the One image is displayed in response to the second sub-frame.

In another embodiment of the present invention, the data driver outputs a plurality of data voltages corresponding to the first sub-frame to the pixels, and applies a plurality of data voltages corresponding to the second sub-frame to the pixels. print out

In another embodiment of the present invention, grayscale values of the data voltages corresponding to the first sub-frames and the data voltages corresponding to the second sub-frames based on the light period output from the backlight unit It further includes a gradation control unit for adjusting the .

In another embodiment of the present invention, the grayscale of the data voltages corresponding to the first sub-frame is set to be higher than the grayscale of the data voltages corresponding to the second sub-frame.

In another embodiment of the present invention, the backlight unit continuously supplies light during the first sub-frame, and supplies light at a predetermined time period during the second sub-frame.

In another embodiment of the present invention, the backlight unit supplies light at a predetermined time period during the first sub-frame and the second sub-frame.

In another embodiment of the present invention, the activation period of the vertical start signal corresponding to the second sub-frame is set longer than the activation period of the vertical start signal corresponding to the first sub-frame.

In another embodiment of the present invention, the activation period of the gate signals output in response to the vertical start signal of the second sub-frame is longer than the activation period of the gate signals output in response to the vertical start signal of the first sub-frame. is set

By operating the display device according to the embodiment of the present invention based on time division driving, the visibility of the liquid crystal display device may be improved.

1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram of a pixel disposed on the display panel shown in FIG. 1 .
3 is a graph showing the response characteristics of a general liquid crystal molecule based on time division driving.
4 is a timing diagram illustrating an operation of a gate driver based on time division driving according to an embodiment of the present invention.
FIG. 5 is a graph showing response characteristics of liquid crystal molecules based on the operation of the gate driver shown in FIG. 3 .
6 is a block diagram of a liquid crystal display device according to another embodiment of the present invention.
7 is a timing diagram illustrating operations of a gate driver and a backlight unit based on time division driving according to an embodiment of the present invention.
8 is a timing diagram illustrating operations of a gate driver and a backlight unit based on time division driving according to another embodiment of the present invention.

Since the present invention can have various changes and can have various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention.

In describing each figure, like reference numerals have been used for like elements. In the accompanying drawings, the dimensions of the structures are enlarged than the actual size for clarity of the present invention. Terms such as first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component. The singular expression includes the plural expression unless the context clearly dictates otherwise.

In the present application, terms such as “comprise” or “have” are intended to designate that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, but one or more other features It is to be understood that it does not preclude the possibility of the presence or addition of elements, numbers, steps, operations, components, parts, or combinations thereof.

1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention.

Referring to FIG. 1 , the liquid crystal display 10 includes a timing controller 110 , a gate driver 120 , a data driver 130 , and a display panel 140 .

The timing controller 110 receives a plurality of image signals RGB and a plurality of control signals CS from the outside of the liquid crystal display 10 . The timing controller 110 converts the data format of the image signals RGB to meet the interface specification with the data driver 130 . The data format-converted image signals RGB' are provided to the data driver 130 .

Also, the timing controller 110 generates a data control signal D-CS and a gate control signal G-CS in response to the control signals CS. For example, the data control signal D-CS may include an output start signal and a horizontal start signal. The gate control signal G-CS may include a vertical start signal and a vertical clock bar signal. The timing controller 110 provides the data control signal D-CS to the data driver 130 and provides the gate control signal G-CS to the gate driver 120 .

In an embodiment, the liquid crystal display 10 according to the present invention may output an image based on a field sequential type. In detail, unlike the existing liquid crystal display that displays one image based on one frame, the liquid crystal display 10 according to the present invention can display one image based on two frames. Meanwhile, although it is described that the liquid crystal display 10 according to the present invention displays one image based on two frames, the present invention is not limited thereto. That is, one image may be displayed based on a plurality of frames according to the frequency setting.

The timing controller 110 may generate a gate control signal G-CS and a data control signal D-CS based on a plurality of frames according to a frequency setting.

The gate driver 120 sequentially outputs the gate signal in response to the gate control signal G-CS provided from the timing controller 110 . The plurality of pixels PX11 to PXnm included in the display panel 140 may be scanned row by row and sequentially by gate signals.

In response to the data control signal D-CS provided from the timing controller 110 , the data driver 130 converts the data format-converted image signals RGB' into a plurality of data voltages. The data driver 130 outputs data voltages to the display panel 140 .

The display panel 140 includes a plurality of gate lines GL1 to GLn, a plurality of data lines DL1 to DLm, and a plurality of pixels PX11 to PXnm.

The gate lines GL1 to GLn are disposed to cross each other with the data lines DL1 to DLm extending in the row direction and extending in the column direction. The gate lines GL1 to GLn are electrically connected to the gate driver 120 to receive gate signals. The data lines DL1 to DLm are electrically connected to the data driver 130 to receive data voltages. Each of the pixels PX11 to PXnm is connected to a corresponding gate line GLn and a corresponding data line DLm.

FIG. 2 is a circuit diagram of a pixel disposed on the display panel shown in FIG. 1 .

Referring to FIG. 2 , any one of the pixels PX11 to PXnm (refer to FIG. 1 ) disposed on the display panel 140 (refer to FIG. 1 ) is disclosed. Also, any one gate line GLi of the plurality of gate lines GL1 to GLn connected to the pixel PX and any one data line DLj among the plurality of data lines DL1 to DLm are shown. . where n and m are integers greater than zero. i is an integer greater than 0 and less than or equal to n. j is an integer greater than 0 and less than or equal to m.

The pixel PX connected to the gate line GLi and the data line DLj includes a thin film transistor Tr and a liquid crystal capacitor Clc connected to the thin film transistor Tr. The thin film transistor Tr includes a gate electrode connected to the gate line GLi, a source electrode connected to the data line DLj, and a drain electrode connected to the liquid crystal capacitor Clc.

In addition, the liquid crystal capacitor Clc includes a pixel electrode PE electrically connected to the drain electrode of the thin film transistor Tr, a common electrode CE facing the pixel electrode PE, and a pixel electrode PE and a common electrode ( CE) is formed by a liquid crystal layer (not shown) disposed between. A difference voltage between the data voltage supplied to the pixel electrode PE and the common voltage supplied to the common electrode CE may be charged in the liquid crystal capacitor Clc.

3 is a graph showing the response characteristics of a general liquid crystal molecule based on time division driving.

Referring to FIG. 3 , the horizontal axis represents each frame t according to the frequency setting, and the vertical axis represents the voltage level V of the pixel electrode PE (refer to FIG. 2 ). In addition, the graph shown in FIG. 3 shows the response characteristics of the liquid crystal molecules during the first and second sub-frames Frame1 and Frame2 based on any one of the plurality of pixels. Here, the first and second subframes Frame1 and Frame2 may be defined as a unit frame that is a unit of time in which one image is provided.

In general, liquid crystal displays have a problem in that side visibility is lower than front visibility according to liquid crystal characteristics. In order to improve the side visibility, the liquid crystal display may be operated based on the time division driving method. For such time division driving, the liquid crystal display may display an image of a desired grayscale based on the first and second sub-frames Frame1 and Frame2. In detail, based on the average of the grayscale corresponding to the data voltage of the first sub-frame Frame1 and the grayscale corresponding to the data voltage of the second sub-frame Frame2, an image of a desired grayscale may be displayed. Here, each of the first and second subframes Frame1 and Frame2 may be set to 120Hz, but is not limited thereto.

Also, the grayscale corresponding to the data voltage of the first sub-frame Frame1 may be higher than the grayscale corresponding to the data voltage of the second sub-frame Frame1 . For example, in order to display 150 gray during the first and second subframes Frame1 and Frame2, a data voltage corresponding to 250 gray may be set during the first subframe Frame1 and the second subframe A data voltage corresponding to 50 gray may be set during (Frame2). Also, in the description of the present invention, it will be described that the data voltage of the first sub-frame Frame1 is higher than the data voltage of the second sub-frame Frame1. However, the technical scope of the present invention is not limited thereto.

Continuing to refer to FIG. 3 , the first sub-frame Frame1 includes first and second times t1 and t2 .

At a first time t1 , by the data voltage applied to the pixel electrode PE (refer to FIG. 2 ) and the common voltage applied to the common electrode CE (refer to FIG. 2 ), the pixel electrode PE and the common electrode CE ), an electric field is formed between The liquid crystal molecules of the liquid crystal layer are rearranged by the electric field formed between the pixel electrode PE and the common electrode CE. That is, the first time t1 is a case in which the voltage level of the pixel electrode PE does not reach the data voltage level corresponding to the desired gray level, and is a period in which liquid crystal molecules of the liquid crystal layer are changed. Here, the data voltage level corresponding to the desired gray level of the first frame frame1 may be the high voltage level HV.

The second time t2 is when the voltage level of the pixel electrode PE reaches the data voltage level corresponding to the desired grayscale, that is, the high voltage level HV, and is a period during which an image corresponding to the desired grayscale is displayed. can

The second sub-frame Frame2 includes third and fourth times t3 and t4.

At a third time t3 , an electric field is formed between the pixel electrode PE and the common electrode CE by the data voltage applied to the pixel electrode PE and the common voltage applied to the common electrode CE. The liquid crystal molecules of the liquid crystal layer are rearranged by the electric field formed between the pixel electrode PE and the common electrode CE. That is, the third time t3 is a case in which the voltage level of the pixel electrode PE does not reach the data voltage level corresponding to the desired gray level, and is a period in which liquid crystal molecules of the liquid crystal layer are changed. Here, the data voltage level corresponding to the desired gray level of the second frame Frame2 may be the low voltage level LV.

The fourth time t4 is when the voltage level of the pixel electrode PE reaches the data voltage level corresponding to the desired grayscale, that is, the low voltage level LV, and is a period in which an image corresponding to the desired grayscale is displayed. can

As described above, an image having a desired grayscale may be displayed based on the second and fourth times t2 and t4. However, in general, the response characteristic of the liquid crystal molecules has a problem in that the response speed is slower in the period in which the low voltage level is reached than in the period in which the high voltage level is reached. For the reasons described above, the fourth time t4 may be shorter than the second time t2. As a result, a wash out defect in which lights of adjacent pixels are mixed may occur.

According to an embodiment of the present invention, in the liquid crystal display 10 , the frequencies of the first and second sub-frames Frame1 and Frame2 may be set differently. That is, in order to increase the period of the fourth time t4 when the low-level voltage is reached, the frequency of the second sub-frame Frame2 may be longer than the frequency of the first sub-frame Frame1 . This operation will be described later.

4 is a timing diagram illustrating an operation of a gate driver based on time division driving according to an embodiment of the present invention.

1 and 4 , the timing controller 110 provides the gate control signal G-CS to the gate driver 120 . The gate control signal G-CS may include a vertical start signal STV for controlling the operation of the gate signals output from the gate driver 120 . The gate driver 120 may sequentially output a plurality of gate signals according to each frame in response to the vertical start signal STV.

Meanwhile, in an embodiment, the timing controller 110 according to the present invention controls the vertical start signal STV so that the frequencies of the first and second subframes Frame1 and Frame2 are set to be different from each other. 3 , the first and second subframes Frame1 and Frame2 may be defined as a unit frame that is a unit of time in which one image is provided. Meanwhile, in the description of the present invention, the grayscale of the data voltages corresponding to the first sub-frame Frame1 may be set higher than that of the data voltages corresponding to the second sub-frame Frame2 .

First, in the first sub-frame Frame1 , the gate driver 120 generates the first gate signal G1 during the first activation period H11 in response to the vertical start signal STV provided from the timing controller 110 . It is provided on the first gate line GL1. The first pixel PX11 transmits a corresponding first data voltage to the pixel electrode PE (refer to FIG. 2 ) in response to the first gate signal G1 . Here, the first data voltage may be the high voltage level described with reference to FIG. 3 .

Also, although it has been described that the vertical start signal STV transitions to the high level simultaneously with the first gate signal G1, the present invention is not limited thereto. That is, the vertical start signal STV may transition to a high level in a section before the first gate signal G1 is activated.

Thereafter, as the first gate signal G1 transitions to the low level, the gate driver 120 outputs the second gate signal G2 to the second gate line (not shown) during the second activation period H12. do. That is, as the first gate signal G1 transitions to the low level, the second gate signal G2, which is the next gate signal, may transition to the high level.

By repeating the above-described operation, the first to nth gate signals G1 to Gn may be sequentially output during the first subframe Frame1 in response to the vertical start signal STV.

On the other hand, after the first to n-th gate signals G1 to Gn according to the first sub-frame Frame1 are output, and before the second sub-frame Frame2, which is the next frame, is started, a blank time (Blank) can exist. In an embodiment, the timing controller 110 according to the present invention may increase the second subframe Frame2 by reducing the blank time Blank. Here, the blank time blank shown in FIG. 4 may be a blank time reduced by a predetermined time compared to the existing blank time.

In detail, the timing controller 110 may increase the frequency of the second subframe Frame2 by the predetermined time longer than the frequency of the first subframe Frame1 based on the blank time reduced by the predetermined time. That is, the vertical start signal STV of the second sub-frame Frame2 may be activated as quickly as the predetermined time. Accordingly, the period in which the first to n-th gate signals G1 to Gn according to the second sub-frame Frame2 are activated may be increased than before.

In the second subframe Frame2 , the gate driver 120 transmits the first gate signal G1 to the first gate signal G1 during the first activation period H21 in response to the vertical start signal STV provided from the timing controller 110 . It is provided on the gate line GL1. The first pixel PX11 transmits a corresponding first data voltage to the pixel electrode PE in response to the first gate signal G1 according to the second sub-frame Frame2 . Here, the first data voltage may be the low voltage level described with reference to FIG. 2 .

As described above, as the frequency of the second sub-frame Frame2 is set to be longer than the frequency of the first sub-frame Frame1, the first activation period of the first gate signal G1 of the second sub-frame Frame2 (H21) may be increased. Due to this, the fourth time t4 for reaching the low voltage level shown in FIG. 3 may be increased.

FIG. 5 is a graph showing response characteristics of liquid crystal molecules based on the operation of the gate driver shown in FIG. 4 .

Referring to FIG. 5 , the horizontal axis represents time according to frequency setting, and the vertical axis represents the voltage level of the pixel electrode. Also, like the graph shown in FIG. 3 , the graph shown in FIG. 5 shows the response characteristics of the liquid crystal molecules during the first and second subframes Frame1 and Frame2 based on any one of the plurality of pixels. show

As shown in FIG. 5 , the frequencies of the first sub-frame Frame1 and the second sub-frame Frame2 may be set differently from each other. In detail, the fourth time t4 of the second sub-frame Frame2 may increase in response to the blank time (Blank, see FIG. 3 ) reduced by a predetermined time. As the fourth time t4 increases by the predetermined time, the low voltage level period may increase.

As described above, as the low voltage level period is increased, the average grayscale between the first and second subframes Frame1 and Frame2 may be output as a normal grayscale. Accordingly, overall visibility of the liquid crystal display 10 (refer to FIG. 1 ) may be improved. In particular, based on the above-described frequency setting, side visibility of the liquid crystal display 10 may be improved more efficiently.

6 is a block diagram of a liquid crystal display according to another exemplary embodiment.

Referring to FIG. 6 , the liquid crystal display 20 includes a timing controller 210 , a gate driver 220 , a data driver 230 , a display panel 240 , a backlight unit 250 , and a grayscale controller 260 . include Compared to the liquid crystal display 10 shown in FIG. 1 , the liquid crystal display 20 according to the present invention has a backlight unit 250 and a grayscale control unit 260 added thereto, except for the timing controller 210 . Their operation may be the same. Accordingly, descriptions of operations of the remaining components will be omitted.

First, like the liquid crystal display 10 described in FIG. 1 , the liquid crystal display 20 according to the present invention may output an image based on a field sequential type. That is, the liquid crystal display 20 may display one image based on two frames. Meanwhile, although it is described that the liquid crystal display 20 according to the present invention displays one image based on two frames, the present invention is not limited thereto. That is, one image may be displayed based on a plurality of frames according to the frequency setting.

In detail, the plurality of pixels PX11 to PXnm disposed on the display panel 240 may display one image according to the average grayscale between the first and second sub-frames Frame1 and Frame2 (refer to FIG. 7 ). have. That is, the pixels PX11 to PXnm according to the present invention may display one image based on the first and second sub-frames Frame1 and Frame2. Meanwhile, the frequencies of the first and second subframes Frame1 and Frame2 may be set differently. For example, as the blank time between the first and second subframes Frame1 and Frame2 is reduced, the frequency of the second subframe Frame2 may increase than the frequency of the first subframe Frame1 . This will be omitted since it is the same as the operation method described with reference to FIG. 4 .

The timing controller 210 generates a data control signal D-CS, a gate control signal G-CS, and a backlight control signal B-CS in response to the control signals CS. The timing controller 210 provides the data control signal D-CS to the data driver 230 , the gate control signal G-CS to the gate driver 220 , and the backlight control signal B-CS ) is provided to the backlight unit 250 .

The backlight unit 250 is disposed on the rear surface of the display panel 240 to supply light to the display panel 240 . In particular, the backlight unit 250 may supply light to the display panel 240 in response to the backlight control signal B-CS provided from the timing controller 210 .

In an embodiment, the backlight unit 250 may continuously supply light during the first sub-frame Frame1 in response to the backlight control signal B-CS, and light at a predetermined period during the second sub-frame Frame2. can supply

In an embodiment, the backlight unit 250 may supply light to each of the first and second sub-frames Frame1 and Frame2 at a predetermined period in response to the backlight control signal B-CS. The backlight unit 250 supplying light at a predetermined period will be described in detail with reference to FIG. 7 .

Although not shown, the grayscale controller 260 may receive grayscale values of the pixels PX11 to PXnm corresponding to each frame from the display panel 240 based on the operation of the backlight unit 250 . Here, the grayscale controller 260 may measure grayscale values of the pixels PX11 to PXnm corresponding to the first and second subframes Frame1 and Frame2 in advance.

The grayscale controller 260 may set grayscale values of the pixels PX11 to PXnm corresponding to the first and second subframes Frame1 and Frame2 based on the measured grayscale value. The grayscale controller 260 transmits the grayscale values of the set pixels PX11 to PXnm to the timing controller 210 . The timing controller 210 sets the data control signal D-CS to be provided to the data driver 230 in response to the grayscale value transmitted from the grayscale controller 260 . Thereafter, the data driver 230 responds to the data control signal D-CS set from the timing controller 210 , and the pixels PX11 to PXnm according to the first and second subframes Frame1 and Frame2 . data voltages to be provided to

7 is a timing diagram illustrating operations of a gate driver and a backlight unit based on time division driving according to an embodiment of the present invention.

In the description of the present invention, the operation of the gate driver illustrated in FIG. 7 may be the same as the operation of the gate driver illustrated in FIG. 4 . Therefore, a description thereof will be omitted.

6 and 7 , in the first sub-frame Frame1 , the backlight unit 250 continuously supplies light to the display panel 240 in response to the backlight control signal B-CS. For example, the backlight unit 250 maintains a turned-on state during the first sub-frame Frame1 to provide light to the display panel 240 .

Meanwhile, in the second sub-frame Frame2 , the backlight unit 250 supplies light to the display panel 240 at a predetermined period in response to the backlight control signal B-CS. For example, the backlight unit 250 may be periodically turned on and off during the second sub-frame Frame2 . That is, the backlight unit 250 supplies light in the turn-on period and does not supply light in the turn-off period.

The timing controller 210 may set the backlight control signal B-CS based on the plurality of image signals RGB received from the outside.

For example, in the second sub-frame Frame2, the backlight unit 250 is defined as a predetermined time from the start point of the first activation period H21 of the first activation period H21 of the first gate signal G1. The light is turned off for the first time td1. That is, the backlight unit 250 does not supply light to the pixels PX11 to PXnm for the first time td1 during the first activation period H21. In this case, the first time td1 during which the light is not supplied may be the same as the extended time of the second sub-frame Frame2 compared to the first sub-frame Frame1, but is not limited thereto. Also, since the first time td1 is defined as a predetermined time from the start point of the first activation period H21, the data voltage level does not reach the low voltage level (LV, see FIG. 5) during the first time td1. It may be part of the missing section.

Accordingly, the liquid crystal display 20 may have the effect that the frequency time of the first sub-frame Frame1 and the second sub-frame Frame2 is set to be the same.

However, since light is not supplied to the pixels PX11 to PXnm for a first time td1 during the first activation period H21 of the second sub-frame Frame2, a grayscale value corresponding to the first time td1 This may be compensated for in the first activation period H11 of the first sub-frame Frame1. For example, during the first time td1 when the backlight unit 250 is turned off, the pixels PX11 to PXnm may display a black image.

In detail, as the black gray level is displayed during the first time td1 of the second frame Frame2 , the average luminance of the first frame Frame1 and the second frame Frame2 may decrease. In order to compensate for the lowered luminance value, the grayscale value of the first frame Frame1 may be compensated. Here, the compensated grayscale value is a value corresponding to a luminance value lowered according to the black grayscale. Accordingly, the grayscale value of the first frame Frame1 may be increased by the grayscale value corresponding to the luminance value lowered by the black grayscale.

Meanwhile, the grayscale controller 260 may measure the grayscale value compensated for in the first activation period H11 of the first subframe Frame1 . The grayscale controller 260 transmits the grayscale value compensated for in the first activation period H11 of the first subframe Frame1 to the timing controller 210 . The timing controller 210 may set the data control signal D-CS to output the data voltage based on the compensated grayscale value during the first activation period H11 of the first subframe Frame1 .

For this reason, the data driver 230 may output the data voltage to the display panel 240 based on the compensated grayscale value during the first activation period H11 of the first subframe Frame1 .

Also, although it has been described that the first time td1 during which light is not supplied among the second sub-frames Frame1 is the same as the extended time of the second sub-frames Frame2, the present invention is not limited thereto. In addition, a time period during which light is not supplied to the first to n-th activation periods of the second sub-frame Frame2 may be different from each other.

8 is a timing diagram illustrating operations of a gate driver and a backlight unit based on time division driving according to another embodiment of the present invention.

Referring to FIGS. 6 and 8 , compared with the timing diagram shown in FIG. 7 , operations other than the section of the first sub-frame Frame1 may be the same. Accordingly, a description of the operation of the second subframe Frane2 will be omitted.

In detail, in the first and second sub-frames Frame1 and Frame2 , the backlight unit 250 supplies light to the display panel 240 at regular intervals in response to the backlight control signal B-CS. The backlight unit 250 may be periodically turned on and off during the first sub-frame Frame1 . That is, the backlight unit 250 supplies light in the turn-on period and does not supply light in the turn-off period.

For example, in the first sub-frame Frame1, the backlight unit 250 emits light for a predetermined time from the start point of the first activation period H11 of the first activation period H11 of the first gate signal G1. turn off That is, the backlight unit 250 does not supply light to the pixels PX11 to PXnm for a predetermined time during the first activation period H11. Also, since the predetermined time is defined as a predetermined time from the start point of the first activation period H11, the predetermined time may be a part of a period in which the data voltage level does not reach the high voltage level (HV, see FIG. 5 ).

Similarly, in the second sub-frame Frame2, the backlight unit 250 turns light for a predetermined time from the start point of the first activation period H21 of the first activation period H21 of the first gate signal G1- off That is, the backlight unit 250 does not supply light to the pixels PX11 to PXnm for a predetermined period of time during the first activation period H21. Also, since the predetermined time is defined as a predetermined time from the start point of the first activation period H21, the predetermined time may be a part of a period in which the data voltage level does not reach the low voltage level LV (refer to FIG. 5).

In addition, as light is not supplied for a predetermined time during the first activation period H11 of the first sub-frame Frame1, the grayscale value corresponding to the predetermined time is changed in the first activation period H21 of the second sub-frame Frame2. ) can be compensated. Similarly, as light is not supplied for a predetermined time during the first activation period H21 of the second sub-frame Frame2, the grayscale value corresponding to the predetermined time is changed in the first activation period H11 of the first sub-frame Frame1. ) can be compensated.

That is, in the first and second sub-frames Frame1 and Frame2, the ratio of the period in which the data voltage level reaches the high or low voltage level may be increased. For example, as the grayscale value according to the first activation period H11 of the first sub-frame Frame1 increases, the data voltage level may increase. As a result, the period in which the voltage level of the pixel electrode PE reaches the data voltage level corresponding to the corresponding grayscale, that is, the high voltage level (HV, see FIG. 5 ) may be accelerated.

As described above, the backlight unit 250 adjusts the light provided to the display panel 240 during the first and second sub-frames Frame1 and Frame2 to improve the liquid crystal response characteristics of pixels. Accordingly, an image of a corresponding grayscale may be displayed from the pixels, and thus overall visibility of the liquid crystal display may be improved.

As described above, embodiments have been disclosed in the drawings and the specification. Although specific terms are used herein, they are used only for the purpose of describing the present invention and are not used to limit the meaning or the scope of the present invention described in the claims. Therefore, it will be understood by those of ordinary skill in the art that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

110: timing controller 210: timing controller
120: gate driver 220: gate driver
130: data driver 230: data driver
140: display panel 240: display panel
250: backlight unit
260: gradation setting unit

Claims (13)

a display panel that displays an image based on a plurality of sub-frames and receives a plurality of gate signals and a plurality of data voltages corresponding to each of the sub-frames;
a timing controller outputting a data control signal and a plurality of vertical start signals respectively corresponding to the sub-frames;
a gate driver outputting the gate signals in response to the vertical start signal according to each of the sub-frames; and
and a data driver outputting the data voltages according to each of the sub-frames in response to the data control signal;
the timing controller controls two successive first and second subframes among the subframes to have different frequencies;
In the first sub-frame, each of the gate signals includes a first activation period, and in the second sub-frame, each of the gate signals includes a second activation period,
The second activation section includes a first section displaying a black image and a section other than the first section,
A width of the first activation section and a width of the remaining section are the same. The method of claim 1,
the display panel includes a plurality of pixels receiving the gate signals and the data voltages according to each of the sub-frames;
The pixels display one image based on the first sub-frame and the second sub-frame. 3. The method of claim 2,
The data driver outputs first data voltages corresponding to the first sub-frame to the pixels, and outputs second data voltages corresponding to the second sub-frame to the pixels. delete 4. The method of claim 3,
The grayscale of the first data voltages is set to be higher than the grayscale of the second data voltages. 4. The method of claim 3,
and a grayscale controller for adjusting grayscale values of the first data voltages corresponding to the first subframe and the second data voltages corresponding to the second subframes. The method of claim 1,
In the timing controller, a width of an activation period of a first vertical start signal corresponding to the first subframe among the vertical start signals is shorter than a width of an activation period of a second vertical start signal corresponding to the second subframe. to control it,
The first activation period corresponds to the first vertical start signal, and the second activation period corresponds to the second vertical start signal. delete a display panel including a plurality of pixels displaying an image based on a plurality of sub-frames and receiving a plurality of gate signals and a plurality of data voltages corresponding to each of the sub-frames;
a timing controller outputting a data control signal and a plurality of vertical start signals respectively corresponding to the sub-frames;
a gate driver outputting the gate signals in response to the vertical start signal according to each of the sub-frames;
and a data driver outputting the data voltages according to each of the sub-frames in response to the data control signal;
The timing controller is configured to control a width of a first activation period included in each of the gate signals in the first sub-frame and the second sub-frame such that at least two first and second sub-frames of the sub-frames have different frequencies. Differently controlling the width of the second activation period included in each of the gate signals in the 2 sub-frames,
The second activation section includes a first section displaying a black image and a section other than the first section,
The width of the first activation section and the width of the remaining section are the same,
The pixels are
The display device continuously displays the image on the display panel during the first sub-frame, and displays the image on the display panel at a predetermined time period during the second sub-frame. 10. The method of claim 9,
The timing controller may be configured to set a width of an activation period of a first vertical start signal corresponding to the first subframe among the vertical start signals and a width of an activation period of a second vertical start signal corresponding to the second subframe from each other. Differently controlled display. 11. The method of claim 10,
A width of the activation period of the second vertical start signal is longer than a width of the activation period of the first vertical start signal,
The first activation period corresponds to the first vertical start signal, and the second activation period corresponds to the second vertical start signal. 10. The method of claim 9,
and a grayscale controller configured to adjust grayscale values of the data voltages corresponding to the first subframe and the data voltages corresponding to the second subframe based on a period in which the pixels display the image. Device. delete

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