JP2007127785A - Light source driving device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a light source driving device capable of reducing the occurrence of a striped pattern without limiting a substantial dimming range. <P>SOLUTION: The light source driving device comprises a dimming control circuit 14 for generating a dimming control signal as a pulse repeated with respect to each frame period of a duty ratio adjusted for setting the brightness of a liquid crystal display panel DP, and an inverter circuit LD for emitting backlight BL for the period corresponding to the pulse width of the dimming control signal. The dimming control circuit 14 includes a phase control part 14B for setting a pulse phase so as to make the pulse of the dimming control signal symmetric with respect to the standard timing for division into two equal halves the total gradation image display period from the beginning of the gradation image display by the liquid crystal pixel PX of the first row to the end of the gradation image display by the liquid crystal pixel PX of the last row, and shifting the pulse phase so as to bring forward the center of the pulse from the standard timing and compensate for the delay of the emission of the back light BL in the case of decreasing the duty radio from the predetermined value. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a light source driving device for a lamp light source that illuminates, for example, an OCB (Optically Compensated Bend) mode liquid crystal display panel, and in particular, a light source that blinks the lamp light source for dimming to adjust the brightness of the liquid crystal display panel. The present invention relates to a driving device.

  Liquid crystal display devices are widely used as display devices for computers, car navigation systems, television receivers, and the like.

  In general, a liquid crystal display device includes a liquid crystal display panel including a matrix array of a plurality of liquid crystal pixels, a backlight that illuminates the display panel, and a display control circuit that controls the backlight and the display panel. The liquid crystal display panel has a structure in which a liquid crystal layer is sandwiched between an array substrate and a counter substrate.

The array substrate has a plurality of pixel electrodes arranged in a substantially matrix, a plurality of gate lines arranged along a row of the plurality of pixel electrodes, a plurality of source lines arranged along a column of the plurality of pixel electrodes, and a plurality of And a plurality of switching elements arranged in the vicinity of the intersection position of the plurality of gate lines and the plurality of source lines. Each switching element is made of, for example, a thin film transistor (TFT), and conducts when one gate line is driven to apply the potential of one source line to one pixel electrode. A common electrode is provided on the counter substrate so as to face a plurality of pixel electrodes arranged on the array substrate. The pair of pixel electrodes and the common electrode constitute a pixel together with the pixel region of the liquid crystal layer, and the liquid crystal molecule arrangement is controlled by an electric field between the pixel electrode and the common electrode in the pixel region.
When the liquid crystal display device is mainly used for a television receiver that displays a moving image, an OCB mode liquid crystal display panel in which liquid crystal molecules exhibit good responsiveness may be used (see Patent Document 1). In this liquid crystal display panel, the liquid crystal molecules are in the splay alignment in which the liquid crystal molecules are almost laid down before the power is turned on by the alignment film rubbed in parallel with each other on the pixel electrode and the common electrode. The liquid crystal display panel performs a display operation after these liquid crystal molecules are changed from a splay alignment to a bend alignment by a relatively strong electric field applied in an initialization process accompanying power-on.

  The reason why the liquid crystal is in the splay alignment before the power is turned on is that the splay alignment is energetically more stable than the bend alignment when no liquid crystal driving voltage is applied. Once such liquid crystal molecules transition to bend alignment, they are reverted to splay alignment again when a voltage application state below the level at which splay alignment energy and bend alignment energy antagonize or when no voltage is applied for a long period of time. It has the property of moving. In the splay alignment, the viewing angle characteristics are significantly different from the bend alignment, resulting in abnormal display.

Conventionally, for example, a driving method has been adopted in which a large voltage is applied to the liquid crystal layer as a reverse transition prevention voltage to the splay alignment in a part of a frame period in which one frame of video is displayed. In the OCB mode liquid crystal display panel, the reverse transition prevention voltage corresponds to a pixel voltage for black display in a normally white display operation, and is called black insertion driving. The black insertion rate is set as a ratio of the black insertion period (non-gradation image display period) to one frame period, and the gradation image display period has a length obtained by subtracting the black insertion period from one frame period. The liquid crystal pixels in a plurality of rows are each driven as a horizontal display line with a phase difference as shown in FIG. 6, and display corresponding to image data, for example, white display, is performed in the gradation image display period, and the splay alignment is performed in the black insertion period. Black display is performed to prevent reverse transition.
JP 2002-202491 A

  Incidentally, the backlight is generally a single discharge lamp light source such as a cold cathode tube, and is driven by an inverter circuit provided in the display control circuit. When it is necessary to perform dimming to adjust the brightness of the liquid crystal display panel, the inverter circuit emits (lights) the lamp light source with a duty ratio corresponding to the dimming control signal as shown in FIG. Since the grayscale image display periods of the horizontal display lines are shifted from each other within one frame period, the dimming control signal is sent from the start of the grayscale image display of the first horizontal display line to the end of the grayscale image display of the final horizontal display line. It is generated so that the light emission period of the lamp light source is symmetric with respect to the reference timing that divides the total gradation image display period until. That is, the period tA from the rising timing to the reference timing of the dimming control signal is equal to the period tB from the reference timing to the falling timing.

  However, conventionally, it has been confirmed that when the duty ratio of the dimming control signal is reduced to a small value, a striped pattern is generated on the screen of the display panel. If the minimum duty ratio of the dimming control signal is set so as not to generate the stripe pattern, there is a problem that a wide dimming range cannot be secured.

  The objective of this invention is providing the light source drive device which can reduce generation | occurrence | production of a striped pattern, without restrict | limiting a substantial light control range.

  According to the present invention, a liquid crystal display panel that is sequentially driven at least row by row is illuminated so that a plurality of rows of liquid crystal pixels perform gradation image display and non-gradation image display at a constant time ratio with respect to one frame period. A light source driving device for a lamp light source, and a dimming control circuit that generates a dimming control signal as a pulse of a duty ratio that is repeated every frame period and adjusted to set the brightness of the liquid crystal display panel; And an inverter circuit that causes the lamp light source to emit light for a period corresponding to the pulse width of the dimming control signal, and the dimming control circuit performs gradation by the liquid crystal pixels in the last row from the start of gradation image display by the liquid crystal pixels in the first row. Set the pulse phase so that the pulse of the dimming control signal is symmetrical with respect to the reference timing that divides the total gradation image display period until the end of image display into two equal parts, and the duty ratio A light source driving device including a phase control section for shifting the pulse phase to compensate for the delay in the emission of the lamp light source earlier than the reference timing the center of the pulse in case of smaller than the predetermined value is provided.

  In this light source driving device, the phase control unit divides the total gradation image display period from the start of gradation image display by the liquid crystal pixels in the first row to the end of gradation image display by the liquid crystal pixels in the last row into two equal parts. When the pulse phase is set so that the pulse of the dimming control signal is symmetric, and the duty ratio is decreased below a predetermined value, the center of the pulse is set earlier than the reference timing to delay the light emission of the lamp light source. The pulse phase is shifted to compensate. Here, even if the light emission of the lamp light source is delayed due to responsiveness, the lamp light amount can be evenly distributed before and after the reference timing. Specifically, the light emission control period is reduced by reducing the duty ratio of the dimming control signal, and the stripe pattern is observed due to the difference between the gradation image display operation of the liquid crystal display panel and the light emission operation of the lamp light source. If the duty ratio to be started is set to a predetermined value, this deviation is canceled by the shift of the pulse phase. In this case, it is possible to reduce the duty ratio of the dimming control signal beyond a predetermined value. As a result, the occurrence of striped patterns can be reduced without restricting the substantial light control range.

  Hereinafter, a liquid crystal display device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 schematically shows a circuit configuration of the liquid crystal display device. The liquid crystal display device includes a liquid crystal display panel DP, a backlight BL that illuminates the display panel DP, and a display control circuit CNT that controls the display panel DP and the backlight BL. The liquid crystal display panel DP has a structure in which a liquid crystal layer 3 is sandwiched between an array substrate 1 and a counter substrate 2 which are a pair of electrode substrates. The liquid crystal layer 3 is a liquid crystal in which, for example, a normally white display operation is previously transitioned from a splay alignment to a bend alignment, and a reverse transition from the bend alignment to the splay alignment is periodically applied and blocked by a voltage that causes black display. Contains materials. The display control circuit CNT controls the transmittance of the liquid crystal display panel DP by the liquid crystal driving voltage applied from the array substrate 1 and the counter substrate 2 to the liquid crystal layer 3. The transition from the splay alignment to the bend alignment can be obtained by applying a relatively large electric field to the liquid crystal by a predetermined initialization process performed by the display control circuit CNT when the power is turned on.

  FIG. 2 shows the cross-sectional structure of the liquid crystal display panel DP in detail. The array substrate 1 includes a transparent insulating substrate GL made of a glass plate or the like, a plurality of pixel electrodes PE formed on the transparent insulating substrate GL, and an alignment film AL formed on the pixel electrodes PE. The counter substrate 2 is a transparent insulating substrate GL made of a glass plate or the like, a color filter layer CF formed on the transparent insulating substrate GL, a common electrode CE formed on the color filter layer CF, and on the common electrode CE. It includes an alignment film AL to be formed. The liquid crystal layer 3 is obtained by filling the gap between the counter substrate 2 and the array substrate 1 with liquid crystal. The color filter layer CF includes a red coloring layer for red pixels, a green coloring layer for green pixels, a blue coloring layer for blue pixels, and a black coloring (light-shielding) layer for black matrix. In FIG. 2, the liquid crystal molecules 19 are in a splay alignment state. The liquid crystal display panel DP includes a pair of retardation plates RT arranged outside the array substrate 1 and the counter substrate 2, a pair of polarizing plates PL arranged outside the retardation plates RT, and the array substrate 1 side. A light source backlight BL is provided outside the polarizing plate PL. The alignment film AL on the array substrate 1 side and the alignment film AL on the counter substrate 2 side are rubbed in parallel with each other. Thereby, the pretilt angle of the liquid crystal molecules is set to about 10 °.

  In the array substrate 1, a plurality of pixel electrodes PE are arranged in a substantially matrix shape on the transparent insulating substrate GL. In addition, a plurality of gate lines Y (Y1 to Ym) are arranged along the rows of the plurality of pixel electrodes PE, and a plurality of source lines X (X1 to Xn) are arranged along the columns of the plurality of pixel electrodes PE. . A plurality of pixel switching elements W are arranged in the vicinity of the intersection position of the gate line Y and the source line X. Each pixel switching element W is formed of a thin film transistor in which a gate is connected to the gate line Y and a source-drain path is connected between the source line X and the pixel electrode PE, and corresponds to when driven through the corresponding gate line Y. Conduction is established between the source line X and the corresponding pixel electrode PE.

  Each pixel electrode PE and common electrode CE is made of a transparent electrode material such as ITO, for example, and is covered with an alignment film AL and controlled to a liquid crystal molecular arrangement corresponding to the electric field from the pixel electrode PE and common electrode CE. A liquid crystal pixel PX is configured together with a pixel region that is a part of the pixel area.

  Each of the plurality of liquid crystal pixels PX has a liquid crystal capacitance CLC between the pixel electrode PE and the common electrode CE. The plurality of auxiliary capacitance lines C1 to Cm are each capacitively coupled to the pixel electrode PE of the liquid crystal pixel PX in the corresponding row to form an auxiliary capacitance Cs.

  The display control circuit CNT includes a gate driver YD that sequentially drives the plurality of gate lines Y1 to Ym so that the plurality of switching elements W are conducted in units of rows, and a period in which the switching elements W in each row are conducted by driving the corresponding gate lines Y. , A source driver XD for outputting the pixel voltage Vs to the plurality of source lines X1 to Xn, a backlight driver LD for driving the backlight BL, a driving voltage generating circuit 4 for generating a driving voltage for the display panel DP, and A controller circuit 5 that controls the gate driver YD, the source driver XD, and the backlight driver (inverter) LD is provided.

  The driving voltage generation circuit 4 generates a compensation voltage generation circuit 6 that generates a compensation voltage Ve applied to the auxiliary capacitance line C through the gate driver YD, and a predetermined number of gradation reference voltages VREF used by the source driver XD. And a common voltage generating circuit 8 for generating a common voltage Vcom applied to the counter electrode CT. The controller circuit 5 includes a vertical timing control circuit 11 that generates a control signal CTY for the gate driver YD based on a synchronization signal SYNC (VSYNC, DE) input from the external signal source SS, and a synchronization signal input from the external signal source SS. A horizontal timing control circuit 12 that generates a control signal CTX for the source driver XD based on SYNC (VSYNC, DE), and, for example, black insertion double speed conversion for image data input from the external signal source SS to a plurality of pixels PX. An image data conversion circuit 13 to be performed and a dimming control circuit 14 for controlling the backlight driving inverter circuit LD based on a pulse width modulation (PWM) dimming signal from the external signal source SS are included. The image data includes a plurality of pixel data DI for a plurality of liquid crystal pixels PX, and is updated every frame period (vertical scanning period V). The control signal CTY is supplied to the gate driver YD, and the control signal CTX is supplied to the source driver XD together with the pixel data DO obtained as a conversion result from the image data conversion circuit 13. The control signal CTY is used to cause the gate driver YD to sequentially drive the plurality of gate lines Y as described above, and the control signal CTX is the liquid crystal pixel PX for one row as the conversion result of the image data conversion circuit 13. The pixel data DO obtained in units and output in series are assigned to a plurality of source lines X and used to cause the source driver XD to perform an operation of designating output polarity.

  The gate driver YD and the source driver XD are configured using, for example, a shift register circuit in order to select the plurality of gate lines Y and the plurality of source lines X, respectively. In this case, the control signal CTY includes a first start signal STHA for controlling the gradation image display start timing, a second start signal STHB for controlling the black insertion start timing, and a clock for shifting the start signals STHA and STHB in the shift register circuit. And an output enable signal for controlling output of drive signals to the gate lines Y1 to Ym that are sequentially selected at least one by one by the shift register circuit corresponding to the holding positions of the signals and the start signals STHA and STHB. On the other hand, the control signal CTX is generated by the shift register circuit corresponding to the start signal for controlling the start timing of taking in the pixel data for one row, the clock signal for shifting the start signal in the shift register circuit, and the holding position of the start signal. A load signal for controlling the parallel output timing of one row of pixel data DO taken in for each of the source lines X1 to Xn selected one by one, and a polarity signal for controlling the signal polarity of the pixel voltage Vs corresponding to the pixel data Etc.

  Here, the gate driver YD sequentially selects a plurality of gate lines Y1 to Ym for gradation image display and black insertion (non-gradation image display) in one frame period under the control of the control signal CTY, and performs pixel switching for each row. An on-voltage is supplied to the selection gate line Y as a drive signal for making the element W conductive for one horizontal scanning period H. When the image data conversion circuit 13 performs black insertion double-speed conversion, one row of black pixel data B and one row of grayscale pixels in which one row of input pixel data DI becomes output pixel data DO every 1H. Converted to data S. The gradation pixel data S has the same gradation value as the pixel data DI, and the black pixel data B has a gradation value for black display. Each of the black pixel data B for one row and the gradation pixel data S for one row is output in series from the image data conversion circuit 13 in the H / 2 period. The source driver XD refers to a predetermined number of gradation reference voltages VREF supplied from the gradation reference voltage generation circuit 7 to convert the pixel data B and S into pixel voltages Vs, respectively. Output to Xn in parallel.

  The pixel voltage Vs is a voltage applied to the pixel electrode PE on the basis of the common voltage Vcom of the common electrode CE, and the polarity is inverted with respect to the common voltage Vcom so as to perform, for example, frame inversion driving and line inversion driving. When black insertion driving is performed at the double vertical scanning speed, the polarity is inverted with respect to the common voltage Vcom so as to perform, for example, line inversion driving and frame inversion driving (1H1V inversion driving). The compensation voltage Ve is applied via the gate driver YD to the auxiliary capacitance line C corresponding to the gate line Y connected to the switching elements W when the switching elements W for one row are turned off. This is used to compensate for variations in the pixel voltage Vs generated in the pixels PX for one row due to the parasitic capacitance of the element W.

  When the gate driver YD drives, for example, the gate line Y1 with the on-voltage to make all the pixel switching elements W connected to the gate line Y1 conductive, the pixel voltage Vs on the source lines X1 to Xn is changed to these pixel switching elements W. To the corresponding pixel electrode PE and one end of the auxiliary capacitor Cs. Further, the gate driver YD outputs the compensation voltage Ve from the compensation voltage generation circuit 6 to the auxiliary capacitance line C1 corresponding to the gate line Y1, and applies all the pixel switching elements W connected to the gate line Y1 to one horizontal scanning period. Immediately after being turned on, an off voltage that makes these pixel switching elements W non-conductive is output to the gate line Y1. The compensation voltage Ve reduces the electric charge drawn from the pixel electrode PE by these parasitic capacitances when these pixel switching elements W become non-conductive, and substantially cancels the fluctuation of the pixel voltage Vs, that is, the punch-through voltage ΔVp.

  Here, the operation of the liquid crystal display device shown in FIG. 1 will be schematically described. FIG. 3 shows the operation of the liquid crystal display device when black insertion driving is performed at a vertical scanning speed of 2 × speed. 3, B represents black pixel data common to the pixels PX in each row, and S1, S2, S3,... Represent grayscale pixel data for the pixels PX in the first row, the second row, the third row,. Represents. +, − Represent the signal polarities when the pixel data B, S1, S2, S3... Are converted into the pixel voltage Vs and output from the source driver XD.

  Here, both the first start signal STHA and the second start signal STHB are pulses input to the gate driver YD with a pulse width corresponding to the H / 2 period. The first start signal STHA is input first, and the second start signal STHB is input later than the first start signal STHA according to the black insertion rate. The black insertion rate is set as a ratio of a black insertion period (non-gradation image display period) in one frame period (1V: vertical scanning period). Here, the black insertion period is a period during which the black pixel voltage B is held in one frame period. The gradation image display period is a period in which the gradation elementary voltage S is held in one frame period, and has a length obtained by subtracting the black insertion period from one frame period.

  The gate driver YD shifts the first start signal STHA to select one of the plurality of gate lines Y1 to Ym per horizontal scanning period H and drive signals to the gate lines Y1, Y2, Y3,... In the second half of the 1H period. Is output. On the other hand, the source driver XD converts each of the gradation pixel data S1, S2, S3,... Into the pixel voltage Vs in the latter half of the corresponding 1H period, and converts them into the source lines X1 to Xn with the polarity inverted every 1H. Output in parallel. These pixel voltages Vs are supplied to the liquid crystal pixels PX in the first row, the second row, the third row, the fourth row, etc. while each of the gate lines Y1 to Ym is driven in the second half of the corresponding 1H period.

  Further, the gate driver YD shifts the second start signal STHB to select a plurality of gate lines Y1 to Ym one by one per horizontal scanning period H, and to the gate lines Y1, Y2, Y3,... In the first half of the 1H period. A drive signal is output. On the other hand, the source driver XD converts each of the black pixel data B, B, B,... Into the pixel voltage Vs in the first half of the corresponding 1H period, and converts these into the source lines X1 to Xn with the polarity inverted every 1H. Output in parallel. These pixel voltages Vs are supplied to the first, second, third,... Liquid crystal pixels PX while each of the gate lines Y1 to Ym is driven in the first half of the corresponding 1H period. In FIG. 3, the first start signal STHA and the second start signal STHB are input at a relatively short interval, but in reality, the relationship between the gradation image display period and the black insertion period is the black insertion rate. Entered separately to fit.

  Incidentally, when black insertion driving is performed at a 1.5 × vertical scanning speed, the image data conversion circuit 13 is configured to perform black insertion 1.5 × conversion on image data input from the external signal source SS. . Further, the source driver XD is configured to output to the source lines X1 to Xn a pixel voltage Vs whose polarity is inverted with respect to the common voltage Vcom so as to perform 2-line unit inversion driving and frame inversion driving (2H1V inversion driving). . In the black insertion 1.5 × speed conversion, input pixel data DI for two rows is converted into black pixel data B for one row and gradation pixel data S for two rows that become output pixel data DO every 2H period. The The gradation pixel data S has the same gradation value as the pixel data DI, and the black pixel data B has a gradation value for black display. The black pixel data B for one row and the grayscale pixel data S for two rows are each output in series from the image data conversion circuit 13 in the 2H / 3 period.

  When black insertion driving is performed at a 1.5 × vertical scanning speed, the operation of the liquid crystal display device is as follows. In this case, the first start signal STHA is a pulse input to the gate driver YD with a pulse width of 2H / 3 period, and the second start signals STHB are all input to the gate driver YD with a pulse width of 2H period. Pulse. The second start signal STHB is input later than the first start signal STHA according to the black insertion rate.

  The gate driver YD shifts the first start signal STHA to sequentially select a plurality of gate lines Y1 to Ym by two per 2H period, and in the second and third 2H / 3 periods included in the corresponding 2H period. Are output to the selection gate lines Y1, Y2; Y3, Y4; On the other hand, the source driver XD converts the gradation pixel data S1, S2; S3, S4,... Into the pixel voltage Vs in the second and third 2H / 3 periods included in the corresponding 2H period, and converts them to 2H. Outputs in parallel to the source lines X1 to Xn with the polarity inverted every time. These pixel voltages Vs are supplied to the first, second, third, and fourth rows while each of the gate lines Y1 to Ym is driven in the second or third 2H / 3 period included in the corresponding 2H period. Supplied to the liquid crystal pixels PX of the eyes,.

  Further, the gate driver YD shifts the second start signal STHB to select two of the plurality of gate lines Y1 to Ym together every 2H period, and selects these in the first 2H / 3 period included in the corresponding 2H period. A drive signal is output to the gate lines Y1, Y2; Y3, Y4; On the other hand, the source driver XD converts each of the black pixel data B, B, B,... Into the pixel voltage Vs in the first 2H / 3 period included in the corresponding 2H period, and inverts them every 2H. Are output in parallel to the source lines X1 to Xn. These pixel voltages Vs are applied to the first row, the second row, the third row, the fourth row, etc. while each of the gate lines Y1 to Ym is driven in the first 2H / 3 period included in the corresponding 2H period. To the liquid crystal pixel PX.

  The backlight BL shown in FIG. 1 includes a discharge lamp light source such as a single cold cathode tube, and is AC driven by an inverter circuit LD to illuminate the display panel DP as a whole. A specific illumination target of the backlight BL is a plurality of liquid crystal pixels PX constituting the display screen of the display panel DP. Here, the liquid crystal pixels PX in each row are treated as one horizontal display line.

  The dimming control circuit 14 shown in FIG. 1 detects the duty ratio of the PWM dimming signal from the external signal source SS and generates a dimming control signal corresponding to the detection result, and this duty ratio detection. A phase control unit 14B that controls the phase of the dimming control signal from the unit 14A and outputs the control signal to the inverter circuit LD. The dimming control signal is a pulse repeated every frame period, and the duty ratio of this pulse is adjusted in accordance with the duty ratio of the PWM dimming signal in order to set the brightness of the liquid crystal display panel DP. The phase control unit 14B totals from the start of the gradation image display by the liquid crystal pixel PX (first horizontal display line) in the first row to the end of the gradation image display by the liquid crystal pixel PX (m-th horizontal display line) in the last row. The pulse phase is set so that the pulse of the dimming control signal is symmetrical with respect to the reference timing that divides the gradation image display period into two equal parts, and the center of the pulse is used as a reference when the duty ratio is reduced below a predetermined value. The pulse phase is shifted so as to compensate for the delay in light emission of the backlight BL earlier than the timing. Here, the reference timing is obtained from the first and second start signals STHA and STHB and the clock signal included in the control signal CTY, for example. Further, the predetermined value reduces the light emission period of the backlight BL by decreasing the duty ratio of the dimming control signal, and the streak is caused by the difference between the gradation image display operation of the liquid crystal display panel DP and the light emission operation of the backlight BL. The duty ratio is set to about 60% at which the pattern starts to be observed. The inverter circuit LD converts the dimming control signal output from the phase control unit 14A into an AC drive voltage and outputs the converted voltage to the backlight BL. The backlight BL is turned on when the dimming control signal is at a high level, and is turned off when the dimming control signal is at a low level.

  FIG. 4 shows the relationship between the dimming control signals having different duty ratios and the lamp brightness of the backlight BL. This relationship is a result of changing the duty ratio of the dimming control signal to 85%, 60%, 30%, and 15%. The lamp brightness becomes maximum brightness (= 100%) after the rise timing of the dimming control signal at any duty ratio, and reaches the minimum brightness (= 0%) after the fall timing of the dimming signal. Become. Even if a deviation between the gradation image display operation and the light emission operation of the backlight BL occurs, if the duty ratio is about 85% or 60%, a striped pattern is not observed at all or only a little, so the pulse phase of the dimming control signal Is controlled in the same manner as in the prior art shown in FIG. On the other hand, when the same control as in the prior art is performed with a duty ratio of 30% or 15% smaller than the duty ratio of 60%, the striped pattern is substantially observed. For this reason, the phase control unit 14B shifts the pulse phase when the duty ratio is 60% or less of the predetermined value, and compensates for the delay in the emission of the backlight BL by making the center of the pulse earlier than the reference timing. TP shown in FIG. 4 is the time difference between the center of the pulse that changes due to this phase shift and the reference timing. When the pulse phase is actually shifted in the dimming control signals having different duty ratios, the relationship shown in FIG. 5 is obtained for the display operation of the horizontal pixel line. That is, tP increases along a curve as shown in FIG. 5 as the duty ratio of the dimming control signal performed to reduce the brightness of the liquid crystal display panel DP.

Note that since the responsiveness of the backlight BL, that is, the discharge lamp light source, also changes depending on the environmental temperature, it is preferable that tP be optimized in accordance with the change in the environmental temperature.

  In the present embodiment, the liquid crystal display panel DP that is sequentially driven at least one row at a time so that the plurality of rows of liquid crystal pixels PX perform gradation image display and non-gradation image display at a constant time ratio with respect to one frame period. Although a discharge lamp light source such as a cold cathode tube is used as the backlight BL to illuminate, good response in light emission cannot be expected with respect to this lamp light source. For this reason, the dimming control circuit 14 and the inverter circuit LD are provided as a light source driving device for the lamp light source. The phase control unit 14A of the dimming control circuit 14 bisects the total gradation image display period from the start of gradation image display by the liquid crystal pixel PX in the first row to the end of gradation image display by the liquid crystal pixel PX in the last row. The pulse phase is set so that the pulse of the dimming control signal is symmetric with respect to the reference timing, and when the duty ratio is reduced below a predetermined value of 60%, the center of the pulse is set earlier than the reference timing to ramp The pulse phase is shifted so as to compensate for the light emission delay of the light source. As described above, since the deviation between the gradation image display operation of the liquid crystal display panel DP and the light emission operation of the lamp light source is canceled by the shift of the pulse phase, even if the light emission of the lamp light source is delayed due to the responsiveness, The amount of light can be evenly distributed before and after the reference timing. In this case, it is possible to reduce the duty ratio of the dimming control signal beyond a predetermined value. As a result, the occurrence of striped patterns can be reduced without restricting the substantial light control range.

  In addition, this invention is not limited to the above-mentioned embodiment, It can deform | transform variously in the range which does not deviate from the summary.

  In the above-described embodiment, the liquid crystal display device using the liquid crystal alignment type that requires black insertion driving has been described. However, the present invention is not limited to black insertion driving, and the pixel voltage is periodically applied to the gradation image. Any liquid crystal display device that requires non-gradation image display that is fixed to a constant value close to the minimum luminance regardless of display can be applied. Therefore, the liquid crystal alignment type need not be OCB.

  In the above-described embodiment, since the backlight BL is a single discharge lamp light source, all of the plurality of liquid crystal pixels PX are illuminated by this lamp light source. However, for example, a display screen may be divided into a plurality of display areas each including, for example, an arbitrary number of liquid crystal pixels PX, and a plurality of lamp light sources that respectively illuminate these display areas may be provided. In this case, the dimming control circuit 14 outputs a number of dimming control signals corresponding to the plurality of lamp light sources, and the inverter circuit LD can independently drive the plurality of lamp light sources corresponding to the dimming control signals. Configured as follows. Here, the pulse phase of each dimming control signal is determined based on the gradation of the liquid crystal pixel PX in the last row from the start of gradation image display by the liquid crystal pixel PX in the first row among the liquid crystal pixels PX in any number of rows illuminated by the corresponding lamp light source. In the optimization, it is preferable to shift from a separate reference timing that divides the total gradation image display period until the end of the tone image display into two equal parts.

It is a figure which shows schematically the circuit structure of the liquid crystal display device which concerns on one Embodiment of this invention. It is a figure which shows the cross-section of the liquid crystal display panel shown in FIG. 2 is a time chart illustrating an operation when black insertion driving is performed at a double vertical scanning speed in the liquid crystal display device illustrated in FIG. 1. It is a figure which shows the relationship between the light control signal of a mutually different duty ratio, and the lamp | ramp brightness | luminance of the backlight shown in FIG. 6 is a time chart showing a relationship obtained for a display operation of a horizontal pixel line when the pulse phase of the light control signal with the duty ratio shown in FIG. 4 is actually shifted. It is a time chart which shows the pulse phase of the light control signal used with the conventional liquid crystal display device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Array substrate, 2 ... Opposite substrate, 3 ... Liquid crystal layer, 4 ... Drive voltage generation circuit, 5 ... Controller circuit, 6 ... Compensation voltage generation circuit, 7 ... Tone reference voltage generation circuit, 8 ... Common voltage generation circuit , 11 ... vertical timing control circuit, 12 ... horizontal timing control circuit, 13 ... image data conversion circuit, 14 ... dimming control circuit, 14A ... duty ratio detection unit, 14B ... phase control unit, BL ... backlight, DP ... liquid crystal Display panel, PE ... pixel electrode, CE ... common electrode, CLC ... liquid crystal capacitor, Cs ... auxiliary capacitor, PX ... liquid crystal pixel, W ... switching element, Y ... gate line, X ... source line, CNT ... display control circuit, LD ... Backlight drive unit, YD ... Gate driver, XD ... Source driver.

Claims (2)

A light source for a lamp light source that illuminates a liquid crystal display panel that is sequentially driven at least row by row so that a plurality of rows of liquid crystal pixels perform gradation image display and non-gradation image display at a constant time ratio with respect to one frame period. A dimming control circuit for generating a dimming control signal as a pulse of a duty ratio which is repeated for each frame period and adjusted to set the brightness of the liquid crystal display panel; An inverter circuit that causes the lamp light source to emit light for a period corresponding to a pulse width of a control signal, and the dimming control circuit includes a first row of liquid crystal pixels from the start of the gradation image display to the last row of liquid crystal pixels. The pulse phase is set so that the pulse of the dimming control signal is symmetrical with respect to the reference timing that divides the total gradation image display period until the end of the dimming image display into two equal parts. A phase control unit that shifts the pulse phase so as to compensate for a delay in light emission of the lamp light source by making the center of the pulse earlier than the reference timing when the duty ratio is decreased below a predetermined value. A light source driving device characterized. 2. The light source driving device according to claim 1, wherein the liquid crystal pixel is an OCB liquid crystal pixel that performs black display in order to obtain a voltage that prevents reverse transition from bend alignment to splay alignment as non-gradation image display. .

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