JP2006119447A - Display panel control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve display quality of moving pictures relating to a display panel control circuit mainly applied for a hold type display panel. <P>SOLUTION: The display panel control circuit includes: an image data processing circuit 4 to process image data comprising a plurality of input pixel data which are updated in each frame period; a gate driver YD to sequentially drive a plurality of gate lines Y twice in one frame period; a source driver XD to output a pixel voltage corresponding to the processing result of the image data processing circuit 4 to each of a plurality of source lines X while each of the plurality of gate lines Y are driven by the gate driver YD; and a controller 5 to control the operation timing of the gate driver YD and the source driver XD. In particular, the image data processing circuit 4 converts the input pixel data changed by update into output pixel data which synchronously vary with driving of the corresponding gate lines Y, and converts the input pixel data not changed by update into output pixel data which does not synchronously vary with driving of the corresponding gate lines Y. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display panel control circuit mainly applied to a hold type display panel.

  A flat display device typified by a liquid crystal display device is widely used as a display device for a personal computer, a car navigation system, a television receiver, or the like.

  A liquid crystal display device generally includes a liquid crystal display panel including a matrix array of a plurality of pixels, and a display control circuit that controls the display panel. The liquid crystal display panel has a structure in which a liquid crystal layer is sandwiched between an array substrate and a counter substrate. The array substrate has a plurality of pixel electrodes arranged in a substantially matrix, a plurality of gate lines arranged along a row of the plurality of pixel electrodes, a plurality of source lines arranged along a column of the plurality of pixel electrodes, and a plurality of And a plurality of switching elements arranged in the vicinity of the intersection position of the plurality of gate lines and the plurality of source lines. Each switching element is formed of, for example, a thin film transistor, and conducts when one gate line is driven to electrically connect one source line to one pixel electrode. A common electrode is provided on the counter substrate so as to face the plurality of pixel electrodes arranged on the array substrate. The pair of pixel electrodes and the common electrode constitute a pixel together with the pixel region of the liquid crystal layer, and the liquid crystal molecule arrangement is controlled by an electric field between the pixel electrode and the common electrode in the pixel region. The display control circuit includes a gate driver connected to the plurality of gate lines, a source driver connected to the plurality of source lines, a controller for controlling operation timings of the gate driver and the source driver, and the like.

  Here, the gate driver sequentially drives a plurality of gate lines in one frame period (vertical scanning period) that is an update period of image data composed of pixel data for a plurality of pixels, and the source driver uses each gate line by a gate driver. In one horizontal scanning period to be driven, pixel data for pixels for one row are converted into pixel voltages, respectively, and output in parallel to a plurality of source lines. These pixel voltages are supplied to each pixel electrode through one row of switching elements assigned to the drive gate line. The pixel voltage is, for example, a potential difference between the common electrode and the pixel electrode set to 0 V, and is applied to the pixel region of the liquid crystal layer disposed between the pixel electrode and the common electrode as a liquid crystal driving voltage. Further, the pixel electrode and the common electrode constitute a liquid crystal capacitor connected in parallel to the auxiliary capacitor, and are charged to the pixel voltage together with the auxiliary capacitor in one horizontal scanning period in which the switching element becomes conductive. The charged charge is held until it becomes conductive and becomes conductive again after one frame period. That is, the liquid crystal display panel is a hold-type display panel that holds the display state until the image data is updated.

  If the direction of the electric field between the pixel electrode and the common electrode is not changed, the uneven distribution of liquid crystal molecules proceeds, and finally the liquid crystal molecule arrangement cannot be controlled. In order to prevent this, the polarity of the pixel voltage is inverted with respect to the potential of the common electrode every frame period, for example. Also, the pixel voltage is generally inverted in polarity for each pixel in each row and each column in order to prevent flickering of the display image, and is usually called dot inversion driving.

  The pixels of the display panel are generally driven by the driving method shown in FIG. The image data is updated in the frame periods N, N + 1, N + 2,. The source driver converts a plurality of pixel data included in the image data input in each of the frame periods N, N + 1, N + 2,... Into a pixel voltage in units of rows and outputs them in parallel to the source line. Each pixel voltage is supplied from the corresponding source line to the corresponding pixel electrode via the corresponding switching element. In FIG. 7, an example of the pixel voltage is indicated by an absolute value. If the display panel is a normally white type in which white display is performed when no pixel voltage is applied, the pixel luminance decreases in response to the rise of the pixel voltage generated in the frame period N, for example, and the pixel voltage generated in the frame period N + 4 It increases in response to the fall of. However, the transition of the pixel luminance is completed with a large delay from the change time of the pixel voltage depending on the response speed of the liquid crystal. This is a cause of reducing the display quality of the moving image.

  Such a delay in luminance transition can be improved, for example, by driving the display panel by the driving method shown in FIG. 8 (see, for example, Patent Document 1). In this driving method, input image data is checked for each frame period, pixel data that changes with respect to pixel data of a preceding frame is specified from among a plurality of pixel data included in the input image data, and the pixel data A compensation voltage corresponding to the difference between the pixel data is superimposed on the corresponding pixel voltage. As a result, the pixel is overdriven by this compensation voltage. In FIG. 8, the pixel is overdriven at the rising edge of the pixel voltage generated in the frame period N, for example, and further overdriven at the falling edge of the pixel voltage generated in the frame period N + 4. As a result, the transition time of pixel luminance is shorter than the time shown in FIG.

On the other hand, in the liquid crystal display panel, a liquid crystal display mode having a high response speed such as OCB may be employed. However, since the liquid crystal display panel is a hold-type display panel that holds the display state until the image data is updated, it is difficult to smoothly show the movement of the object due to the influence of the retinal afterimage generated in the viewer's vision in the moving image display. Such a reduction in the visibility of a moving image due to the viewer's vision can be improved by driving the display panel by a driving method shown in FIG. 9 (see, for example, Patent Document 2). In this driving method, vertical scanning is performed at a double speed, and a black image frame is inserted before a normal image frame, thereby making the pixel luminance a pseudo discrete impulse response waveform. In this case, since the normal image is displayed after the retinal afterimage is cleared with the black image, the moving image visibility can be improved.
JP 2003-143556 A JP 2003-295156 A

  Incidentally, in the driving method shown in FIG. 8, a compensation voltage is superimposed on the pixel voltage in order to improve the delay in luminance transition. However, since this superimposition control is performed in units of one frame period, it is not easy to set a compensation amount that appropriately compensates for the slow response speed of the liquid crystal. As a result, the amount of compensation is too large or too small, making it difficult to stably improve the luminance response.

  In the driving method shown in FIG. 9, the black image frame is inserted in front of the normal image frame with the vertical scanning being doubled. However, the insertion of the black image frame reduces the effective luminance of the normal image and gives the viewer the impression that the screen is dark. If this is to be solved by increasing the brightness of the backlight, the current consumption will increase. Further, since the pixel luminance is changed to a pseudo impulse response by repeating the insertion of the black image frame, the problem of an increase in flicker occurs while the moving image visibility is improved.

  An object of the present invention is to provide a display panel control circuit capable of improving the display quality of moving images.

  According to the present invention, there is provided a display panel control circuit for controlling a display panel in which a plurality of pixels are arranged in the vicinity of intersection positions of a plurality of gate lines and a plurality of source lines, and a predetermined update cycle for the plurality of pixels. An image data processing circuit for processing image data composed of a plurality of input pixel data updated in step (a), a gate driver for sequentially driving a plurality of gate lines at least twice for each input of the image data, and a gate driver A source driver that outputs a pixel voltage corresponding to a processing result of the image data processing circuit to each of the plurality of source lines while each of the plurality of gate lines is driven; and a controller that controls the operation timing of the gate driver and the source driver. And the image data processing circuit synchronizes each pixel data changed by the update with the driving of the corresponding gate line. It was converted into the output pixel data of the display panel control circuit configured to convert each of the input pixel data that is not changed by updating the output pixel data that does not change in synchronism with the driving of the corresponding gate line is provided.

  In this display panel control circuit, a gate driver sequentially drives a plurality of gate lines at least twice for each input of image data, and each of the input pixel data changed by the image data processing circuit is updated. The pixel data is converted into output pixel data that changes in synchronization with the driving, and each of the input pixel data that does not change due to the update is converted into output pixel data that does not change in synchronization with the driving of the corresponding gate line.

  In order to improve luminance response, this configuration allows the pixel voltage to transition in a stepwise manner from a value exceeding the value corresponding to the input pixel data to a value corresponding to the input pixel data as the output pixel data changes. To. Specifically, for example, the pixel voltage is set to a value exceeding the value corresponding to the input pixel data by superimposing a compensation voltage for luminance response at the time of driving the corresponding gate line for the first time, and the second corresponding gate line is set. The pixel voltage can be set to a value corresponding to the input pixel data at the time of driving, and the pixel can be overdriven only for ½ period of one frame period, for example. In this case, since the drive frequency of the pixel is doubled, it is difficult for the compensation amount to be excessive or insufficient.

  Further, the above-described configuration is an intermediate corresponding to the result of interpolating the input pixel data and the preceding pixel data with the change of the output pixel data in order to improve the moving image visibility which is deteriorated due to the visual influence of the observer. The pixel voltage can be gradually changed from the value to the value corresponding to the input pixel data. In this case, the change in pixel luminance is not steep and the observer's vision can follow the change in luminance, so that the visibility of the moving image can be improved. Further, since a black image frame as in the prior art in which all pixels are displayed in black is not required, the utilization efficiency of backlight light is improved. That is, a bright screen can be obtained without increasing the power consumption of the backlight power, and flickers that can occur when black image frames are inserted periodically can be prevented.

Furthermore, the above-described configuration improves the video visibility, which decreases due to the viewer's visual influence.
As the output pixel data changes, it is possible to make the pixel voltage transition from a black display value to a value corresponding to the input pixel data. Even in this case, since the change in luminance of the pixels is effectively moderated, the visual perception of the observer can follow the change in pixel luminance, so that the moving image visibility can be improved. Also, since only the pixels whose input pixel data changes with respect to the preceding pixel data due to image movement temporarily display black, a bright screen can be obtained with low power consumption, and the black image frame is cycled. Flickering that occurs when the card is inserted in a normal manner can be prevented.

  That is, since the luminance responsiveness or moving image visibility can be improved as described above, the moving image display quality can be improved.

  Hereinafter, a liquid crystal display device according to a first embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 schematically shows a circuit configuration of the liquid crystal display device. In the liquid crystal display device, a plurality of pixels PX includes a liquid crystal display panel DP and a display panel control circuit CNT that controls the display panel DP. The liquid crystal display panel DP has a structure in which a liquid crystal layer 3 is sandwiched between the array substrate 1 and the counter substrate 2.

  The array substrate 1 includes a plurality of pixel electrodes PE arranged in a substantially matrix on a transparent insulating substrate such as glass, and a plurality of gate lines Y (Y1 to Ym) arranged along a row of the plurality of pixel electrodes PE. And a plurality of source lines X (X1 to Xn) arranged along a column of the plurality of pixel electrodes PE, and a plurality of pixel switching elements W arranged in the vicinity of the intersection positions of the gate lines Y and the source lines X. . Each pixel switching element W is formed of, for example, a thin film transistor. A gate of the thin film transistor is connected to one gate line Y, and a source-drain path is connected between one source line X and one pixel electrode PE.

The counter substrate 2 includes a color filter (not shown) disposed on a transparent insulating substrate such as glass, and a common electrode CE disposed on the color filter so as to face the plurality of pixel electrodes PE. Each pixel electrode PE and common electrode CE is made of a transparent electrode material such as ITO, and constitutes a pixel PX together with a pixel region of the liquid crystal layer 3 controlled to a liquid crystal molecular arrangement corresponding to the electric field from the pixel electrode PE and common electrode CE. To do.
All the pixels PX have an auxiliary capacitor Cs. The auxiliary capacitance Cs of each pixel PX is obtained by capacitive coupling between the pixel electrode PE of the pixel PX and the gate line Y that controls the pixel switching element W of the pixel PX in the next row adjacent to the pixel PX. The capacitance value is sufficiently larger than the parasitic capacitance of the element W. In FIG. 1, a plurality of dummy pixels arranged around the matrix array of the plurality of pixels PX constituting the display screen are omitted. These dummy pixels are wired in the same manner as the pixels PX in the display screen, and are provided to make all the pixels PX in the display screen have the same conditions with respect to parasitic capacitance and the like. The gate line Ymd is a gate line for such a dummy pixel.

  The display panel control circuit CNT has an image data processing circuit 4 for processing image data composed of a plurality of pixel data inputted for each frame period (vertical scanning period) for a plurality of pixels PX, and each gate line is an image. A gate driver YD that sequentially drives the plurality of gate lines Y1 to Ym at least twice for each data input, and an image data processing circuit in one horizontal scanning period in which each of the gate lines Y1 to Ym is driven by the gate driver YD 4 includes a source driver XD that outputs pixel voltages corresponding to the processing results obtained from 4 to the plurality of source lines X1 to Xn, and a controller 5 that controls the operation timing of the gate driver YD and the source driver XD. The gate driver YD and the source driver XD are integrated circuit (IC) chips mounted near the outer edge of the array substrate 1 by, for example, COG (Chip On Glass) technology. On the other hand, the image data processing circuit 4 and the controller 5 are arranged on an external circuit board PCB. One frame period is an image data update cycle, and the image data processing circuit 4 converts each of the input pixel data changed by this update into output pixel data that changes in synchronization with the driving of the corresponding gate line Y, and this update. Thus, a process of converting each of the input pixel data that does not change by the above to output pixel data that does not change in synchronization with driving of the corresponding gate line Y is performed.

  Here, the controller 5 outputs the control signal CTY for sequentially selecting a plurality of gate lines Y as described above and output pixel data obtained in units of pixels PX for one row as a processing result of the image data processing circuit 4. A control signal CTX and the like for assigning to a plurality of source lines X are generated. The control signal CTY is supplied from the controller 5 to the gate driver YD, and the control signal CTX is supplied from the controller 5 to the source driver XD together with the output pixel data DATA obtained as a processing result from the image data processing circuit 4.

  The gate driver YD sequentially selects a plurality of gate lines Y1 to Ym in each of the first half and the second half obtained by dividing one frame period into two under the control of the control signal CTY, and selects a scanning signal for making the pixel switching element W conductive. Supply to the gate line Y. As a result, the plurality of gate lines Y1 to Ym are driven twice in one frame period. The image data processing circuit 4 outputs a processing result, which is output pixel data for one row of pixels PX, for each horizontal scanning period, and the source driver XD converts these output pixel data into pixel voltages, respectively, and outputs a plurality of source lines. Output in parallel to X1 to Xn. The pixel voltages on these source lines X1 to Xn are respectively supplied to the corresponding pixel electrodes PE via one row of pixel switching elements W driven by the scanning signal. That is, each of the plurality of pixel electrodes PE receives a pixel voltage corresponding to output pixel data obtained from the image data processing circuit 4 in the first half and the second half of one frame period. This pixel voltage is a voltage applied to the pixel electrode PE with reference to the potential Vcom of the common electrode CE. Here, the common voltage Vcom is set to a constant value, and the polarity of the pixel voltage is inverted with respect to the common voltage Vcom so as to perform frame inversion driving and dot inversion driving.

FIG. 2 shows a circuit configuration of the image data processing circuit 4 shown in FIG. The image data processing circuit 4
The delay circuit 11 delays the image data by one frame period, and each input pixel data is compared with the delayed output of the delay circuit 11 and is synchronized with the driving of the corresponding gate line Y when a mismatch is detected with respect to the input pixel data. And an arithmetic circuit 12 that generates output pixel data that changes and generates output pixel data that does not change in synchronization with driving of the corresponding gate line Y when no mismatch is detected with respect to the input pixel data. Here, the delay circuit 11 is configured using, for example, a frame memory. The gate driver YD outputs scanning signals to the gate lines Y1 to Ym at a rate of two per one horizontal scanning period as shown in FIG. Thereby, the gate lines Y1 to Ym are driven once in the first half of one frame period and further driven once in the second half. Accordingly, the output image data for the first half is output to the display panel DP in the first half of one frame period, and the output image data for the second half is output to the display panel DP in the second half of one frame period.

  When the input pixel data does not match the delayed output of the delay circuit 11, the arithmetic circuit 12 sets the pixel voltage to a value exceeding the value corresponding to the input pixel data when the corresponding gate line is driven for the first time (the first half of one frame period). Output pixel data to be set is generated, and output pixel data for setting a pixel voltage to a value corresponding to the input pixel data is generated when the corresponding gate line is driven for the second time (second half of one frame period). That is, the change in the output pixel data causes the pixel voltage to gradually change from a value exceeding the value corresponding to the input pixel data to a value corresponding to the input pixel data.

  At the time of driving the corresponding gate line for the first time, the pixel voltage is set to a value exceeding the value corresponding to the input pixel data by superimposing the compensation voltage on the luminance response. This compensation voltage is a voltage that accelerates the response of the liquid crystal, and thereby the pixel PX is overdriven in the first half of one frame period.

  The arithmetic circuit 12 sets the pixel voltage to a value corresponding to the input pixel data when the corresponding gate line is driven for the first time (first half of one frame period) when the input pixel data matches the delayed output of the delay circuit 11. The output pixel data is generated, and the output pixel data for setting the pixel voltage to the value corresponding to the input pixel data is generated when the corresponding gate line is driven for the second time (the second half of one frame period). In this case, the output pixel data does not change in one frame period, and the pixel voltage is maintained at a value corresponding to the input pixel data.

  FIG. 4 shows an example of the pixel driving operation of the liquid crystal display device. The input image data is updated in the frame periods N, N + 1, N + 2,. Here, it is one of the plurality of input pixel data included in the input image data, and changes with respect to the delay output of the delay circuit 11 in the frame periods N and N + 4, that is, the input pixel data in the preceding frame period. Pay attention. In the frame period N in which it is detected that the input pixel data does not match the corresponding pixel data in the preceding frame period N−1, the source driver XD corresponds to the input pixel data by superimposing a compensation voltage in the first half of the frame period N. A pixel voltage set to a value exceeding the value (overdrive level) is output to the corresponding source line Y. This pixel voltage is supplied from the corresponding source line Y to the corresponding pixel electrode PE via the corresponding switching element W, and is applied to the pixel region of the liquid crystal layer 3 as a potential difference between the pixel electrode PE and the common electrode CE. This pixel voltage is shown as an absolute value in FIG. That is, the pixel voltage rises to the overdrive level in the first half of the frame period N. Subsequently, the source driver XD outputs a pixel voltage set to a value corresponding to the input pixel data to the corresponding source line Y in the second half of the frame period N. This pixel voltage is supplied from the corresponding source line Y to the corresponding pixel electrode PE via the corresponding switching element W, and the potential difference between the pixel electrode PE and the common electrode CE is applied to the pixel region of the liquid crystal layer 3 as the liquid crystal driving voltage. That is, the pixel drive voltage falls to the original level based on the input pixel data in the second half of the frame period N.

  On the other hand, in the frame period N + 1 in which it is detected that the input pixel data matches the corresponding pixel data in the preceding frame period N, the source driver XD corresponds to the input pixel data in each of the first half and the second half of the frame period N + 1. The pixel voltage set to the same value is output to the corresponding source line Y. This pixel voltage is supplied from the corresponding source line Y to the corresponding pixel electrode PE via the corresponding switching element W, and is applied to the pixel region of the liquid crystal layer 3 as a potential difference between the pixel electrode PE and the common electrode CE. Incidentally, the pixel voltage is set to the same value as that set in the second half of the frame period N in the first half and the second half of the level frame period N + 1. This value is continued until immediately before the frame period N + 4 in which the mismatch between the input pixel data and the preceding frame period pixel data is detected again. In the frame period N + 4, the same control as in the frame period N is performed, and the pixel voltage falls to the overdrive level in the first half and rises to the original level based on the input pixel data in the second half.

  In the present embodiment, the driving frequency of the pixel PX is doubled, and the overdrive period can be shortened to ½ of one frame period. That is, the luminance responsiveness can be improved by appropriately and sufficiently compensating the liquid crystal responsiveness.

  In the above-described embodiment, since one frame period is divided into two equal parts, the gate lines Y1 to Ym are sequentially driven twice in one frame period. However, the number of divisions in one frame period is not limited to this, and may be increased further. That is, the gate lines Y1 to Ym are driven at least twice in one frame period, and from the overdrive level that accelerates the liquid crystal response in synchronization with the driving of the corresponding gate line Y in the frame period in which the input pixel data for each pixel changes. What is necessary is just to change a pixel voltage to the level corresponding to input pixel data.

Next, a liquid crystal display device according to a second embodiment of the present invention will be described. This liquid crystal display device is configured similarly to the first embodiment except for the function of the arithmetic circuit 12 shown in FIG. For this reason, the description which overlaps with 1st Embodiment is simplified or abbreviate | omitted.
Also in this liquid crystal display device, the gate driver YD sequentially selects a plurality of gate lines Y1 to Ym in each of the first half and the second half obtained by dividing one frame period into, for example, two under the control of the control signal CTY, and the pixel switching element W is selected. A scanning signal to be conducted is supplied to the selection gate line Y. As a result, the plurality of gate lines Y1 to Ym are driven twice in one frame period. The image data processing circuit 4 outputs a processing result, which is output pixel data for one row of pixels PX, for each horizontal scanning period, and the source driver XD converts these output pixel data into pixel voltages, respectively, and outputs a plurality of source lines. Output in parallel to X1 to Xn. The delay circuit 11 delays image data by one frame period. The arithmetic circuit 12 compares each input pixel data with the delay output of the delay circuit 11, and outputs output pixel data that changes in synchronization with the driving of the corresponding gate line Y when a mismatch is detected with respect to the input pixel data. When no mismatch is detected with respect to the input pixel data, output pixel data that does not change in synchronization with driving of the corresponding gate line Y is generated.

  When the input pixel data does not coincide with the delay output of the delay circuit 11, the arithmetic circuit 12 corresponds to the result of interpolating the delay output and the input pixel data when the corresponding gate line is driven for the first time (the first half of one frame period). Pixel data for setting the pixel voltage to the intermediate value is output, and pixel data for setting the pixel voltage to the value corresponding to the input pixel data is output when the corresponding gate line is driven for the second time (the second half of one frame period). In this case, the interpolation result is an average value of the delayed output and the input pixel data. This change in the output pixel data causes the pixel voltage to transition stepwise from an intermediate value corresponding to the interpolation result to a value corresponding to the input pixel data. A specific difference from the first embodiment is that the arithmetic circuit 12 outputs pixel data for setting the pixel voltage to a value corresponding to the interpolation result when the corresponding gate line is driven for the first time. This is effective when the arithmetic circuit 12 is applied to a liquid crystal display panel DP such as an OCB mode having a high liquid crystal response speed.

  Incidentally, when the input pixel data matches the delayed output of the delay circuit 11, the arithmetic circuit 12 sets the pixel voltage to a value corresponding to the input pixel data when the corresponding gate line is driven for the first time (the first half of one frame period). The pixel data for setting the pixel voltage to the value corresponding to the input pixel data is output when the corresponding gate line is driven for the second time (the second half of one frame period). Accordingly, the output pixel data does not change, and the pixel voltage is maintained at a value corresponding to the input pixel data.

  FIG. 5 shows a pixel driving operation of the liquid crystal display device. The input image data is updated in the frame periods N, N + 1, N + 2,. Here, attention is focused on one of a plurality of input pixel data included in the input image data, which changes in the frame periods N and N + 4 with respect to the delay output of the delay circuit 11. In the frame period N in which it is detected that the input pixel data does not match the corresponding pixel data in the preceding frame period N-1, the source driver XD outputs the input pixel data and the delayed output of the delay circuit 11 in the first half of the frame period N. The pixel voltage set to the intermediate value corresponding to the interpolated result is output to the corresponding source line Y. This pixel voltage is supplied from the corresponding source line Y to the corresponding pixel electrode PE via the corresponding switching element W, and is applied to the pixel region of the liquid crystal layer 3 as a potential difference between the pixel electrode PE and the common electrode CE. Subsequently, the source driver XD outputs a pixel voltage set to a value corresponding to the input pixel data to the corresponding source line Y in the second half of the frame period N. This pixel voltage is supplied from the corresponding source line Y to the corresponding pixel electrode PE via the corresponding switching element W, and the potential difference between the pixel electrode PE and the common electrode CE is applied to the pixel region of the liquid crystal layer 3 as the liquid crystal driving voltage. That is, the pixel voltage rises to an intermediate value corresponding to the interpolation result in the first half of the frame period N, and further rises to a value corresponding to the input pixel data in the second half of the frame period N.

  On the other hand, in the frame period N + 1 in which it is detected that the input pixel data matches the corresponding pixel data in the preceding frame period N, the source driver XD corresponds to the input pixel data in each of the first half and the second half of the frame period N + 1. The pixel voltage set to the same value is output to the corresponding source line Y. This pixel voltage is supplied from the corresponding source line Y to the corresponding pixel electrode PE via the corresponding switching element W, and is applied to the pixel region of the liquid crystal layer 3 as a potential difference between the pixel electrode PE and the common electrode CE. In this example, the pixel voltage is set to the same value as that set in the second half of the frame period N in the first half and the second half of the level frame period N + 1. This value is continued until immediately before the frame period N + 4 in which the mismatch between the input pixel data and the preceding frame period pixel data is detected again. In the frame period N + 4, control similar to that in the frame period N is performed, and the pixel voltage falls to the intermediate value corresponding to the interpolation result in the first half and further falls to the value corresponding to the input pixel data in the second half.

  In this embodiment, in order to improve the visibility of a moving image that is deteriorated due to the visual influence of the observer, the pixel voltage is an intermediate corresponding to the result of interpolating the delayed output and the input pixel data as the output pixel data changes. Transition is made in steps from the value to the value corresponding to the input pixel data. Therefore, even in a liquid crystal display mode such as OCB having a high liquid crystal response speed, the change in pixel luminance is not steep, and the viewer's vision can follow the change in luminance, thereby improving the visibility of moving images. Specifically, the display image is improved to a smooth movement that does not get jerky. Further, since a black image frame as in the prior art in which all pixels are displayed in black is not required, the utilization efficiency of backlight light is improved. That is, a bright screen can be obtained without increasing the power consumption of the backlight power, and flickers that can occur when black image frames are inserted periodically can be prevented.

  As in the first embodiment, the number of divisions in one frame period is not limited to 2, and may be further increased. That is, the gate lines Y1 to Ym are driven twice or more in one frame period, and gradually become a value corresponding to the input pixel data in synchronization with the driving of the corresponding gate line Y in the frame period in which the input pixel data for each pixel changes. What is necessary is just to change a pixel voltage so that it may approach.

  Next, a liquid crystal display device according to a third embodiment of the present invention is described. This liquid crystal display device is configured similarly to the first embodiment except for the function of the arithmetic circuit 12 shown in FIG. For this reason, the description which overlaps with 1st Embodiment is simplified or abbreviate | omitted.

  Also in this liquid crystal display device, the gate driver YD sequentially selects a plurality of gate lines Y1 to Ym in each of the first half and the second half obtained by dividing one frame period into, for example, two under the control of the control signal CTY, and the pixel switching element W is selected. A scanning signal to be conducted is supplied to the selection gate line Y. As a result, the plurality of gate lines Y1 to Ym are driven twice in one frame period. The image data processing circuit 4 outputs a processing result, which is output pixel data for one row of pixels PX, for each horizontal scanning period, and the source driver XD converts these output pixel data into pixel voltages, respectively, and outputs a plurality of source lines. Output in parallel to X1 to Xn. The delay circuit 11 delays image data by one frame period. The arithmetic circuit 12 compares each input pixel data with the delay output of the delay circuit 11, and outputs output pixel data that changes in synchronization with the driving of the corresponding gate line Y when a mismatch is detected with respect to the input pixel data. When no mismatch is detected with respect to the input pixel data, output pixel data that does not change in synchronization with driving of the corresponding gate line Y is generated.

  When the input pixel data does not coincide with the delayed output of the delay circuit 11, the arithmetic circuit 12 sets pixel data for setting the pixel voltage to a black display value when the corresponding gate line is driven for the first time (the first half of one frame period). When the second corresponding gate line is driven (second half of one frame period), pixel data for setting the pixel voltage to a value corresponding to the input pixel data is output. This change in the output pixel data causes the pixel voltage to transition stepwise from a black display value to a value corresponding to the input pixel data. A specific difference from the first embodiment is that the arithmetic circuit 12 outputs pixel data for setting the pixel voltage to a black display value when the corresponding gate line is driven for the first time. This is effective when the arithmetic circuit 12 is applied to a liquid crystal display panel DP such as an OCB mode having a high liquid crystal response speed.

  Incidentally, when the input pixel data matches the delayed output of the delay circuit 11, the arithmetic circuit 12 sets the pixel voltage to a value corresponding to the input pixel data when the corresponding gate line is driven for the first time (the first half of one frame period). The pixel data for setting the pixel voltage to the value corresponding to the input pixel data is output when the corresponding gate line is driven for the second time (the second half of one frame period). Accordingly, the output pixel data does not change, and the pixel voltage is maintained at a value corresponding to the input pixel data.

  FIG. 6 shows a pixel driving operation of this liquid crystal display device. The input image data is updated in the frame periods N, N + 1, N + 2,. Here, attention is focused on one of a plurality of input pixel data included in the input image data, which changes in the frame periods N and N + 4 with respect to the delay output of the delay circuit 11. In the frame period N in which it is detected that this input pixel data does not match the corresponding pixel data in the preceding frame period N−1, the source driver XD sets the pixel voltage set to the black display value in the first half of the frame period N. Output to the corresponding source line Y. This pixel voltage is supplied from the corresponding source line Y to the corresponding pixel electrode PE via the corresponding switching element W, and is applied to the pixel region of the liquid crystal layer 3 as a potential difference between the pixel electrode PE and the common electrode CE. Subsequently, the source driver XD outputs a pixel voltage set to a value corresponding to the input pixel data to the corresponding source line Y in the second half of the frame period N. This pixel voltage is supplied from the corresponding source line Y to the corresponding pixel electrode PE via the corresponding switching element W, and the potential difference between the pixel electrode PE and the common electrode CE is applied to the pixel region of the liquid crystal layer 3 as the liquid crystal driving voltage. That is, the pixel voltage rises to a black display value in the first half of the frame period N and is maintained at a black display value corresponding to the input pixel data in the second half of the frame period N.

  On the other hand, in the frame period N + 1 in which it is detected that the input pixel data matches the corresponding pixel data in the preceding frame period N, the source driver XD corresponds to the input pixel data in each of the first half and the second half of the frame period N + 1. The pixel voltage set to the same value is output to the corresponding source line Y. This pixel voltage is supplied from the corresponding source line Y to the corresponding pixel electrode PE via the corresponding switching element W, and is applied to the pixel region of the liquid crystal layer 3 as a potential difference between the pixel electrode PE and the common electrode CE. In this example, the pixel voltage is set to the same value as that set in the second half of the frame period N in the first half and the second half of the level frame period N + 1. This value is continued until immediately before the frame period N + 4 in which the mismatch between the input pixel data and the preceding frame period pixel data is detected again. In the frame period N + 4, the same control as that in the frame period N is performed, and the pixel voltage becomes a black display value in the first half and further falls to a value corresponding to the input pixel data in the second half.

  In this embodiment, in order to improve the visibility of a moving image that is deteriorated due to the influence of the viewer's vision, the pixel voltage transitions from a value for black display to a value corresponding to the input pixel data as the output pixel data changes. To do. Even in this case, since the change in luminance of the pixels is effectively moderated, the visual perception of the observer can follow the change in pixel luminance, so that the moving image visibility can be improved. In addition, since only the pixels in which the input pixel data changes with respect to the input pixel data in the preceding frame period due to the movement of the image are temporarily displayed in black, a bright screen can be obtained with low power consumption. Flicker that may occur when a working frame is periodically inserted can be prevented. According to actual verification, the white screen became brighter and flicker was completely eliminated in the still image. Moreover, the power consumption of the backlight required for obtaining the same luminance is reduced.

  As in the first embodiment, the number of divisions in one frame period is not limited to 2, and may be further increased. In this case, the gate lines Y1 to Ym are driven twice or more in one frame period, and the difference between the input pixel data and the delayed output is synchronized with the driving of the corresponding gate line Y in the frame period in which the input pixel data for each pixel is changed. It is preferable that the pixel voltage is changed to a value corresponding to the input pixel data after the pixel voltage is set to a black display value for a duration that depends on.

  The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention.

  In the above-described embodiment, the display panel control circuit CNT is applied to the liquid crystal display panel DP. However, the display panel control circuit CNT may be applied to, for example, an organic EL display panel or other display panels.

1 is a diagram schematically illustrating a circuit configuration of a liquid crystal display device according to a first embodiment of the present invention. It is a figure which shows the circuit structure of the image data processing circuit shown in FIG. It is a figure for demonstrating the operation timing of the gate driver shown in FIG. FIG. 3 is a diagram illustrating an example of a pixel driving operation of the liquid crystal display device illustrated in FIG. 1. It is a figure which shows an example of the pixel drive operation | movement of the liquid crystal display device which concerns on 2nd Embodiment of this invention. It is a figure which shows an example of the pixel drive operation | movement of the liquid crystal display device which concerns on 3rd Embodiment of this invention. It is a figure for demonstrating the general conventional drive method. It is a figure for demonstrating the conventional drive method which performs overdrive. It is a figure for demonstrating the conventional drive method which inserts a black image frame.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Array substrate, 2 ... Opposite substrate, 3 ... Liquid crystal layer, 4 ... Image data processing circuit, 5 ... Controller, 11 ... Delay circuit, 12 ... Arithmetic circuit, CNT ... Display panel control circuit, DP ... Liquid crystal display panel, YD ... Gate driver, XD ... Source driver.

Claims (6)

A display panel control circuit for controlling a display panel in which a plurality of pixels are arranged in the vicinity of intersections of a plurality of gate lines and a plurality of source lines, wherein the plurality of pixels are updated at a predetermined update cycle. An image data processing circuit that processes image data composed of input pixel data, a gate driver that sequentially drives the plurality of gate lines at least twice for each input of the image data, and the gate driver A source driver that outputs a pixel voltage corresponding to a processing result of the image data processing circuit to each of the plurality of source lines while each gate line is driven, and a controller that controls operation timing of the gate driver and the source driver And the image data processing circuit outputs each of the input pixel data changed by the update. It is configured to convert output pixel data that changes in synchronization with the driving of the corresponding gate line, and to convert each of the input pixel data that does not change by the update into output pixel data that does not change in synchronization with the driving of the corresponding gate line. A display panel control circuit. The image data processing circuit compares the input pixel data with the delay output of the delay circuit by delaying the image data by one frame period equal to the predetermined update period, and detects a mismatch with the input pixel data. Output pixel data that changes in synchronization with the corresponding gate line drive, and output pixel data that does not change in sync with the corresponding gate line drive when no mismatch is detected in the input pixel data. A display panel control circuit comprising an arithmetic circuit for performing the operation. The arithmetic circuit is configured to transition the pixel voltage stepwise from a value exceeding a value corresponding to the input pixel data to a value corresponding to the input pixel data in accordance with a change in the output pixel data. The display panel control circuit according to claim 2, wherein: The arithmetic circuit gradually changes the pixel voltage from an intermediate value corresponding to a result obtained by interpolating the delayed output and the input pixel data to a value corresponding to the input pixel data as the output pixel data changes. The display panel control circuit according to claim 2, wherein the display panel control circuit is configured to make a transition. The arithmetic circuit is configured to transition the pixel voltage from a black display value to a value corresponding to the input pixel data in accordance with a change in the output pixel data. The display panel control circuit described. 6. The display panel control circuit according to claim 5, wherein a duration of the black display value depends on a difference between the delayed output and the input pixel data.

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