JP2006085009A - Display control circuit, display control method, and liquid crystal display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a contrast from varying due to change in the dimming signal, in blinking driving. <P>SOLUTION: A display control circuit is equipped with a vertical timing control circuit 11 which generates start signals STHA and STHB; panel-driving parts 13, YD, and XD which drive a plurality of OCB liquid crystal pixels PX sequentially, in units of prescribed number of lines under the control of the signal STHA to make pixels PX of a drive line hold a pixel voltage for gray-level display, and also drive pixels PX together, in units of prescribed number of lines under the control of the signal STHB to make pixels PX of the drive line hold a pixel voltage for black insertion; and light source driving parts 14, 15, and LD which drive a plurality of black light sources LD nearly in parallel with the line of the pixels PX. The light source driving parts 14, 15, and LD, in particular, are configured to make the operation of blinking a plurality of light sources BL start in sequence at a prescribed duty ratio corresponding to an external dimming signal DIM, in synchronism with the signal STHA; and at least one of the generation timing of the signal STHB and the voltage level of the pixel voltage for black insertion is adjusted so as to compensate for the variations in contrast due to the alteration of the dimming signal DIMI. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display control circuit, a display control method, and a liquid crystal display device suitable for moving image display using, for example, an OCB (Optically Compensated Birefringence) mode liquid crystal display panel.

  A flat display device typified by a liquid crystal display device is widely used as a display device such as a computer, a car navigation system, or a television receiver.

  A liquid crystal display device generally includes a liquid crystal display panel including a matrix array of a plurality of liquid crystal pixels, a backlight that illuminates the liquid crystal display panel, and a display control circuit that controls the display panel and the backlight. The liquid crystal display panel has a structure in which a liquid crystal layer is sandwiched between an array substrate and a counter substrate.

The array substrate has a plurality of pixel electrodes arranged in a substantially matrix, a plurality of gate lines arranged along a row of the plurality of pixel electrodes, a plurality of source lines arranged along a column of the plurality of pixel electrodes, and a plurality of And a plurality of switching elements arranged in the vicinity of the intersection position of the plurality of gate lines and the plurality of source lines. Each switching element is made of, for example, a thin film transistor (TFT), and conducts when one gate line is driven to apply the potential of one source line to one pixel electrode. A common electrode is provided on the counter substrate so as to face a plurality of pixel electrodes arranged on the array substrate. The pair of pixel electrodes and the common electrode constitute a pixel together with a pixel region which is a part of the liquid crystal layer located between these electrodes, and the liquid crystal molecular arrangement is controlled by the electric field between the pixel electrode and the common electrode in the pixel region. The display control circuit includes a gate driver that drives a plurality of gate lines, a source driver that drives a plurality of source lines, and a controller circuit that controls these gate drivers, source drivers, and backlights.
In the case where the liquid crystal display device is mainly used for a television receiver that displays a moving image, use of an OCB mode liquid crystal display panel in which liquid crystal molecules exhibit good responsiveness has been studied (see Patent Document 1). In this liquid crystal display panel, the OCB liquid crystal is in a spray alignment almost lying down before power-on by an alignment film rubbed in parallel with each other on the pixel electrode and the common electrode. The liquid crystal display panel performs a display operation after the OCB liquid crystal is changed from the spray alignment to the bend alignment by a relatively strong electric field applied in the initialization process when the power is turned on.

  The reason why the OCB liquid crystal is in the spray orientation before the power is turned on is that the spray orientation is more stable in energy than the bend orientation in a state where no liquid crystal driving voltage is applied. Even if such OCB liquid crystal transitions to bend alignment once, it reverses again to spray alignment when the voltage application state below the level where the energy of spray alignment and the energy of bend alignment antagonize or when no voltage application state continues for a long time. It has the property of moving. In the spray orientation, the viewing angle characteristic is greatly different from that of the bend orientation, resulting in abnormal display.

  Conventionally, in order to prevent a reverse transition from bend alignment to spray alignment, for example, a driving method in which a large voltage is applied to the OCB liquid crystal in a part of a frame period for displaying an image of one frame is employed. In a normally white liquid crystal display panel, since this voltage corresponds to a pixel voltage for black display, this is called black insertion driving.

The black insertion pixel voltage and the gradation display pixel voltage are applied to all the liquid crystal pixels in a row unit in one frame period, that is, one vertical scanning period (V). Here, the ratio of the black insertion pixel voltage holding period to the gradation display pixel voltage holding period is the black insertion ratio. When each gate line is driven for black insertion for half of one horizontal scanning period (H), that is, H / 2 period, and is further driven for gradation display only for H / 2 period, the vertical scanning speed is black insertion. The speed is doubled compared to the case where no operation is performed. Also, since the black insertion pixel voltage is a common value for all pixels or pixel columns of the same color, for example, two gate lines can be driven together as one set. When the two gate lines of each set are driven together for 2H / 3 periods for black insertion and sequentially driven for 2H / 3 periods for 4H / 3 periods for gradation display, the vertical scanning speed is black insertion. The speed is 1.5 times that in the case where the operation is not performed.
JP 2002-202491 A

  By the way, since the liquid crystal display panel is a hold type display device that holds the display state until the image data is updated, it is difficult to smoothly show the movement of the object due to the influence of the retinal afterimage generated in the observer's vision in moving image display. The above-described black insertion drive is effective in improving the visibility of the moving image, which is deteriorated by the observer's vision, because the retinal afterimage is cleared by changing the pixel luminance to a pseudo discrete impulse response waveform. However, the black display state obtained by the black insertion drive is not completely black as obtained when the backlight is turned off. For this reason, it has been studied to obtain better moving image visibility using blinking driving in which the backlight blinks.

  When the backlight is blinking driven, the duty ratio of the backlight, that is, the ratio of the lighting period to the blinking period which is usually one vertical scanning period, determines the brightness of the entire liquid crystal display panel as a dimming signal from an external signal source. It is possible to adjust correspondingly.

  However, if the brightness of the entire liquid crystal display panel is controlled mainly by the duty ratio of the backlight, when the duty ratio is decreased by changing the dimming signal, the backlight extinction period is increased and the contrast is increased. Become. This increase in contrast is preferable, but when the backlight duty ratio is increased from this state, it results in impressing the observer on the decrease in contrast.

  An object of the present invention is to provide a display control circuit, a display control method, and a liquid crystal display device that can prevent a change in contrast due to a change in a dimming signal from the outside in blinking driving of a backlight.

  According to a first aspect of the present invention, there is provided a display control circuit for a display panel in which a plurality of OCB liquid crystal pixels are arranged in a substantially matrix shape, and a timing control circuit for generating a gradation display start signal and a black insertion start signal; The OCB liquid crystal pixels are sequentially driven in units of a predetermined number of rows by controlling the grayscale display start signal, and the OCB liquid crystal pixels in the drive row are held with the grayscale display pixel voltage, and the plurality of OCB liquid crystal pixels are controlled by controlling the black insertion start signal. A panel driving unit that drives the OCB liquid crystal pixels together in units of a predetermined number of rows to hold the pixel voltage for black insertion in the OCB liquid crystal pixels of the driving row, and a plurality of backs arranged substantially parallel to the rows of the plurality of OCB liquid crystal pixels A light source drive unit that drives the light source, and the light source drive unit uses a grayscale display start signal as an operation for sequentially flashing a plurality of backlight light sources at a predetermined duty ratio corresponding to a dimming signal from the outside. A display control circuit configured to start at a time, and at least one of a black insertion start signal generation timing and a black insertion pixel voltage voltage level is adjusted to compensate for a contrast variation due to a change of a dimming signal Provided.

  According to a second aspect of the present invention, there is provided a display control method for a display panel in which a plurality of OCB liquid crystal pixels are arranged in a substantially matrix shape, wherein a gradation display start signal and a black insertion start signal are generated, and gradation display is performed. By controlling the start signal, the plurality of OCB liquid crystal pixels are sequentially driven in units of a predetermined number of rows so that the OCB liquid crystal pixels in the drive row hold the gradation display pixel voltage, and by controlling the black insertion start signal, the plurality of OCB liquid crystal pixels are controlled. A plurality of backlight light sources arranged in parallel with a plurality of liquid crystal pixel rows are controlled by an external dimming signal by driving the OCB liquid crystal pixels of the driving row together in a predetermined number of rows to hold the pixel voltage for black insertion. The operation of sequentially blinking at a predetermined duty ratio corresponding to the signal is started in synchronization with the gradation display start signal, and at least one of the generation timing of the black insertion start signal and the voltage level of the black insertion pixel voltage is the dimming signal. Display control method to be adjusted is provided to compensate for variations in the further by contrast.

  According to the third aspect of the present invention, a display panel in which a plurality of OCB liquid crystal pixels are arranged in a substantially matrix shape, a timing control circuit for generating a gradation display start signal and a black insertion start signal, and a gradation display start signal The OCB liquid crystal pixels are sequentially driven in units of a predetermined number of rows by controlling the number of pixels so that the OCB liquid crystal pixels in the driving row hold the gradation display pixel voltage, and the plurality of OCB liquid crystal pixels are controlled by predetermined black lines by controlling the black insertion start signal. A panel drive unit that drives the OCB liquid crystal pixels in the drive row to hold the pixel voltage for black insertion by driving several units together, and a light source that drives a plurality of backlight light sources arranged substantially parallel to the row of the plurality of OCB liquid crystal pixels And a light source driving unit that sequentially starts blinking a plurality of backlight light sources at a predetermined duty ratio corresponding to a dimming signal from the outside in synchronization with a gradation display start signal. Is configured, the liquid crystal display device is provided which is adjusted to compensate for variations in the contrast due to changes in at least one of the dimmer signal voltage level of the generation timing and the black insertion pixel voltage in the black insertion start signal.

  In the display control circuit, the display control method, and the liquid crystal display device, at least one of the black insertion start signal generation timing and the black insertion pixel voltage voltage level is adjusted so as to compensate for the contrast variation due to the change of the dimming signal. Is done. If the turn-off period of each backlight light source is increased by changing the dimming signal, this increases the contrast of the entire liquid crystal display panel. On the other hand, when the generation timing of the black insertion start signal is adjusted, the start of holding the black insertion pixel voltage for the OCB liquid crystal pixels in the drive row is made earlier than the corresponding backlight light source is turned off, and the black insertion pixel voltage In the period from the start of holding until the backlight light source is turned off, the pixel luminance can be shifted to a brighter value than the backlight light source is turned off. In addition, when the voltage level of the black insertion pixel voltage is adjusted, the pixel brightness is adjusted for the period from the lighting of the backlight light source to the liquid crystal response and the period from the start of holding the black insertion pixel voltage to the extinguishing of the backlight light source. It is possible to maintain a state shifted to a brighter value compared to the unlit state. Therefore, the contrast can be kept constant even if the external dimming signal is changed in the backlight blinking drive. Furthermore, if the voltage level of the black insertion pixel voltage is set to a different reduction amount for each pixel color of the OCB liquid crystal pixel in the drive row, it is possible to prevent not only contrast variation but also color balance loss.

  Hereinafter, a liquid crystal display device according to an embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 schematically shows a circuit configuration of the liquid crystal display device. The liquid crystal display device includes a liquid crystal display panel DP, a backlight BL that illuminates the display panel DP, and a display control circuit CNT that controls the display panel DP and the backlight BL. The liquid crystal display panel DP has a structure in which a liquid crystal layer 3 is sandwiched between an array substrate 1 and a counter substrate 2 which are a pair of electrode substrates. For example, the liquid crystal layer 3 is an OCB liquid crystal that is previously transitioned from spray alignment to bend alignment for a normally white display operation, and reverse transition from bend alignment to spray alignment is periodically applied and blocked by a voltage that causes black display. Including as a liquid crystal material. The display control circuit CNT controls the transmittance of the liquid crystal display panel DP by the liquid crystal driving voltage applied from the array substrate 1 and the counter substrate 2 to the liquid crystal layer 3. The transition from the spray alignment to the bend alignment is obtained by applying a relatively large electric field to the OCB liquid crystal in a predetermined initialization process performed by the display control circuit CNT when the power is turned on.

  The array substrate 1 includes a plurality of pixel electrodes PE arranged in a substantially matrix on a transparent insulating substrate such as glass, and a plurality of gate lines Y (Y1 to Ym) arranged along a row of the plurality of pixel electrodes PE. , A plurality of source lines X (X1 to Xn) arranged along a column of the plurality of pixel electrodes PE, and the gate lines Y and the source lines X arranged in the vicinity of the intersection positions and driven through the corresponding gate lines Y, respectively. In this case, the corresponding source line X and the corresponding pixel electrode PE are conducted to have a plurality of pixel switching elements W. Each pixel switching element W is made of, for example, a thin film transistor, the gate of the thin film transistor is connected to the gate line Y, and the source-drain path is connected between the source line X and the pixel electrode PE.

  The counter substrate 2 is disposed on a transparent insulating substrate such as glass, for example, and is formed with a color filter composed of red, green, and blue colored layers formed as stripes facing the pixel electrodes PE in the corresponding columns, and a plurality of pixel electrodes PE. A common electrode CE and the like disposed on the color filter so as to face each other is included. Each pixel electrode PE and common electrode CE are made of a transparent electrode material such as ITO, for example, and are covered with alignment films that are rubbed in parallel to each other, and have a liquid crystal molecular arrangement corresponding to the electric field from the pixel electrode PE and common electrode CE. An OCB liquid crystal pixel PX is formed together with a pixel region which is a part of the liquid crystal layer 3 to be controlled.

  Each of the plurality of liquid crystal pixels PX has a liquid crystal capacitance CLC between the pixel electrode PE and the common electrode CE. The plurality of auxiliary capacitance lines C1 to Cm are each capacitively coupled to the pixel electrode PE of the liquid crystal pixel PX in the corresponding row to form an auxiliary capacitance Cs. The auxiliary capacitor Cs has a sufficiently large capacitance value with respect to the parasitic capacitance of the pixel switching element W.

  The display control circuit CNT includes a gate driver YD that sequentially drives the plurality of gate lines Y1 to Ym so that the plurality of switching elements W are conducted in units of rows, and a period in which the switching elements W in each row are conducted by driving the corresponding gate lines Y. , A source driver XD for outputting the pixel voltage Vs to the plurality of source lines X1 to Xn, a backlight driver LD for driving the backlight BL, a driving voltage generating circuit 4 for generating a driving voltage for the display panel DP, and A controller circuit 5 that controls the gate driver YD, the source driver XD, and the backlight driver LD is provided.

  The driving voltage generation circuit 4 generates a compensation voltage generation circuit 6 that generates a compensation voltage Ve applied to the auxiliary capacitance line C through the gate driver YD, and a predetermined number of gradation reference voltages VREF used by the source driver XD. And a common voltage generating circuit 8 for generating a common voltage Vcom applied to the counter electrode CT. The controller circuit 5 includes a vertical timing control circuit 11 that generates a control signal CTY for the gate driver YD based on a synchronization signal SYNC (VSYNC, DE) input from the external signal source SS, and a synchronization signal input from the external signal source SS. A horizontal timing control circuit 12 that generates a control signal CTX for the source driver XD based on SYNC (VSYNC, DE), and, for example, black insertion double speed conversion for image data input from the external signal source SS to a plurality of pixels PX. The image data conversion circuit 13 to be performed, the inverter control circuit 14 for controlling the backlight driver (inverter) LD based on the control signal CTX output from the vertical timing control circuit 11, and the dimming signal input from the external signal source SS Duty ratio detection to detect DIM duty ratio Including the circuit 15. The image data includes a plurality of pixel data DI for a plurality of liquid crystal pixels PX, and is updated every frame period (vertical scanning period V). The control signal CTY is supplied to the gate driver YD, and the control signal CTX is supplied to the source driver XD together with the pixel data DO obtained as a conversion result from the image data conversion circuit 13. The control signal CTY is used for the gate driver YD to sequentially drive the plurality of gate lines Y as described above, and the control signal CTX is obtained in units of liquid crystal pixels PX for one row as a conversion result of the image data conversion circuit 13. The pixel data DO output in series are assigned to a plurality of source lines X and used to specify the output polarity. The dimming signal DIM is a pulse width modulation signal that designates the brightness of the liquid crystal display panel DP by, for example, a duty ratio. The duty ratio detection circuit 15 is configured to detect the duty ratio of the dimming signal DIM and output a numerical value representing the duty ratio as a duty ratio detection result.

  The gate driver YD and the source driver XD are configured using, for example, a shift register circuit in order to select the plurality of gate lines Y and the plurality of source lines X, respectively. In this case, the control signal CTY includes a first start signal (gradation display start signal) STHA for controlling the gradation display start timing, a second start signal (black insertion start signal) STHB for controlling the black insertion start timing, and a shift register. A clock signal for shifting the start signals STHA and STHB in the circuit, and a drive signal to the gate lines Y1 to Ym that are sequentially or together selected by the shift register circuit corresponding to the holding positions of the start signals STHA and STHB Including an output enable signal for controlling the output of. On the other hand, the control signal CTX is generated by the shift register circuit corresponding to the start signal for controlling the start timing of taking in the pixel data DO for one row, the clock signal for shifting the start signal in the shift register circuit, and the holding position of the start signal. A load signal for controlling the parallel output timing of the pixel data DO for one row captured for each of the source lines X1 to Xn selected one by one, and a polarity for controlling the signal polarity of the pixel voltage Vs corresponding to the pixel data Including signals.

  The gate driver YD sequentially selects a plurality of gate lines Y1 to Ym for gradation display and black insertion in one frame period under the control of the control signal CTY, and conducts the pixel switching elements W in each row for one horizontal scanning period H. An ON voltage is supplied to the selection gate line Y as a drive signal. When the image data conversion circuit 13 performs the black insertion double speed conversion, one row of black insertion pixel data B and one row of gradations where the input pixel data DI of one row becomes the output pixel data DO every 1H. It is converted into display pixel data S. The gradation display pixel data S has the same gradation value as the pixel data DI, and the black insertion pixel data B has an independent black display gradation value for each pixel color of the liquid crystal pixel PX. The black insertion pixel data B for one row and the gradation display pixel data S for one row are each output in series from the image data conversion circuit 13 in the H / 2 period. The source driver XD refers to a predetermined number of gradation reference voltages VREF supplied from the gradation reference voltage generation circuit 7 to convert the pixel data B and S into pixel voltages Vs, respectively. Output to Xn in parallel.

  The pixel voltage Vs is a voltage applied to the pixel electrode PE on the basis of the common voltage Vcom of the common electrode CE, and the polarity is inverted with respect to the common voltage Vcom so as to perform, for example, frame inversion driving and line inversion driving. When black insertion driving is performed at the double vertical scanning speed, the polarity is inverted with respect to the common voltage Vcom so as to perform, for example, line inversion driving and frame inversion driving (1H1V inversion driving). The compensation voltage Ve is applied via the gate driver YD to the auxiliary capacitance line C corresponding to the gate line Y connected to the switching elements W when the switching elements W for one row are turned off. This is used to compensate for variations in the pixel voltage Vs generated in the pixels PX for one row due to the parasitic capacitance of the element W.

  When the gate driver YD drives, for example, the gate line Y1 with the on-voltage to make all the pixel switching elements W connected to the gate line Y1 conductive, the pixel voltage Vs on the source lines X1 to Xn is changed to these pixel switching elements W. To the corresponding pixel electrode PE and one end of the auxiliary capacitor Cs. Further, the gate driver YD outputs the compensation voltage Ve from the compensation voltage generation circuit 6 to the auxiliary capacitance line C1 corresponding to the gate line Y1, and applies all the pixel switching elements W connected to the gate line Y1 to one horizontal scanning period. Immediately after being turned on, an off voltage that makes these pixel switching elements W non-conductive is output to the gate line Y1. The compensation voltage Ve reduces the electric charge drawn from the pixel electrode PE by these parasitic capacitances when these pixel switching elements W become non-conductive, and substantially cancels the fluctuation of the pixel voltage Vs, that is, the punch-through voltage ΔVp.

  Here, the operation of the liquid crystal display device shown in FIG. 1 will be described with reference to FIGS. 2 and 3, B represents pixel data for black insertion common to the pixels PX in each row, and S1, S2, S3,... Correspond to the pixels PX in the first row, the second row, the third row,. Represents gradation display pixel data. +, − Represent the signal polarities when the pixel data B, S1, S2, S3... Are converted into the pixel voltage Vs and output from the source driver XD.

  FIG. 2 shows the operation of the liquid crystal display device when black insertion driving is performed at a double vertical scanning speed. Here, both the first start signal STHA and the second start signal STHB are pulses input to the gate driver YD with a pulse width corresponding to the H / 2 period. The first start signal STHA is input first, and the second start signal STHB is more than the first start signal STHA in accordance with the ratio of the black insertion pixel voltage holding period to the gray scale display pixel voltage holding period, that is, the black insertion rate. Input late.

  The gate driver YD shifts the first start signal STHA to select one of the plurality of gate lines Y1 to Ym per horizontal scanning period H, and drive signals to the gate lines Y1, Y2, Y3,... In the second half of the 1H period. Is output. On the other hand, the source driver XD converts each of the gradation display pixel data S1, S2, S3,... Into the pixel voltage Vs in the second half of the corresponding 1H period, and converts them into the source line X1 with the polarity inverted every 1H. Output in parallel to ~ Xn. These pixel voltages Vs are supplied to the liquid crystal pixels PX in the first row, the second row, the third row, the fourth row, etc. while each of the gate lines Y1 to Ym is driven in the second half of the corresponding 1H period.

  Further, the gate driver YD shifts the second start signal STHB to select a plurality of gate lines Y1 to Ym one by one per horizontal scanning period H, and to the gate lines Y1, Y2, Y3,... In the first half of the 1H period. A drive signal is output. On the other hand, the source driver XD converts each of the black insertion pixel data B, B, B,... Into the pixel voltage Vs in the first half of the corresponding 1H period, and converts them to the source lines X1 to X1 with the polarity inverted every 1H. Output in parallel to Xn. These pixel voltages Vs are supplied to the first, second, third,... Liquid crystal pixels PX while each of the gate lines Y1 to Ym is driven in the first half of the corresponding 1H period. In FIG. 2, the first start signal STHA and the second start signal STHB are input at a relatively short interval, but actually, the black insertion pixel voltage holding period for the gradation display pixel voltage holding period is set. The period ratios are input separately to match the black insertion rate. Also, black insertion for the pixels PX near the last row continues from the preceding frame as shown in the lower left part of FIG. 2, for example.

  In addition, when black insertion driving is performed at a 1.5 × vertical scanning speed, the image data conversion circuit 13 is configured to perform black insertion 1.5 × conversion on image data input from the external signal source SS. . Further, the source driver XD is configured to output to the source lines X1 to Xn a pixel voltage Vs whose polarity is inverted with respect to the common voltage Vcom so as to perform 2-line unit inversion driving and frame inversion driving (2H1V inversion driving). . In the black insertion 1.5 × speed conversion, the input pixel data DI for two rows becomes the output pixel data DO for every 2H period, the black insertion pixel data B for one row, and the gradation display pixel data S for two rows. Is converted to The gradation display pixel data S has the same gradation value as the pixel data DI, and the black insertion pixel data B has an independent black display gradation value for each pixel color of the liquid crystal pixel PX. The black insertion pixel data B for one row and the gradation display pixel data S for two rows are each output in series from the image data conversion circuit 13 in the 2H / 3 period.

  FIG. 3 shows the operation of the liquid crystal display device when black insertion driving is performed at a 1.5 × vertical scanning speed. Here, the first start signal STHA is a pulse input to the gate driver YD with a pulse width of 2H / 3 periods, and the second start signals STHB are all input to the gate driver YD with a pulse width of 2H periods. Pulse. The first start pulse STHA is input first, and the second start signal STHB is more than the first start signal STHA in accordance with the ratio of the gradation display pixel voltage holding period and the black insertion pixel voltage holding period, that is, the black insertion ratio. Input late.

  The gate driver YD shifts the first start signal STHA to sequentially select a plurality of gate lines Y1 to Ym by two per 2H period, and in the second and third 2H / 3 periods included in the corresponding 2H period. Are output to the selection gate lines Y1, Y2; Y3, Y4; On the other hand, the source driver XD converts the gradation display pixel data S1, S2; S3, S4;... Into the pixel voltage Vs in the second and third 2H / 3 periods included in the corresponding 2H period. Are output in parallel to the source lines X1 to Xn with the polarity inverted every 2H. These pixel voltages Vs are supplied to the first, second, third, and fourth rows while each of the gate lines Y1 to Ym is driven in the second or third 2H / 3 period included in the corresponding 2H period. Supplied to the liquid crystal pixels PX of the eyes,.

  Further, the gate driver YD shifts the second start signal STHB to select two of the plurality of gate lines Y1 to Ym together every 2H period, and selects these in the first 2H / 3 period included in the corresponding 2H period. A drive signal is output to the gate lines Y1, Y2; Y3, Y4; On the other hand, the source driver XD converts each of the black insertion pixel data B, B, B,... Into a pixel voltage Vs in the first 2H / 3 period included in the corresponding 2H period, and converts them into every 2H. Outputs in parallel to the source lines X1 to Xn with the inverted polarity. These pixel voltages Vs are applied to the first row, the second row, the third row, the fourth row, etc. while each of the gate lines Y1 to Ym is driven in the first 2H / 3 period included in the corresponding 2H period. To the liquid crystal pixel PX. In FIG. 3, the first start signal STHA and the second start signal STHB are input at a relatively short interval. In practice, however, the black insertion pixel voltage is held during the gradation display pixel voltage holding period. The period ratios are input separately to match the black insertion rate. Further, black insertion for the pixels PX near the last row continues from the preceding frame as shown in the lower left part of FIG. 3, for example.

  FIG. 4 shows the relationship between the backlight BL and the display panel DP shown in FIG. The display screen DS shown in FIG. 4 includes a plurality of OCB liquid crystal pixels PX arranged in a matrix. The backlight BL is composed of, for example, k backlight light sources BL1 to BLk arranged at a predetermined pitch in parallel with the rows of the plurality of OCB liquid crystal pixels PX on the back surface of the display panel DP. These backlight sources BL1 to BLk mainly illuminate a plurality of display areas in which the screen DS is equally divided in the vertical direction. Here, each of the backlight light sources BL1 to BKk is composed of one cold cathode tube, and illuminates one display area composed of about 30 rows of liquid crystal pixels PX.

  FIG. 5 shows in more detail the circuit configuration of the inverter control circuit 14, the backlight driver LD, and the backlight BL shown in FIG. 1, and FIG. 6 shows the lighting periods of the backlight sources BL1 to BKk corresponding to the liquid crystal pixels PX. The operation of the inverter control circuit 14 in the case where the grayscale display pixel voltage is made to coincide with the holding period is shown. The inverter control circuit 14 controls the backlight driver LD so as to start an operation of sequentially flashing the plurality of backlight light sources BL1 to BLk at a predetermined duty ratio in synchronization with the first start signal STHA. The backlight driving unit LD includes k inverters LD1 to LDk that generate driving voltages for the backlight light sources BL1 to BLk, respectively. The inverter control circuit 14 is illustrated in FIG. 5 in order to control the inverters LD1 to LDk, respectively. The k pulse width modulation signals PWM (PWM1 to PWMk) shown are generated.

  The pulse width modulation signal PWM1 is generated using the first start signal STHA output from the vertical timing control circuit 11 as the control signal CTX in the same manner as the second start signal STHB. The first start signal STHA is a reference timing for holding the gradation display pixel voltage in the first row of liquid crystal pixels PX, and the second start signal STHB is used for holding the black insertion pixel voltage in the first row of liquid crystal pixels PX. Reference timing. That is, the holding period of the gradation display pixel voltage is substantially equal to the period from the input of the first start signal STHA to the input of the second start signal STHB, and the holding period of the black insertion pixel voltage is a pulse of the second start signal STHB. The period from the input to the input of the next first start signal STHA is approximately equal.

  When the lighting periods of the backlight light sources BL1 to BKk are made to coincide with the holding periods of the gradation display pixel voltages by the corresponding liquid crystal pixels PX, the respective duty ratios of the backlight light sources BL1 to BLk are the gradation display pixel voltages. This is approximately equal to the ratio of the gradation display pixel voltage holding period to the total period of the holding period and the black insertion pixel voltage holding period. The inverter control circuit 14 detects the transition of the start signal STHA (that is, the leading edge or trailing edge of the pulse), raises the pulse width modulation signal PWM1 to a high level, and corresponds to the holding period of the gradation display pixel voltage from this rising edge. As the predetermined period elapses, the pulse width modulation signal PWM1 falls. Specifically, for example, a counter that counts clock pulses is provided, the clock pulse is counted from the transition timing of the start signal STHA, and the pulse width modulation signal PWM1 is lowered at a timing when a predetermined count value is reached.

  Thereby, the pulse width modulation signal PWM1 has a predetermined duty ratio corresponding to the ratio of the holding period of the gradation display pixel voltage to the total period of the holding period of the gradation display pixel voltage and the holding period of the black insertion pixel voltage. Will have. The pulse width modulation signals PWM2 to PWMk can be obtained by delaying the pulse width modulation signal PWM1, and are shifted by a phase difference T with respect to the pulse width modulation signals PWM1 to PWMk-1 as shown in FIG. This phase difference T is determined corresponding to the pitch of the backlight sources BL1 to BLk. The inverters LD1 to LDk convert the pulse width modulation signals PWM1 to PWMk from the inverter control circuit 14 into drive voltages, respectively, and output them to the backlight light sources BL1 to BLk. The backlight sources BL1 to BLk are turned on when the pulse width modulation signals PWM1 to PWMk are at a high level, and are turned off when the pulse width modulation signals PWM1 to PWMk are at a low level.

  The pulse width modulation signal PWM1 may be provided with a fixed offset time instead of transitioning simultaneously with the start signal STHA. In this case, the offset time is determined based on the number of rows of the liquid crystal pixels PX constituting each display area.

  Here, a method using a synchronization signal VSYNC, DE or the like supplied from the outside as a reference for the transition timing of the pulse width modulation signal PWM1 is also conceivable, but the method using the start signal STHA is more suitable for the backlight light sources BL1 to BLk. It is possible to obtain a high accuracy in superimposing the respective lighting periods and extinguishing periods on the gradation display pixel voltage holding period and the black insertion pixel voltage holding period of the liquid crystal pixel PX in the corresponding display region.

  6 schematically illustrates the case where the lighting periods of the backlight light sources BL1 to BKk are made to coincide with the holding periods of the gradation display pixel voltages by the corresponding liquid crystal pixels PX. However, the vertical timing control circuit shown in FIG. 11 and the image data conversion circuit 13 adjust the generation timing of the black insertion start signal and the voltage level of the black insertion pixel voltage so as to compensate for the contrast variation due to the change of the dimming signal DIM. This adjustment is performed corresponding to the duty ratio detection result output from the duty ratio detection circuit 15.

  The vertical timing control circuit 11 responds to the start of holding the pixel voltage for black insertion with respect to the OCB liquid crystal pixel PX in the driving row when the dimming signal DIM is changed to a reference value or less such as a duty ratio of 50%. The black insertion start signal STHB is generated at a timing earlier than the turn-off of BL1, BL2,. On the other hand, the image data conversion circuit 13 reduces the gradation value of the black insertion pixel data B for one row when the dimming signal DIM is changed to a reference value or less such as a duty ratio of 20%. It is configured to perform gamma correction. As shown in FIG. 7, the black insertion pixel data B for one row is composed of red pixel black insertion pixel data Br, green pixel black insertion pixel data Bg, and blue pixel black insertion pixel data Bb. The gradation values of the pixel data Br, Bg, and Bb are gamma-corrected with different reduction amounts in order to maintain color balance by gamma correction. As a result, the voltage level of the black insertion pixel voltage for the OCB liquid crystal pixel PX in the driving row is lowered, and the black insertion pixel voltage is set to a different amount for each pixel color of the OCB liquid crystal pixel PX in the driving row in order to maintain color balance. Set the voltage level.

  8 to 11 show the relationship between the backlight light source luminance and the pixel transmittance obtained when the duty ratio of the dimming signal is 50%, 40%, 30%, and 20%, respectively.

  As shown in FIG. 8, when the duty ratio of the dimming signal DIM is set to 50%, the generation timing of the start signal STHB is higher than the timing of turning off the backlight light source BL1, and the pixel voltage for insertion by the liquid crystal pixels PX in the corresponding row. Is generated so as to delay the holding start timing. In this case, the liquid crystal pixel PX is in a substantially complete black display state after the backlight light source BL1 is turned off. Therefore, the duty ratio of the backlight source BL1 becomes a dominant factor that determines the darkness of the liquid crystal pixel PX.

  As shown in FIG. 9, when the duty ratio of the dimming signal DIM is changed to 40%, the generation timing of the start signal STHB is the pixel voltage for black insertion by the liquid crystal pixel PX in the row corresponding to the extinction timing of the backlight light source BL1. Are generated so as to substantially match the holding start timing. In this case, the liquid crystal pixel PX becomes a black display state that is brighter than the complete black display state from the holding start timing of the black insertion pixel voltage, and is almost completely black display state after the backlight light source BL1 is turned off. Since the liquid crystal pixel PX has a shorter response time than the backlight light source BL1, the ratio of the black insertion pixel voltage holding period to the total period of the gradation display pixel voltage holding period and the black insertion pixel voltage holding period is It becomes a dominant factor that determines the darkness of the liquid crystal pixel PX only during the period until the backlight light source BL1 is completely turned off. Therefore, as shown in FIG. 8, the increase in contrast with respect to the decrease in the duty ratio of the dimming signal DIM can be mitigated as compared with the case where the duty ratio of the backlight source BL1 is the dominant factor that determines the darkness of the liquid crystal pixel PX.

  As shown in FIG. 10, when the duty ratio of the dimming signal DIM is changed to 30%, the generation timing of the start signal STHB advances the holding start timing of the black insertion pixel voltage earlier than the turn-off timing of the backlight light source BL1. Is generated as follows. In this case, the liquid crystal pixel PX becomes a black display state that is brighter than the complete black display state from the holding start timing of the black insertion pixel voltage, and is almost completely black display state after the backlight light source BL1 is turned off. Accordingly, the ratio of the black insertion pixel voltage holding period to the total period of the gradation display pixel voltage holding period and the black insertion pixel voltage holding period is longer than that shown in FIG. It becomes the dominant factor that determines the degree. Here, the black display state brighter than the complete black display state is longer than that shown in FIG. 9, and the increase in contrast with respect to the decrease in the duty ratio of the dimming signal DIM can be further alleviated.

  As shown in FIG. 11, when the duty ratio of the dimming signal DIM is changed to 20%, the generation timing of the start signal STHB is the same as that shown in FIG. It is generated so as to be earlier than the turn-off timing of the light source BL1. Also, the voltage level of the black insertion pixel voltage is adjusted to be high. In this case, the liquid crystal pixel PX further has a period from the lighting timing of the backlight light source BL1 to the liquid crystal response and a period from the start timing of holding the black insertion pixel voltage to the extinguishing timing of the backlight light source BL1 as compared with a complete black display state. The display is shifted to a bright black display state, and the display is almost completely black after the backlight light source BL1 is turned off. Accordingly, the ratio of the black insertion pixel voltage holding period to the total period of the grayscale display pixel voltage holding period and the black insertion pixel voltage holding period and the voltage level of the black insertion pixel voltage are the darkness of the liquid crystal pixel PX. It becomes the dominant factor that determines the degree. Here, since a brighter black display state than in the case shown in FIG. 10 continues in the same manner as in FIG. 10, an increase in contrast with respect to a decrease in the duty ratio of the dimming signal DIM can be further alleviated.

  In the liquid crystal display device of the present embodiment, the generation timing of the black insertion start signal and the voltage level of the black insertion pixel voltage are adjusted so as to compensate for contrast variation due to the change of the dimming signal. When the turn-off period of each backlight light source BL1, BL2,... Increases due to the change of the dimming signal DIM, this increases the contrast of the entire liquid crystal display panel DP. On the other hand, when the generation timing of the black insertion start signal is adjusted, the start of holding the black insertion pixel voltage for the OCB liquid crystal pixel PX in the driving row is made earlier than the corresponding backlight light source is turned off, and the black insertion pixel voltage is set. In the period from the start of holding the backlight sources BL1, BL2,..., The pixel luminance can be shifted to a brighter value than the backlight sources BL1, BL2,. . Further, when the voltage level of the black insertion pixel voltage is adjusted, the backlight light sources BL1, BL2,... Are turned off from the lighting of the backlight light sources BL1, BL2,. It is possible to maintain the pixel brightness shifted to a brighter value than the backlight light sources BL1, BL2,. Therefore, the contrast can be kept constant even when the external dimming signal DIM is changed in the blinking drive of the backlight BL. Furthermore, since the voltage level of the pixel voltage for black insertion is set to a different reduction amount for each pixel color of the OCB liquid crystal pixel PX in the drive row, it is possible to prevent not only the contrast variation but also the color balance from being lost. It is.

  In addition, this invention is not limited to the above-mentioned embodiment, It can deform | transform variously in the range which does not deviate from the summary.

  For example, in the above-described embodiment, the black insertion start signal STHB is generated at a timing that starts holding the pixel voltage for black insertion with respect to the OCB liquid crystal pixel PX in the drive row earlier than the turn-off of the corresponding backlight light sources BL1, BL2,. Although the duty ratio of the dimming signal DIM is set to 50% as the reference value, this reference value is not limited to the duty ratio of 50% and can be corrected to a value that matches the characteristics of the individual liquid crystal display panel DP. In addition, the duty ratio of the dimming signal DIM is set to 20% as a reference value for performing gamma correction that reduces the gradation value of the black insertion pixel data B for one row. The ratio is not limited to 20% and can be corrected to a value suitable for the characteristics of the individual liquid crystal display panel DP.

  Further, in the above-described embodiment, both the generation timing of the black insertion start signal and the voltage level of the black insertion pixel voltage are adjusted so as to compensate for the contrast variation due to the change of the dimming signal DIM. Modified as shown in FIG. 12 or FIG. 13 to adjust only one of the black insertion start signal generation timing and the black insertion pixel voltage voltage level to compensate for the contrast variation due to the change of the dimming signal DIM. Also good.

It is a figure which shows schematically the circuit structure of the liquid crystal display device which concerns on one Embodiment of this invention. 2 is a time chart showing the operation of the liquid crystal display device shown in FIG. 1 when black insertion driving is performed at a double scanning speed. 2 is a time chart showing the operation of the liquid crystal display device shown in FIG. 1 when black insertion driving is performed at a 1.5 × vertical scanning speed. It is a figure which shows the relationship between the backlight shown in FIG. 1, and a liquid crystal display panel. It is a figure which shows the circuit structure of the inverter control circuit, backlight drive part, and backlight which are shown in FIG. 1 in detail. 6 is a time chart showing the operation of the inverter control circuit shown in FIG. It is a figure which shows that the pixel data for 1 row of black insertion supplied to the source driver shown in FIG. 1 differ for every pixel color of an OCB liquid crystal pixel. It is a figure which shows the relationship between the backlight light source brightness | luminance and pixel transmittance | permeability obtained when the duty ratio of the light control signal shown in FIG. 1 is 50%. It is a figure which shows the relationship between the backlight light source brightness | luminance obtained when the duty ratio of the light control signal shown in FIG. 1 is 40%, and pixel transmittance | permeability. It is a figure which shows the relationship between the backlight light source brightness | luminance and pixel transmittance | permeability obtained when the duty ratio of the light control signal shown in FIG. 1 is 30%. It is a figure which shows the relationship between the backlight light source brightness | luminance and pixel transmittance | permeability obtained when the duty ratio of the light control signal shown in FIG. 1 is 20%. FIG. 6 is a diagram showing a first modification of the controller circuit shown in FIG. 1. FIG. 10 is a diagram showing a second modification of the controller circuit shown in FIG. 1.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Array substrate, 2 ... Opposite substrate, 3 ... Liquid crystal layer, 4 ... Drive voltage generation circuit, 5 ... Controller circuit, 6 ... Compensation voltage generation circuit, 7 ... Tone reference voltage generation circuit, 8 ... Common voltage generation circuit , 11 ... vertical timing control circuit, 12 ... horizontal timing control circuit, 13 ... image data conversion circuit, 14 ... inverter control circuit, 15 ... duty ratio detection circuit, BL ... backlight, BL1 to BLk ... backlight light source, DP ... Liquid crystal display panel, PE ... pixel electrode, CE ... common electrode, CLC ... liquid crystal capacitor, Cs ... auxiliary capacitor, PX ... liquid crystal pixel, W ... switching element, Y ... gate line, X ... source line, CNT ... display control circuit, LD: Backlight drive unit, LD1 to LDk: Inverter, YD: Gate driver, XD: Source driver.

Claims (6)

A display control circuit for a display panel in which a plurality of OCB liquid crystal pixels are arranged in a substantially matrix shape, and a timing control circuit for generating a gradation display start signal and a black insertion start signal, and control of the gradation display start signal The plurality of OCB liquid crystal pixels are sequentially driven in units of a predetermined number of rows so that the OCB liquid crystal pixels in the driving row hold the gradation display pixel voltage, and the plurality of OCB liquid crystal pixels are controlled to the predetermined rows by controlling the black insertion start signal. A panel driving unit that drives the OCB liquid crystal pixels in the driving row to hold the pixel voltage for black insertion by driving several units together, and a plurality of backlight light sources arranged substantially parallel to the row of the plurality of OCB liquid crystal pixels. A light source driving unit, wherein the light source driving unit sequentially starts blinking the plurality of backlight light sources at a predetermined duty ratio corresponding to a dimming signal from the outside. And at least one of the black insertion start signal generation timing and the black insertion pixel voltage level is adjusted to compensate for contrast variation due to the change of the dimming signal A display control circuit. When the dimming signal is changed to a reference value or less, the timing control circuit is configured to start the holding of the black insertion pixel voltage for the OCB liquid crystal pixels in the drive row earlier than the corresponding backlight light source is turned off. The display control circuit according to claim 1, wherein the display control circuit is configured to generate a black insertion start signal. The panel driving unit is configured to reduce a voltage level of the black insertion pixel voltage with respect to an OCB liquid crystal pixel in the driving row when the dimming signal is changed to a reference value or less. The display control circuit according to claim 1. 4. The display control circuit according to claim 3, wherein the voltage level of the black insertion pixel voltage is set to a different reduction amount for each pixel color of the OCB liquid crystal pixels in the drive row in order to maintain color balance. A display control method for a display panel in which a plurality of OCB liquid crystal pixels are arranged in a substantially matrix form, wherein a gradation display start signal and a black insertion start signal are generated, and the plurality of OCBs are controlled by controlling the gradation display start signal. The liquid crystal pixels are sequentially driven in a predetermined number of rows so that the OCB liquid crystal pixels in the driving row hold the gradation display pixel voltage, and the plurality of OCB liquid crystal pixels are combined together in the predetermined number of rows by controlling the black insertion start signal. To drive the OCB liquid crystal pixels in the drive row to hold the pixel voltage for black insertion, and a plurality of backlight light sources arranged substantially in parallel to the rows of the plurality of liquid crystal pixels have a predetermined duty corresponding to a dimming signal from the outside The operation of sequentially blinking at a ratio is started in synchronization with the gradation display start signal, and at least one of the generation timing of the black insertion start signal and the voltage level of the black insertion pixel voltage is Display control method, characterized in that it is adjusted to compensate for variations in the contrast due to the change of the optical signal. A display panel in which a plurality of OCB liquid crystal pixels are arranged in a substantially matrix form, a timing control circuit for generating a gradation display start signal and a black insertion start signal, and the plurality of OCB liquid crystal pixels by controlling the gradation display start signal Are sequentially driven in units of a predetermined number of rows so that the OCB liquid crystal pixels in the driving row hold the gradation display pixel voltage, and the plurality of OCB liquid crystal pixels are driven together in units of the predetermined number of rows by controlling the black insertion start signal. And a panel driving unit that holds the pixel voltage for black insertion in the OCB liquid crystal pixels in the driving row, and a light source driving unit that drives the plurality of backlight light sources arranged substantially parallel to the row of the plurality of OCB liquid crystal pixels. The light source driving unit starts an operation of sequentially flashing the plurality of backlight light sources at a predetermined duty ratio corresponding to a dimming signal from the outside in synchronization with the gradation display start signal. And at least one of the generation timing of the black insertion start signal and the voltage level of the black insertion pixel voltage is adjusted so as to compensate for contrast variation due to the change of the dimming signal. Liquid crystal display device.

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