KR20070025662A - Liquid crystal display device and method for driving the same - Google Patents

Abstract

A liquid crystal display device and a method for driving the same are provided to reduce power consumption by supplying black data to data lines in a non-display region and supplying a common voltage to a liquid crystal panel during a blank period. A blank control signal generator generates a blank control signal by using a vertical synchronous signal and a data enable signal. A data driver(106) supplies an analog voltage corresponding to predetermined black data during a blank period according to the blank control signal. A common voltage generator(116) supplies a common voltage of low level during the blank period according to the blank control signal. A liquid crystal panel(102) displays an image according to the difference between the analog voltage and the common voltage.

Description

Liquid crystal display device and method for driving the same

1 is a view showing a conventional liquid crystal display device.

FIG. 2 is a waveform diagram illustrating a control signal for controlling driving of the liquid crystal display of FIG. 1. FIG.

3 is a view showing a liquid crystal display device according to the present invention.

4A and 4B illustrate the black data controller of FIG. 3 in detail.

5 is a waveform diagram illustrating a control signal and a data voltage of the liquid crystal display of FIG. 3.

<Brief description of the main parts of the drawing>

102: liquid crystal panel 104: gate driver

106: data driver 108: timing controller

110: system 112: black data output unit

113: blank control signal generator 114: black data controller

115: counter 116: common voltage generator

118: first common voltage generator 120: second common voltage generator

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof capable of reducing power consumption.

As the information society develops, the demand for display devices is increasing in various forms. In response to this, various flat panel display devices such as liquid crystal display (LCD), plasma display panel (PDP), and electro luminescent display (ELD) have been studied, and some of them have already been used as display devices in various devices.

Among them, LCD (hereinafter referred to as 'liquid crystal display device') is most widely used as a substitute for CRTs for mobile image display devices due to its excellent image quality, light weight, thinness, and low power consumption. In addition to mobile applications such as monitors of notebook computers, liquid crystal displays have been developed in various ways such as television monitors.

A liquid crystal display device displays an image using the optical anisotropy and polarization property of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and the image information can be expressed by changing the polarization state of light in the molecular arrangement direction of the liquid crystal by optical anisotropy.

1 is a view showing a conventional liquid crystal display device.

As shown in FIG. 1, a conventional liquid crystal display device includes a liquid crystal panel 2 for displaying a predetermined image, a gate driver 4 and a data driver 6 for driving the liquid crystal panel 2, A timing controller 8 for controlling the gate driver 4 and the data driver 6 and a system 10 for supplying a predetermined synchronization signal and data to the timing controller 8 and a common voltage Vcom are generated. The common voltage generator 12 is included.

Since the liquid crystal display is a well known technique, a detailed description thereof will be omitted.

In the liquid crystal panel 2, a plurality of gate lines GL0 to GLn and data lines DL1 to DLm are arranged, and a thin film transistor TFT which is a switching element is formed at an intersection thereof.

The gate driver 4 drives the gate lines GL0 to GLn according to the gate control signal generated from the timing controller 8.

The data driver 6 drives the data lines DL1 to DLm in accordance with a data control signal generated from the timing controller 8.

The timing controller 8 uses the vertical / horizontal synchronization signal (Vsync / Hsync), the data enable (DE) signal, and a predetermined clock signal supplied from the system 10 to receive the gate control signal and the data control signal. Create

The common voltage generator 12 generates a common voltage Vcom which is a DC voltage of a constant level and supplies the generated common voltage Vcom to the liquid crystal panel 2.

FIG. 2 is a waveform diagram illustrating a control signal for controlling driving of the liquid crystal display of FIG. 1.

As shown in FIGS. 1 and 2, the system 10 transmits the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable DE to the timing controller 8 as mentioned above. Signal and a predetermined clock signal. 2, the horizontal sync signal Hsync is omitted for convenience.

The vertical synchronization signal Vsync indicates a start and end of a frame, that is, a signal indicating one frame. The high section of the vertical synchronization signal Vsync means a section in which data in units of frames supplied from the system 10 are displayed on the liquid crystal panel 2. In addition, a low section of the vertical synchronization signal Vsync means a section for preparing data corresponding to the next frame.

The data enable signal DE is a signal for controlling the display of a predetermined image on the liquid crystal panel 2. That is, the high section of the data enable signal DE refers to a section in which one line of data is displayed on the liquid crystal panel 2.

In addition, a low section of the data enable signal DE refers to a section in which data for the next one line is prepared to be displayed on the liquid crystal panel 2. That is, data is not displayed on the liquid crystal panel 2 in a low section of the data enable DE signal.

As a result, the data enable signal DE is synchronized with the high section of the vertical synchronization signal Vsync to display a predetermined image on the liquid crystal panel 2.

Meanwhile, the low section of the vertical synchronization signal Vsync informs the boundary between the current frame and the next frame. In the low section of the vertical synchronization signal Vsync, the data enable signal DE does not generate a high section.

In this case, a blank (a period from a high drop of high to low of the last data enable DE of the current frame to a start of a high section of the first data enable DE of the next frame starts with a blank ( It is called a section.

The blank period also means a boundary between the current frame and the next frame. That is, the blank section means a section in which data corresponding to the current frame is displayed on the liquid crystal panel 2 and then data corresponding to the next frame is prepared before the next frame starts.

The system 10 prepares to supply the data corresponding to the next frame to the timing controller 8 during the blank period.

At the same time, the data driver 6 supplies the data voltage of the last line of the current frame to the data lines DL1 to DLm in the blank period. In this case, the data voltage is not displayed on the liquid crystal panel 2 in the blank period. The common voltage Vcom generated by the common voltage generator 12 is also supplied to the liquid crystal panel 2 in the blank period.

That is, in the blank period in which no data is displayed on the liquid crystal panel 2, the data driver 6 supplies the data voltage of the last line of the current frame to the data lines DL1 to DLm. . As the data driver 6 performs an operation of supplying the data voltage of the last line of the current frame and the common voltage Vcom in the blank period, power consumption of the liquid crystal display increases.

In addition, as the data driver 6 and the common voltage generator 12 continuously operate in the blank period, the heating temperature of the data driver 6 and the common voltage generator 12 increases. This causes problems such as causing malfunctions of the data driver 6 and the common voltage generator 12.

It is an object of the present invention to provide a liquid crystal display and a driving method thereof which can reduce power consumption by reducing the levels of data voltage and common voltage during a blank period.

The liquid crystal display according to the first embodiment of the present invention for achieving the above object is a means for generating a blank control signal using a vertical synchronization signal and a data enable signal, and predetermined during a blank period in accordance with the blank control signal. A data driver for supplying an analog voltage corresponding to the black data of It includes a liquid crystal panel to display.

A liquid crystal display according to a second embodiment of the present invention for achieving the above object is a means for generating a blank control signal by using the count number, and supplies a low level common voltage during the blank period in accordance with the blank control signal A common voltage generator, a data driver for supplying an analog voltage corresponding to predetermined black data during a blank period according to the blank control signal, and a liquid crystal panel configured to display an image according to a difference between the analog voltage and the common voltage. Include.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display device, the method including generating a blank control signal using a vertical synchronization signal and a data enable signal, and blank period according to the blank control signal. Supplying an analog voltage corresponding to a predetermined black data, supplying a low level common voltage during a blank period according to the blank control signal, and displaying an image according to a difference between the analog voltage and the common voltage. Steps.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display device, the method including generating a blank control signal using a count number, and applying predetermined black data during a blank period according to the blank control signal. Supplying a corresponding analog voltage, supplying a low level common voltage during a blank period according to the blank control signal, and displaying an image according to the difference between the analog voltage and the common voltage.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention.

3 is a view showing a liquid crystal display according to the present invention.

As shown in FIG. 3, the liquid crystal display of the present invention drives a liquid crystal panel 102 in which a plurality of gate lines GL0 to GLn and data lines DL1 to DLm are arranged, and drives the liquid crystal panel 102. The gate driver 104 and the data driver 106, the timing controller 108 controlling the gate driver 104 and the data driver 106, and the control signal and the RGB data. It includes a system 110 for supplying the PDP, a common voltage generator 116 for generating the first and second common voltages Vcom-1 and Vcom-2, and a black data controller 114 for controlling the black data. .

A plurality of gate lines GL0 to GLn and data lines DL1 to DLm are arranged on the liquid crystal panel 102, and thin film transistors TFTs, which are switching elements, are formed at the intersections thereof. The liquid crystal panel 102 includes two glass substrates (not shown) and liquid crystals injected onto the glass substrate.

The gate driver 104 sequentially supplies a scan signal, that is, a gate high voltage VGH, to the gate lines GL0 to GLn according to the gate control signal generated from the timing controller 108. When the gate high voltage VGH is supplied to the gate lines GL0 to GLn, the thin film transistor TFT is turned on, and the gate low voltage VGL is turned on to the gate lines GL0 to GLn. When supplied to GLn), the thin film transistor TFT is turned off.

The data driver 106 supplies a data voltage to the data lines DL1 to DLm when the thin film transistor TFT is turned on according to a data control signal generated from the timing controller 108. do. In addition, the data driver 106 has a built-in black data output unit 112 for generating black data having a gray level of zero.

The timing controller 108 uses the vertical / horizontal synchronization signal (Vsync / Hsync), the data enable (DE) signal, and a predetermined clock signal supplied from the system 110 to receive the gate control signal and the data control signal. Create The timing controller 108 also arranges and supplies the RGB data supplied from the system 110 to the data driver 106.

The system 110 supplies a vertical / horizontal synchronization signal (Vsync / Hsync) and a data enable (DE) signal to the timing controller 108 and the black data controller 114.

The common voltage generator 116 may include a first common voltage generator 118 for generating a first common voltage Vcom-1 and a second common voltage generator for generating a second common voltage Vcom-2. 120).

The common voltage generator 116 generates first and second common voltages Vcom-1 and Vcom-2 and supplies them to the liquid crystal panel 102. The first common voltage Vcom is higher than the second common voltage Vcom-2. The second common voltage Vcom-2 is equal to the ground voltage GND level.

As illustrated in FIG. 4A, the black data controller 114 uses the vertical synchronization signal Vsync and the data enable signal DE supplied from the system 110 to generate a high or low signal. Generate a signal. The generated high or low signal is supplied to the black data output unit 112 and the common voltage generator 116.

In detail, the vertical synchronization signal Vsync and the data enable signal DE are supplied to the blank control signal generator 113 embedded in the black data controller 114. The blank control signal generator 113 determines a blank section using the vertical synchronization signal Vsync and the data enable signal DE.

The blank control signal generator 113 determines the blank section to generate a high signal during the blank section, and a low signal during the section except for the blank section. Create

The high or low signal generated by the blank control signal generator 113 is supplied to the black data output unit 112 as mentioned above.

When the high signal is supplied from the blank control signal generator 113, the black data output unit 112 generates black data having a gray level of 0 to generate a DAC (not shown) of the data driver 106. To supply. The black data is supplied to the DAC, converted into an analog voltage, and supplied to the data lines DL1 to DLm. That is, the black data output unit 112 generates black data having a gray level of 0 during a blank period.

In addition, when the low signal is supplied from the blank control signal generator 113, the black data output unit 112 does not generate black data. That is, the black data output unit 112 does not generate black data during a section except for a blank section.

In addition, the high or low signal generated by the blank control signal generator 113 is supplied to the common voltage generator 116. When a high signal is supplied from the blank control signal generator 113, the common voltage generator 116 generates a second common voltage Vcom-2 and supplies it to the liquid crystal panel 102. When the low signal is supplied from the blank control signal generator 113, the common voltage generator 116 generates a first common voltage Vcom-1 and supplies it to the liquid crystal panel 102.

Meanwhile, as illustrated in FIG. 4B, the black data controller 114 includes the same blank control signal generator 113 as described above, and a counter 115 that counts a predetermined clock signal according to a model of the liquid crystal display. It can also be configured as).

The counter 115 counts a predetermined clock signal corresponding to the number of gate lines corresponding to the model of the liquid crystal display. That is, the counter 115 counts a predetermined clock signal in synchronization with the gate start pulse (GSP) signal. That is, the counter 115 counts the gate shift clock signal GSC in synchronization with the gate start pulse signal GSP.

For example, when the LCD is a 1024 * 768 model, 768 gate lines exist in a region where a predetermined image is displayed, and 38 extra gate lines exist in a non-display region where no image is displayed. The liquid crystal display has a total of 806 gate lines. As a result, the counter 115 generates 806 gate shift clock (GSC) signals and supplies them to the blank control signal generator 113.

The blank control signal generator 113 generates a low signal when the 1 st to 768 th gate shift clock GSC signal is supplied from the gate shift clock GSC signals supplied from the counter 115. . In addition, the blank control signal generator 113 generates a high signal when the 769th to 806th clock signals of the gate shift clock (GSC) signals supplied from the counter 115 are supplied.

The high or low signal generated by the blank control signal generator 113 is supplied to the common voltage generator 116. When a high signal is supplied from the blank control signal generator 113, the common voltage generator 116 generates a second common voltage Vcom-2 and supplies it to the liquid crystal panel 102. In addition, when a low signal is supplied from the blank control signal generator 113, the common voltage generator 116 generates a first common voltage Vcom-1 and supplies it to the liquid crystal panel 102. .

That is, during the blank period, the common voltage generator 116 generates the second common voltage Vcom-2 and supplies it to the liquid crystal panel 102, and during the period except for the blank period, One common voltage Vcom-1 is generated and supplied to the liquid crystal panel 102.

In addition, the high or low signal generated by the blank control signal generator 113 is supplied to the black data output unit 112 embedded in the data driver 106. When the high signal is supplied from the blank control signal generator 113, the black data output unit 112 outputs black data having a gray level of 0 to the DAC (not shown) of the data driver 106. Supply.

The black data output unit 112 does not generate the black data when a low signal is supplied from the blank control signal generator 113. That is, during the blank period, the black data output unit 112 outputs black data having a gray level of 0, and the black data output unit 112 does not output the black data during the period except for the blank period. Do not.

As a result, the high or low signal generated by the blank control signal generator 113 controls the black data output unit 112 and the common voltage generator 116. During the blank period, the black data output unit 112 outputs black data having a gray level of 0 and at the same time, the common voltage generator 116 generates the second common voltage Vcom-2.

During the period except for the blank period, the black data output unit 112 does not output the black data and at the same time, the common voltage generator 116 generates the first common voltage Vcom-1.

The second common voltage Vcom is the same voltage as the ground voltage GND and is lower than the first common voltage Vcom. The first common voltage Vcom is the same as a common voltage having a constant level generated in a conventional liquid crystal display. The first and second common voltages Vcom-1 and Vcom-2 output from the common voltage generator 116 are supplied to the liquid crystal panel 102 to serve as reference voltages.

5 is a waveform diagram illustrating a control signal, a data voltage, and a common voltage of the liquid crystal display of FIG. 3.

As shown in FIG. 5, the vertical sync signal Vsync and data enable DE signals supplied from the system 110 of FIG. 3 and the data voltage and common voltage generated from the data driver 106 of FIG. 3 are generated. The first and second common voltages Vcom-1 and Vcom-2 supplied from the negative portion 116 of FIG. 3 are shown.

The horizontal sync signal Hsync generated by the system 110 is omitted for convenience.

A section including a low section and a high section of the vertical synchronization signal Vsync means one frame. The data enable signal DE refers to a clock signal having a predetermined interval in synchronization with a high section of the vertical synchronization signal Vsync. The data enable signal DE does not have a high section in the blank section mentioned above. That is, the system 110 does not supply the data enable signal DE in the blank period.

In addition, the data voltage supplied from the data driver 106 is supplied to the data lines DL1 to DLm in synchronization with a high section of the data enable DE signal. The high section of the data enable DE signal is the same as the section in which the data voltage is supplied to the data lines DL1 to DLm arranged alternately on one horizontal line.

The image displayed on the liquid crystal panel 102 by the data voltage means that white and black gray levels are alternately displayed for a predetermined frame.

In the blank period, the data driver 106 supplies black data having a gray level of zero to the data lines DL1 to DLm arranged to cross the gate line located on the non-display area.

In addition, the first common voltage Vcom-1 generated by the common voltage generator 116 is supplied to the liquid crystal panel 102 of FIG. 3 in a section other than the blank period, and the common voltage generator The second common voltage Vcom-2 generated at 116 is supplied to the liquid crystal panel 102 in the blank period.

As a result, in the blank period, the data driver 106 supplies black data having a gray level of zero to the data lines DL1 to DLm arranged to cross the gate line positioned in the non-display area of the liquid crystal panel 102. The common voltage generator 116 supplies the second common voltage Vcom-2 to the liquid crystal panel 102.

Accordingly, the data driver 106 supplies black data having zero gray level to the data lines DL1 to DLm in the blank period, thereby outputting a low level data voltage instead of a high level voltage value. The power consumption can be reduced.

In addition, the common voltage generator 116 supplies the second common voltage Vcom-2, which is a low level, that is, a ground voltage GND, to the liquid crystal panel 102 in the blank period. It is possible to reduce the power consumption by outputting a common voltage of a low level rather than the common voltage of.

In the conventional LCD, the data voltage output in the high section of the last data enable (DE) signal of the current frame is output to the data lines DL1 to DLm during the blank section and at the same time constant. Since a common voltage Vcom having a voltage level is outputted, a power consumption problem increases.

When a data voltage having a high voltage level is output in the high section of the last data enable (DE) signal of the current frame, a data voltage having a high voltage level is output during the blank period. Since the data voltage output in the blank period is not displayed on the liquid crystal panel, only a loss of power consumption for outputting the data voltage is caused.

Also, by supplying the common voltage Vcom having a constant voltage level on the liquid crystal panel 102 during the blank period in which no image is displayed, only the power consumption loss of the liquid crystal display device is further caused.

The power consumption when the low level voltage, in particular, the voltage corresponding to zero gray scale is supplied on the liquid crystal panel 102 is reduced than the power consumption when the high level data voltage is supplied on the liquid crystal panel 102. . In addition, the power consumption when the second common voltage Vcom-2 corresponding to the ground voltage GND is supplied to the liquid crystal panel 102 may include the common voltage Vcom having a constant voltage level. It is less than the power consumption when supplying

As mentioned above, the liquid crystal display according to the present invention supplies black data having zero gray level and a common voltage Vcom corresponding to the ground voltage GND on the liquid crystal panel in a blank period, thereby providing power consumption. Can be reduced.

As described above, the liquid crystal display according to the present invention supplies black data having a gray level of zero to a data line arranged to intersect with a gate line positioned on a non-display area in a blank period, and at the same time a ground voltage ( By supplying a common voltage Vcom corresponding to GND on the liquid crystal panel, power consumption may be reduced.

Claims (14)

Means for generating a blank control signal using the vertical synchronization signal and the data enable signal; A data driver for supplying an analog voltage corresponding to predetermined black data during a blank period according to the blank control signal; A common voltage generator configured to supply a low level common voltage during a blank period according to the blank control signal; And And a liquid crystal panel which displays an image according to a difference between the analog voltage and the common voltage. Means for generating a blank control signal using the count number; A common voltage generator configured to supply a low level common voltage during a blank period according to the blank control signal; A data driver for supplying an analog voltage corresponding to predetermined black data during a blank period according to the blank control signal; And And a liquid crystal panel which displays an image according to a difference between the analog voltage and the common voltage. The method of claim 2, The means, A counter for counting in synchronization with a predetermined gate shift pulse signal; A blank control signal generator configured to determine a blank period according to the number of times counted by the counter and output a control signal according to the blank period; And And a black data output unit configured to output black data according to the control signal. The method of claim 3, And a frequency range corresponding to the blank period is set in advance in the blank control signal generator. The method according to claim 1 or 2, And the data driver supplies a normal RGB data voltage when the data driver is not in the blank period. The method according to claim 1 or 2, And the common voltage generator supplies a normal high level when the common voltage generator is not in the blank period. The method according to claim 1 or 2, And the low level common voltage is the same voltage as the ground voltage GND. The method according to claim 1 or 2, And the low level common voltage is lower than the high level common voltage. The method of claim 1, And wherein the blank period is determined by a data enable signal located before and after a low level of the vertical synchronization signal. Generating a blank control signal using the vertical synchronization signal and the data enable signal; Supplying an analog voltage corresponding to predetermined black data during a blank period according to the blank control signal; Supplying a low level common voltage during a blank period according to the blank control signal; And And displaying an image according to a difference between the analog voltage and the common voltage. Generating a blank control signal using the count number; Supplying an analog voltage corresponding to predetermined black data during a blank period according to the blank control signal; Supplying a low level common voltage during a blank period according to the blank control signal; And And displaying an image according to a difference between the analog voltage and the common voltage. The method according to claim 10 or 11, wherein The low level common voltage is the same as the ground voltage GND. The method according to claim 10 or 11, wherein And the low level common voltage is lower than the high level common voltage. The method of claim 10, And wherein the blank period is determined by a data enable signal located before and after a low level of the vertical synchronization signal.

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