KR20070014561A - Liquid crystal display device - Google Patents

Abstract

An LCD is provided to compensate for kickback voltage, thereby suppressing the badness of picture quality, such as flicker and afterimage, due to the kickback voltage, by supplying a first gate low voltage, and then supplying a second gate low voltage having a higher level than the first gate low voltage. An LCD panel(102) has pixels defined by plural gate lines and plural data lines. A gate driver(104) supplies a gate high voltage, a first gate low voltage, and a second gate low voltage to the gate lines of the LCD panel. A data driver(106) supplies a predetermined data voltage to the data lines of the LCD panel. The second gate low voltage has a higher level than the first gate low voltage. A kickback voltage generated when the gate high voltage is changed into the first gate low voltage is compensated by a voltage generated when the first gate low voltage is changed into the second gate low voltage.

Description

Liquid crystal display device

1 is a view showing a conventional liquid crystal display device.

2 is a waveform diagram illustrating a voltage applied to the liquid crystal display of FIG. 1.

3 is a view showing a liquid crystal display device according to the present invention.

4 is a detailed view of the gate driver of FIG.

5 illustrates an output waveform of the gate line of FIG. 3.

<Brief description of the main parts of the drawing>

102: liquid crystal panel 104: gate driver

105: Shift register 106: Data driver 1

107: logical product operation unit 108: timing controller

109: level shifter 110: first power supply

111: gate low voltage selector 112: second power supply

113: buffer part

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device which can improve image quality by compensating kickback voltage (Vp).

As information society develops, the demand for display devices is increasing in various forms. In response to this, various flat panel display devices such as liquid crystal display (LCD), plasma display panel (PDP), and electro luminescent display (ELD) have been studied, and some of them have already been used as display devices in various devices.

Among them, LCD (hereinafter referred to as 'liquid crystal display device') is most commonly used to replace CRTs for mobile image display devices due to its excellent image quality, light weight, thinness, and low power consumption. In addition to mobile applications such as notebook computers, various monitors have been developed.

A liquid crystal display device displays an image using the optical anisotropy and polarization property of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and the image information can be expressed by changing the polarization state of light in the molecular arrangement direction of the liquid crystal by optical anisotropy.

1 is a view showing a conventional liquid crystal display device.

As shown in FIG. 1, a conventional liquid crystal display device includes a liquid crystal panel 2 in which a plurality of gate lines GL0 to GLn and data lines DL1 to DLm are arranged to display a predetermined image, and the gate line. A gate driver 4 for supplying scan signals to GL0 to GLn, a data driver 6 for supplying a data voltage to the data lines DL1 to DLm, the gate driver 4 and a data driver 6 And a timing controller 8 for generating a control signal for controlling ().

In the liquid crystal panel 2, a plurality of gate lines GL0 to GLn and data lines DL1 to DLm are arranged, and a thin film transistor TFT which is a switching element is formed at an intersection thereof. In addition, a storage capacitor Cst is formed between the front gate line and the pixel electrode (not shown) connected to the thin film transistor TFT.

The storage capacitor Cst charges the data voltage supplied through the data lines DL1 to DLm.

Since the liquid crystal display is a well known technique, a detailed description thereof will be omitted.

The scan signals, that is, the gate high voltage VGH and the gate low voltage VGL, are supplied to the gate lines GL0 to GLn of the liquid crystal display configured in this manner. Here, the gate high voltage VGH is supplied during the horizontal period 1H corresponding to the gate lines GL0 to GLn, and the gate low voltage VGL is applied during the remaining period.

The gate high voltage VGH turns on the thin film transistor TFT on the liquid crystal panel 2 and the data during the period in which the thin film transistor TFT is turned on. The data voltage Vd supplied from the driver 6 is charged in the storage capacitor Cst.

When the gate high voltage VGH supplied to the gate lines GL0 to GLn is transitioned to the gate low voltage VGL, the thin film transistor TFT is turned off and at that moment is applied to the pixel electrode. As shown in FIG. 2, the charged data voltage Vd drops as much as the kickback voltage? Vp by the parasitic capacitance Cgs generated between the gate electrode and the source electrode of the thin film transistor TFT.

Signal distortion occurs in the scan signals supplied to the gate lines GL0 to GLn due to line resistance, and the kickback voltage Vp is generated due to distortion of the scan signals. Due to the kickback voltage Vp, flicker and residual images are generated in the image displayed on the liquid crystal panel 2, resulting in a problem of deterioration in image quality.

An object of the present invention is to provide a liquid crystal display device which can eliminate flicker and afterimage by compensating kickback voltage (Vp).

According to an exemplary embodiment of the present invention, a liquid crystal panel includes a liquid crystal panel in which pixels defined by a plurality of gate lines and data lines are arranged, and a gate high voltage and a first and second gate lines are provided to each gate line. And a gate driver for supplying a gate low voltage and a data driver for supplying a predetermined data voltage to a data line of the liquid crystal panel, wherein the second gate low voltage is at least higher than the first gate low voltage.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention.

3 is a view showing a liquid crystal display according to the present invention.

As shown in FIG. 3, the liquid crystal display device displays a predetermined image and includes a liquid crystal panel 102 in which a plurality of gate lines GL0 to GLn and data lines DL1 to DLm are arranged, and the liquid crystal panel ( A gate driver 104 and a data driver 106 for driving 102 and a timing controller 108 for controlling the gate driver 104 and the data driver 106 are included.

The liquid crystal display device is configured to generate a driving voltage, a gate high voltage VGH, and a first gate low voltage VGL-1 driving the timing controller 108, the data driver 106, and the gate driver 104. The apparatus further includes a first power supply 110 and a second power supply 112 that generates the second gate low voltage VGL-2.

A plurality of gate lines GL0 to GLn and data lines DL1 to DLm are arranged in the liquid crystal panel 102, and thin film transistors are formed at intersections of the gate lines GL0 to GLn and data lines DL1 to DLm. TFT) is formed.

The thin film transistor TFT is turned on due to the gate high voltage VGH supplied from the gate driver 104 and the first and second gate low voltages VGL-1 and VGL-2. This is turned off.

The first power supply 110 generates a driving voltage for driving the timing controller 108, the data driver 106, and the gate driver 104 using an input voltage supplied from a system (not shown). In addition, the first power supply 110 generates and supplies a gate high voltage VGH and a first gate low voltage VGL-1 to the gate driver 104.

The second power supply 112 generates a second gate low voltage VGL-2 that is different from the first gate low voltage VGL-1 and supplies the same to the gate driver 104. In this case, the second gate low voltage VGL-2 has at least a voltage higher than the first gate low voltage VGL-1.

The gate high voltage VGH, the first gate low voltage VGL-1, and the second gate low voltage VGL-2 are continuously supplied to each gate line GL0 to GLn at regular intervals.

That is, the thin film transistor TFT connected to the gate lines GL0 to GLn is turned on by the gate high voltage VGH supplied to the gate lines GL0 to GLn. In this case, a predetermined data voltage Vd supplied through the data lines DL1 to DLm is applied to the pixel electrode (not shown) via the thin film transistor TFT.

The gate high voltage VGH is supplied to the gate lines GL0 to GLn during one horizontal section 1H. After the first horizontal section 1H, a first gate low voltage VGL-1 is supplied to the gate lines GL0 to GLn, and accordingly, a thin film transistor TFT connected to the gate lines GL0 to GLn. Is turned off.

Therefore, the data voltage Vd supplied through the data lines DL1 to DLm is blocked by the thin film transistor TFT and is no longer applied to the pixel electrode (not shown).

At this time, the transition from the gate high voltage VGH to the first gate low voltage VGL-1 affects the parasitic capacitance Cgs, thereby causing a kickback voltage Vp. Accordingly, the pixel electrode (not shown) is charged with a voltage lowered by the kickback voltage Vp from the actual data voltage Vd.

In the present invention, the first gate low voltage VGL-1 is applied to a high voltage higher than this voltage to compensate for the kickback voltage Vp.

That is, the second gate low voltage VGL-2 which is at least higher than the first gate low voltage VGL-1 is supplied to the gate lines GL0 to GLn. Accordingly, as the voltage transitions from the first gate low voltage VGL-1 having the low voltage to the second gate low voltage VGL-2 having the high voltage, the voltage increases by a predetermined voltage.

Accordingly, as the voltage of the kickback voltage qVp decreased as the voltage transitions from the gate high voltage VGH to the first gate low voltage VGL-1, the decrease of the kickback voltage qVp is increased by the increased voltage. As much as possible, flicker and afterimages can be eliminated.

Details of the first and second gate low voltages VGL-1 and VGL-2 are as follows.

The thin film transistor TFT is turned on when the gate high voltage VGH is supplied, and at the same time, the data voltage Vd is supplied from the data lines DL1 to DLm, thereby providing a pixel electrode (not shown). Is charged to the phase.

As soon as the gate high voltage VGH supplied to the thin film transistor TFT is changed to the first gate low voltage VGL-1, the data voltage Vd charged on the pixel electrode (not shown) is changed. do. The voltage drop charged on the pixel electrode (not shown) generates a voltage drop equal to the kickback voltage (Vp).

The kickback voltage Vp is generated when the gate high voltage VGH supplied to the thin film transistor TFT is changed to the first gate low voltage VGL-1. Therefore, the second gate low voltage VGL-2, which is greater than the first gate low voltage VGL-1, is supplied to the thin film transistor TFT to influence the data voltage Vd charged on the pixel electrode. To compensate for the kickback voltage (Vp).

That is, the data voltage Vd having the voltage drop equal to the kickback voltage VVp is interlocked at the moment when the data voltage Vd is changed from the first gate low voltage VGL-1 to the second gate low voltage VGL-2. This results in an effect of raising the predetermined voltage.

The timing controller 108 generates a predetermined control signal using a vertical / horizontal synchronization signal Vsync / Hsync supplied from a system (not shown), a predetermined clock signal, and a data enable signal DE. The predetermined control signal is supplied to the gate driver 104 and the data driver 106 to control the gate driver 104 and the data driver 106.

The gate driver 104 receives the gate high voltage VGH and the first and second gate low voltages VGL-1 and VGL-2 from the first and second power supply units 110 and 112. The gate high voltage VGH and the first and second gate low voltages VGL-1 and VGL-2 are supplied to the gate lines GL0 to GLn.

As illustrated in FIG. 4, the gate driver 104 includes a shift register 105 and an AND operation unit 107 that logically operates an output signal and a gate output enable signal of the shift register 105. And a level shifter 109 for selecting gate high voltage VGH and first and second gate low voltages VGL-1 and VGL-2 according to the output signal of the AND product 107. And a buffer unit 113 for supplying the output voltage supplied from the shifter 109 to the gate lines GL0 to GLn.

The shifter register 105 outputs a high or low signal according to a gate start pulse (GSP) signal and a gate shift clock (GSC) signal among the gate control signals supplied from the timing controller 108. do. The gate shift clock signal GSC is synchronized to a high section of the gate start pulse signal GSP.

The high or low signal output from the shift register 105 is supplied to the AND product 107.

The AND operation unit 107 combines the signal output from the shift register 105 with the gate output enable signal supplied from the timing controller 108 to generate a high or low signal. Output

When the signal output from the shift register 105 is high and the gate output enable signal is high, the AND product 107 outputs a high signal. . The AND operation unit 107 performs the same logical operation as that of the AND gate.

In addition, when at least one low signal between the signal output from the shift register 105 and the gate output enable signal is supplied to the logical product operator 107, the logical product operator 107 is provided. Outputs a low signal.

The high or low signal output from the AND product 107 is supplied to the level shifter 109.

The level shifter 109 serves to supply a voltage value corresponding to a high or low signal supplied from the AND product 107 to the buffer 113. In this case, the level shifter 109 includes the gate high voltage VGH generated by the first and second power supply units 110 and 112 and the first and second gate low voltages VGL-1 and VGL-2. Supplied.

The level shifter 109 further includes a gate low voltage selector 111 that sequentially selects the first and second gate low voltages VGL-1 and VGL-2 and supplies them to the buffer unit 113. do.

When a high signal is supplied to the level shifter 109, the level shifter 109 selects the gate high voltage VGH and supplies it to the buffer unit 113. In addition, when the low signal is supplied to the level shifter 109, the gate low voltage selector 111 selects the first gate low voltage VGL-1 and supplies it to the buffer 113. do.

After the first gate low voltage VGL-1 is selected, the gate low voltage selector 111 selects the second gate low voltage VGL-2 after at least one horizontal section 1H. The buffer unit 113 is supplied. In this case, the gate low voltage selector 111 selects the first and second gate low voltages VGL-1 and VGL-2 according to a predetermined control signal supplied from the timing controller 108.

When the control signal supplied from the timing controller 108 is high, the gate low voltage selector 111 selects the first gate low voltage VGL-1 to the buffer unit 113. The first gate low voltage VGL-1 is supplied.

When the control signal supplied from the timing controller 108 is low, the gate low voltage selector 111 selects the second gate low voltage VGL-2 and transmits the selection to the buffer unit 113. The second gate low voltage VGL-2 is supplied. At this time, the control signal generated from the timing controller 108 has a high signal for one horizontal section, and has a low signal for the remaining horizontal sections except for the one horizontal section.

Thus, the gate low voltage selector 111 selects the first gate low voltage VGL-1 and supplies it to the buffer unit 113, and then, after at least one horizontal section 1H, the second gate low voltage is selected. VGL-2 is selected and supplied to the buffer unit 113.

The buffer unit 113 is electrically connected to the gate lines GL0 to GLn so that the gate high voltage VGH and the first and second gate low voltages VGL-1 and VGL-2 are connected to the gate lines. Supply sequentially to (GL0 to GLn).

As a result, as shown in FIG. 5, the gate high voltage VGH is supplied to the gate lines GL0 to GLn for one horizontal period 1H, and then the first gate low voltage VGL-1 is applied to the gate lines GL0 to GLn. It is supplied to the gate lines GL0 to GLn.

Subsequently, the first gate low voltage VGL-1 is greater than the first gate low voltage VGL-1 after at least one horizontal section 1H after the first gate low voltage VGL-1 is supplied to the gate lines GL0 to GLn. The two gate low voltage VGL-2 is supplied to the gate lines GL0 to GLn.

The thin film transistor TFT connected to the gate lines GL0 to GLn is turned on when the gate high voltage VGH is supplied, and at the same time, the data voltage is increased through the data lines DL1 to DLm. It is supplied to a pixel electrode (not shown).

Next, the thin film transistor TFT connected to the gate lines GL0 to GLn is turned off when the first gate low voltage VGL-1 is supplied, and at the same time, the pixel electrode (not shown). The voltage drop supplied by the controller generates a voltage drop equal to the kickback voltage (Vp).

Subsequently, after the first gate low voltage VGL-1 is supplied to the gate lines GL0 to GLn, the second gate low voltage (V1) to the gate lines GL0 to GLn after at least one horizontal section 1H. When the VGL-2) is supplied, the thin film transistor TFT maintains a turn-off state.

The second gate low voltage VGL-2, which is greater than the first gate low voltage VGL-1, is supplied to the thin film transistor TFT so that the second gate low voltage VGL-2 is charged on the pixel electrode in association with the kickback voltage Vp. The data voltage at which the voltage drop occurs has risen by a predetermined amount.

As described above, the kickback voltage (Vp) is generated in association with the thin film transistor TFT when it is turned from a turn-on state to a turn-off state. The kickback voltage Vp is then compensated by supplying the second gate low voltage VGL-2 to the gate lines GL0 to GLn in the horizontal section.

That is, the kickback voltage VV-1 is generated at the moment when the gate high voltage VGH is changed from the first gate low voltage VGL-1 to the first gate low voltage VGL-1. The kickback voltage VVp may be compensated by supplying a larger second gate low voltage VGL-2.

In response to the change from the first gate low voltage VGL-1 to the second gate low voltage VGL-2, the data voltage charged in the storage capacitor Cst is affected. As a result, the data voltage, which has a voltage drop equal to the kickback voltage (Vp), is increased by a predetermined voltage.

The second gate low voltage VGL-2 is continuously supplied to the gate lines GL0 to GLn until the gate high voltage VGH is supplied in the next frame period.

As described above, the liquid crystal display according to the present invention supplies the gate high voltage VGH and the first gate low voltage VGL-1 to the gate lines GL0 to GLn, and starts the first gate from the next horizontal section. By supplying the second gate low voltage VGL-2 greater than the low voltage VGL-1, the image quality may be improved by overcoming the flicker generated in the conventional liquid crystal display.

As described above, in the liquid crystal display according to the present invention, after the first gate low voltage VGL-1 is supplied, the second gate low voltage VGL-2 increased after a predetermined interval is supplied to the kickback voltage ( By compensating (Vp), the image quality can be improved by overcoming the flicker and the afterimage caused by the kickback voltage (Vp) generated in the conventional liquid crystal display.

Claims (7)

A liquid crystal panel in which pixels defined by a plurality of gate lines and data lines are arranged; A gate driver configured to supply a gate high voltage and first and second gate low voltages to the gate lines; And A data driver supplying a predetermined data voltage to a data line of the liquid crystal panel; And the second gate low voltage is at least higher than the first gate low voltage. The method of claim 1, The kickback voltage generated when the gate high voltage transitions from the first gate low voltage is compensated by the voltage generated when the transition from the first gate low voltage to the second gate low voltage. Device. The method of claim 1, And a voltage generated when the first gate low voltage transitions from the first gate low voltage to the second gate low voltage. The method of claim 1, The thin film transistor is turned on when the first gate high voltage is supplied, and is turned off when the first and second gate low voltages are supplied. The method of claim 1, The gate driver, A shift register which sequentially outputs an output signal according to a first predetermined control signal; An AND product controlling the output of the output signal output from the shift register; A level shifter configured to output a gate high voltage and first and second gate low voltages according to an output signal controlled by the AND operation unit; And And a buffer unit for supplying a voltage supplied from the level shifter to the gate line. The method of claim 5, And the level shifter includes a selector configured to select the first and second gate low voltages in order. The method of claim 6, And the gate low voltage selector selects and outputs the first gate low voltage and then selects and outputs the second gate low voltage after at least one horizontal period.

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