KR20200052137A - Display device and data device of transmitting and receiving data thereof - Google Patents

Abstract

The present invention relates to a display device and a data transmission/reception device thereof. The display device comprises: a transmission device scrambling pixel data of an input image after the pixel data is reset at a predetermined time period according to reset data; a reception device receiving the data scrambled with the reset data received from the transmission device through a data wire and restoring the scrambled pixel data after the pixel data is reset at the predetermined time period according to the reset data; and a display panel driving unit writing pixel data restored by the reception device to pixels of the display panel. A value of the reset data is changed at the predetermined time period. A scrambler and a descrambler may always maintain a synchronized state.

Description

Display device and its data transmission / reception device {DISPLAY DEVICE AND DATA DEVICE OF TRANSMITTING AND RECEIVING DATA THEREOF}

The present invention relates to a display device for reducing electromagnetic interference (EMI) on a data transmission line by scrambled data and a data transmission / reception device.

Various flat panel display devices such as liquid crystal display devices (LCDs) and electroluminescent display devices are commercially available. The electroluminescent display device is roughly classified into an inorganic light emitting display device and an organic light emitting display device according to the material of the light emitting layer. The active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter referred to as “OLED”) that emits light by itself, and has a fast response speed, high luminous efficiency, high luminance, and wide viewing angle. There are advantages.

In order to reduce the EMI on the data transmission line in such a flat panel display device, data may be transmitted by scrambled by a transmitting device and de-scrambled by a receiving device to be restored.

When the scrambler of the transmitting device and the descrambler of the receiving device are not synchronized, data may not be restored normally. In this case, an abnormal noise image may be displayed on the screen until the descrambler of the receiving device is reset according to the reset data received from the transmitting device.

Accordingly, the present invention provides a display device and a data transmission / reception device capable of maintaining a synchronous state of a scrambler and a descrambler.

The display device of the present invention receives a scrambled data together with the reset data received from the transmission device through a data wiring, a transmission device that scrambles pixel data of an input image after being reset at a predetermined time period according to the reset data, And a receiving device for restoring the scrambled pixel data after being reset in the predetermined time period according to the reset data, and a display panel driver for writing pixel data restored by the receiving device to pixels of a display panel. The value of the reset data is changed in the predetermined time period.

The transmitting device and the receiving device are synchronized according to the reset data inputted every predetermined time period, including the same linear feedback shift register (LFSR).

In the display device of the present invention, data lines and gate lines are intersected, and a display panel in which pixels are arranged in a matrix form, reset data is input to a scrambler to reset the scrambler, and then pixel data of an input image is input to the scrambler. A timing controller that outputs a signal including scrambled pixel data as a data wiring pair, and separates the scrambled pixel data from a signal received from the timing controller through the data wiring pair, inputs it to a descrambler, and inputs the pixels of the input image. And a data driver that restores data, converts the pixel data into a data voltage, and outputs the data lines to the data lines. The value of the reset data is changed to a predetermined time period set to a time shorter than one frame period, input to the scrambler, and input to the descramble block through the data wiring pair.

The data transmitting and receiving device of the present invention receives a scrambled data together with the reset data received from the transmitting device through a data wiring and a transmitting device that scrambles pixel data of an input image after being reset at a predetermined time period according to the reset data. And a receiving device that restores the scrambled data after being reset in the predetermined time period according to the reset data. The value of the reset data is changed in the predetermined time period.

According to the present invention, the scrambler and the descrambler can always maintain a synchronous state by generating reset data at a predetermined time period set to a time shorter than one frame period and periodically changing the value.

The present invention can automatically synchronize the scrambler and the descrambler every horizontal period without a separate reset sequence by transmitting reset data whose values vary in the horizontal blank period to the scrambler and descrambler. In addition, the present invention can minimize the periodicity of the data transmitted through the data wiring pair by updating the reset data to different values every horizontal period, thereby maximizing the random and EMI improvement effect of the data.

The present invention increases the random effect of data by generating reset values for resetting the scrambler and descrambler in multiple bits, and further improving the random effect by changing the values to different values every horizontal period.

Furthermore, the present invention can scramble pixel data without scrambling the control data and clock, thereby increasing the random effect of the data without malfunction of the receiving device to reduce EMI in the wiring through which the data is transmitted.

1 is a block diagram showing a display device according to an exemplary embodiment of the present invention.
2 is a diagram showing an EPI interface topology for connecting a timing controller and source drive ICs.
3 is a waveform diagram showing a signal transmission protocol of the EPI interface.
4 is a diagram illustrating one data packet in the EPI interface.
5 is a waveform diagram showing an EPI signal transmitted during a horizontal blank period.
6 is a waveform diagram showing an internal clock restored by the clock recovery unit.
7 is a block diagram showing a timing controller and a source drive IC in detail.
8 is a view showing an example in which reset data of the LFSR is generated with the same value.
FIG. 9 is a view comparing an abnormal screen when the transmitting LFSR and the receiving LFSR are not synchronized with the original image.
10 is a view showing an LFSR circuit according to an embodiment of the present invention.
11 is a waveform diagram showing an example in which a transmitting side LFSR and a receiving side LFSR are reset in a horizontal blank period.
12 is a waveform diagram showing an example in which the value of the LFSR reset data is changed every horizontal period.
13 is a view showing a simulation result for reset data according to an embodiment of the present invention.
14 is a waveform diagram showing an example in which timing signals are abnormally output from a source drive IC when data bits of a control packet are scrambled.
15 is a waveform diagram showing an example of a clock embedded in an EPI signal transmitted to a source drive IC.

Advantages and features of the present invention, and methods for achieving them will be clarified with reference to embodiments described below in detail together with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the embodiments allow the disclosure of the present invention to be complete, and those skilled in the art to which the present invention pertains. It is provided to fully inform the scope of the invention to the present invention, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing the embodiments of the present invention are exemplary, and the present invention is not limited to the details shown in the drawings. Throughout the specification, the same reference numerals refer to substantially the same components. In addition, in the description of the present invention, when it is determined that detailed descriptions of related known technologies may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted.

When "equipped", "includes", "haves", "consists of" and the like referred to herein are used, other parts may be added unless '~ only' is used. When a component is expressed in singular, it may be interpreted in plural unless otherwise specified.

In interpreting the components, it is interpreted as including the error range even if there is no explicit description.

In the case of the description of the positional relationship, for example, when the positional relationship between the two components is described as' on the top ',' on the top ',' on the bottom ',' on the side ',' One or more other components may be interposed between those components for which no 'direct' or 'direct' is used.

First, second, etc. may be used to classify the components, but the functions or structures of these components are not limited by the ordinal number or the name of the component before the component. Since the claims are described mainly on essential components, the ordinal number preceding the component name of the claims and the ordinal number preceding the component name of the embodiments may not match.

The following embodiments may be partially or totally combined or combined with each other, and technically various interlocking and driving are possible. Each of the embodiments may be implemented independently of each other, or may be implemented together in an association relationship.

Hereinafter, various embodiments of the present specification will be described in detail with reference to the accompanying drawings.

The display device of the present invention can be applied to any flat panel display device that scrambles and transmits data. It should be noted that in the following embodiments, the display device is described, but not limited to, the organic light emitting display device.

Referring to FIG. 1, a display device according to an exemplary embodiment of the present specification includes a display panel 100 and a display panel driver.

The display panel 100 includes a screen AA in which an input image is reproduced. The screen AA includes a pixel array in which pixel data of an input image is displayed. The pixel array includes a plurality of data lines DL, a plurality of gate lines GL intersecting the data lines DL, and a plurality of pixels.

The pixels may be arranged on the screen AA in a matrix form defined by the data lines DL and the gate lines GL. The pixels may be arranged in various ways on the screen AA, such as a shape sharing a pixel emitting the same color, a stripe shape, a diamond shape, etc., in addition to the matrix shape.

When the resolution of the pixel array is m * n, the pixel array includes m (m is a positive integer greater than or equal to 2) pixel columns, and n (n is a positive integer greater than or equal to 2) pixel lines intersecting Fields (L1 to Ln) are included. The pixel column includes pixels arranged along the y-axis direction. The pixel line includes pixels arranged along the x-axis direction. One vertical period is one frame period required to write one frame of pixel data to all pixels on the screen. It is the time required to write one line of pixel data sharing the gate line to pixels of one pixel line. One horizontal period is a time obtained by dividing one frame period by the number of m pixel lines L1 to Lm.

Each of the pixels may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color realization. Each of the pixels may further include a white sub-pixel. Each of the sub-pixels 101 includes the same pixel circuit.

In the case of the organic light emitting diode display, the pixel circuit may include a light emitting element, a driving element, one or more switch elements, and a capacitor. The light emitting device can be implemented with an OLED. The current of the OLED can be adjusted according to the voltage between the gate and the source of the driving element. The driving element and the switching element may be implemented as transistors. The pixel circuit is connected to the data line DL and the gate line GL. In FIG. 1, “D1 to D3” indicated in a circle are data lines, and “Gn-2 to Gn” are gate lines. Each of the sub-pixels 101 may include the same pixel circuit.

Touch sensors may be disposed on the display panel 100. The touch input may be sensed using separate touch sensors or may be sensed through pixels. The touch sensors are placed on-screen (AA) of the display panel 100 in an on-cell type or an add-on type, or an in-cell type embedded in a pixel array. It can be implemented with touch sensors.

The display panel driver includes a data driver 110 and a gate driver 120. The display panel driver writes pixel data of an input image to pixels of the display panel 100 under the control of a timing controller (TCON) 130.

The data driving unit 110 converts the pixel data SDATA of the input image received from the timing controller 130 into a gamma compensation voltage using a digital to analog converter (hereinafter referred to as “DAC”), and thus the data voltage. Occurs. The data driver 110 supplies the data voltage to the data lines DL. The pixel data voltage is supplied to the data lines DL and is applied to the pixel circuit of the sub pixels 101 through a switch element. The data driver 110 may be implemented with one or more source drive ICs SIC1 to SICn as shown in FIG. 2.

The gate driver 120 may be formed on the bezel area BZ outside the screen on which the image is not displayed on the display panel 100. The gate driver 120 sequentially supplies a gate signal synchronized with the data voltage to the gate lines GL under the control of the timing controller 130. The gate signal simultaneously selects the pixel line to which the data voltage is charged.

The gate driver 120 outputs a gate signal using one or more shift registers and shifts the gate signal. The gate signal may include one or more scan signals and a light emission control signal EM.

The timing controller 130 receives pixel data DATA of an input image and a timing signal synchronized with the pixel data DATA from a host system (not shown). The timing signal includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock signal (DCLK), and a data enable signal (DE). Since the vertical period and the horizontal period are known as a method of counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted.

The timing controller 130 reduces the EMI on the wire through which data is transmitted by inputting reset data changed to a different value at a predetermined time less than one frame period into a scrambler and transmitting the reset data to the data driver 110. . In order to improve the random effect of data transmitted to the data driving unit 110, the reset data may be updated with different values at a predetermined time period.

The timing controller 130 includes a source timing control signal (DDC) for controlling the operation timing of the data driver 110 based on the timing signals (Vsync, Hsync, DE) received from the host system, and the gate driver 120. A gate timing control signal (GDC) for controlling operation timing is generated.

The timing controller 130 may control the operation timing of the display panel driving units 110 and 120 by multiplying the input frame frequency by i times to a frame frequency of input frame frequency x i (i is a positive integer greater than 0) Hz. . The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) method and 50 Hz in the Phase-Alternating Line (PAL) method.

The host system may be any one of a TV (Television), a set-top box, a navigation system, a personal computer (PC), a home theater, a mobile device, and a wearable device. In the mobile device and the wearable device, the data driver 110, the timing controller 130, and the level shifter 140 may be integrated in one drive IC.

The level shifter 140 converts the voltage of the gate timing control signal GDC output from the timing controller 130 into a gate high voltage VGH and a gate low voltage VGL and supplies them to the gate driver 120. The low level voltage of the gate timing control signal GDC is converted to the gate low voltage VGL, and the high level voltage of the gate timing control signal GDC is the gate high voltage VGH. Is converted to

In each of the sub-pixels of the organic light emitting display device, the electrical characteristics of the sub-pixel such as the threshold voltage (Vth) of the driving element, the electron mobility (μ) of the driving element, the temperature deviation of the driving element, the threshold voltage of the OLED, etc. Ids), so it must be the same for all pixels. However, electrical characteristics may vary between pixels due to various causes such as process variation of the pixel array and change over time. Variations in electrical characteristics of these pixels may lead to deterioration in image quality and shortened life. In order to reduce the deterioration of the pixels and prolong the life, an internal compensation method or an external compensation method may be applied.

The internal compensation method samples the threshold voltage of the driving element by using a compensation circuit disposed in the pixel circuit, and compensates the gate-source voltage of the driving element by the threshold voltage. The external compensation method senses an electrical characteristic of a sub-pixel that changes according to the electrical characteristics of the sub-pixel through a sensing path connected to the sub-pixel, and modulates the pixel data of the input image based on the sensing result to compensate for the deviation of the electrical characteristics between the sub-pixels. To compensate.

In the external compensation method, the sensing data voltage output from the data driver 110 may be supplied to the data lines. The sensing data voltage is a voltage for presetting a voltage of a gate and a capacitor of a driving element to a preset voltage regardless of data of an input image.

The timing controller 130 and the source drive ICs SIC1 to SICn of the data driver 110 may be connected through a mini Low Voltage Differential Signaling (LVDS) interface. In this case, the control for controlling the R data transmission wiring, G data transmission wiring, B data transmission wiring, and source drive ICs SIC1 to SICn between the timing controller 130 and the source drive ICs SIC1 to SICn. Many wires are needed, including wires, clock transfer wires. Therefore, the mini LVDS (Low Voltage Differential Signaling) interface is difficult to reduce its width because many wirings must be formed on the source printed circuit board (PCB) mounted between the timing controller and the source drive ICs.

The EPI (Embedded Clock Point to Point Interface) interface connects the timing controller 130 and the source drive ICs SIC1 to SICn in a point-to-point manner, as shown in FIG. ) And the number of wires between the source drive ICs SIC1 to SICn. The EPI (Embedded Clock Point to Point Interface) interface does not require separate clock wiring and control wiring because the EPI signal including the control data and pixel data with a clock is transmitted through the data wiring pair 12.

In the EPI interface, clock recovery units for clock and data recovery (CDR) are incorporated in each of the source drive ICs SIC1 to SICn. The timing controller 130 transmits a clock training pattern or preamble signal to the source drive ICs SIC1 to SICn so that the output phase and frequency of the clock recovery unit can be locked. The clock recovery unit embedded in the source drive ICs SIC1 to SICn restores the clock signal when the clock training pattern signal and the clock signal of the EPI signal received through the data wiring pair 12 are input, thereby multi-phased as shown in FIG. 6. Generate an internal clock (CDR CLK).

The source drive ICs SIC1 to SICn timing controller 130 locks a lock signal (LOCK) of a high logic level indicating a stable output state when the phase and frequency of the internal clock are locked. ) To provide feedback. A high logic level DC power supply voltage VCC is input to the lock signal input terminal of the first source drive ICs SIC1. The lock signal LOCK is fed back to the timing controller 130 through the lock feedback wiring 13 connected to the timing controller and the last source drive IC SICn.

In the signal transmission protocol of the EPI interface, the timing controller 130 transmits a clock training pattern signal to source drive ICs SIC1 to SICn before transmitting control data and pixel data of an input image. The clock recovery unit of the source drive ICs SIC1 to SICn performs a clock training operation based on the clock training pattern signal to restore the clock received through the data wiring pair 120 to generate an internal clock, and internal When the phase and frequency of the clock are stably fixed, a data link with the timing controller 130 is established. The timing controller 130 starts to transmit control data and pixel data to the source drive ICs SIC1 to SICn in response to a lock signal LOCK received from the last source drive IC SICn. The output signal of the timing controller 130 is converted to a differential signal through the transmission end buffer of the timing controller 130 and transmitted to the source drive ICs SIC1 to SICn through the data wiring pair 12.

The source drive ICs SIC1 to SICn sample control data bits from signals received through the data wiring pair 12 at internal clock timing, and restore timing signals and control signals of the driving circuit from the sampled control data. The control data includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), and a source timing control signal (DDC) for controlling the operation timing of the source drive ICs SIC1 to SICn. can do.

The source drive ICs SIC1 to SICn sample bits of pixel data from a signal received through a pair of wires according to an internal clock timing, and then convert bits of sampled pixel data into parallel data. The source drive ICs SIC1 to SICn convert pixel data to a gamma compensation voltage through a DAC in response to the restored source control data to output a data voltage. The data voltage is supplied to the data lines DL.

3 is a waveform diagram showing a signal transmission protocol of the EPI interface.

Referring to FIG. 3, the timing controller 130 transmits a clock training pattern signal (or preamble signal) having a constant frequency to the source drive ICs SIC1 to SICn in the first phase (Phase-I) and locks the feedback wiring ( When the lock signal LOCK of the high logic level (1) is input through 13), the second step (Phase-II) is performed to start transmission of the control data CTR. When the lock signal LOCK is maintained at a high logic level following the second phase (Phase-II), the timing controller 130 performs the third phase (Phase-III) to transmit an EPI signal including pixel data of the input image. do. The EPI signal is transmitted to the source drive ICs SIC1 to SICn as a serial signal including a data packet defined in the EPI interface signal transmission protocol.

The timing controller 130 scrambles pixel data to reduce EMI on the data wiring pair 12. In FIG. 3, SDATA refers to scrambled pixel data. The scrambler of the timing controller 130 may scramble pixel data using a linear feedback shift register (hereinafter referred to as “LFSR”). The source drive ICs SIC1 to SICn include a de-scrambler that de-scrambles pixel data in synchronization with a scrambling device. The descrambler restores pixel data DATA by inputting reset data LFSR-RST and scrambled pixel data SDATA to the LFSR every horizontal period.

In FIG. 3, “Tlock” is a clock signal that is stabilized by the internal clock output from the clock recovery units of the source drive ICs SIC1 to SICn after the clock training pattern signal starts to be input to the source drive ICs SIC1 to SICn. It is the time until it is inverted to the high logic level (H). This time (Tlock) may be a time of one horizontal period or more.

The timing controller TCON is a first step (to resume clock training of the source drive ICs SIC1 to SICn) when the lock signal LOCK of the low logic level L is input from the last source drive IC SICn. Phase-I) is executed to transmit the clock training pattern signal to the source drive ICs SIC1 to SICn. If the clock is not normally restored from the clock recovery unit in an unexpected situation during the second phase (Phase-II) signal and the third phase (Phase-III) execution, either of the source drive ICs SIC1 to SICn is locked. LOCK) to the low logic level (L). In this case, the timing controller 130 is connected to the lock signal LOCK of the low logic level L from the last source drive IC SICn in the second phase (Phase-II) signal or the third phase (Phase-III) process. In response, the first step (Phase-I) is executed to transmit the clock training pattern signal to the source drive ICs SIC1 to SICn. At this time, control data CTR and pixel data SDATA are not received in the source drive ICs SIC1 to SICn. In addition, since the reset data for synchronization of the scrambler and the descrambler (LFSR-RST) is not received by the source drive ICs SIC1 to SICn, all the pixel data of one frame is not written on the screen AA. Noise is visible on (AA).

4 is a diagram illustrating one data packet in the EPI interface.

Referring to FIG. 4, one data packet of the EP signal transmitted from the EPI interface to the source drive ICs SIC1 to SICn includes data bits, clock bits allocated before and after data bits (EPI CLK). . Data bits are bits of control data or pixel data. One bit transmission time is one UI (Unit Interval) time. 1 UI depends on the resolution of the display panel (PNL) or the number of data bits.

The clock bits (EPI CLK) are allocated by 4 UI between neighboring data packets, and the logic value may be set to “0 0 1 1 (or L L H H)”, but is not limited thereto. When the number of data bits is 10 bits, one packet may include 30 UI data bits and 4 UI clock bits. When the number of data bits is 8 bits, one packet may include 24 UI data bits and 4 UI clock bits. When the number of data bits is 6 bits, one packet may include 18 UI RGB data bits and 4 UI clock bits, but is not limited thereto.

In the EPI interface protocol, the first phase (Phase-I) and the second phase (Phase-II) are performed on the source drive ICs SIC1 to SICn for each horizontal blank period (HB) as shown in FIG. 5. Lose. The horizontal blank period HB is a time during which no pixel data is input within one horizontal period 1H and corresponds to a low logic level period of the data enable signal DE. In FIG. 5, “DE” is a data enable signal DE. One pulse period of the data enable signal DE is one horizontal period (1H). In the high logic section of the data enable signal DE, that is, the third phase (Phase-III) is executed within the pulse width, and a data packet including pixel data SDATA is transmitted. In FIG. 5, “CST” is a control start bit indicating the start of a data packet, and “CTR1” and “CTR2” are control data bits. “SDATA” is pixel data scrambled by the timing controller 130.

6 is a waveform diagram showing an internal clock restored by the clock recovery unit. In FIG. 6, “EPI” is an EPI signal received by the source drive ICs SIC1 to SICn through the data wiring pair 12. “CDR CLK” is a multi-phase internal clock output from the clock recovery units of the source drive ICs SIC1 to SICn.

Referring to FIG. 6, clock recovery units of each of the source drive ICs SIC1 to SICn use multi-phase internal clocks using a phase locked loop (PLL) or a delay locked loop (DLL). (CDR CLK) is output. The clock recovery unit receives the clock training pattern signal received through the data wiring pair 12, generates an output, and inverts the lock signal (LOCK) to a high level when the phase and frequency of the output are equal to the input clock, and then EPI The clock of the signal is restored to generate a multi-phase internal clock (CDR CLK). The multi-phase internal clock (CDR CLK) is generated with clocks that are sequentially delayed so that the rising edge of the clock is synchronized with each bit of the data packet. The source drive ICs SIC1 to SICn sample bits of data on the rising edge of the internal clock (CDR CLK).

7 is a block diagram showing a timing controller and a source drive IC in detail. In FIG. 7, only the first source drive IC SIC1 is shown. Other source drive ICs also have the same configuration as the first source drive IC SIC1.

Referring to FIG. 7, the timing controller 130 includes a data randomization processing unit 20, a clock generation unit 31, and a packer 41.

The data randomization processing unit 20 includes a reset processing unit 21 and a scrambler 22. The data randomization processing unit 20 scrambles bits of pixel data using the scrambler 22. The scrambler 22 scrambles the bits of the pixel data DATA by inputting the pixel data DATA of the input image to the LFSR. LFSR generates output as a linear function using exclusive OR (XOR) operation. The LFSR outputs scrambled pixel data SDATA after being reset according to the reset data LFSR-RST from the initialization processing unit 21.

The reset processing unit 21 outputs reset data LFSR-RST and a selection signal SEL. Reset data (LFSR-RST) is supplied to the scrambler 22 and the packer 41. The selection signal SEL is input to the control terminal of the scrambler 22. The clock generator 31 generates a clock CLK using an oscillator and a PLL and supplies it to the data randomization processor 20 and the packer 41. The value of the reset data is changed to a predetermined time period so that the random effect of the data is improved and the scrambler 22 and the descrambler 52 are automatically synchronized at a predetermined time period. The predetermined time period is set to a shorter time than one frame period.

The packer 41 converts serial data including clock, control data, and pixel data (SDATA) according to a data packet configuration that satisfies a signal transmission protocol of a preset EPI interface. The packer 41 converts the EPI signal in the form of a differential signal through the transmission end buffer and outputs it to the data wiring pair 12. Accordingly, the EPI signal whose time is output from the controller 130 is transmitted to the source drive IC SIC1 through the data wiring pair 12.

Only when the scrambler 22 and the descrambler 52 are synchronized can the pixel data be restored normally in the descrambler 52. In order to synchronize the scrambler 22 and the descrambler 52, reset data LFSR-RST is periodically transmitted to the source drive IC SIC1 through the data wiring pair 12.

The source drive IC SIC1 includes an unpacker 42, a data recovery unit 50, and a clock recovery unit 32.

The receiving end buffer of the unpacker 42 receives the EPI signal through the data wiring pair 12 through. The unpacker 42 separates reset data (LFSR-RST), control data and pixel data (SDATA), and clock (CLK) from the received EPI signal.

The reset processing unit 51 outputs the selection signal SEL together with the reset data LFSR-RST received from the unpacker 42. The reset data LFSR-RST is supplied to the descrambler 52. The selection signal SEL is input to the control terminal of the descrambler 52.

The data restoration unit 50 resets the LFSR of the descrambler 52 by inputting the reset data LFSR-RST to the descrambler 52. The LFSR of the descrambler 52 is periodically reset by the reset data LFSR-RST from the reset processing unit 51 and synchronized with the LFSR of the scrambler 22. The descrambler 52 restores the pixel data DATA by inputting the scrambled pixel data SDATA to the LFSR. The reconstructed pixel data is sampled at the internal clock (CDR CLK) timing, converted into a parallel scheme, and then converted to a gamma compensation voltage through a DAC (not shown).

The clock recovery unit 32 receives the clock bits separated from the EPI signal, outputs a multi-phase internal clock (CDR), and transmits it to the data recovery unit 52.

In order for the scrambled pixel data SDATA to be restored normally, the circuit configuration of the transmitting side LFSR (Tx) and the receiving side LFSR (Rx) must be the same and synchronized with each other. The transmitting LFSR is the LFSR of the scrambler 22, and the receiving LFSR is the LFSR of the descrambler 52. The transmitting side LFSR and the receiving side LFSR are synchronized by the reset data (LFSR-RST) transmitted to the receiving side LFSR.

The reset data LFSR-RST may be set to one preset value, for example, OxFFF as illustrated in FIG. 8. When the reset LFSRs receive reset data (LFSR-RST) and are reset, they begin to scramble the bits of the pixel data (DATA) with the output of XORing the LFSR values obtained by the sender LFSR output and the bits of the input data. The receiving LFSRs receive reset data (LFSR-RST), and when reset, the pixel data (DATA) is restored to the output of XORing the LFSR value obtained from the receiving LFSR output and the bit of the pixel data (SDATA). In FIG. 8, Tx_LFSR is an LFSR value obtained as a transmission LFSR output.

Before resetting the LFSR, the synchronization between the transmitting LFSR and the receiving LFSR may be out of sync due to external noise or electrostatic discharge (ESD). In this case, as shown in (B) of FIG. 9, abnormal noise may be displayed on the screen. If the reset period of the sending LFSR and the receiving LFSR is long, the user may see an abnormal screen. In FIG. 9, (A) is an original image, and (B) illustrates an abnormal screen when the transmitting LFSR and the receiving LFSR are not synchronized.

In order to reduce EMI noise by randomizing data on the data transmission wiring, data scramble is performed. However, if the reset data of the LFSR (LFSR-RST) is the same as in the example of FIG. 8, the random effect of the data is reduced because the bits of the same reset data are periodically transmitted through the data wiring pair 12. When the data value of the reset signal for resetting the LFSR is a fixed value, since the reset data of the same value is transmitted in the LFSR reset period, the EMI reduction effect may be lowered according to the data pattern of the input image and the LFSR period.

10 is a view showing an LFSR circuit according to an embodiment of the present invention. In FIG. 10, (A) shows the LFSR circuits of the transmitting LFSR [22 (Tx)] and the receiving LFSR [52 (Rx)]. (B) shows an example of scramble data obtained as a result of XORing 3 bit data and LFSR OUT (LFSR OUT). 10, “0” to 15 denote bits of input data that are sequentially shifted through the output transfer units of the shift registers 23 and 53.

Referring to FIG. 10, the transmitting side LFSR [22 (Tx)] and the receiving side LFSR [52 (Rx)] have the same circuit configuration in which a plurality of XOR gates are connected to the shift registers 23 and 53.

The shift registers 23 and 53 shift input data by one bit in accordance with clock timing through a plurality of output transfer units that are connected in series. The output transfer unit may be a D flip-flop. XOR gates are connected to the output nodes between the output transfers in the shift register. The final output terminals of the shift registers 23 and 53 are fed back to the input terminal and XOR gates.

Each of the XOR gates generates an XOR operation result for the bits of the LFSR values (Tx_LFSR OUT, Rx_LFSR OUT) and the input data bits fed back from the final output terminals of the shift registers 23 and 53, and delivers them to the next output transfer unit.

The transmitting LFSR [22 (Tx)] and the receiving LFSR [52 (Rx)] further include multiplexers 24, 54 connected to the input terminals of the shift registers 23, 53. When the LFSR is reset under the control of the reset processing units 21 and 51 shown in Fig. 7, the multiplexers 24 and 54 send the reset data Tx_LFSR-RST and Rx_LFSR-RST to the input terminals of the shift registers 23 and 53. After supply, the input data (DATA, SDATA) is supplied to the input terminals of the shift registers (23, 53) after reset.

The reset processing units 21 and 51 generate a selection signal at a high level (H) at a preset timing every horizontal period to cause the multiplexers 24 and 54 to output reset data (Tx_LFSR-RST, Rx_LFSR-RST). . Subsequently, the reset processing unit 21 inverts the selection signal SEL to the low level L after the LFSRs 22 (Tx, 52 (Rx)) are reset for every horizontal period, and then from the multiplexers 24, 54. The multiplexers 24 and 54 are controlled so that the input data DATA and SDATA are output. The reset processing unit 21 changes the values of the reset data (Tx_LFSR-RST, Rx_LFSR-RST) to different values every horizontal period in order to increase the random effect of the data. For example, the value of the reset data is generated as FFFFFF in the first horizontal period (Mth DE) as shown in FIG. 13, and is generated as DC9892 in the second horizontal period (Nth DE), and then the third horizontal period (Oth DE). Can be caused by D235F6. Therefore, the value of the reset data can be updated to another value in one horizontal period period.

As another embodiment, the reset data (Tx_LFSR-RST, Rx_LFSR-RST) may be changed in a predetermined period smaller than one frame period. In this case, the reset data (Tx_LFSR-RST, Rx_LFSR-RST) are updated with different values at a predetermined period.

The transmitting LFSR [22 (Tx)] is reset by receiving reset data Tx_LFSR-RST and outputting an LFSR value (Tx_LFSR OUT). Subsequently, the transmitting-side LFSR [22 (Tx)] performs XOR operation on the bit of the LFSR value (Tx_LFSR OUT) to the bit of the pixel data DATA of the input image to output scrambled data SDATA. The LFSR value (Tx_LFSR OUT) changes each time a bit is shifted in the shift register.

The receiving side LFSR 52 (Rx) is reset by receiving the reset data Rx_LFSR-RST received from the timing controller 130 and outputting the LFSR value Rx_LFSR OUT. Subsequently, the receiving side LFSR 52 (Rx) outputs the restored data DATA by XORing the bits of the LFSR value Rx_LFSR OUT to the bits of the scrambled data SDATA.

Since the reset data LFSR-RST is transmitted from the timing controller 130 to the source drive ICs SIC1 to SICn every horizontal period, the transmitting side LFSR [22 (Tx)] and the transmitting side LFSR [22 (Tx)] Is reset simultaneously with the reset data and is synchronized every horizontal period. The reset data (LFSR-RST) is the same value in the current horizontal period, but is changed to a different value in the next horizontal period. In FIG. 10, Tx_LFSR_RST and Rx_LFSR_RST are divided into a transmitter and a receiver, but are generated with the same value in the current horizontal period.

11 is a waveform diagram showing an example in which the transmitting side LFSR and the receiving side LFSR are reset in the horizontal blank period HB. 12 is a waveform diagram showing an example in which the value of the LFSR reset data is changed every horizontal period.

11 and 12, the timing controller 130 sets the reset data (LFSR-RST) for synchronizing the transmitting LFSR [22 (Tx)] and the receiving LFSR [52 (Rx)] every horizontal period. It is transmitted to the source drive ICs SIC1 to SICn within the horizontal blank period HB. The reset data LFSR-RST may be transmitted in addition to specific data CTR3 in the control packet transmitted within the horizontal blank period HB. Alternatively, the reset data LFSR-RST is transmitted to the source drive ICs SIC1 to SICn at the time when the low logic period starts or the low logic period ends in the data enable signal DE as shown in FIG. 12. Can be.

In FIG. 11, Tx_LFSR and Rx_LFSR are LFSR values generated from the transmitting LFSR [22 (Tx)] and the receiving LFSR [52 (Rx)], respectively. Tx_LFSR and Rx_LFSR must be the same to synchronize the sending LFSR [22 (Tx)] and the receiving LFSR [52 (Rx)]. However, Tx_LFSR and Rx_LFSR may be temporarily changed due to external noise or static electricity.

In the example of FIG. 11, the LFSR values of Tx_LFSR within any horizontal blank period HB are LFSR_N-3, LFSR_N-2, LFSR_N-1, ... When LFSR_N + 1 occurs, Rx_LFSR is LFSR_N, LFSR_N + 1, LFSR_N + 2, ... It may occur in the order of LFSR_N + 4, so the synchronization between the transmitting LFSR [22 (Tx)] and the receiving LFSR [52 (Rx)] may not match. The timing controller 130 adds reset data LFSR-RST to the EPI signal when Tx_RFSR = LFSR_O in this horizontal blank period HB and transmits it to the source drive ICs SIC1 to SICn. As a result, when Tx_RFSR = LFSR_O, the transmitting LFSR [22 (Tx)] and the receiving LFSR [52 (Rx)] are simultaneously reset and synchronized with each other.

In the example of FIG. 12, when the LFSR values of Tx_LFSR are generated in the order of LFSR_N-2, LFSR_N-1, Rx_LFSR is generated in the order of LFSR_C-1, LFSR_C, and the transmitting side LFSR [22 (Tx)] and the receiving side LFSR [52] (Rx)] may be out of sync. The timing controller 130 adds reset data LFSR-RST to the EPI signal when Tx_RFSR = LFSR_N in the first horizontal blank period HB and transmits it to the source drive ICs SIC1 to SICn. As a result, when Tx_RFSR = LFSR_N, the transmitting side LFSR [22 (Tx)] and the receiving side LFSR [52 (Rx)] are simultaneously reset and synchronized with each other. In this case, the timing controller 130 adds reset data (LFSR-RST) to the EPI signal when Tx_RFSR = LFSR_S in the second horizontal blank period (HB), transmits it to the source drive ICs (SIC1 to SICn), and transmits it. Synchronize LFSR [22 (Tx)] with the receiving LFSR [52 (Rx)]. In FIG. 12, DATA_A-1 to DATA_H-1 of the EPI signal are data SDATA scrambled by the transmitting LFSR [22 (Tx)].

Therefore, since the present invention synchronizes the transmitting LFSR [22 (Tx)] and the receiving LFSR [52 (Rx)] every horizontal period, the transmitting LFSR [22 (Tx)] and the receiving LFSR [52 (Rx) ] May be restored temporarily, and the scrambled pixel data SDATA can be restored normally by quickly recovering the synchronization within a time that the user does not recognize.

The present invention transmits the reset data (LFSR-RST) whose value is variable in the horizontal blank period (HB) to the receiving side LFSR [52 (Rx)], thereby transmitting LFSR [22 (Tx) without a separate reset sequence. ] And the receiving LFSR [52 (Rx)] can be automatically synchronized every horizontal period. In addition, the present invention can minimize the periodicity of data transmitted through the data wiring pair 12 by updating the reset data (LFSR-RST) to different values every horizontal period, thereby maximizing the random and EMI improvement effect of data. .

On the other hand, a method of simplifying the reset data (LFSR-RST) to a single bit may be considered, but since the random effect of the data is small, the reset data (LFSR-RST) is generated as multi-bit data as in the above-described embodiment. desirable. Single-bit scramble is a method of inputting one bit of a specific value to all XOR gates constituting an LFSR. This method does not scramble data randomly because data is inverted or transmitted as it is.

For example, a single bit may scramble the following data with “1” or “0”. In the example below, “^” is the XOR operator.

When Single Bit = 1,

  1 (Single Bit) ^ 0 (Data) = 1

  1 (Single Bit) ^ 1 (Data) = 0

Therefore, when Single Bit = 1, scrambled data is inverted data of input data, so 1 and 0 are not scrambled as shown below, so there is no random effect of data.

When 8Bit data = 00000000 and Single Bit = 1, scrambled data = 11111111. 8Bit data = 11111111, and when Single Bit = 1, scrambled data = 00000000.

When Single Bit = 0,

  0 (Single Bit) ^ 0 (Data) = 0

  0 (Single Bit) ^ 1 (Data) = 1

Therefore, when Single Bit = 0, the scrambled data is the same as the input data, so there is no random effect of the data as shown below.

When 8Bit data = 00000000 and Single Bit = 0, scrambled data = 00000000. 8Bit data = 11111111, and when Single Bit = 0, scrambled data = 11111111.

Therefore, the present invention can increase the random effect of data by generating a reset value for resetting the LFSR in multiple bits, and further improve the random effect by changing the value to a different value every horizontal period.

When the control packet and clock are scrambled in the EPI signal transmitted to the source drive ICs SIC1 to SICn, a malfunction may occur. As shown in FIG. 14, since the control packet CP is a very small proportion of the data amount of the EPI signal, it has little effect on the EMI effect with or without scramble. 14, “Tx Vsync” and “Tx DE” are timing signals in a control packet output from the timing controller 130. “Rx Vsync” and “Rx DE” are timing signals output from the source drive ICs (SIC1 to SICn).

The control data includes important timing information such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), and a data enable signal (DE) that provide reference timing in driving the display device. For this reason, if the timing information transmitted through the control packet cannot be restored because the transmitting LFSR [22 (Tx)] and the receiving LFSR [52 (Rx)] are asynchronous, an abnormal image is displayed on the screen, and the source drive ICs The timing signals and the source timing control signal (DDC), etc. in (SIC1 to SICn) are not restored normally, so the source drive ICs (SIC1 to SICn) may malfunction and adversely affect peripheral devices.

15 is a waveform diagram showing an example of a clock embedded in an EPI signal transmitted to a source drive IC.

As shown in the example of FIG. 15, the clock CLK transmitted to the source drive ICs SIC1 to SICn is toggled in units of 1 bit (1 UI) and generated as 10101010 when viewed in 8 bits.

The LFSR OUT output from the transmitting LFSR may be 10101010. In this case, if XOR operation is performed on the above clock bit and the LFSR OUT bit, it becomes 00000000, and there is no transition of the bit value. When LFSR OUT = 01010101, the XOR operation of the above clock bit and LFSR OUT bit results in 11111111, and there is no transition. When the scramble data of the clock CLK maintained at low or high is transmitted to the source drive ICs SIC1 to SICn, normal CDR operation cannot be performed at the source drive ICs SIC1 to SICn. No internal clock (CDR CLK) is generated. In this case, since the circuit elements of the source drive ICs SIC1 to SICn do not operate, normally restored data cannot be output.

In detail, the receiving device may generate a CDR output at the time of transition of data to restore the clock from the received data in an interface protocol that embeds clock information in data without transmitting a separate clock, such as the EPI interface. have. However, when data without a transition is received, all operations of the receiving device are disabled because the clock is not recovered from the CDR.

The timing controller 130 of the present invention can scramble only the pixel data from the EPI signals transmitted to the source drive ICs SIC1 to SICn by inputting only pixel data among clock, control packets, and pixel data to the scrambler 22. Therefore, the present invention can scramble the pixel data without scramble the control data and clock, thereby increasing the random effect of the data without malfunction of the source drive IC to reduce EMI in the wiring through which the data is transmitted.

Through the above description, those skilled in the art will appreciate that various changes and modifications are possible without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the scope of the claims.

20: data randomization processing unit 21, 51: reset processing unit
22: scrambler 22 (Tx): transmitting side LFSR
31: clock generator 32: clock recovery unit
41: packer 42: Unpacker
50: data restoration unit 52: descrambler
52 (Rx): Receiver LFSR

Claims (17)

A transmitting device that scrambles pixel data of the input image after being reset at a predetermined time period according to the reset data;
A receiving device receiving scrambled data together with the reset data received from the transmitting device through a data line, and restoring the scrambled pixel data after being reset in the predetermined time period according to the reset data; And
And a display panel driver which writes the pixel data restored by the receiving device to pixels of the display panel,
A display device in which the value of the reset data is changed in the predetermined time period. According to claim 1,
The transmitting device and the receiving device
A display device synchronized with the reset data inputted every predetermined time period, including the same linear feedback shift register (LFSR). A display panel in which data lines and gate lines are crossed and pixels are arranged in a matrix;
A timing controller that resets the scrambler by inputting reset data to a scrambler and then inputs pixel data of an input image to the scrambler to output a signal including scrambled pixel data as a data wiring pair; And
The scrambled pixel data is separated from the signal received from the timing controller through the data wiring pair and input to a descrambler to restore pixel data of the input image, convert the pixel data to a data voltage, and convert the pixel data into data lines. It includes a data driver to output,
A display device in which the value of the reset data is changed to a predetermined time period set to a time shorter than one frame period, input to the scrambler, and input to the descramble block through the data wiring pair. The method of claim 3,
A display device wherein the predetermined period is one horizontal period. The method of claim 3,
A display device wherein the reset data is added to the signal within a horizontal blank period every horizontal period and transmitted to the data driver. The method of claim 3,
The signal further includes a control packet,
The control packet includes timing information synchronized with pixel data of the input image and source timing information for controlling an operation timing of the data driver,
A display device in which the reset data is added to a specific position in the control packet. The method of claim 3,
A display device wherein the reset data is added to the signal at the start or end point of a specific logic section indicating a horizontal blank section in the data enable signal. The method of claim 3,
The signal further includes a clock and a control packet,
The control packet includes timing information synchronized with pixel data of the input image and source timing information for controlling an operation timing of the data driver,
The scrambler is a display device that scrambles the pixel data by receiving only the pixel data among the clock, the control packet, and the pixel data. The method according to any one of claims 2 to 8,
Each of the scrambler and the descrambler includes a linear feedback shift register (LFSR)
A display device synchronized with the reset data inputted every predetermined time period, including the same linear feedback shift register (LFSR). A transmitting device that scrambles pixel data of the input image after being reset at a predetermined time period according to the reset data; And
And a receiving device for receiving scrambled data together with the reset data received from the transmitting device through a data line, and restoring the scrambled data after being reset in the predetermined time period according to the reset data,
A data transmission / reception device of a display device in which the value of the reset data is changed at the predetermined time period. The method of claim 10,
The data wiring
A data transmission / reception device of a display device including a data wiring pair through which a differential signal is transmitted. The method of claim 11,
The transmitting device,
A transmission-side reset processing unit generating reset data and a selection signal at a predetermined time period;
A scrambler to scramble pixel data of an input image after being reset according to reset data from the reset processing unit on the transmission side;
A first multiplexer for supplying the pixel data to the scrambler after supplying the reset data to the scrambler in response to a selection signal from the transmission-side reset processing unit;
A clock generator for generating a clock; And
And a packer for converting a signal including the clock, scrambled data from the scrambler, and the reset data into a differential signal and outputting the data wiring pair. The method of claim 12,
The receiving device,
An unpacker separating the clock, the scrambled data, and the reset data from a signal received through the data wiring pair;
A receiving side reset processing unit outputting reset data and a selection signal from the unpacker;
A descrambler to restore the scrambled data after being reset according to reset data from the receiving side reset processing unit;
A second multiplexer that supplies the scrambled data to the descrambler after supplying the reset data to the descrambler in response to a selection signal from the reception reset unit; And
And a clock recovery unit for restoring the multi-phase internal clock from the clock. The method of claim 13,
The signal further includes a control packet,
The control packet includes timing information synchronized with pixel data of the input image and source timing information for controlling an operation timing of the data driver,
A data transmission / reception device of a display device in which the reset data is added to a specific position in the control packet. The method of claim 13,
A data transmitting / receiving device of a display device wherein the reset data is added to the signal at a start or end point of a specific logic section indicating a horizontal blank section in the data enable signal. The method of claim 13,
The signal further includes a control packet,
The control packet includes timing information synchronized with pixel data of the input image and source timing information for controlling an operation timing of the receiving device,
The scrambler receives and transmits only the pixel data among the clock, the control packet, and the pixel data, and the data transmitting and receiving device of the display device scrambles the pixel data. The method of claim 13,
Each of the scrambler and the descrambler includes a linear feedback shift register (LFSR).

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