JP2018148275A - Receiving apparatus of image transmission system and operating method of receiving apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restore image disorder due to noise etc. of image data at an early stage.SOLUTION: A receiving apparatus of an image transmission system according to the present invention for transmitting image data via a plurality of lanes includes a descrambling unit for descrambling the image data scrambled by an LFSR by the LFSR. The descrambling unit of each of the lanes includes a code detection unit for detecting a special code, an LFSR operation unit for performing an LFSR operation based on a seed value to be updated, and a preliminary seed calculation unit that updates a preliminary seed value having the same initial value as the seed value. The LFSR operation unit initializes the seed value by detecting the first code, and the preliminary seed calculation unit initializes the preliminary seed value by detecting the first code or the second code. The LFSR operation unit updates the seed value with the preliminary seed value such that the seed value coincides with a predetermined seed value in the predetermined number or more of lanes from among the plurality of lanes.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a receiving apparatus and a method for operating the receiving apparatus, and more particularly, to a receiving apparatus for an image transmission system that transmits an image data sequence through a plurality of lanes and an operating method for the receiving apparatus.

  The image transmission system transmits a generated image / video / audio data (hereinafter simply referred to as “image data” unless otherwise distinguished), and image data transmitted from the transmission device. And a receiving device that outputs an output signal suitable for the display device according to the image data. In such an image transmission system, typically, image data is subjected to high-speed serial communication via a differential signal line pair called a lane, and therefore countermeasures against electromagnetic interference (EMI) are extremely important. As one of EMI countermeasures, a scramble / descramble technique (hereinafter referred to as “scramble technique”) is known.

  The scramble technique is a technique in which image data is randomly encoded and transmitted on the transmission side, and is decoded into original data on the reception side. More specifically, both the transmission side and the reception side hold a linear feedback shift register (LFSR: Linear Feedback Shift Register; hereinafter referred to as “LFSR”) in which a predetermined common polynomial is incorporated. The transmission side generates a pseudo random number value using LFSR, performs an exclusive OR (EXOR) operation of the generated pseudo random number value and image data, transmits the operation result after 8B / 10B encoding, and receives it. After the 8B / 10B decoding of the received data, the side performs an exclusive OR operation between this and the pseudo random number value generated by the LFSR, and restores the original image data. Generation of pseudo-random values using LFSR is performed in a chain based on a common seed.

  In such a scramble technique, it is necessary to synchronize the random number generation values on the transmission side and the reception side. Therefore, in an image transmission system adopting a data transmission standard using 8B / 10B encoding, the LFSR seed value is reset by a specific delimiter code (K28.5), and synchronization is established between the transmission side and the reception side. Yes. For example, in a certain serial interface technology, the seed value of the LFSR is reset at the timing when a specific delimiter code BE_SR (Blanking End Scrambler Reset) (K28.0) is transmitted and received, thereby synchronizing the transmitting side and the receiving side. ing.

  Patent Document 1 below relates to a transmission / reception system for the purpose of quickly recovering synchronization between an encoding process in a transmission apparatus and a decoding process in a reception apparatus when noise is lost due to noise. . In Patent Document 1, a specific bit string for synchronizing communication between the transmission device and the reception device is used in order to correctly decode the serial data encoded in the transmission device in the reception device. It is disclosed that the data (specific data) to be transmitted is transmitted from the transmission device to the reception device in synchronization with the clock during a period in which the synchronization signal is at the second level in one cycle.

JP 2015-204513 A

  As the resolution of display devices increases, a larger number of lanes are required to transmit and receive a huge amount of image data at a predetermined data rate. When a plurality of lanes are used, it is necessary to synchronize the plurality of lanes at the same timing on the transmission side and the reception side. However, as a practical problem, it is very difficult to synchronize all lanes at the same timing due to the occurrence of inherent skew in each lane.

  Further, in the transmission / reception system described in Patent Document 1 described above, the specific data is output during a period in which the synchronization signal is at the second level in one cycle, whereby the encoding process in the transmission device and the decoding process in the reception device are performed. However, the synchronization timing between lanes was not considered.

  Therefore, an object of the present invention is to enable early restoration of image disturbance due to noise mixed in image data by synchronizing at an appropriate timing in an image transmission system having a plurality of lanes. And

  It is another object of the present invention to provide an image transmission system that can synchronize a plurality of lanes with appropriate timing on the transmission side and the reception side, and a data transmission method in the system.

  The present invention for solving the above-described problems is configured to include the following invention specific items or technical features.

  That is, the present invention according to a certain aspect can be a receiving device of an image transmission system that transmits an image data sequence via a plurality of lanes. The receiving device may include a descrambling unit corresponding to each of the plurality of lanes and descrambles an image data sequence scrambled based on the LFSR based on the LFSR. Each of the descrambling units updates a predetermined seed value according to a code detection unit that detects a predetermined code and a clock cycle, and supplies the updated predetermined seed value to the LFSR to perform an LFSR calculation. In accordance with the clock cycle of the LFSR to be performed, at least one reserve seed value that shares the predetermined seed value and the initial value is updated according to the clock period, and the updated at least one reserve seed value is stored in the LFSR calculator. And a preliminary seed calculation unit for outputting. The LFSR calculation unit may return to the initial value by initializing the predetermined seed value when a first code is detected by the code detection unit. Further, the preliminary seed calculation unit initializes the at least one preliminary seed value when at least one of the first code and the second code is detected by the code detection unit. Can return to value. Then, the LFSR calculation unit matches the predetermined seed value of the LFSR calculation unit in the other descrambling unit corresponding to the predetermined number of lanes of the plurality of lanes. Thus, the own predetermined seed value may be updated with the at least one preliminary seed value.

  As a result, the receiving device unintentionally initializes a predetermined seed value due to a bit error, or even if the predetermined seed value cannot be initialized unintentionally, the code ( For example, in consideration of the reception status of the initialization code), the predetermined seed value can be updated with the preliminary seed value calculated in advance.

The code detection unit includes a first code detection unit that detects a first code (for example, an initialization code SR) as the predetermined code, and a second code (for example, a blanking end code) as the predetermined code. And a second code detector for detecting BE). In addition, the backup LFSR calculation unit
Calculating a first preliminary seed value that shares the predetermined seed value and the initial value in accordance with a cycle of the clock, and outputting the first preliminary seed value to the LFSR calculation unit;
A second preliminary seed calculation unit that calculates a second preliminary seed value that shares the predetermined seed value and the initial value in accordance with a period of the clock and outputs the second preliminary seed value to the LFSR calculation unit;

  The LFSR calculation unit is a case where the second code detection unit detects the second code and the other descrambling corresponding to a predetermined number or more of the plurality of lanes The first preliminary seed output from the first preliminary seed calculation unit when the first code detection unit determines that the first code is detected by the first preliminary seed calculation unit. Can be updated with value.

  Thereby, even if the descrambling unit cannot unintentionally initialize the predetermined seed value, the reception status of the code (for example, the initialization code SR) in the entire lane is considered, The predetermined seed value can be updated with the preliminary seed value that has been initialized in advance.

  Further, the second preliminary seed calculation unit is a case where the second code is detected, and in the other descrambling unit corresponding to a predetermined number or more of the plurality of lanes. When it is determined that the first code is detected, the second preliminary seed value may be updated with the first preliminary seed value output from the first preliminary seed calculation unit.

  As a result, even if the descrambling unit erroneously receives a code different from the original code, the second preliminary seed value is set to the predetermined value in consideration of the code reception status in the entire lane. It becomes possible to match the seed value.

  In addition, the LFSR calculation unit may detect the second code in the other descrambling unit corresponding to a predetermined predetermined number or more of the plurality of lanes when the first code is detected. When it is determined that the second code is detected, the predetermined seed value may be updated with the second preliminary seed value output from the second preliminary seed calculation unit. On the other hand, the second backup LFSR calculation unit does not initialize the second backup seed value in response to the detection of the first code or the detection of the second code. , Continuing to update the second preliminary seed value.

  Thereby, even if the descramble unit erroneously receives a code different from the original code and initializes a predetermined seed value, the reception status of the code in the entire lane is considered, The predetermined seed value can be updated by the second spare LFSR that has been updated without being initialized.

  The descrambling unit may further include a code reception determination unit that determines that the first code is received based on a detection result by the code detection unit corresponding to each of the plurality of lanes. .

  The descrambling unit may further include a data enable signal detection unit that detects a transition of a data enable signal related to the image data sequence. The code reception determination unit receives the first code when the data enable signal detection unit determines that the data enable signal related to the image data sequence of the plurality of lanes has a first value. It can be determined that

  The first code and the second code may have a bit configuration similar to each other.

  Further, the present invention according to a certain aspect may be an image transmission system including the receiving device and a transmitting device that transmits the image data sequence to the receiving device via the plurality of lanes.

Further, the present invention according to a certain aspect may be a method of operating a receiving device of an image transmission system that transmits an image data sequence via a plurality of lanes. In the operating method, in each of the plurality of lanes, receiving an image data sequence scrambled based on LFSR; descrambling the received image data sequence based on LFSR;
Outputting the descrambled image data sequence. Further, the descrambling updates a predetermined seed value according to a clock cycle, while giving the updated current seed value to the LFSR to perform an LFSR operation, and receiving the received image data sequence Detecting at least one spare seed value that is common to the predetermined seed value and the initial value according to a period of the clock and updating the at least one spare current Outputting a seed value to the LFSR computing unit; initializing the predetermined seed value when a first code is detected as the predetermined code; and a first code as the predetermined code And if at least one of the second code is detected, initializing the at least one preliminary seed value; As a seed value of the constant is equal to a predetermined seed value in a predetermined number or more lanes of the plurality of lanes may include, and updating the predetermined seed value by the preliminary seed value.

  Calculating the at least one preliminary seed value includes calculating a first preliminary seed value that shares an initial value with the predetermined seed value according to the clock cycle; and calculating the predetermined preliminary seed value according to the clock cycle. Calculating a second preliminary seed value that shares a common seed value with the initial value.

  Also, initializing the at least one preliminary seed value is to initialize the first preliminary seed value when at least one of the first code and the second code is detected. Can include.

  In addition, the predetermined seed value is updated when the second code is detected, and the first code is detected in a predetermined number or more of the plurality of lanes. If it is determined that the predetermined seed value is updated with the first preliminary seed value.

  The at least one preliminary seed value is initialized when the second code is detected, and the first code in a predetermined number or more of the plurality of lanes And updating the second preliminary seed value with the first preliminary seed value.

  In addition, the predetermined seed value is updated when the first code is detected, and the second code is detected in a predetermined predetermined number or more of the plurality of lanes. If it is determined that the predetermined seed value is updated with the second preliminary seed value.

  In addition, the present invention according to a certain aspect can be a reception device of an image transmission system that transmits an image data sequence via a plurality of lanes. The receiving apparatus includes a descrambling unit that descrambles an image data sequence scrambled based on the LFSR based on the LFSR so as to correspond to each of the plurality of lanes. Each of the descrambling units includes a code detection unit that detects a predetermined code, an LFSR calculation unit that generates a random value by performing an LFSR calculation based on a predetermined seed value according to a clock cycle, and the predetermined code according to the clock cycle. A preliminary LFSR calculation unit that generates a preliminary random number value by performing a calculation of the preliminary LFSR based on the seed value of the LFSR, and outputs the preliminary random value. The LFSR calculation unit initializes the seed value when a first code is detected by the code detection unit. Further, the spare LFSR calculation unit can initialize the seed value of itself when at least one of the first code and the second code is detected by the code detection unit. The LFSR calculation unit converts the random number value of the LFSR calculation unit into the spare LFSR calculation unit so as to match a code detection result in another descrambling unit corresponding to a predetermined number or more of the plurality of lanes. It can be updated with the preliminary random number value calculated by.

  In this specification and the like, the means does not simply mean a physical means, but includes a case where the functions of the means are realized by software. Further, the function of one means may be realized by two or more physical means, or the functions of two or more means may be realized by one physical means.

  According to the present invention, even if a bit error occurs in a certain lane of an image transmission system using LFSR, and thus a disturbance of the image occurs, a bit can be transmitted at an early stage without waiting for a predetermined synchronization timing. Errors can be corrected, and image disturbance can be minimized.

  Other technical features, objects, and operational effects or advantages of the present invention will become apparent from the following embodiments described with reference to the accompanying drawings.

1 is a block diagram illustrating an image transmission system according to an embodiment of the present invention. It is a block diagram which shows the schematic structure of the descrambling part of the receiver which concerns on one Embodiment of this invention. It is a figure which shows an example of the image data sequence in the image transmission system which concerns on one Embodiment of this invention. It is a figure which shows an example of the reception estimation pattern of the initialization code in the image data sequence in the image transmission system which concerns on one Embodiment of this invention. It is a block diagram which shows an example of a structure of the initialization code reception determination part of the descrambling part which concerns on one Embodiment of this invention. It is a flowchart for demonstrating operation | movement of the descrambling part of the receiver which concerns on one Embodiment of this invention. It is a flowchart for demonstrating operation | movement of the descrambling part of the receiver which concerns on one Embodiment of this invention. It is a flowchart for demonstrating operation | movement of the descrambling part of the receiver which concerns on one Embodiment of this invention. It is a flowchart for demonstrating operation | movement of the descrambling part of the receiver which concerns on one Embodiment of this invention. It is a flowchart for demonstrating operation | movement of the descrambling part of the receiver which concerns on one Embodiment of this invention. It is a timing chart which shows the operation example of the descrambling part of the receiver which concerns on one Embodiment of this invention. It is a timing chart which shows the operation example of the descrambling part of the receiver which concerns on one Embodiment of this invention. It is a timing chart which shows the operation example of the descrambling part of the receiver which concerns on one Embodiment of this invention. It is a timing chart which shows the operation example of the descrambling part of the receiver which concerns on one Embodiment of this invention. It is a block diagram which shows the schematic structure of the descrambling part of the receiver which concerns on other embodiment of this invention.

  Embodiments of the present invention will be described below with reference to the drawings. However, the embodiment described below is merely an example, and there is no intention to exclude various modifications and technical applications that are not explicitly described below. The present invention can be implemented with various modifications (for example, by combining the embodiments) without departing from the spirit of the present invention. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. The drawings are schematic and do not necessarily match actual dimensions and ratios. In some cases, the dimensional relationships and ratios may be different between the drawings.

  FIG. 1 is a block diagram illustrating an image transmission system according to an embodiment of the present invention. As shown in the figure, the image transmission system 100 is a system designed in conformity with a predetermined data transmission interface, and includes, for example, a transmission device 110 as a source and a reception device 120 as a sink. The predetermined image data is transmitted / received via the predetermined transmission channel. The predetermined data transmission interface can be, for example, LVDS (Low Voltage Differential Signaling), PublishaPort, or the like. The image data is, for example, data configured in units of pixels, and a plurality of line data sequences configuring one frame are set as one frame image data. Each line data string may include several special codes depending on the data transmission interface, for example. In this example, the transmission device 110 and the reception device 120 are connected by a transmission channel having four lanes, that is, four differential signal line pairs, but is not limited thereto. For example, it can be composed of 8 lanes or 16 lanes. As will be described later, the transmission device 110 and the reception device 120 hold a common LFSR (linear feedback shift register) and operate so as to be synchronized (or reset) at a predetermined timing.

  The special code is, for example, a code added at a timing when data is to be enabled / disabled. As an example of a special code, a vertical synchronization code VSYN that indicates a vertical synchronization position, a horizontal synchronization code HSYN that indicates a horizontal synchronization position, a blanking start code BS that indicates the start of a blank position, and a blanking that indicates the end of a blank position There is an end code BE or the like. As will be described later, an initialization code SR for initializing (resetting) the seed value of the LFSR can be added to the image data as a special code at a predetermined timing during data transmission. For example, in a serial interface technique using a small amplitude differential signal, the initialization code SR is defined as “BE_SR (K28.0)”. In this case, the differential signal of the blanking end code BE (K28.2) is “0011110101/1100001010”, while the differential signal of the initialization code BE_SR (K28.0) is “0011110100/1100001011”. These are bit patterns that differ only in the least significant bit.

  The transmission device 110 is, for example, a device that converts image data to be displayed on a display device (not shown) into transmission data in a predetermined format and transmits the transmission data to the reception device 120. The transmission apparatus 110 includes, for example, a plurality of transmission processing units 111 corresponding to each of a plurality of lanes (only one transmission processing unit 111 is shown in the figure), and the plurality of transmission processing units 111. Each includes a scrambler 112, an 8B / 10B encoder 113, and a parallel / serial converter (hereinafter referred to as a “P / S converter”) 114, for example.

  The scrambler 112 performs random encoding on the transmitted image data of, for example, 8 bits / parallel format. Specifically, for example, the scramble unit 112 generates a random value based on the stored LFSR seed, performs an exclusive OR (EXOR) operation between the generated random value and the image data, and scrambled data Is generated. In this case, the scramble unit 112 adds or inserts the initialization code SR to the image data at a predetermined timing according to the LFSR. As an example, the scramble unit 112 adds the initialization code SR to the beginning of the frame (first of the first line) and a position (for example, the first of the 512th line) spaced a predetermined number of line intervals. The scrambler 112 sends the generated scramble data to the 8B / 10B encoder 113.

  The 8B / 10B encoding unit 113 converts the scrambled data into 10-bit format image data. Such data conversion is typically performed for high-speed serial data transmission. Specifically, the 8B / 10B encoding unit 113, for example, divides 8-bit image data such as 'HGFDDCBA' into 3 bits / 5 bits of 'HGF / EDCBA' according to a predetermined conversion table (not shown), A clock bit of 1 bit is added to each to convert it into 10-bit format image data (transmission image data) consisting of 6 bits / 4 bits of 'abcdei / fghj'. The 8B / 10B encoding unit 113 sends the converted transmission image data to the P / S conversion unit 114.

  The P / S converter 114 converts the parallel transmission image data into serial transmission image data. The P / S converter 114 outputs the converted serial image data for transmission to the corresponding lane. The P / S conversion unit 114 may include a buffer memory for parallel / serial conversion.

  The receiving device 120 is a device that receives, for example, image data transmitted from the transmitting device 110, restores the original image data, and outputs the original image data to a display device (not shown). The receiving apparatus 120 includes, for example, a plurality of reception processing units corresponding to each of a plurality of lanes (only one reception processing unit 121 is shown in the figure). Each includes a serial / parallel converter (hereinafter referred to as “S / P converter”) 122, an 8B / 10B decoder 123, and a descrambler 124.

  The S / P converter 122 converts the serial format transmission image data received from the corresponding lane into parallel format image data. The parallel-converted image data is 10-bit format data. The S / P conversion unit 122 sends the parallel-converted image data to the 8B / 10B decoding unit 123.

  The 8B / 10B decoding unit 123 converts the table 10-bit format image data into 8-bit format image data according to a predetermined conversion table. The 8B / 10B decoding unit 123 sends the converted image data to the descrambling unit 124 together with the control code (that is, the K code).

  The descrambling unit 124 descrambles the 8-bit / parallel format image data. The descrambling unit 124 generally generates a random value based on the stored seed value for the LFSR (linear feedback shift register), and performs an exclusive OR (EXOR) operation between the generated random value and the image data. To generate descrambling data (original image data). The descrambling unit 124 sends the restored image data to the display device. As will be described later, the descrambling unit 124 of this embodiment includes a mechanism for compensating for synchronization of transmission data between lanes.

  FIG. 2 is a block diagram illustrating a schematic configuration of the descrambling unit 124 of the receiving device 120 according to an embodiment of the present invention. This figure illustrates the schematic configuration of the descrambling unit 124 of the reception processing unit 121 in the 0th lane. In this connection, in order to distinguish that some of the signals in the figure are signals in the descrambling section 124 of the corresponding lane, numbers are added to the labels. When there is no need to distinguish, the number is omitted. In the following description, it is assumed that the data configuration bits of the initialization code SR are similar to the blanking end BE in the bit configuration. For example, when the bit configurations are different by only one to several bits, they are considered to be similar to each other and have a high possibility of being erroneously recognized when a bit error occurs.

  As shown in the figure, the descrambling unit 124 includes, for example, an initialization code detection unit (hereinafter referred to as “SR detection unit”) 1241 and a blanking end detection unit (hereinafter referred to as “BE detection unit”) 1242. , An initialization code reception determination unit (hereinafter referred to as “SR reception determination unit”) 1243, a data enable signal detection unit (hereinafter referred to as “DE signal detection unit”) 1244, an LFSR calculation unit 1245, and a first spare A seed calculation unit 1246, a second preliminary seed calculation unit 1247, and an EXOR operation unit 1248 are included.

  The SR detector 1241 detects the initialization code SR from the input image data string DATA_IN. Specifically, the SR detection unit 1241 sequentially fetches the image data string DATA_IN for each data block according to the K_IN signal indicating the K code, and determines whether or not the fetched data block is the initialization code SR. When the SR detection unit 1241 determines that the data block is the initialization code SR, the SR detection unit 1241 outputs the SR detection signal SR_D to the LFSR calculation unit 1245 and the first preliminary seed calculation unit 1246. The SR detection unit 1241 outputs the SR detection signal SR_D to its own SR reception determination unit 1243 and also determines the SR reception of the descrambling unit 124 in other lanes (first to third lanes in this example). Output to the unit 1243. The SR detection signal SR_D is output by, for example, transitioning the SR detection signal SR_D from a first value (for example, “L”) to a second value (for example, “H”).

  The BE detection unit 1242 detects a blanking end code BE from the input image data string DATA_IN. Specifically, the BE detection unit 1242 sequentially fetches the image data string DATA_IN for each data block according to the K_IN signal, and determines whether or not the fetched data block is a blanking end code BE. If the BE detection unit 1242 determines that the data block is the blanking code BE, it outputs a BE detection signal BE_D to the first preliminary seed calculation unit 1246. The BE detection signal BE_D is output, for example, by transitioning the BE detection signal BE_D from a first value (for example, “L”) to a second value (for example, “H”).

  The SR reception determination unit 1243 determines whether or not the descrambling unit 124 of each lane in the reception device 120 has received the initialization code SR at a predetermined time point. Specifically, the SR reception determination unit 1243, for example, when a rising edge of the data enable signal DE of all lanes is detected, is a predetermined number or more (for example, a majority or more) among the descrambling units 124 of all lanes. When the descrambling unit 124 determines that the initialization code SR has been received, it is determined that the initialization code SR has been received. When the SR reception determination unit 1243 determines that the initialization code SR has been received at this time, the SR seed calculation signal SEED_UPDATE indicating that the initialization code SR has been received is sent to the LFSR calculation unit 1245 and the second When output to the preliminary seed calculation unit 1247 while determining that the initialization code SR has not been received at that time, the second seed update signal SEED_UPDATE # indicating that the initialization code SR has not been received. Are output to the LFSR calculation unit 1245 and the second preliminary seed calculation unit 1247, respectively.

  In this embodiment, it is determined whether or not the initialization code SR has been received for the descrambling sections 124 of all lanes. However, the present invention is not limited to this. For example, the initialization code SR is received. Several descrambling units 124 for determination may be determined, and the descrambling unit 124 may be configured to determine whether or not the initialization code SR has been received. For example, when there are 16 lanes, the SR reception determination unit 1243 receives the SR detection signal from the descrambling unit 124 of the predetermined half of the 8 lanes, and whether the initialization code SR is received based on these SR detection signals. It may be determined whether or not.

  The DE signal detection unit 1244 detects that all the data enable signals DE in the receiving device 120 have reached a predetermined value. Specifically, the DE signal detection unit 1244 monitors the value of each data enable signal DE and, when detecting the rise of all the data enable signals DE, sends the all DE detection trigger signal DE_ALL_TRIG to the SR reception determination unit 1243. Output. The data enable signal DE is a signal indicating a first value (for example, “H”) between the beginning and the end of each line in one frame, for example.

  The LFSR operation unit 1245 holds an LFSR containing a predetermined polynomial, and generates a random value by giving the LFSR a seed value at that time calculated for each clock cycle. Further, when receiving the SR detection signal SR_D, the LFSR calculation unit 1245 initializes a seed value for the LFSR. That is, the seed value is reset to an initial value (for example, “FFFF”) by the initialization. In the present embodiment, when it is determined that there is a bit error, the LFSR calculation unit 1245 obtains the seed value at that time from one of the first preliminary seed calculation unit 1246 and the second preliminary seed calculation unit 1247. The random number value is generated based on the updated or rewritten seed value.

  The first preliminary seed calculation unit 1246 holds a seed value common to the LFSR calculation unit 1245, calculates the seed value for each clock cycle, and uses the seed value for the LFSR calculation unit 1245 and the second preliminary seed calculation unit 1246. Respectively. Here, the seed value calculated by the first preliminary seed calculation unit 1246 will be referred to as a first preliminary seed value. Further, upon receiving either the SR detection signal SR_D or the BE detection signal BE_D, the first preliminary seed calculation unit 1246 initializes the first preliminary seed value. That is, the first preliminary seed calculation unit 1246 initializes the first preliminary seed value even when a code having a bit configuration similar to the initialization code SR (in this example, the blanking code BE) is detected. Thus, when it is determined that there was a bit error later, the seed value in the LFSR calculation unit 1245 can be rewritten with the first preliminary seed value, and in addition to this, The second preliminary seed value of the second preliminary seed calculation unit 1247 can also be rewritten. The bit error here is, for example, a case where the initialization code SR has a bit error and is recognized as a code having a bit configuration similar to this (in this example, a blanking end code BE). Hereinafter, such a bit error is referred to as a bit error of the first form.

  The second preliminary seed calculation unit 1247 also holds the LFSR seed value common to the LFSR calculation unit 1245, calculates the seed value for each clock cycle, and outputs the seed value to the LFSR calculation unit 1245. Here, the seed value calculated by the second preliminary seed calculation unit 1247 will be referred to as a second preliminary seed value. It should be noted that the second spare seed calculation unit 1247 does not initialize the second spare LFSR, for example, while receiving one frame image data, regardless of whether or not the initialization code SR is received. It is. In this example, the second preliminary seed calculation unit 1247 initializes the seed value only at the beginning of one frame in accordance with, for example, standard technology. That is, when the transmission of the one-frame image data sequence is started, the second preliminary seed calculation unit 1247 does not initialize the second preliminary seed value, and thus there is a bit error later. If it is determined, the seed value in the LFSR calculation unit 1245 can be rewritten with the second preliminary seed value. The bit error here is, for example, a case where there is a bit error in the blanking end code BE and it is recognized as a code having a bit configuration similar to this (in this example, an initialization code SR). Hereinafter, such a bit error is referred to as a second type of bit error. Also, the second spare seed calculation unit 1247 also determines that the bit error of the first form has occurred in any lane, and also determines that the initialization code SR has been correctly received. The second preliminary seed value is rewritten with the first preliminary seed value output from the first preliminary seed calculation unit 1246.

  The EXOR operation unit 1248 performs an exclusive OR (EXOR) operation between the random value input from the LFSR operation unit and the image data sequence DATA_IN, restores the original image data sequence, and outputs this to the output image data sequence The data is output as DATA_OUT to a display device (not shown).

  In the present disclosure, the display device is not illustrated, but the display device is a device including a liquid crystal panel or an organic EL panel, for example, but is not limited thereto. Further, the display device may be configured separately from the receiving device 120 or may be configured as a part of the receiving device 120.

  FIG. 3 is a diagram for explaining an example of an image data string based on a serial interface technique using a small amplitude differential signal. The image data string to be transmitted is typically transmitted in a data block in units of pixels (3 bytes, 4 bytes, or 5 bytes). This figure shows a transmission code in the 3-Byte mode, and at a timing when the data enable signal DE rises, a predetermined special code (“VSYN H / L”, “HSYN H / L”, and “BE”). Or “BE_SR”). BE_SR is an initialization code, and is transmitted at the beginning of a frame and at an interval of 512 lines. The screen data body is transmitted while the data enable signal DE rises. A predetermined special code (“VSYN H / L”, “HSYN H / L”, “BS”) is transmitted at the timing when the data enable signal DE falls.

  As an example in which it is estimated that the initialization code SR (that is, “BE_SR” in the above technique) is received in the image data sequence, arrangement patterns of various data blocks (symbols) can be considered. FIG. 4 is a diagram illustrating an example of a reception estimation pattern of the initialization code SR in the image data sequence in the image transmission system according to the embodiment of the present invention. That is, FIG. 9A shows an example of estimation of reception of the initialization code SR in the case of the 3-Byte mode. Similarly, FIG. 5B shows an example of reception estimation of the initialization code SR in the 4-Byte mode, and FIG. 6B shows an example of reception estimation of the initialization code SR in the 5-Byte mode. Indicates. In the figure, the image data string in the first row shows a state where there is no bit error. Therefore, the SR detection unit 1241 described above can be configured to detect the initialization code SR in consideration of such a pattern. The same applies to the BE detection unit 1242.

  FIG. 5 is a block diagram showing an example of the configuration of the SR reception determination unit 1243 of the descrambling unit 124 according to an embodiment of the present invention.

  The SR reception determination unit 1243, when detecting the rising edge of the data enable signal DE for all lanes, for example, when receiving the all DE detection trigger signal DE_ALL_TRIG from the DE signal detection unit 1244, For example, when it is determined that the majority of descrambling units 124 of the units 124 have received the initialization code SR, it is determined that the initialization code SR has been received. As shown in the figure, the SR reception determination unit 1243 includes first to third adders 501a to 501c, a comparator 502, and an LFSR update signal output unit 503.

  Each of the first to third adders 501a to 501c adds two inputs and outputs the result. For example, when the SR detection signal SR_D0 has a first value (for example, “H”) and the SR detection signals SR_D1 to SR_D3 have a second value (for example, “L”), the output of the third adder 501c is , “1”.

  The comparator 502 receives the output of the third adder 501c, compares the input with a predetermined value, and if the input exceeds the predetermined value, the first value (eg, “H”) Is output, the second value (for example, “L”) is output. In this example, since the number of lanes is 4, the predetermined value is set to “2”.

  The seed update signal output unit 503 includes, for example, a first AND gate and a second AND gate. When the all-DE detection trigger signal DE_ALL_TRIG is detected, the seed update signal output unit 503 outputs outputs from the comparator 502 as seed update signals SEED_UPDATE and SEED_UPDATE #. Specifically, when the all DE detection trigger signal DE_ALL_TRIG is a first value (for example, “H”), the first AND gate 503a outputs the output from the comparator 502 as the first seed update signal SEED_UPDATE. On the other hand, the second AND gate 503b outputs a logical negation of the output from the comparator 502 as the second seed update signal SEED_UPDATE #. That is, the first seed update signal SEED_UPDATE is a pulse indicating that the initialization code SR is received, and the second seed update signal SEED_UPDATE # is a pulse indicating that the initialization code SR is not received. In this case, the first seed update signal SEED_UPDATE is logically negated. In other words, when the output from the comparator 502 is “H”, the first AND gate 503a outputs the first seed update signal SEED_UPDATE as “H”, and the second AND gate 503b When the output from 502 is “L”, the second seed update signal SEED_UPDATE # is output as “H”.

  6 to 10 are flowcharts for explaining the operation of the descrambling unit 124 of the receiving apparatus 120 according to an embodiment of the present invention. Specifically, FIG. The special code detection processing for the processed image data sequence is shown. FIG. 7 shows the processing of the LFSR calculation unit 1245 of the descrambling unit 124. 8 shows the processing of the first preliminary seed calculation unit 1246 of the descrambling unit 124, and FIG. 9 shows the processing of the second preliminary seed calculation unit 1247 of the descrambling unit 124. Further, FIG. 10 shows processing of the SR reception determination unit 1243 in the descrambling unit 124.

  First, referring to FIG. 6, the descrambling unit 124 receives an image data string DATA_IN (S601). Thereby, the SR detection unit 1241 of the descrambling unit 124 determines whether or not the initialization code SR is included in the image data string DATA_IN (S602a), while the BE detection unit 1242 determines whether the blanking end code is included. It is determined whether BE is included (S602b). When the SR detecting unit 1241 detects the initialization code SR (Yes in S602a), the SR detecting unit 1241 outputs an SR detection signal SR_D (S603a). Further, when the BE detection unit 1242 detects the blanking code BE (Yes in S602b), the BE detection signal BE_D is output (S603b).

  Next, referring to FIG. 7, the LFSR calculation unit 1245 first outputs the first preliminary seed value output from the first preliminary seed calculation unit 1246 and the second preliminary seed calculation unit 1247 output from the first preliminary seed calculation unit 1247. 2 preliminary seed values are received (S701). Further, the LFSR calculation unit 1245 determines whether or not the SR detection signal SR_D has been received (S702). When it is determined that the SR detection signal SR_D has been received (Yes in S702), the LFSR calculation unit 1245 initializes its own seed value (S703), and thereafter, based on the initialized seed value as described later. The LFSR calculation is performed (S708).

  When it is determined that the SR detection signal SR_D is not received (No in S702), the LFSR calculation unit 1245 subsequently checks the value of the seed update signal (704 and 706). That is, the LFSR calculation unit 1245 determines whether or not the first seed update signal SEED_UPDATE is a first value (eg, “H”) (S704), and the first seed update signal SEED_UPDATE is a first value. (Yes in S704), the current seed value is rewritten with the first preliminary seed value received from the first preliminary seed calculation unit 1246 (S705). When the LFSR calculation unit 1245 determines that the first seed update signal SEED_UPDATE is not the first value (No in S704), the second seed update signal SEED_UPDATE # is subsequently set to the first value (for example, It is determined whether or not it is “H”) (S706). If the LFSR calculation unit 1245 determines that the second seed update signal SEED_UPDATE # is the first value (Yes in S706), the second seed update unit 1247 receives the current seed value from the second preliminary seed calculation unit 1247. The preliminary seed value is rewritten (S707). On the other hand, when determining that the second seed update signal SEED_UPDATE # is not the first value (No in S706), the LFSR calculation unit 1245 does not rewrite its own seed value with the received preliminary seed value.

  Subsequently, the LFSR calculation unit 1245 performs LFSR calculation based on the current seed value (S708). That is, the LFSR calculation unit 1245 generates a random value by substituting the current seed value into a predetermined polynomial, and outputs this. Then, the LFSR calculation unit 1245 updates the seed value (S709). The seed value is updated by, for example, counting up, but is not limited to this.

  As described above, the LFSR calculation unit 1245 generates and outputs a random value by LFSR calculation based on the current seed value. When the SR detection signal SR_D is received, the LFSR calculation unit 1245 operates to reset the seed value. . In addition, the LFSR calculation unit 1245 operates to rewrite its own seed value with either the first preliminary seed value or the second preliminary seed value when the seed value is instructed by the seed update signal. To do.

  Next, referring to FIG. 8, first preliminary seed calculation unit 1246 includes at least one of SR detection signal SR_D output from SR detection unit 1241 and BE detection signal BE_D output from BE detection unit 1242. Is monitored (S801). If it is determined that at least one of the SR detection signal SR_D and the BE detection signal BE_D has been received (Yes in S801), the first preliminary seed calculation unit 1246 initializes the current first preliminary seed value (S802). ), And outputs the initialized first preliminary seed value to the LFSR calculation unit 1245 and the second preliminary seed calculation unit (S803). On the other hand, when it is determined that neither the SR detection signal SR_D nor the DE detection signal DE_D is received (No in S801), the first preliminary seed calculation unit 1246 uses the current first preliminary seed value as the LFSR calculation unit. It outputs to 1245 and the 2nd preliminary seed calculation part as it is (S803). The first preliminary seed value calculation unit 1246 updates the first seed value after outputting the first preliminary seed value (S804).

  As described above, when receiving at least one of the SR detection signal SR_D and the BE detection signal BE_D, the first preliminary seed calculation unit 1246 initializes the first preliminary seed value, and the initialized first seed Is output to the LFSR calculation unit 1245 and the second preliminary seed calculation unit, and when neither the SR detection signal SR_D nor the BE detection signal BE_D is received, the current first preliminary seed value is LFSR. It operates so as to output to the arithmetic unit 1245 and the second preliminary seed calculation unit as they are.

  Subsequently, referring to FIG. 9, second reserve seed calculator 1247 first receives the first reserve seed value output from first reserve seed calculator 1246 (S901). Next, the second preliminary seed calculation unit 1247 determines whether or not the second seed update signal SEED_UPDATE # is a first value (eg, “H”) (S902). When the second reserve seed calculation unit 1247 determines that the second seed update signal SEED_UPDATE # is the first value (Yes in S902), the current second reserve seed value is set to the first reserve seed value. (S903), and outputs the rewritten second seed value to the LFSR calculation unit 1245 (S904). On the other hand, when the second preliminary seed calculation unit 1247 determines that the second seed update signal SEED_UPDATE # is not the first value (No in S902), the current second seed value is directly input to the LFSR calculation unit 1245. It outputs (S905). The second preliminary seed value calculation unit 1247 updates the second seed value after outputting the second preliminary seed value (S905).

  As described above, when the second seed update signal SEED_UPDATE # is instructed by the second seed update signal SEED_UPDATE #, the second spare seed calculator 1247 uses the current second spare seed value as the first spare seed value. And when the rewriting of the seed value is not instructed, the current second preliminary seed value is sent to the LFSR calculation unit 1245 as it is. Operates to output.

  Although not shown in the figure, in the second preliminary seed calculation unit 1247, as described above, the seed value is initialized, for example, at the first time point of the frame image data sequence.

  Next, referring to FIG. 10, the DE signal detection unit 1244 of the descrambling unit 124 monitors whether or not the rising edge of the data enable signal DE of all lanes has been detected (S1001). If the DE signal detection unit 1244 determines that the rising edge of the data enable signal DE of all lanes has been detected (Yes in S1001), then the SR reception determination unit 1243 of the descrambling unit 124 It is determined whether a predetermined number or more of the descrambling units 124 among the descrambling units 124 have received the initialization code SR by the SR reception detection unit 1241 (S1002). When the SR reception determination unit 1243 of the descrambling unit 124 determines that the predetermined number or more of the descrambling units 124 among the descrambling units 124 of all the lanes have received the initialization code SR (Yes in S1002), 1 seed update signal SEED_UPDATE is output to each of the LFSR calculation unit 1245 and the second preliminary seed calculation unit 1247 (S1003). As a result, the LFSR calculation unit 1245 rewrites the current seed value with the first preliminary seed value output from the first preliminary seed calculation unit 1246, while the second preliminary seed calculation unit 1247 Own seed value (that is, the second preliminary seed value) is rewritten with the first preliminary seed value output from the first preliminary seed calculation unit 1246.

  On the other hand, the SR reception determination unit 1243 of the descrambling unit 124 receives the initialization code SR from the SR reception detection unit 1241 by a predetermined number or more of the descrambling units 124 among the descrambling units 124 of all lanes If it is determined that it has not been performed (No in S1002), the second seed update signal SEED_UPDATE # is output to the LFSR calculation unit 1245 and the second preliminary seed calculation unit 1247, respectively (S1004). As a result, the LFSR calculation unit 1245 rewrites the current seed value with the second preliminary seed value output from the second preliminary seed calculation unit 1246.

  As described above, the descrambling unit 124 performs an EXOR operation on the random number value generated by the LFSR operation unit 1245 and the corresponding data block of the image data string DATA_IN using the current seed value, and the result is obtained. Output as an image data string DATA_OUT.

  Next, an operation example of the descrambling unit 124 will be described. 11A and 11B are timing charts illustrating an example of the operation of the descrambling unit 124 of the receiving apparatus 120 according to an embodiment of the present invention. Specifically, FIG. The rewriting process of the seed value when the blanking end code BE is correctly received is described. FIG. B shows the seed when the initialization code SR is correctly received in each lane of the receiving device 120. The value rewriting process is described. In the figure, data and signals in descrambling sections 124 (0) to 124 (3) corresponding to each of the four lanes operating according to the clock LINK_CLK are shown. The numbers at the end of each label indicating these data and signals indicate the number of each lane.

  Referring to FIG. 5A, each of descrambling units 124 (0) to 124 (3) receives an image data string DATA_IN in accordance with clock LINK_CLK. In addition, the seed values SEED0 to SEED3, the first spare seed values SEED0_1 to SEED3_1, and the second spare seed values SEED0_2 to SEED3_2 in the descrambling units 124 (0) to 124 (3) are respectively sequentially according to the clock LINK_CLK. Has been updated. In the receiving apparatus 120, the occurrence of a unique skew in each lane cannot be ignored. Therefore, in this example, the 0th lane is delayed by one clock with respect to the 2nd lane and the 3rd lane. Is delayed by two clocks.

  First, since the descrambling unit 124 (2) for the second lane and the descrambling unit 124 (3) for the third lane have received the initialization code SR at time t1, the SR detection signals SR_D2 and SR_D3 are received at time t2. , Transition from “L” to “H”, respectively. Further, the descrambling unit 124 (2) for the second lane initializes the seed value SEED2 and the first preliminary seed value SEED2_1 to “FFFF”, respectively, and the descrambling unit 124 (3) for the third lane The seed value SEED3 and the first preliminary seed value SEED3_1 are respectively initialized to “FFFF”.

  Further, since descrambling section 124 (0) of the 0th lane has received initialization code SR at time t2, SR detection signal SR_D0 transitions from “L” to “H” at time t3. Also, the descrambling unit 124 (0) of the 0th lane initializes the seed value SEED0 and the first spare seed value SEED0_1 to “FFFF”, respectively.

  Similarly, the descrambling unit 124 (1) of the first lane that has received the initialization code SR at time t3 causes the SR detection signal SR_D1 to transition from “L” to “H” at time t4, and the seed value SEED1 and first preliminary seed value SEED1_1 are respectively initialized to “FFFF”.

  In the above situation, it is assumed that the data enable signals DE0 to DE3 of all the lanes transition from “L” to “H” at time t6. As a result, each of the descrambling units 124 (0) to 124 (3) determines whether or not a predetermined number or more of the descrambling units 124 in all lanes have received the initialization code SR based on the SR detection signals SR_D0 to SR_D3. The first seed update signal SEED_UPDATE # and the second seed update signal SEED_UPDATE # are generated. In this case, since the first seed update signal SEED_UPDATE is “H” in all the descrambling units 124, the seed values SEED0 to SEED3 are rewritten with the first preliminary seed values SEED0_1 to SEED3_1, respectively, and the second The preliminary seed values SEED0_2 to SEED3_2 are also rewritten with the first preliminary seed values SEED0_1 to SEED3_1, respectively. The descrambling units 124 (0) to 124 (3) thereafter continue to update from the rewritten seed values SEED0 to SEED3 and the second spare seed values SEED0_2 to SEED3_2, but in this example, the initialization code SR Therefore, even if rewriting occurs, the seed values SEED0 to SEED3 and the second preliminary seed values SEED0_2 to SEED3_2 are not substantially changed.

  Next, referring to FIG. B, first, at time t1, the descrambling unit 124 (2) of the second lane and the descrambling unit 124 (3) of the third lane received the blanking end code BE. At time t2, the descrambling unit 124 (2) of the second lane initializes the first preliminary seed value SEED2_1 to “FFFF”, and the descrambling unit 124 (3) of the third lane The preliminary seed value SEED3_1 is initialized to “FFFF”. In addition, the descrambling unit 124 (0) of the 0th lane that has received the blanking end code BE at time t2 initializes the first preliminary seed value SEED0_1 to “FFFF” at time t3. Similarly, the descrambling unit 124 (1) of the first lane that has received the blanking end code BE at time t3 initializes the first preliminary seed value SEED1_1 to “FFFF” at time t4. In this example, since each of the descrambling units 124 (0) to 124 (3) receives the blanking end code BE, the SR detection signals SR_D0 to SR_D3 remain “L”.

  In the above situation, it is assumed that the data enable signals DE0 to DE3 of all the lanes transition from “L” to “H” at time t6. As a result, each of the descrambling units 124 (0) to 124 (3) determines whether or not a predetermined number or more of the descrambling units 124 in all lanes have received the initialization code SR based on the SR detection signals SR_D0 to SR_D3. The first seed update signal SEED_UPDATE # and the second seed update signal SEED_UPDATE # are generated. In this case, since the second seed update signal SEED_UPDATE # is “H” in all the descrambling units 124, the seed values SEED0 to SEED3 are rewritten with the second preliminary seed values SEED0_2 to SEED3_2, respectively. The descrambling units 124 (0) to 124 (3) thereafter continue to update from the rewritten seed values SEED0 to SEED3. However, in this example, the blanking end code BE is correctly received. Even if this occurs, the seed values SEED0 to SEED3 are not substantially changed.

  12A and 12B are timing charts showing an example of the operation of the descrambling unit 124 of the receiving apparatus 120 according to an embodiment of the present invention. Specifically, FIG. The seed value rewriting process when the initialization code SR is recognized as a blanking end code BE due to a bit error (in the case of the bit error of the first form) is described, and FIG. In the 0th lane of the receiving device 120, the seed value rewriting process when the blanking end code BE is recognized as the initialization code SR due to a bit error (in the case of the bit error of the second form) will be described. ing.

  Referring to FIG. 3A, each descrambling unit 124 (0) to (3) receives the image data string DATA_IN according to the clock LINK_CLK. In this case, let us consider a case where the image data string DATA_IN0 received by the descrambling unit 124 (0) originally receives the initialization code SR but receives the blanking end code BE due to a bit error.

  First, at time t1, the descrambling unit 124 (2) for the second lane and the descrambling unit 124 (3) for the third lane receive the initialization code SR. Accordingly, the descrambling unit 124 (2) for the second lane and the descrambling unit 124 (3) for the third lane that have received the initialization code SR at time t2 change the SR detection signal SR from “L” to “H”. Transition to. Further, the descrambling unit 124 (2) for the second lane initializes the seed value SEED2 and the first preliminary seed value SEED2_1 to “FFFF”, respectively, and the descrambling unit 124 (3) for the third lane The seed value SEED3 and the first preliminary seed value SEED3_1 are respectively initialized to “FFFF”. The descrambling unit 124 (2) for the second lane and the descrambling unit 124 (3) for the third lane are respectively initialized with the seed values SEED2 and SEED3 and the first preliminary seed values SEED2_1 and SEED3_1 according to the clock LINK_CLK. Continue updating from.

  At time t2, descrambling section 124 (0) in the 0th lane is supposed to receive initialization code SR, but receives blanking end code BE due to a bit error. Therefore, the descrambling unit 124 (0) of the 0th lane does not cause the SR detection signal SR to transition to “L”. In addition, the descrambling unit 124 (0) that has received the blanking end code BE initializes the first preliminary seed value 0_1 to “FFFF” at the time point t3. The descrambler 124 (0) in the 0th lane continues updating from the initialized first preliminary seed value SEED0_1 according to the clock LINK_CLK.

  Further, since descrambling section 124 (1) of the first lane has received initialization code SR at time t3, the SR detection signal is transitioned from “L” to “H” at time t4. Further, the descrambling unit 124 (1) of the first lane that has received the initialization code SR initializes the seed value SEED1 and the first preliminary seed value SEED1_1 to “FFFF”, respectively. The descrambling unit 124 (1) of the first lane continues updating from the initialized seed value and the first preliminary seed value according to the clock LINK_CLK.

  In the above situation, it is assumed that the data enable signals DE0 to DE3 of all the lanes transition from “L” to “H” at time t6. As a result, each of the descrambling units 124 (0) to 124 (3) determines whether or not a predetermined number or more of the descrambling units 124 in all lanes have received the initialization code SR based on the SR detection signals SR_D0 to SR_D3. The first seed update signal SEED_UPDATE # and the second seed update signal SEED_UPDATE # are generated. In this example, the descrambling unit 124 (1) to 124 (3) receives the initialization code SR, while the descrambling unit 124 (0) does not receive the initialization code SR. The descrambling unit 124 (0) that has not received the code SR assumes that the initialization code SR should be received at the time t7, and sets the seed value SEED0 and the second spare seed value SEED0_2 to the first value. Rewrite with the preliminary seed value SEED0_1 of 1. In the figure, the seed value SEED0 is rewritten to “4” at time t7. Accordingly, thereafter, the descrambling unit 124 (0) continues to update from the rewritten seed value SEED0 and the second preliminary seed value SEED0_2.

  The descrambling units 124 (1) to 124 (3) that have correctly received the initialization code SR receive the seed values SEED1 to SEED3 and the second spare seed values SEED1_2 to SEED3_2 at the time t7 as the first spare seed. Rewrite with values SEED1_1 to SEED3_1, respectively.

  As described above, a bit error occurs in the image data string DATA_IN of a certain lane, and the descrambling unit 124 determines that a blanking end code BE different from the original code has been received, and initializes the seed value. Even if not, it is possible to return to the original seed value after initialization in consideration of the reception status of the image data string DATA_IN of other lanes. Thus, for example, the received image data string can be corrected without waiting until the timing determined by the data transmission standard (for example, the first of the first line of the frame or the first of the 512th line). Generation of noise in the image to the extent possible is prevented.

  Next, referring to FIG. B, in the image data string DATA_IN0 received by the descrambling unit 124 (0), the blanking end code BE should be received originally, but the initialization code SR was received due to a bit error. Think about the case.

  First, at time t1, the descrambling unit 124 (2) for the second lane and the descrambling unit 124 (3) for the third lane have received the blanking end code BE, so that the descrambling of the second lane at time t2. The unit 124 (2) initializes the first preliminary seed value SEED2_1 to “FFFF”, and the descrambling unit 124 (3) of the third lane initializes the first preliminary seed value SEED3_1 to “FFFF”. Turn into. The descrambling unit 124 (2) of the second lane and the descrambling unit 124 (3) of the third lane continue to be updated from the initialized first preliminary seed value SEED3_1. Similarly, the descrambling unit 124 (1) of the first lane that has received the blanking end code BE at time t3 initializes the first preliminary seed value SEED1_1 to “FFFF” at time t4. In this example, each of the descrambling units 124 (1) to 124 (3) receives the blanking end code BE, and therefore, the SR detection signals SR_D1 to SR_D3 in these remain at “L”.

  On the other hand, at time t2, descrambling section 124 (0) in the 0th lane should receive blanking end code BE, but has received initialization code SR due to a bit error. Therefore, at time t3, the descrambling unit 124 (0) of the 0th lane that has received the initialization code SR changes the SR detection signal SR_D0 from “L” to “H”. In addition, the descrambling unit 124 (0) initializes the seed value SEED0 and the first preliminary seed value SEED0_1 to “FFFF”, respectively. The descrambling unit 124 (0) continues updating from the initialized seed value SEED0 and the first preliminary seed value SEED0_1.

  In the above situation, it is assumed that the data enable signals DE0 to DE3 of all the lanes transition from “L” to “H” at time t6. As a result, each of the descrambling units 124 (0) to 124 (3) determines whether or not a predetermined number or more of the descrambling units 124 in all lanes have received the initialization code SR based on the SR detection signals SR_D0 to SR_D3. The first seed update signal SEED_UPDATE # and the second seed update signal SEED_UPDATE # are generated. In this example, only the descrambling unit 124 (0) receives the initialization code SR, and the remaining descrambling units 124 (1) to 124 (3) do not receive the initialization code SR. The descrambling unit 124 (0) that has not received the blanking end code BE assumes that the blanking end code BE should be received at the time t7, and sets the seed value SEED0 as the second spare seed. Rewrite with value SEED0_2. In the figure, the seed value SEED0 is rewritten to “n + 5” at time t7. Accordingly, the descrambling unit 124 (0) continues to update from the rewritten seed value SEED0 thereafter.

  As described above, a bit error occurs in the image data string DATA_IN of a certain lane, and the descrambling unit 124 determines that the initialization code SR different from the original code is received, and initializes the seed value. Even in this case, it is possible to return to the seed value before initialization in consideration of the reception status of the image data string DATA_IN of other lanes. Thus, for example, the received image data string can be corrected without waiting until the timing determined by the data transmission standard (for example, the first of the first line of the frame or the first of the 512th line). Generation of noise in the image to the extent possible is prevented.

  As described above, according to the present invention, the LFSR is unintentionally initialized, or even when the LFSR cannot be initialized unintentionally, the code (for example, initialization code) in the entire lane The seed value can be updated with the preliminary seed value calculated in advance, and the correct LFSR calculation can be performed based on the updated seed value.

  Therefore, according to the present invention, even if a bit error occurs in a certain lane of the image transmission system using the LFSR, and thus a disturbance of the image occurs, it is not necessary to wait until the specified synchronization timing. Therefore, it is possible to correct bit errors and minimize image disturbance.

  In the above example, each of the first preliminary seed calculation unit 1246 and the second preliminary seed calculation unit 1247 always outputs the preliminary seed value to the LFSR calculation unit 1245 according to the clock cycle. For example, triggered by reception of a seed update signal from the SR reception determination unit 1243, a preliminary seed value is output to the LFSR calculation unit 1245, and the LFSR calculation unit 1245 updates its own seed value with the received seed value. You may make it do.

  FIG. 13 is a block diagram illustrating a schematic configuration of a descrambling unit 124 ′ of a receiving apparatus 120 according to another embodiment of the present invention. In the figure, the same elements as those shown in FIG. 2 are denoted by the same reference numerals. The descrambling unit 124 ′ of the present embodiment includes a first backup LFSR calculation unit 1301 and a second backup LFSR calculation unit 1302 instead of the first backup seed calculation unit 1246 and the second backup seed calculation unit 1247. This is different from the descramble unit 124 shown in FIG. That is, each of the first reserve seed calculation unit 1246 and the second reserve seed calculation unit 1247 does not output the seed value to the LFSR calculation unit 1245 ′ but outputs the reserve random number value to the LFSR calculation unit 1245 ′. , The LFSR operation unit 1245 ′ rewrites the random value itself according to the seed update signal. As a result, the LFSR calculation unit 1245 ′ may not receive the predetermined special code because of a bit error and does not initialize the seed value, or receives the predetermined special code and initializes the seed value unintentionally. Even when a random value is generated based on the seed value, it can be restored to a correct random value.

  In the above example, each of the first backup LFSR calculation unit 1301 and the second backup LFSR calculation unit 1302 always outputs the backup random number value to the LFSR calculation unit 1245 ′ according to the clock. For example, triggered by reception of the seed update signal, the preliminary random number value is output to the LFSR calculation unit 1245 ′, and the LFSR calculation unit 1245 ′ may update its own random number value with the received preliminary random number value. good.

  Each of the above embodiments is an example for explaining the present invention, and is not intended to limit the present invention only to these embodiments. The present invention can be implemented in various forms without departing from the gist thereof.

  For example, in the method disclosed herein, steps, operations, or functions may be performed in parallel or in a different order, as long as the results do not conflict. The steps, operations, and functions described are provided as examples only, and some of the steps, operations, and functions may be omitted and combined with each other without departing from the spirit of the invention. There may be one, and other steps, operations or functions may be added.

  Further, although various embodiments are disclosed in this specification, specific features (technical matters) in one embodiment are added to other embodiments while appropriately improving the other features, or other Specific features in the embodiments can be replaced, and such forms are also included in the gist of the present invention.

  The present invention can be widely used in the field of image transmission systems.

DESCRIPTION OF SYMBOLS 100 ... Image transmission system 110 ... Transmission apparatus 111 ... Transmission processing part 112 ... Scramble part 113 ... 8B / 10B encoding part 114 ... Parallel / serial conversion part 120 ... Reception apparatus 121 ... Reception processing part 122 ... Serial / parallel conversion part 123 ... 8B / 10B decoding part 124 ... descrambling part 1241 ... initialization code detecting part 1242 ... blanking end detecting part 1243 ... SR reception determining part 1244 ... DE signal detecting part 1245 ... LFSR calculating part 1246 ... first preliminary seed Calculation unit 1247 ... second preliminary seed calculation unit 1248 ... EXOR operation units 501a to 501c ... first to third adders 502 ... comparator 503 ... LFSR update signal output unit 503a ... first AND gate 503b ... first AND gate 1301 of the first spare LFSR operation unit 302 ... second preliminary LFSR operation unit

Claims (15)

A receiving device of an image transmission system for transmitting an image data string through a plurality of lanes,
A descrambling unit corresponding to each of the plurality of lanes, and descrambles an image data sequence scrambled based on the LFSR based on the LFSR;
Each said descrambling part is
A code detector for detecting a predetermined code;
An LFSR operation unit that updates a predetermined seed value according to a cycle of the clock, and supplies the updated current seed value to the LFSR to perform an LFSR operation;
According to the cycle of the clock, the at least one reserve seed value that shares the initial value with the predetermined seed value is updated, and the at least one reserve seed value that is updated is output to the LFSR calculation unit. And comprising
The LFSR calculation unit
When the first code is detected by the code detection unit, the predetermined seed value is initialized to return to the initial value,
The preliminary seed calculation unit includes:
When at least one of the first code and the second code is detected by the code detection unit, the at least one preliminary seed value is initialized to return to the initial value,
The LFSR calculation unit
The predetermined value of the self is set so that the predetermined seed value of the self coincides with a predetermined seed value of the LFSR calculation unit in the other descrambling unit corresponding to a predetermined number or more of the plurality of lanes. Updating a seed value with the at least one preliminary seed value;
Receiver device. The spare LFSR calculation unit
Calculating a first preliminary seed value that shares the predetermined seed value and the initial value in accordance with a cycle of the clock, and outputting the first preliminary seed value to the LFSR calculation unit;
A second preliminary seed calculation unit that calculates a second preliminary seed value that shares the predetermined seed value and an initial value in accordance with a cycle of the clock and outputs the second preliminary seed value to the LFSR calculation unit,
The first preliminary seed calculation unit includes:
Outputting the calculated first preliminary seed value to the second preliminary seed calculation unit;
Initializing the first preliminary seed value when at least one of the first code and the second code is detected;
The receiving device according to claim 1.   The LFSR calculation unit is a case where the second code is detected, and the first code is transmitted to the other descrambling unit corresponding to a predetermined number or more of the plurality of lanes. The receiving apparatus according to claim 2, wherein when it is determined that the predetermined seed value has been detected, the predetermined seed value is updated with the first preliminary seed value output from the first preliminary seed calculation unit. The second spare seed calculation unit is a case where the second code is detected, and the other descrambling unit corresponding to a predetermined number of lanes or more of the plurality of lanes When it is determined that one code is detected, the second preliminary seed value is updated with the first preliminary seed value output from the first preliminary seed calculation unit.
The receiving device according to claim 3. The LFSR calculation unit is the case where the first code is detected, and the second code in the other descrambling unit corresponding to a predetermined predetermined number or more of the plurality of lanes. The predetermined seed value is updated with the second preliminary seed value output from the second preliminary seed calculation unit.
The receiving device according to claim 3 or 4. The second backup LFSR calculation unit does not initialize the second backup seed value in response to the detection of the first code or the detection of the second code. Continue updating the second preliminary seed value;
The receiving device according to claim 2. The descrambling unit further includes a code reception determination unit that determines that the first code is received based on a detection result by the descrambling unit and the code detection unit respectively corresponding to the plurality of lanes.
The receiving device according to claim 2. The descrambling unit further includes a data enable signal detection unit that detects a transition of a data enable signal related to the image data sequence,
The code reception determination unit determines that the first code has been received when the data enable signal detection unit determines that the data enable signal related to the image data sequence of the plurality of lanes has a first value. judge,
The receiving device according to claim 7.   The receiving apparatus according to claim 2, wherein the first code and the second code have bit configurations similar to each other. A receiving device according to any one of claims 1 to 9;
A transmitting device that transmits the image data sequence to the receiving device via the plurality of lanes;
An image transmission system comprising: An operation method of a receiving device of an image transmission system for transmitting an image data string through a plurality of lanes,
Receiving an image data sequence scrambled based on LFSR in each of the plurality of lanes;
Descrambling the received image data sequence based on the LFSR;
Outputting the descrambled image data sequence;
The descrambling is
Updating a predetermined seed value according to a cycle of the clock, while giving an updated current seed value to the LFSR to perform an LFSR operation;
Detecting a predetermined code from the received image data sequence;
According to the period of the clock, at least one reserve seed value that shares the initial value with the predetermined seed value is updated, and the updated at least one reserve seed value is output to the LFSR calculation unit. And
Initializing the predetermined seed value when a first code is detected as the predetermined code;
Initializing at least one preliminary seed value when at least one of a first code and a second code is detected as the predetermined code;
Updating the predetermined seed value with the preliminary seed value such that the predetermined seed value matches a predetermined seed value in a predetermined number or more of the plurality of lanes;
including,
Actuation method. Calculating the at least one preliminary seed value comprises:
Calculating a first preliminary seed value that shares the initial value with the predetermined seed value according to a period of the clock;
Calculating a second preliminary seed value that shares an initial value with the predetermined seed value according to a period of the clock,
Initializing the at least one preliminary seed value includes initializing the first preliminary seed value when at least one of the first code and the second code is detected. Including,
The operating method according to claim 11. The updating of the predetermined seed value is when the second code is detected, and it is determined that the first code is detected in a predetermined number or more of the plurality of lanes. Updating the predetermined seed value with the first preliminary seed value, if
The operating method according to claim 12. The initialization of the at least one spare seed value is when the second code is detected, and the first code is detected in a predetermined number or more of the plurality of lanes. Updating the second reserve seed with the first reserve seed value if determined to have been
The operating method according to claim 13. The predetermined seed value is updated when the first code is detected, and when the second code is detected in a predetermined predetermined number or more of the plurality of lanes. If determined, including updating the predetermined seed value with the second preliminary seed value;
15. The operating method according to claim 13 or 14.