KR102448062B1 - Display Device, Virtual reality Display Device and Method of Driving the same - Google Patents

Abstract

The present invention provides a device that is robust to environmental problems (such as clock asynchronization between devices due to ESD) that may occur in an interface connected to a system in order to improve the stable image implementation capability and can support stable duty driving will be.
To this end, in the present invention, the internal clock signal is recovered by controlling the internal clock generator in a section where the external clock signal does not normally come in.

Description

Display Device, Virtual Reality Display Device and Method of Driving the Same

The present invention relates to a display device, a virtual reality display device, and a driving method thereof.

As information technology develops, the market for display devices, which is a connection medium between users and information, is growing. Accordingly, organic light emitting display (OLED), quantum dot display (QDD), liquid crystal display (LCD), plasma display (PDP), etc. The use of the same display device is increasing.

The display device described above includes a display panel including a plurality of sub-pixels, a driving unit outputting a driving signal for driving the display panel, and a power supply unit generating power to be supplied to the display panel and the driving unit.

Display devices are implemented in small, medium or large sizes such as TVs, set-top boxes, navigation devices, video players, Blu-ray players, personal computers (PCs), wearables, home theaters, mobile phones, and virtual reality (VR) display devices. do.

On the other hand, the virtual reality display device can immerse the user in an environment that reproduces reality as it is. To this end, the user wears equipment that can exchange information, such as goggles, headsets, gloves, and special clothes, and is exposed to the virtual environment created by the system (eg, a computer, etc.).

However, in the conventionally proposed virtual reality display device, it is necessary to design a device that is robust to environmental problems (such as clock asynchronization between devices due to ESD) that may occur in the interface connected to the system in order to improve the stable image implementation capability. have.

The present invention for solving the problems of the above-mentioned background art is robust and stable to environmental problems (eg, clock asynchronization between devices due to ESD) that may occur in the interface connected to the system in order to improve the stable image implementation capability. It is to provide a device capable of supporting duty driving.

As a means of solving the above problems, the present invention provides a display device including a display panel and a clock signal compensation circuit unit. The display panel displays an image. The clock signal compensation circuit unit drives the display panel and includes an internal clock generator that generates an internal clock signal for driving a device provided therein based on an external clock signal, and an internal clock generator in a section where the external clock signal does not normally come in. Control to recover the internal clock signal.

The clock signal compensation circuit unit compares and counts the external clock signal and the internal clock signal during the display period in which the display panel displays an image, and the internal clock signal during the blank period in which the display panel does not display an image in the period in which the external clock signal is not normally received. signal can be restored.

The clock signal compensation circuit unit compares and counts the register unit having register values corresponding to the frequency information, the external clock signal and the internal clock signal, and recovers the internal clock signal to one of the register values in a section where the external clock signal does not normally come in. It may include a signal comparison and compensating unit.

The register unit may have a first register value composed of fixed frequency information and a second register value composed of changed frequency information.

In another aspect, the present invention provides a virtual reality display device including a display panel, a system, and a panel driver including a display panel, a system, and a panel driver. The display panel displays an image. The system has a MIPI transmitter. The panel driver has a MIPI receiver that receives data transmitted through the MIPI transmitter and drives the display panel. The panel driver includes an internal clock generator that generates an internal clock signal for driving an internally provided device based on the external clock signal transmitted from the MIPI transmitter, and controls the internal clock generator in a section where the external clock signal does not normally come in. and a clock signal compensation circuit unit for recovering the clock signal.

The clock signal compensation circuit unit compares and counts the external clock signal and the internal clock signal during the display period in which the display panel displays an image, and the internal clock signal during the blank period in which the display panel does not display an image in the period in which the external clock signal is not normally received. signal can be restored.

The clock signal compensation circuit unit compares and counts the register unit having register values corresponding to the frequency information, the external clock signal and the internal clock signal, and recovers the internal clock signal to one of the register values in a section where the external clock signal does not normally come in. It may include a signal comparison and compensating unit.

The register unit may have a first register value composed of fixed frequency information and a second register value composed of changed frequency information.

In another aspect, the present invention provides a method of driving a virtual reality display device. A method of driving a virtual reality display device includes: receiving a signal including an external clock signal; Comparing and counting the external clock signal and the internal clock signal, and restoring the internal clock signal to one of the register values stored in the internal register unit in a section in which the external clock signal does not normally enter.

In the step of recovering the frequency, the internal clock signal may be recovered based on the fixed frequency information or the changed frequency information stored in the register unit.

Since the present invention manufactures a virtual reality display device based on a display device capable of variable duty, it is possible to increase visual response speed or motion picture response time (MPRT), thereby improving the ability to implement a virtual environment. In addition, the present invention has an effect of providing a device that is robust to environmental problems (eg, clock asynchronization between devices due to ESD) that may occur in an interface connected to the system in order to improve the stable image implementation capability. In addition, the present invention has an effect of providing a device capable of generating a clock signal for supporting stable duty driving by itself.

1 is a block diagram schematically illustrating a display device according to an embodiment of the present invention;
FIG. 2 is a configuration diagram schematically illustrating the sub-pixel shown in FIG. 1;
3 is a view showing a part of a virtual reality display device.
4 is a block diagram of a system and a panel driving unit of a virtual reality display device according to an experimental example.
FIG. 5 is a packet waveform diagram for explaining a clock transmission method between the system of FIG. 4 and a panel driver;
6 is a gate signal waveform diagram for explaining the problems of the experimental example.
7 is a display state diagram of a display panel according to a problem in an experimental example;
8 is a block diagram of a system and a panel driver of a virtual reality display device according to a first embodiment of the present invention.
9 is a block diagram for explaining a main configuration of a panel driving unit;
10 is a gate signal waveform diagram for explaining an improvement point according to the first embodiment of the present invention;
11 is a display state diagram of a display panel according to an improvement according to the first embodiment;
Fig. 12 is a driving flowchart of the apparatus according to the first embodiment;
13 is a block diagram for explaining a main configuration of a panel driving unit according to a second embodiment of the present invention;

Hereinafter, specific details for carrying out the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram schematically showing a display device according to an embodiment of the present invention, and FIG. 2 is a configuration diagram schematically illustrating the sub-pixel shown in FIG. 1 .

1 , the display device basically includes a host system 100 , a timing controller 170 , a data driver 130 , a power supply 140 , a gate driver 150 , and a display panel 110 . do.

The host system 100 includes a system on chip (SoC) having a built-in scaler, and converts digital video data of an input image into a data signal having a format suitable for display on the display panel 110 . The host system 100 supplies various timing signals along with the data signal to the timing controller 170 .

The timing controller 170 operates the data driver 130 and the gate driver 150 based on timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a main clock signal input from the host system 100 . Control the timing.

The timing controller 170 supplies the data signal input from the host system 100 to the data driver 130 after image processing (data compensation, etc.).

The data driver 130 operates in response to the first driving signal DDC output from the timing controller 170 . The data driver 130 converts the digital data signal DATA input from the timing controller 170 into an analog data signal and outputs it.

The data driver 130 converts the digital data signal DATA into an analog data signal in response to the gamma voltage of the gamma unit provided inside or outside. The data driver 130 supplies data signals to the data lines DL1 to DLn of the display panel 110 .

The gate driver 150 operates in response to the second driving signal GDC output from the timing controller 170 . The gate driver 150 outputs a gate signal (or scan signal) of a gate high voltage or a gate low voltage.

The gate driver 150 may sequentially output the gate signal in a forward direction or sequentially output the gate signal in a reverse direction. The gate driver 150 supplies a gate signal to the gate lines GL1 to GLm of the display panel 110 .

The power supply 140 outputs the first voltage sources VCC and GND for driving the data driver 130 and the like and the second voltage sources EVDD and EVSS for driving the display panel 110 . In addition, the power supply unit 140 generates a voltage necessary for driving the display device, such as a gate high voltage or a gate low voltage to be transmitted to the gate driver 150 .

The display panel 110 includes sub-pixels SP, data lines DL1 to DLn connected to the sub-pixels SP, and gate lines GL1 to GLm connected to the sub-pixels SP. The display panel 110 displays an image corresponding to the gate signal output from the gate driver 150 and the data signal DATA output from the data driver 130 . The display panel 110 includes a lower substrate and an upper substrate. The sub-pixels SP are formed between the lower substrate and the upper substrate.

As shown in FIG. 2 , one sub-pixel is supplied through the switching thin film transistor SW and the switching thin film transistor SW connected to (or formed at the intersection of) the gate line GL1 and the data line DL1. A pixel circuit PC operating in response to the data signal DATA is included.

The display panel 110 is implemented as a liquid crystal display panel or an organic light emitting display panel according to the configuration of the pixel circuit PC of the sub-pixels SP. For example, when the display panel 110 is implemented as a liquid crystal display panel, it is a TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode, FFS (Fringe Field Switching) mode, or ECB (Electrically) mode. Controlled Birefringence) mode.

As another example, when the display panel 110 is implemented as an organic light emitting display panel, it operates in a top-emission method or a bottom-emission method.

As the display panel of the above-described display device, a liquid crystal display panel, an organic light emitting display panel, an electrophoretic display panel, a plasma display panel, or the like may be selected. However, hereinafter, for convenience of description, a display device in which the display panel includes an organic light emitting display panel is exemplified.

In addition, the display devices described above are small, medium-sized, such as a TV, a set-top box, a navigation system, an image player, a Blu-ray player, a personal computer (PC), a wearable, a home theater, a mobile phone, and a virtual reality display device (VR). Or it can be implemented in a large format. However, the display device described below has a greater advantage when realizing a virtual reality display device based on a display device having an organic light emitting display panel.

3 is a diagram illustrating a part of a virtual reality display device.

As shown in FIG. 3 , the virtual reality display device includes left eye display drivers 180L, 150L, LAA for displaying images in the left eye direction and right eye display drivers 180R, 150R and RAA for displaying images in the right eye direction. do.

The left-eye display drivers 180L, 150L, and LAA and the right-eye display drivers 180R, 150R, and RAA include panel drivers 180L and 180R, gate drivers 150L and 150R, and displays LAA and RAA.

The panel drivers 180L and 180R control the gate drivers 150L and 150R and serve to supply data signals to the display units LAA and RAA. The panel drivers 180L and 180R are integrated circuits (ICs) in which the timing controller 170 and the data driver 130 of FIG. 1 are integrated. The panel driving units 180L and 180R may further include the power supply unit 150 of FIG. 1 .

Meanwhile, in FIG. 3 , the left eye display drivers 180L, 150L, LAA for displaying an image in the left eye direction and the right eye display drivers 180R, 150R, and RAA for displaying an image in the right eye direction are separated as an example, but this is one example. This is only an example, but is not limited thereto.

The virtual reality display device as described above can immerse the user in an environment that mimics and reproduces reality as it is. To this end, the user wears equipment that can exchange information, such as goggles, headsets, gloves, and special clothes, and is exposed to the virtual environment created by the system (eg, a computer, etc.).

Hereinafter, an exemplary embodiment of the present invention capable of improving the problem of the conventionally proposed virtual reality display device by making an experiment, and based on this, the capability of the device can be improved will be described.

4 is a block diagram of a system of a virtual reality display device and a panel driver according to an experimental example, FIG. 5 is a packet waveform diagram for explaining a clock transmission method between the system of FIG. 4 and a panel driver, and FIG. 6 is a problem of the experimental example is a gate signal waveform diagram for explaining the , and FIG. 7 is a display state diagram of the display panel according to the problem of the experimental example.

In the experimental example, a virtual reality display device is implemented based on an organic light emitting display device. The organic light emitting diode display has a driving characteristic of emitting light (ON) or non-emission (OFF) of an organic light emitting diode of a sub-pixel in units of gate lines (or scan lines) or frames.

Due to such driving characteristics, the organic light emitting display device can increase the visual response speed or the motion picture response time (MPRT) when realizing the virtual reality display device, and as a result, the ability to implement a virtual environment compared to other devices has been shown to be able to improve

However, in order to emit light (ON) or non-emission (OFF) the organic light emitting diode, a function capable of varying the duty is required. According to the experimental results of a virtual reality display device manufactured based on an organic light emitting display device capable of variable duty, a signal capable of driving the gate driver is continuously output during a blank section in which the display panel does not display an image. Failure to do so may result in poor image quality.

Hereinafter, the problem of the virtual reality display device according to the experimental example will be described in more detail.

As shown in FIG. 4 , in the virtual reality display device according to the experimental example, the system 100 and the panel driving unit 180 in which the timing control unit 170 (T-CON) and the data driving unit 130 (Source) of FIG. 1 are integrated. is included

The system 100 includes the MIPI transmitter 101 and the panel driver 180 includes the MIPI receiver 181 . That is, the system 100 (Master) and the panel driver 180 (Peripheral) are connected to a MIPI-based communication interface (hereinafter abbreviated as MIPI).

The system 100 transmits the clock signal CLK P/N and the data signal DATA P/N in the form of a differential or differential signal combined with positive polarity and negative polarity through MIPI, and the panel driver 180 ) receives it.

The panel driver 180 includes a MIPI receiver 181 , an internal clock generator 183 , a timing controller 170 , a gate controller 185 , and a data driver 130 .

The MIPI receiver 181 receives the signal output through the MIPI transmitter 101, restores it, and transmits it to a device (eg, an internal clock generator, a timing controller) provided inside the panel driver 180 .

The internal clock generator 183 receives the MIPI clock signal transmitted from the MIPI receiver 181 and based on the received internal clock signal (internal clock signal) for driving a device (eg, a timing controller) provided inside the panel driver 180 . OSC) is created.

The timing controller 170 performs synchronization for outputting the data signal transferred from the MIPI receiver 181 based on the internal clock signal (internal OSC) transferred from the internal clock generator 183 .

The timing controller 170 generates a gate timing signal and a data timing signal for synchronizing and driving the driving timings of the gate controller 185 and the data driver 130 based on the internal clock signal (internal OSC). The timing controller 170 generates a control signal for compensating a data signal or controlling a division ratio of the internal clock generator 183 based on a logic block provided therein.

The gate control unit 185 includes a gate high voltage VGH, a gate low voltage VGL, and a clock signal CLK for controlling the gate driver in response to a synchronization signal such as a gate timing signal transmitted from the timing control unit 170 . to output

The data driver 130 converts a digital data signal into an analog data signal DATA in response to a synchronization signal such as a data timing signal transmitted from the timing controller 170 and outputs the converted data signal DATA.

As shown in FIG. 5 , the MIPI coupled between the system 100 and the panel driver 180 includes a clock lane (using one clock line) for transmitting a clock signal and a data lane (using one clock line) for transmitting a data signal. data lane) (using 1 to 4 data lines). The signal transmission method using MIPI has two clock modes, and their characteristics are described as follows.

Referring to the clock lane shown in (a) of FIG. 5 , in the continuous mode, the MIPI clock signal is continuously output even during a blank period in which the display panel does not display an image.

On the other hand, referring to the clock lane shown in (b) of FIG. 5, the non-continuous mode does not output the MIPI clock signal during the blank period, and LPS (Low Power Stop) state (LPS). LPS is a mode in which all data is sent and the remaining section waits to reduce power consumption.

In addition, in the waveform of FIG. 5, SOT (Start of Transmission) and EOT (End of Transmission) mean a section separating the beginning and the end of an actually transmitted data packet, and HS (high speed) (HS transmission section). ) means a section in which data packets are transmitted in high-speed mode. Although not shown, unlike the HS mode, there is also an LP (Low power) mode for transmitting in a low power consumption mode.

As can be seen from the waveform of FIG. 5, when the virtual reality display device according to the experimental example uses the non-continuous mode among the MIPI signal transmission system, the signal required for driving the display panel during the blank section is provided. It cannot be created continuously.

As a result of the simulation, when the duty of the gate driver is varied in this way, the image quality of the display panel may be deteriorated due to a clock unsynchronization problem. That is, when the virtual reality display device is based on a system that supports only a non-continuous mode, it is difficult to achieve a stable image quality as well as poor image quality.

Contrary to this, the continuous mode can continuously output the MIPI clock signal even during the blank section, so there is an advantage in stably realizing an image compared to the non-continuous mode. However, in the case of the continuous mode, when an external shock occurs during the blank section, the MIPI clock signal is momentarily unstable.

As shown in FIGS. 4 and 6, in the experimental example, when an external shock (eg, static electricity = ESD) occurs, the MIPI clock signal momentarily becomes unstable, and the internal clock generator 183 controls the timing controller 170 ), etc., the internal clock signal to be supplied cannot be output normally (abnormal state).

Due to this influence, the timing controller 170 also cannot output a synchronization signal such as a gate timing signal in a normal form. As a result, the gate driver cannot normally output the gate signal after an external shock (eg, static electricity = ESD) occurs.

As can be seen from FIG. 6 , in the device of the experimental example, there is no preparation for an environmental problem that may occur in the interface (eg, a problem of clock synchronization between devices due to ESD).

Environmental problems that may occur in the interface are non-continuous mode and there is no contrast. Therefore, the method as in the experimental example, without distinction between the non-continuous mode and the continuous mode, affects the signal generation of the gate driver and the like.

As a result, in the experimental example, an abnormal image is displayed on the display panel 110 as shown in FIG. 7 , a line is formed in a specific line momentarily, or flickering is caused by an environmental problem that may occur in the interface. When image quality is defective, it cannot be recovered in a short time.

In the above experimental example, since a virtual reality display device is manufactured based on an organic light emitting display device capable of variable duty, the visual response speed or motion picture response time (MPRT) can be increased. It has been shown that the ability to implement the environment can be improved.

However, in the experimental example, it is necessary to design a device that is robust to environmental problems that may occur in the interface connected to the system (eg, clock asynchronization problem between devices due to ESD) in order to improve the stable image implementation capability. In addition, in the experimental example, it is necessary to design a device capable of independently generating a clock signal to stably support duty driving.

<First embodiment>

8 is a block diagram of a system of a virtual reality display device and a panel driving unit according to a first embodiment of the present invention, FIG. 9 is a block diagram illustrating the main configuration of the panel driving unit, and FIG. 10 is a first embodiment of the present invention. It is a gate signal waveform diagram for explaining an improvement point according to the embodiment, FIG. 11 is a display state diagram of a display panel according to the improvement point according to the first embodiment, FIG. 12 is a driving flowchart of the device according to the first embodiment, 13 is a block diagram for explaining the main configuration of the panel driving unit according to the second embodiment of the present invention.

As shown in FIG. 8 , the virtual reality display device according to the first embodiment of the present invention includes the system 100 and the timing control unit 170 (T-CON) and the data driving unit 130 (Source) of FIG. 1 are integrated. A panel driver 180 is included.

The system 100 includes the MIPI transmitter 101 and the panel driver 180 includes the MIPI receiver 181 . That is, the system 100 (Master) and the panel driver 180 (Peripheral) are connected to a MIPI-based communication interface (hereinafter abbreviated as MIPI).

The system 100 transmits the clock signal CLK P/N and the data signal DATA P/N in the form of a differential or differential signal combined with positive polarity and negative polarity through MIPI, and the panel driver 180 ) receives it.

The panel driver 180 includes a MIPI receiver 181 , an internal clock generator 183 , a signal comparison and compensator 187 , a register 188 , a timing controller 170 , a gate controller 185 , and a data driver ( 130) are included.

The MIPI receiver 181 receives the signal output through the MIPI transmitter 101, restores it, and transmits it to a device (eg, an internal clock generator, a timing controller) provided inside the panel driver 180 .

The internal clock generator 183 receives the MIPI clock signal transmitted from the MIPI receiver 181 and based on the received internal clock signal (internal clock signal) for driving a device (eg, a timing controller) provided inside the panel driver 180 . OSC) is created.

The signal comparison and compensator 187 receives the MIPI clock signal transmitted from the MIPI receiver 181 and the internal clock signal (internal OSC) output from the internal clock generator 183 . The signal comparison and compensator 187 compares the MIPI clock signal and the internal clock signal (internal OSC) and performs a compensation operation to recover (restore) the internal clock signal (internal OSC) according to the comparison result.

The register unit 188 has register values corresponding to frequency information required for driving a device or a display panel provided in the panel driver 180 . The register unit 188 may have, for example, register values as shown in Table 1 below.

frequency number of clocks 60Hz 0x005A 75Hz 0x008A 90Hz 0x01C7

The timing controller 170 synchronizes the data signal transferred from the MIPI receiver 181 based on the internal clock signal (internal OSC) transferred from the internal clock generator 183 . The timing controller 170 generates a gate timing signal and a data timing signal for synchronizing and driving the driving timings of the gate controller 185 and the data driver 130 based on the internal clock signal (internal OSC). The timing controller 170 generates a control signal for compensating a data signal or controlling a division ratio of the internal clock generator 183 based on a logic block provided therein.

The gate control unit 185 includes a gate high voltage VGH, a gate low voltage VGL, and a clock signal CLK for controlling the gate driver in response to a synchronization signal such as a gate timing signal transmitted from the timing control unit 170 . to output

The data driver 130 converts a digital data signal into an analog data signal DATA in response to a synchronization signal such as a data timing signal transmitted from the timing controller 170 and outputs the converted data signal DATA.

On the other hand, the signal comparison and compensating unit 187 and the register unit 188 described above are included in the clock signal compensation circuit units 187 and 188 for compensating so that the internal clock generating unit 183 can generate a clock signal by itself. .

8, 9 and 12, when the MIPI clock signal is transmitted from the MIPI transmitter 101 (S110), the MIPI receiver 181 receives it (S120). The signal comparison and compensator 187 compares and counts the MIPI clock signal and the internal clock signal (internal OSC) for M time (M is a specific unit time of 1 second or more) of the N-1 th frame (N-1 th). (S130).

The signal comparison and compensator 187 compares two signals during an active period (or display period) in which the display panel displays an image, and stores the result in the register unit 188 . The register unit 188 outputs and transmits specific frequency information to the internal clock generation unit 183 in response to the result of the signal comparison and compensation unit 187 .

The clock signal compensation circuit units 187 and 188 compare and count the MIPI clock signal and the internal clock signal (internal OSC) during an active period (or display period) in which the display panel displays an image, and the frequency at which the comparison is performed The value is stored in the register unit 188 .

The clock signal compensation circuit units 187 and 188 perform a compensation operation for controlling the internal clock generator 183 so that the previous frequency is restored (restored) during the blank period in a section where the MIPI clock signal is not normally received. (S140).

For example, the clock signal compensation circuit units 187 and 188 include frequency information ICLK (required for driving the currently configured device) stored in the register unit 188 so that the internal clock generator 183 can recover the previous frequency. frequency information) to the internal clock generator 183 .

The internal clock generator 183 recovers the previous frequency based on the frequency information ICLK transmitted from the register unit 188 . As a result, the internal clock generator 183 continuously and stably supplies the internal clock signal (internal OSC) to the timing controller 170 and the like even during a blank period in which the display panel does not display an image.

That is, the timing controller 170 may continuously and stably output a signal capable of driving the display panel based on the internal clock signal (internal OSC) even during the blank period.

Meanwhile, the first embodiment of the present invention is also implemented so that the virtual reality display device uses the MIPI signal transmission system. As can be seen from the description of FIG. 5 , when a non-continuous mode is used, a signal necessary for driving the display panel cannot be continuously generated during a blank section.

Contrary to this, the continuous mode can continuously output the MIPI clock signal even during the blank section, so there is an advantage in stably realizing an image compared to the non-continuous mode. However, in the case of the continuous mode, when an external shock occurs during the blank section, the MIPI clock signal is momentarily unstable.

8 to 10 , clock signal compensation circuit units 187 and 188 are included in the panel driver 180 according to the first embodiment of the present invention. In the first embodiment of the present invention, when an external shock (eg, static electricity = ESD) occurs, the MIPI clock signal may be momentarily unstable.

However, by the compensation operation of the clock signal compensation circuit units 187 and 188 , the internal clock generator 183 recovers the previous frequency, and the internal clock generator 183 provides an internal clock signal to be supplied to the timing controller 170 , etc. can be printed normally.

Due to this effect, the timing controller 170 can also output a synchronization signal such as a gate timing signal in a normal form. As a result, the gate driver can normally output the gate signal even after an external shock (eg, static electricity = ESD) occurs.

As can be seen from FIG. 10 , the device according to the first embodiment of the present invention includes clock signal compensation circuit units 187 and 188 that can prepare for environmental problems that may occur in the interface (eg, clock asynchronization between devices due to ESD). exist.

Therefore, it is possible to compensate internally for problems affecting signal generation, such as the gate driver, without distinction between non-continuous mode and continuous mode.

As a result, in the first embodiment of the present invention, even if an environmental problem that may occur in the interface occurs, an abnormal image is displayed on the display panel 110 as shown in FIG. 11 or a line is temporarily generated in a specific line. It is possible to quickly recover from image quality defects such as flickering or flickering.

<Second embodiment>

As shown in FIG. 13 , the register unit 188 is divided to have a first register value R1 corresponding to previous frequency information and a second register value R2 corresponding to current frequency information. The first register value R1 has fixed frequency information, but the second register value R2 has variable frequency information.

The first register value R1 is set to have fixed register values as shown in Table 1. On the other hand, the second register value R2 stores this value separately when the frequency information is changed by the user's setting, device requirements, or external environment, and variably drives the internal clock generator 183 in response to the stored register value. It is set to have register values that change so that

More specifically, since the first embodiment uses only the first register value R1, when the frequency required for driving the device is determined, only one register value among the register values is used. That is, in the first embodiment, when an external shock is present, only the frequency corresponding to the preset driving condition is recovered (frequency fixed type).

In contrast, in the second embodiment, not only the first register value R1 but also the second register value R2 can be used, so after the frequency required for driving the device is determined, the frequency for the purpose and effect of reducing power consumption of the device Even if is changed, the register value corresponding to the changed frequency can be used. That is, in the second embodiment, when an external shock is present, a frequency corresponding to a preset driving condition and a changed driving condition is restored (frequency variation type).

For example, after the frequency required for normal driving of the device is set to 60 Hz, the frequency is changed to 30 Hz due to power consumption-saving driving of the device. However, thereafter, an external shock occurs, causing a problem of clock synchronization between the system and the panel driver.

However, since the clock signal compensation circuit units 187 and 188 store frequency information about the changed frequency of 30 Hz, a compensation operation for recovering the internal clock generator 183 is performed based on this. Accordingly, the timing controller and the like can drive the device at the changed frequency of 30 Hz.

Meanwhile, in FIG. 13 , the signal comparison and compensator 187 stores the frequency information changed based on the comparison result of the MIPI clock signal and the internal clock signal (internal OSC) in the second register value R2 as an example. .

However, this is only an example, and the signal comparison and compensator 187 compares the MIPI clock signal with the clock signal, the vertical synchronization signal, the horizontal synchronization signal output from the timing controller, and then provides the changed frequency information based on the comparison result. It can also be stored in two register values (R2).

As described above, since the present invention manufactures a virtual reality display device based on a display device capable of variable duty, it is possible to increase the visual response speed or motion picture response time (MPRT), thereby improving the ability to implement a virtual environment. . In addition, the present invention has an effect of providing a device that is robust to environmental problems (eg, clock asynchronization between devices due to ESD) that may occur in an interface connected to the system in order to improve the stable image implementation capability. In addition, the present invention has an effect of providing a device capable of generating a clock signal for supporting stable duty driving by itself.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention can be changed to other specific forms by those skilled in the art to which the present invention pertains without changing the technical spirit or essential features of the present invention. It will be appreciated that this may be practiced. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. In addition, the scope of the present invention is indicated by the claims to be described later rather than the above detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention.

100: system 170: timing control
130: data driver 140: power supply
150: gate driver 110: display panel
183: internal clock generation unit 187: signal comparison and compensation unit
188: register unit 170: timing control unit
185: gate control

Claims (10)

a display panel for displaying an image; and
an internal clock generator that drives the display panel and generates an internal clock signal for driving a device provided therein based on an external clock signal, and controls the internal clock generator in a section where the external clock signal does not normally enter a clock signal compensation circuit unit for recovering the internal clock signal;
The clock signal compensation circuit unit
a register unit having register values corresponding to frequency information;
and a signal comparison and compensator for comparing and counting the external clock signal and the internal clock signal, and recovering the internal clock signal to one of the register values in a section in which the external clock signal does not normally enter;
The register unit includes a first register value composed of fixed frequency information and a second register value composed of changed frequency information,
The clock signal compensation circuit unit
The register unit compares and counts the external clock signal and the internal clock signal during a display period in which the display panel displays an image, and during a blank period in which the display panel does not display an image when the external clock signal is not normally received A display device for recovering the internal clock signal based on the changed frequency information transmitted from delete delete delete a display panel for displaying an image;
a system having a MIPI transmitter; and
and a panel driving unit having a MIPI receiving unit for receiving data transmitted through the MIPI transmitting unit and driving the display panel;
The panel driver
an internal clock generator for generating an internal clock signal for driving a device provided therein based on the external clock signal transmitted from the MIPI transmitter;
and a clock signal compensation circuit unit for controlling the internal clock generator to recover the internal clock signal in a section where the external clock signal does not normally enter;
The clock signal compensation circuit unit
a register unit having register values corresponding to frequency information;
and a signal comparison and compensator for comparing and counting the external clock signal and the internal clock signal, and recovering the internal clock signal to one of the register values in a section in which the external clock signal does not normally enter;
The register unit includes a first register value composed of fixed frequency information and a second register value composed of changed frequency information,
The clock signal compensation circuit unit
The register unit compares and counts the external clock signal and the internal clock signal during a display period in which the display panel displays an image, and during a blank period in which the display panel does not display an image when the external clock signal is not normally received A virtual reality display device for recovering the internal clock signal based on the changed frequency information transmitted from delete delete delete In the driving method of the virtual reality display device manufactured by claim 5,
receiving a signal including an external clock signal;
comparing and counting the external clock signal and the internal clock signal; and
recovering the internal clock signal to one of the register values stored in the internal register unit in a section in which the external clock signal does not normally enter,
and recovering the internal clock signal based on the changed frequency information when the frequency is changed in a section in which the external clock signal does not normally enter. delete

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