KR20200036570A - Pixel sensing device and electroluminescence display using the same - Google Patents

Abstract

The present invention relates to a pixel sensing device capable of improving sensing of a lower gradation voltage, and an electroluminescent display using the same. The pixel sensing device comprises: a first analog-to-digital converter converting an upper gradation voltage into digital data; a second analog-to-digital converter converting a lower gradation voltage into digital data; and a selection unit selecting an output of the first analog-to-digital converter when the upper gradation voltage is inputted into a comparison unit in response to a selection signal and selecting an output of the second analog-to-digital converter when the lower gradation voltage is inputted into the comparison unit.

Description

Pixel sensing device and electroluminescent display device using the same {PIXEL SENSING DEVICE AND ELECTROLUMINESCENCE DISPLAY USING THE SAME}

The present invention modulates the pixel data of the input image based on the sensing voltage obtained from the pixel circuit of the subpixel by real-time sensing the electrical characteristics of the subpixel, thereby real-time changing the electrical characteristics of each of the subpixels or the deviation of the electrical characteristics between the subpixels. It relates to a compensation pixel sensing device and an electroluminescent display device using the same.

The electroluminescent display device is roughly classified into an inorganic light emitting display device and an organic light emitting display device according to the material of the light emitting layer. The active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter referred to as “OLED”) that emits light by itself, and has a high response speed, high luminous efficiency, brightness and viewing angle. There are advantages.

The pixels of the organic light emitting display device include an OLED and a driving element that supplies the current to the OLED according to the voltage between the gate and the source to drive the OLED. The OLED of the organic light emitting display device includes an anode and a cathode, and an organic compound layer formed between the electrodes. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (Electron Injection layer, EIL). When a current flows through the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) are moved to the emission layer (EML) to form excitons, and as a result, the emission layer (EML) generates visible light. .

The driving element may be implemented with a TFT of a metal oxide semiconductor field effect transistor (MOSFET) structure. The driving element must have uniform electrical characteristics among all pixels, but may have a difference between pixels due to process variation and variation in device characteristics, and may change according to passage of display driving time. In order to compensate for the electrical characteristics of the driving element, an internal compensation method and an external compensation method may be applied to the electroluminescent display device. The internal compensation method samples the gate-source voltage Vgs of the driving element that changes according to the electrical characteristics of the driving element and compensates the data voltage by the gate-source voltage. The external compensation method senses a voltage of a pixel that changes according to an electrical characteristic of a driving element, and modulates data of an input image in an external circuit based on the sensed voltage, thereby changing an electrical characteristic of each subpixel or an electrical characteristic between subpixels. Deviation can be compensated in real time.

In order to compensate for the electrical characteristics of the sub-pixel in the external compensation method, the current value or voltage value sensed from the pixel circuit must be accurately sensed. However, if the current or voltage value sensed from the pixel circuit is lower than the input voltage range of the analog-to-digital converter (hereinafter referred to as “ADC”), the driving element because the data output from the ADC cannot accurately represent the sensed value. Deterioration and deviation compensation may be inaccurate. For example, when lower grayscale data is written to the pixel circuit, the sensing value may be lower than the voltage range of the ADC, resulting in inaccurate sensing in the lower grayscale.

Accordingly, the present invention provides a pixel sensing device capable of improving the sensing of the lower gradation voltage and an electroluminescent display device using the pixel sensing device.

The pixel sensing device of the present invention compares an input voltage obtained from a pixel circuit with a predetermined gradation division reference voltage to generate a selection signal for distinguishing an upper gradation voltage above the gradation division reference voltage and a lower gradation voltage smaller than the gradation division voltage. A comparator, a first analog-to-digital converter for converting the upper gradation voltage to digital data, a second analog-digital converter for converting the lower gradation voltage to digital data, and the upper part in response to the selection signal And a selection unit selecting an output of the first analog data converter when a grayscale voltage is input and selecting an output of the second analog data converter when the lower grayscale voltage is input to the comparison unit.

The electroluminescent display device of the present invention uses the pixel sensing device to sense the electrical characteristics of the sub-pixel and modulate the pixel data of the input image.

The present invention compares the input voltage obtained from the pixel circuit in the sensing mode with a predetermined gradation division reference voltage to distinguish the upper gradation voltage and the lower gradation voltage from the input voltage, and the upper gradation voltage is digital data through a first analog data converter. To convert the lower gradation voltage into digital data through a second analog data converter. As a result, the present invention can reduce the ADC input voltage to expand the ADC input voltage range, increase the resolution of the ADC even in the low current and low voltage range, and obtain the bit expansion effect of the ADC as well as a smaller number of bits than the existing ADC. ADC can reduce bit size because bit expansion effect can be obtained.

1 is a block diagram showing an electroluminescent display device according to an exemplary embodiment of the present invention.
2 is a circuit diagram showing an external compensation circuit connected to a pixel circuit.
3 and 4 are diagrams showing a sensing mode.
5 is a view showing in detail the active section and the vertical blank section.
FIG. 6 is a circuit diagram showing in detail the sensing unit shown in FIG. 2.
7 is a diagram showing voltages for each gradation when the input voltage range of the ADC is 3V.
8 is a diagram illustrating an example in which a sensing error occurs in a lower grayscale ADC input voltage.
9 is a flowchart illustrating a pixel sensing method according to an embodiment of the present invention.
10 is a circuit diagram illustrating a pixel sensing device according to an embodiment of the present invention.
11 is a view showing an example of amplifying a lower gradation ADC input voltage.
12 is a diagram showing the voltage amplified in the lower gradation.
13 is a circuit diagram showing the first and second ADCs in detail.
14 is a view showing various application examples of the first and second ADCs.
15 is a circuit diagram illustrating a pixel sensing device according to another embodiment of the present invention.

Advantages and features of the present invention, and methods for achieving them will be clarified with reference to embodiments described below in detail together with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the embodiments allow the disclosure of the present invention to be complete, and those skilled in the art to which the present invention pertains. It is provided to fully inform the scope of the invention, and the invention is only defined by the scope of the claims.

Since the shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing the embodiments of the present invention are exemplary, the present invention is not limited to the details shown in the drawings. Throughout the specification, the same reference numerals refer to substantially the same components. In addition, in the description of the present invention, when it is determined that detailed descriptions of related known technologies may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted.

When "equipped", "includes", "haves", "consists of" and the like referred to herein are used, other parts may be added unless '~ only' is used. When a component is expressed in singular, it may be interpreted in plural unless otherwise specified.

In analyzing the components, it is interpreted as including the error range even if there is no explicit description.

In the case of the description of the positional relationship, for example, when the positional relationship between the two components is described as' on the top ',' on the top ',' on the bottom ',' on the side ',' One or more other components may be interposed between those components for which no 'direct' or 'direct' is used.

The first, second, etc. may be used to classify the components, but the functions or structures of these components are not limited by the ordinal number or the name of the component before the component.

The following embodiments may be partially or totally combined or combined with each other, and technically various interlocking and driving are possible. Each of the embodiments may be implemented independently of each other or may be implemented together in an association relationship.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following embodiments, the electroluminescent display device of the present invention will be mainly described with an example in which an external compensation circuit is applied.

In the electroluminescent display device of the present invention, an external compensation circuit is applied.

1 is a block diagram showing an electroluminescent display device according to an exemplary embodiment of the present invention. 2 is a circuit diagram showing an external compensation circuit connected to a pixel circuit.

1 and 2, an electroluminescent display device according to an exemplary embodiment of the present invention includes a display panel 100 and a display panel driving circuit.

The electroluminescent display device of the present invention operates in a normal driving mode for displaying an input image on a screen and a sensing mode for sensing the electrical characteristics of pixels. In the normal driving mode, the display panel driving circuits 110, 112, and 120 write pixel data of the input image to pixels during the active period AT of the display driving period in FIG. 3 under the control of the timing controller 130. In the sensing mode, the display panel driving circuits 110, 112, and 120 are powered on in FIG. 3 under the control of the timing controller 130 (Power ON), vertical blank period (VB) of the display driving period, and powered off (Power) OFF), the electrical characteristics of the driving element DT are sensed for each sub-pixel, and a compensation value is selected according to the sensing value to compensate for changes in the electrical characteristics of the driving element DT.

The screen of the display panel 100 includes an active area AA displaying an input image. A pixel array is disposed in the active area AA. The pixel array includes a plurality of data lines 102, a plurality of gate lines 104 intersecting the data lines 102, and pixels arranged in a matrix form.

Each of the pixels may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color realization. Each of the pixels may further include a white sub-pixel. Each of the sub pixels 101 includes a pixel circuit.

Touch sensors may be disposed on the display panel 100. The touch input may be sensed using separate touch sensors or may be sensed through pixels. The touch sensors may be implemented as in-cell type or in-cell type touch sensors disposed on a screen of a display panel or embedded in a pixel array in an on-cell type or an add-on type. You can.

The display panel driving circuits 110, 112, and 120 include a data driving unit 110 and a gate driving unit 120. A demultiplexer 112 disposed between the data driver 110 and the data lines 102 may be disposed. The demultiplexer 112 may be omitted.

The display panel driving circuits 110, 112, and 120 write pixel data of an input image on the pixels of the display panel 100 under the control of a timing controller (TCON) 130 in the normal driving mode to write on the screen. Display the input image. The display panel driving circuits 110, 112, and 120 may further include a touch sensor driver for driving touch sensors. The touch sensor driver is omitted in FIG. 1. In a mobile device or a wearable device, the data driver 110, the timing controller 130, and the power circuit omitted in the drawing may be integrated in one drive integrated circuit (IC). The power supply circuit generates power required for driving the display panel driving circuits 110, 112, and 120.

As shown in FIG. 2, the data driver 110 uses the digital to analog converter (hereinafter referred to as “DAC”) pixel data of the input image received from the timing controller 130 every frame period. (Digital data) is converted to a gamma compensation voltage to output the data voltage Vdata. The data voltage Vdata is supplied to the pixels through the demultiplexer 112 and the data line 102. The data voltage Vdat is a sensing data voltage supplied to the sub-pixels in the sensing mode to sense deterioration of the driving element in each of the sub-pixels, and pixel data written to the sub-pixels in the normal driving mode and reproduced as an input image. Divided by voltage.

The demultiplexer 112 is disposed between the data driver 110 and the data lines 102 using a plurality of switch elements to distribute the data voltage Vdata output from the data driver 110 to the data lines 102. do. Since the data voltage Vdata output from one channel of the data driver 110 by the demultiplexer 112 is time-divided and distributed to a plurality of data lines, the number of channels of the data driver 110 may be reduced.

The gate driver 120 may be implemented as a gate in panel (GIP) circuit formed directly on the display panel 100 together with the pixel array of the active area AA. The GIP circuit may be disposed on a bezel area of the display panel 100 outside the pixel array. The gate driver 120 outputs a gate signal to the gate lines 104 under the control of the timing controller 130. The gate driver 120 may sequentially supply the signals to the gate lines 104 by shifting the gate signal using a shift register. The gate signal may include a scan signal SCAN and a sensing signal SENSE, but is not limited thereto. The scan signal SCAN and the sensing signal SENSE may be synchronized with the data voltage Vdata.

The timing controller 130 controls the operation timing of the display panel driving circuits 110, 112, and 120 in the normal driving mode and the sensing mode. The timing controller 130 receives pixel data (digital data A) of an input image from a host system (not shown) and a timing signal synchronized therewith. The timing signal received by the timing controller 130 may include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock (CLK), and a data enable signal (DE). One period of the vertical synchronization signal Vsync is one frame period. One period of the horizontal synchronization signal Hsync and the data enable signal DE is one horizontal period 1H. The pulse of the data enable signal DE is synchronized with the pixel data of one pixel line to be displayed on the pixels of the active area AA. Since the frame period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted.

The host system may be any one of a TV (Television) system, a set top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a wearable device.

The timing controller 130 may adjust the frame rate to a frequency greater than or equal to the input frame frequency. For example, the timing controller 130 multiplies the input frame frequency by i times, thereby operating the timing of the display panel drivers 110, 112, and 120 at a frame frequency of i × i (i is a positive integer greater than 0) Hz. Can be controlled. The frame frequency is 60 Hz in the NTSC (National Television Standards Committee) method and 50 Hz in the PAL (Phase-Alternating Line) method.

The timing controller 130 generates data timing control signals for controlling the operation timing of the display panel driving circuits 110, 112, and 120 based on the timing signals Vsync, Hsync, CLK, DE received from the host system. The display panel driving circuits 110, 112, and 120 are controlled. The voltage level of the gate timing control signal output from the timing controller 130 may be converted into a gate-on voltage and a gate-off voltage through a level shifter (not shown) and supplied to the gate driver 120.

As illustrated in FIG. 2, the external compensation circuit receives digital data (ADC OUT) output from the sensing line 103, the sensing unit 111, and the sensing unit 111 connected to the pixel circuit in each of the sub-pixels 101. It includes a compensation unit 131 to receive. The sensing unit 111 may sense an electric characteristic of the driving element DT by sensing a current flowing through the OLED. The DAC and the sensing unit 111 may be integrated in an integrated circuit (IC) of the data driving unit 110. The compensation unit 131 may be built in the timing controller 130.

The external compensation circuit initializes the source voltage Vs of the sensing line 103 and the driving element DT as a reference voltage, that is, the voltage of the second node n2, and then senses the source voltage of the driving element DT. The electrical characteristics of the driving element DT may be sensed. The electrical characteristics of the driving element DT include a threshold voltage Vth, mobility Vth, μ, and the like.

The sensing unit 111 samples the voltage on the sensing line 103 connected to the pixel circuit in the sensing mode and outputs digital data (ADC OUT) through the ADC.

In the look-up table of the compensation unit 131, compensation values for compensating the threshold voltage Vth and mobility μ of the driving element DT for each sub-pixel are stored. The compensation unit 131 modulates pixel data by modulating pixel data by adding or multiplying the compensation data output from the lookup table by inputting the sensed data received through the ADC to the lookup table and multiplying the pixel data of the input image. To compensate. The pixel data modulated by the compensation unit 131 is transmitted to the data driving unit 110 and converted into a data voltage Vdata by the DAC of the data driving unit 110 and supplied to the data line 102. The driving element DT of the pixel circuit is driven by the data voltage Vdata supplied through the data line 102 to generate a current. The current flowing through the driving element DT to the light emitting element OLED is determined according to the gate-source voltage Vgs of the driving element DT.

The pixel circuit includes an OLED, a driving element DT connected to the OLED, a plurality of switch TFTs M1 and M2, and a capacitor Cst, as shown in the example of FIG. 2. The driving element DT and the switch TFTs M1 and M2 may be implemented as an n-channel transistor NMOS, but are not limited thereto.

The OLED emits light with a current generated according to the gate-source voltage Vgs of the driving element DT that changes according to the data voltage Vdata. The OLED includes an organic compound layer formed between the anode and the cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode of the OLED is connected to the driving element DT through the second node n2, and the cathode of the OLED is connected to the VSS electrode to which the low potential power voltage VSS is applied. In FIG. 2, “Coled” is the capacity (capacitance) of the OLED.

The first switch TFT M1 is turned on according to the gate-on voltage of the scan signal SCAN to connect the data line 102 to the first node n1 to connect the data voltage Vdata to the first node n1. It supplies to the gate of the driving element DT connected to. The first switch TFT M1 includes a gate connected to the first gate line 1041 to which the first scan signal SCAN is applied, a first electrode connected to the data line 102, and a first node connected to the first node n1. Includes 2 electrodes.

The second switch TFT M2 is turned on according to the sensing signal SENSE to supply the reference voltages VPRES and VPRER to the second node n2. The second switch TFT M2 includes a gate connected to the second gate line 1042 to which the sensing signal SENSE is applied, a first electrode connected to the sensing line 103 to which the reference voltages VPRES and VPRER are applied, and And a second electrode connected to the second node n2.

The driving element DT drives the OLED by supplying a current to the OLED according to its gate-source voltage Vgs. The driving element DT is OLED through the gate connected to the first node n1, the first electrode (or drain) connected to the VDD line 105 to which the pixel driving voltage VDD is supplied, and the second node n2. It includes a second electrode (or source) connected to the anode. The capacitor Cst is connected between the first node n1 and the second node n2. The capacitor Cst charges the gate-source voltage Vgs of the driving element DT.

3 and 4 are diagrams showing a sensing mode. 5 is a diagram showing in detail the active section AT and the vertical blank section VB.

3 to 5, the sensing mode is divided into before and after product shipment. Before the product is shipped, the electrical characteristics (Vth, μ) of the driving element DT are sensed in each of the sub-pixels through an external compensation circuit connected to the pixels, and this sensing value is determined for each sub-pixel of the driving element DT ( Vth, μ) changes or deviations are compensated.

Sensing mode after shipment from the product is ON RF mode performed in the Power ON sequence, RT MODE performed in the vertical blank (VB) during the display driving period, and Power OFF sequence. It can be divided into OFF RS mode to be carried out.

The ON RF mode senses the mobility (μ) of the driving element (DT) in each of the pixels when the field emission display is turned on, and the mobility sensing value (DT) is measured for each sub-pixel before shipment of the product. Compare the mobility compensation value of and update the mobility compensation value based on the difference. In the sensing mode before shipment, the threshold voltage and mobility of the driving element for each sub-pixel are sensed, and the threshold voltage compensation value and mobility compensation value of the driving element are set in a look-up table. The mobility μ of the driving element is compensated by a mobility compensation value reflecting the mobility sensing value of the driving element DT for each sub pixel.

In the RT mode, the mobility (μ) of the driving element DT is sensed in real time in a vertical blank interval (VB) every frame period during a display driving period in which an image is displayed, and a sub-pixel according to the mobility sensing value. The mobility compensation value is updated for each. The vertical blank period VB is allocated at a predetermined time between the active period AT of the N-1th frame period and the active period AT of the Nth frame period.

The OFF RS mode senses the threshold voltage Vth of the driving element DT in each of the pixels when the display device is turned off, and updates the threshold voltage compensation value for each sub pixel according to the threshold voltage sensing value. In the OFF RS mode, the display panel driving circuits 110, 112, and 120 and external compensation circuits are driven for a predetermined delay time before the power is completely turned off, thereby reducing the threshold voltage Vth of the driving element in each of the pixels in each of the sub-pixels. The threshold voltage compensation value is updated for each sub-pixel by sensing. When the threshold voltage compensation value is updated at the N-th power OFF point (OFF (N)), it may be updated at the N-th power OFF point (OFF (N)) after being maintained in the ON RF mode and RT mode.

Meanwhile, electrical characteristics of the driving element DT may be sensed in a predetermined number of pixel lines in a predetermined order within an active period AT in which pixel data of an input image is written in pixels.

In FIG. 5, the vertical synchronization signal Vsync defines one frame period. One frame period is a time obtained by adding the active period (AT) and the vertical blank period (VB). The horizontal synchronization signal (Hsync) defines one horizontal time (Horizontal time). The data enable signal DE defines an effective data section including pixel data to be displayed on the screen.

The data enable signal DE is synchronized with valid data to be displayed on the pixel array of the display panel 100. One pulse period of the data enable signal DE is one horizontal period, and a high logic section of the data enable signal DE represents data input timing of one pixel line. One horizontal period is a time required to write data to pixels of one pixel line in the display panel 100.

The timing controller 130 receives the data enable signal DE and the data of the input image during the active period AT. There is no data enable signal DE and input image data in the vertical blank period VB. Timing controller 130 receives one frame of data to be written to all pixels during the active period AT.

As can be seen from the data enable signal DE, input data is not received by the display device during the vertical blank period VB. The vertical blank period (VB) includes a vertical sync time (VS), a vertical front porch (Vertical Front Porch, FP), and a vertical back porch (Vertical Back Porch, BP). The vertical sync time (VS) is a time from a falling edge of a Vsync to a rising edge, and indicates the start (or end) timing of the screen.

6 is a circuit diagram showing the sensing unit 111 in detail.

Referring to FIG. 6, the sensing unit 111 includes switch elements SW1 to SW3 for switching the reference voltages VPRER and VPRES, a capacitor Csam, a sample & scaller circuit 112, And an analog-to-digital converter (hereinafter referred to as “ADC”). In FIG. 6, “Csio” is a capacitor connected to the sensing line 103. The switch elements SW1 to SW3 may be implemented with n-channel transistors (NMOS).

The reference voltages VPRER and VPRES are divided into a first reference voltage VPRES for initializing the pixel circuit and a second reference voltage VPRER set to a voltage higher than the first reference voltage VPRES. The first reference voltage VPRES is set to a voltage for initializing the driving element DT and the OLED in the sensing mode. The second reference voltage VPRER charges the source voltage Vs of the driving element DT to a voltage higher than 0 V in the normal driving mode. The second reference voltage VPRER is a voltage margin for setting the compensation voltage of the data voltage Vdata when the threshold voltage is shifted in the negative polarity direction due to the gate bias stress of the driving element DT. ) To provide a voltage higher than 0V. VPRES = 0V, VPRER = 3V, but is not limited thereto.

The first switch element SW1 is turned on according to a high logic voltage of the first switch control signal SPRE to receive the first reference voltage VPRES to the sensing line 103. To supply. The second switch element SW2 is turned on according to the high logic voltage of the second switch control signal RPRE to supply the second reference voltage VPRER to the sensing line 103. The third switch element M3 is turned on according to the high logic voltage of the third switch control signal SAM to connect the sensing line 103 to the capacitor Csam. The capacitor Csam is formed between the reference voltage terminal EVREF2 and a node between the third switch element SW3 and the input terminal of the sample & scaler circuit 112. The reference voltage terminal EVREF2 may be set to GND = OV.

The sampling & scaler circuit 112 includes a fourth switch and a voltage scaler (not shown). The fourth switch is turned on alternately with the third switch M3 to supply the sampling voltage charged in the capacitor Csam to the voltage scaler. The voltage scaler adjusts the sampling voltage within the ADC's input voltage range. The ADC converts the input voltage to digital data and outputs digital data (ADC OUT) indicating the sensing value. When a voltage lower than the input voltage range of the ADC is input to the ADC, the electrical characteristics of the driving element are not accurately sensed.

7 shows voltages for each gradation when the input voltage range of the ADC is 3V. In FIG. 7, the x-axis is grayscale of pixel data, and the y-axis is input voltage Vin of the ADC. 8 is a diagram illustrating an example in which a sensing error occurs when the input voltage Vin of the ADC is low. In FIG. 8, the y-axis represents the voltage difference (ΔV) between gradations. In FIG. 8, 0.003V is a voltage between gradation 44 and gradation 45, and 0.01V is a voltage between gradation 120 and gradation 121.

When the input voltage range of the ADC is 3V, 3/1024 = 0.0003V per 10-bit reference bit. However, as can be seen in FIG. 7, if the current flowing through the OLED is small in the case of the lower gradation, there is a difference in gradation, but the voltage sensed in the gradation in the lower gradation range is input to the ADC as the minimum voltage in the ADC's input voltage range. There is an example in which data output from the ADC is not distinguishable between gradations. For example, as illustrated in FIGS. 7 and 8, since the sensing voltage of the lower gradation range of gradation 45 or less is ΔV or less than 0.003 V, a conversion error occurs due to conversion to the same digital data through the ADC.

9 is a flowchart illustrating a pixel sensing method according to an embodiment of the present invention. The sensing method of the present invention may be implemented with the pixel sensing device illustrated in FIG. 10. In order to increase the resolution of the ADC for the lower gradation voltage, which is impossible to distinguish between gradations in the prior art, the sensing voltage received from the pixel circuit, that is, the ADC input voltage is converted into digital data, as shown in FIG. 10. .

9, the present invention senses the current or voltage from the pixel circuit (S1). The sensed current is converted into a voltage. Subsequently, the present invention inputs the current or voltage sensed from the pixel circuit to the ADC, and compares the ADC input voltage Vin with a predetermined gradation division reference voltage Vref (S2 and S3).

The gradation division reference voltage Vref may be set to a lower gradation voltage in which it is difficult to distinguish gradation from the input voltage range of the ADC. The gradation division reference voltage Vref may be appropriately set between a voltage of 1/2 or less within an input voltage range between a maximum voltage and a minimum voltage of the input voltage Vin, and a voltage higher than a minimum voltage of the input voltage range. have. For example, the gradation section reference voltage Vref may be selected between 0.003V and 1.5V in the case of a 10-bit ADC having an input voltage range of 3V.

In the present invention, when the ADC input voltage Vin is determined to be a higher gradation voltage than the gradation division reference voltage Vref, the sensing value output from the first ADC, that is, digital data (ADC OUT) is selected and transmitted to the compensation unit 131 (S3 and S4). On the other hand, in the present invention, if the ADC input voltage Vin is a lower gradation voltage smaller than the gradation division reference voltage Vref, the digital data output from the second ADC (ADC OUT) is selected and transmitted to the compensation unit 131 ( S3 and S4). The ADC input voltage smaller than the gradation division reference voltage Vref may be amplified within the input voltage range of the second ADC and input to the second ADC.

Referring to FIG. 10, the pixel sensing device of the present invention includes a comparator 10, a first ADC 12, an amplifier 14, a second ADC 16, and a selector 18.

The comparator 10 compares the input voltage Vin obtained from the pixel circuit with a predetermined gradation division reference voltage to generate a selection signal for distinguishing an upper gradation voltage above the gradation division reference voltage and a lower gradation voltage smaller than the gradation division voltage. . The comparator 10 transmits the input voltage Vin obtained from the pixel circuit to the first and second ADCs 12 and 16. The ADC input voltage Vin has a different voltage level depending on the gradation of the data voltage supplied to the pixel circuit. The amplifier 14 amplifies the input voltage Vin of the second ADC 16.

The comparator 10 selects digital data ADC OUT output from the first ADC 12 as the final ADC data when the ADC input voltage Vin is a higher gradation voltage equal to or higher than the gradation division reference voltage Vref. On the other hand, when the ADC input voltage Vin is a lower gradation voltage smaller than the gradation division reference voltage Vref, the comparator 10 uses digital data ADC OUT output as the final ADC data. Choose.

The first ADC 12 may be implemented as an M (M is a positive integer greater than or equal to 4) bit ADC. The first ADC 12 converts the input voltage Vin input from the comparator 10 into digital data. The first ADC 12 converts the input voltage Vin of the higher grayscale voltage equal to or higher than the grayscale division reference voltage Vref into digital data ADC OUT. The second ADC 16 may be implemented as an N (N is a positive integer less than or equal to M) bit ADC. The second ADC 16 converts the input voltage Vin of the lower gradation voltage smaller than the gradation division reference voltage Vref into digital data ADC OUT.

The selector 18 selects one of output data of the first ADC 12 and output data of the second ADC 16 under the control of the comparator 10. The comparator 10 generates a selection signal as a first logic voltage when the ADC input voltage Vin is a higher gradation voltage, and a selection signal as a second logic voltage when the ADC input voltage Vin is a lower gradation voltage. do. The selection unit 18 selects the output data of the first ADC 12 in response to the first logic voltage of the selection signal and transmits it to the compensation unit 131. The selection unit 18 selects the output data of the second ADC 14 in response to the second logic voltage of the selection signal and transmits it to the compensation unit 131.

11 is a view showing an example of amplifying a lower gradation ADC input voltage. 12 is a diagram showing the voltage amplified in the lower gradation.

The ADC applied to the conventional sensing unit could obtain a sensing value as digital data through a 10-bit ADC or a 12-bit ADC, but in the case of lower gradations, it could not be classified as ADC output data. The present invention expands the ADC input voltage range by lowering the ADC input voltage by separating the upper gray voltage and the lower gray voltage as the reference voltage and dividing the ADC into the first and second ADCs 12 and 16. Therefore, the present invention can increase the resolution of the ADC even in the low current and low voltage ranges to obtain the bit magnification effect of the ADC, as well as the bit magnification effect of the ADC with a smaller number of bits than the existing ADC, thereby reducing the size of the ADC.

13 is a circuit diagram showing the first and second ADCs 12 and 16 in detail. Each of the first and second ADCs in FIG. 13 is illustrated as a 10 bit ADC, but is not limited thereto.

Referring to FIG. 13, the first ADC 12 includes a reference voltage generator 30 that generates a plurality of reference voltages, a comparison unit 32 that compares an input voltage Vin with a reference voltage, and a comparison unit 32 Encoder 34 that encodes the output of) and outputs digital data (ADC OUT).

The comparator 30 divides the highest reference voltage (3V) and the gradation division reference voltage (Vref) by using a divider circuit in which resistors are connected in series, thereby resolving the highest reference voltage (3V) and the gradation division reference voltage from each of the divided nodes ( Vref) to output reference voltages having different voltage levels. The reference voltages may be input to the comparator 32 through an amplifier (not shown).

The comparator 32 includes a plurality of comparators that compare the input voltage Vin with reference voltages. Each of the comparators outputs a low logic (low = 0) when the input voltage Vin is greater than the reference voltage, while outputs a high logic (high = 1) when the reference voltage is greater than the input voltage Vin. The output of the comparator 32 is known as a so-called “Thermometer Code” by indicating the boundary between '1' and '0' according to the comparison result of the input voltage and the reference voltages. The encoder 34 selects the digital code of the higher gradation voltage corresponding to the thermometer code from the comparator 32 and outputs digital data ADC OUT.

The second ADC 16 encodes the output of the reference voltage generator 36 that generates a plurality of reference voltages, the comparison unit 38 that compares the input voltage Vin with the reference voltage, and the output of the comparison unit 38. And an encoder 40 for outputting digital data (ADC OUT).

The comparator 30 divides the highest reference voltage (3V) and the gradation division reference voltage (Vref) by using a divider circuit in which resistors are connected in series, thereby gradation division reference voltage (Vref) and lowest reference voltage ( 0V) to output reference voltages having different voltage levels. The reference voltages may be input to the comparator 38 through an amplifier (not shown).

The comparator 38 outputs a thermometer code including a plurality of comparators that compare the input voltage Vin with reference voltages. Each of the comparators outputs a low logic (low = 0) when the input voltage Vin is greater than the reference voltage, while outputs a high logic (high = 1) when the reference voltage is greater than the input voltage Vin. The encoder 40 selects the digital code of the lower gradation voltage corresponding to the thermometer code from the comparator 38 and outputs digital data ADC OUT.

As illustrated in FIG. 14, the first ADC 12 may be implemented as an 11 bit ADC, and the second ADC 16 may be implemented as a 9 bit ADC. As another example, the first ADC 12 may be implemented as a 13 bit ADC, and the second ADC 16 may be implemented as a 12 bit ADC.

Another embodiment of the present invention removes the quantization error of the data (ADC OUT) output from the second ADC by using a feedback compensation loop as shown in Figure 15 results in the sensing value of the lower gradation voltage Can be corrected. The feedback compensation loop converts the input voltage (Vin) to digital data in the primary loop, feeds back the value, and inverts the amplification to add the inverted amplified voltage to the input voltage (Vin), thereby digital data output from the second ADC (12) Eliminate the error of (ADC OUT).

15 is a circuit diagram illustrating a pixel sensing device according to another embodiment of the present invention. In FIG. 15, the same reference numerals are assigned to the same components as the embodiments and the detailed description thereof will be omitted.

15, the pixel sensing device includes a comparator 10, a first ADC 12, an amplifier 14, a feedback compensator 20, a second ADC 16, a selector 18, and a DAC (22).

The first ADC 12 converts the input voltage Vin of the higher grayscale voltage equal to or higher than the grayscale division reference voltage Vref into digital data ADC OUT. The second ADC 12 converts the input voltage Vin of the lower gradation voltage smaller than the gradation division reference voltage Vref into digital data ADC OUT.

The output data ADC of the second ADC 16 is converted to an analog voltage through the DAC 22 and is input to the non-inverting input terminal (-) of the feedback compensator 20. The DAC 22 may be implemented as a 10 bit DAC when the second ADC 16 is a 10 bit ADC.

The operational amplifier of the feedback compensator 20 includes a non-inverting input terminal (+) connected to the output node of the amplifier 14 through a resistor, an inverting input terminal (-) connected to the output node of the DAC 22 through a resistor, and It includes an output terminal connected to the input node of the second ADC 16 and connected to the inverting input terminal (-) through a resistor. The feedback compensator 20 adds an inverted voltage between the feedback voltage from the DAC 22 and the input voltage to the input voltage Vin to compensate for errors in the digital data ADC OUT output from the second ADC 16. Remove it.

The selector 18 selects one of output data of the first ADC 12 and output data of the second ADC 16 under the control of the comparator 10. The comparator 10 generates a selection signal as a first logic voltage when the ADC input voltage Vin is a higher gradation voltage, and a selection signal as a second logic voltage when the ADC input voltage Vin is a lower gradation voltage. do. The selection unit 18 selects the output data of the first ADC 12 in response to the first logic voltage of the selection signal and transmits it to the compensation unit 131. The selection unit 18 selects the output data of the second ADC 14 in response to the second logic voltage of the selection signal and transmits it to the compensation unit 131.

When Vin = 2.99395V is input to the second ADC 16 and converts digital data (ADC OUT) output from the second ADC 16 into an analog voltage through the DAC 22, if it is 2.991 V, the second ADC (16 Due to the quantization error of), a difference between the input voltage Vin and the feedback voltage from the DAC occurs. In this example, the feedback compensator 20 compensates for the quantization error of the second ADC 16 as follows.

2.99395V + 0.00295V = 2.9969V

Here, 2.99395V is the input voltage Vin and 0.00295V is 2.99395-2.991 = 0.00295 which inverted and amplified the DAC conversion voltage of the output data ADC OUT of the second ADC 16.

Through the above description, those skilled in the art will appreciate that various changes and modifications are possible without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention is not limited to the contents described in the detailed description of the specification, but should be determined by the scope of the claims.

10: comparator 12: first ADC
14: amplifier 16: second ADC
18: selection unit 20: feedback compensation unit
22: DAC 30, 36: reference voltage generator
32, 38: comparator 34, 40: encoder
100: display panel 110: data driver
120: gate driver 130: timing controller
111: sensing unit 131: compensation unit

Claims (8)

A comparator for comparing an input voltage obtained from the pixel circuit with a predetermined gradation division reference voltage and generating a selection signal for distinguishing an upper gradation voltage above the gradation division reference voltage and a lower gradation voltage less than the gradation division voltage;
A first analog-to-digital converter for converting the upper gradation voltage into digital data;
A second analog-to-digital converter converting the lower gradation voltage into digital data; And
The output of the first analog data converter is selected when the upper gradation voltage is input to the comparator in response to the selection signal, and the output of the second analog data converter when the lower gradation voltage is input to the comparator. Pixel sensing device including a selection unit for selecting. According to claim 1,
And an amplifier that amplifies the lower gradation voltage and inputs it to the second analog-to-digital converter. According to claim 2,
A digital-to-analog converter for converting digital data output from the second analog-to-digital converter into an analog voltage; And
And a feedback compensator configured to receive the digital-to-analog converter at the lower gradation voltage and remove errors in digital data output from the digital-to-analog converter. According to claim 1,
The first analog-to-digital converter includes M (M is a positive integer of 4 or more) bit analog-to-digital converter,
The second analog-to-digital converter, N (N is a positive integer less than or equal to M) bit analog-to-digital converter pixel converter. The method according to any one of claims 1 to 4,
The gradation division reference voltage is a pixel sensing device that is set between a voltage of 1/2 or less within an input voltage range between a maximum voltage and a minimum voltage of the input voltage and a voltage higher than a minimum voltage of the input voltage range. A display panel in which data lines and gate lines are crossed and sub-pixels are disposed; And
A sensing unit that senses electrical characteristics of the sub-pixels;
A compensation unit for modulating pixel data of an input image based on digital data received from the sensing unit; And
And a display panel driving circuit for writing pixel data modulated by the compensation unit to the sub-pixels,
Each of the sub-pixels
And a pixel circuit including a light emitting element and a driving element driving the light emitting element,
The sensing unit
A comparator for comparing an input voltage obtained from the pixel circuit with a predetermined gradation division reference voltage and generating a selection signal for distinguishing an upper gradation voltage above the gradation division reference voltage and a lower gradation voltage less than the gradation division voltage;
A first analog-to-digital converter for converting the upper gradation voltage into digital data;
A second analog-to-digital converter converting the lower gradation voltage into digital data; And
The output of the first analog data converter is selected when the upper gradation voltage is input to the comparator in response to the selection signal, and the output of the second analog data converter when the lower gradation voltage is input to the comparator. An electroluminescent display device comprising a selector for selecting. The method of claim 6,
And an amplifier that amplifies the lower gradation voltage and inputs it to the second analog-to-digital converter. The method according to claim 6 or 7,
A digital-to-analog converter for converting digital data output from the second analog-to-digital converter into an analog voltage; And
And a feedback compensator configured to receive the digital-to-analog converter at the lower gradation voltage and to eliminate errors in digital data output from the digital-to-analog converter.

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