KR102544502B1 - Pixel sensing device and electroluminescence display using the same - Google Patents

Abstract

The present invention relates to a pixel sensing device and an electroluminescence display using the same, a first analog-to-digital converter for converting an upper grayscale voltage into digital data, a second analog-to-digital converter for converting a lower grayscale voltage into digital data, and In response to the selection signal, when the upper grayscale voltage is input to the comparator, the output of the first analog data converter is selected, and when the lower grayscale voltage is input to the comparator, the output of the second analog data converter is selected. Includes a selector to choose from.

Description

Pixel sensing device and electroluminescence display using the same

The present invention modulates pixel data of an input image based on the sensing voltage obtained from the pixel circuit of the sub-pixel by sensing the electrical characteristics of the sub-pixel in real time, thereby detecting changes in the electrical characteristics of each sub-pixel or deviation of the electrical characteristics between the sub-pixels in real time. It relates to a pixel sensing device that compensates and an electroluminescent display device using the same.

The electroluminescent display device is roughly divided into an inorganic light emitting display device and an organic light emitting display device according to the material of the light emitting layer. An active matrix type organic light emitting display includes an organic light emitting diode (OLED) that emits light by itself, and has a fast response speed, high luminous efficiency, luminance, and viewing angle. There are advantages.

The pixels of the organic light emitting display device include an OLED and a driving element that drives the OLED by supplying a current to the OLED according to a voltage between a gate and a source. An OLED of an organic light emitting display device includes an anode, a cathode, and an organic compound layer formed between the electrodes. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer, EIL). When current flows through the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the light emitting layer (EML) to form excitons, and as a result, the light emitting layer (EML) emits visible light. .

The driving element may be implemented as a TFT having a metal oxide semiconductor field effect transistor (MOSFET) structure. The electrical characteristics of the driving element should be uniform among all pixels, but there may be differences between the pixels due to process variation and element characteristic variation, and may change according to the lapse of display driving time. In order to compensate for the electrical characteristics of the driving element, an internal compensation method and an external compensation method may be applied to the electroluminescent display. The internal compensation method samples the gate-source voltage (Vgs) of the driving device, which varies according to the electrical characteristics of the driving device, and compensates for the data voltage by the gate-source voltage. The external compensation method senses the voltage of a pixel that changes according to the electrical characteristics of a driving element and modulates the data of the input image in an external circuit based on the sensed voltage, thereby changing the electrical characteristics of each sub-pixel or the electrical characteristics between the sub-pixels. Deviations can be compensated in real time.

In the external compensation method, a current value or a voltage value sensed from a pixel circuit must be accurately sensed in order to compensate for electrical characteristics of a subpixel. However, if the current or voltage value sensed from the pixel circuit is lower than the input voltage range of the Analog to Digital Converter (hereinafter referred to as “ADC”), the data output from the ADC cannot accurately represent the sensed value. Deterioration of , deviation compensation may become inaccurate. For example, when lower grayscale data is written into a pixel circuit, a sensed value is lower than a voltage range of an ADC, so that sensing in a lower grayscale may be inaccurate.

Accordingly, the present invention provides a pixel sensing device capable of improving lower grayscale voltage sensing and an electroluminescent display device using the same.

The pixel sensing device of the present invention compares an input voltage obtained from a pixel circuit with a predetermined grayscale division reference voltage to generate a selection signal for distinguishing an upper grayscale voltage equal to or higher than the grayscale division reference voltage and a lower grayscale voltage smaller than the grayscale division voltage. A comparator, a first analog-digital converter converting the upper grayscale voltage into digital data, a second analog-digital converter converting the lower grayscale voltage into digital data, and the comparator in response to the selection signal to convert the upper grayscale voltage into digital data and a selector that selects an output of the first analog data converter when a grayscale voltage is input and selects an output of the second analog data converter when the lower grayscale voltage is input to the comparator.

The electroluminescent display device of the present invention senses electrical characteristics of the sub-pixels using the pixel sensing device and modulates pixel data of an input image.

According to the present invention, an input voltage obtained from a pixel circuit in a sensing mode is compared with a reference voltage for dividing a predetermined gray level, and an upper gray level voltage and a lower gray level voltage are distinguished from the input voltage, and the upper gray level voltage is converted into digital data through a first analog data converter. and converts the lower grayscale voltage into digital data through the second analog data converter. As a result, the present invention can expand the ADC input voltage range by lowering the ADC input voltage, and increase the resolution of the ADC even in the low current and low voltage range to obtain the effect of expanding the bit of the ADC, as well as reducing the number of bits smaller than that of the existing ADC. Since the bit expansion effect can be obtained with the ADC, the size of the ADC can be reduced.

1 is a block diagram showing an electroluminescent display device according to an exemplary embodiment of the present invention.
2 is a circuit diagram showing an external compensation circuit connected to a pixel circuit.
3 and 4 are diagrams showing a sensing mode.
5 is a diagram showing an active period and a vertical blank period in detail.
6 is a circuit diagram showing the sensing unit shown in FIG. 2 in detail.
7 is a diagram showing voltages for each gradation when the input voltage range of the ADC is 3V.
8 is a diagram illustrating an example in which a sensing error occurs in a lower grayscale ADC input voltage.
9 is a flowchart illustrating a pixel sensing method according to an embodiment of the present invention.
10 is a circuit diagram showing a pixel sensing device according to an embodiment of the present invention.
11 is a diagram showing an example in which a lower grayscale ADC input voltage is amplified.
12 is a diagram showing amplified voltage in a lower gray level.
13 is a circuit diagram showing the first and second ADCs in detail.
14 is a diagram showing various application examples of the first and second ADCs.
15 is a circuit diagram showing a pixel sensing device according to another embodiment of the present invention.

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only the embodiments will make the disclosure of the present invention complete, and those of ordinary skill in the art to which the present invention belongs It is provided to fully inform the scope of the invention, the invention is defined only by the scope of the claims.

Since the shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, the present invention is not limited to those shown in the drawings. Like reference numbers designate substantially like elements throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted.

When "comprises", "includes", "has", "consists of", etc. mentioned in this specification is used, other parts may be added unless '~ only' is used. When a component is expressed in the singular, it may be interpreted in the plural unless specifically stated otherwise.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, when a positional relationship between two components is described as 'on ~', 'on top of ~', 'on the bottom of ~', 'next to', etc., ' One or more other components may be interposed between those components where 'immediately' or 'directly' is not used.

Although first, second, etc. may be used to distinguish the components, the function or structure of these components is not limited to the ordinal number or component name attached to the front of the component.

The following embodiments may be partially or wholly combined or combined with each other, and technically various interlocking and driving operations are possible. Each of the embodiments may be implemented independently of each other or together in an association relationship.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following embodiments, the electroluminescent display device of the present invention will be mainly described with an example in which an external compensation circuit is applied.

An external compensation circuit is applied to the electroluminescent display device of the present invention.

1 is a block diagram showing an electroluminescent display device according to an exemplary embodiment of the present invention. 2 is a circuit diagram showing an external compensation circuit connected to a pixel circuit.

Referring to FIGS. 1 and 2 , an electroluminescent display device according to an exemplary embodiment of the present invention includes a display panel 100 and a display panel driving circuit.

The electroluminescent display device of the present invention operates in a normal driving mode for displaying an input image on the screen and a sensing mode for sensing electrical characteristics of pixels. In the normal driving mode, the display panel driving circuits 110, 112, and 120 write pixel data of an input image into pixels during the active period AT of the display driving period in FIG. 3 under the control of the timing controller 130. In the sensing mode, the display panel driving circuits 110, 112, and 120, under the control of the timing controller 130, in FIG. OFF), the electrical characteristics of the driving element DT are sensed for each sub-pixel, and a compensation value is selected according to the sensed value to compensate for a change in electrical characteristics of the driving element DT.

The screen of the display panel 100 includes an active area AA displaying an input image. A pixel array is disposed in the active area AA. The pixel array includes a plurality of data lines 102, a plurality of gate lines 104 crossing the data lines 102, and pixels arranged in a matrix form.

Each of the pixels may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color implementation. Each of the pixels may further include a white sub-pixel. Each of the subpixels 101 includes a pixel circuit.

Touch sensors may be disposed on the display panel 100 . A touch input may be sensed using separate touch sensors or sensed through pixels. Touch sensors are implemented as on-cell type or add-on type touch sensors disposed on the screen of a display panel or embedded in a pixel array. can

The display panel driving circuits 110 , 112 , and 120 include a data driver 110 and a gate driver 120 . A demultiplexer 112 may be disposed between the data driver 110 and the data lines 102 . The demultiplexer 112 may be omitted.

The display panel driving circuits 110, 112, and 120 write pixel data of an input image into the pixels of the display panel 100 under the control of a timing controller (TCON) 130 in the normal driving mode to display on the screen. Display the input video. The display panel driving circuits 110, 112, and 120 may further include a touch sensor driver for driving the touch sensors. The touch sensor driver is omitted in FIG. 1 . In a mobile device or a wearable device, the data driver 110, the timing controller 130, and a power circuit omitted from the drawings may be integrated into a single drive IC (integrated circuit). The power circuit generates power necessary for driving the display panel driving circuits 110, 112, and 120 and the pixels.

As shown in FIG. 2 , the data driver 110 uses a digital-to-analog converter (hereinafter referred to as “DAC”) to provide pixel data of an input image received from the timing controller 130 in every frame period. (digital data) is converted into a gamma compensation voltage to output a data voltage (Vdata). The data voltage Vdata is supplied to the pixels through the demultiplexer 112 and the data line 102 . The data voltage Vdat is a data voltage for sensing supplied to subpixels in a sensing mode to sense deterioration of a driving element in each subpixel, and pixel data written to a subpixel and reproduced as an input image in a normal driving mode. divided by voltage.

The demultiplexer 112 is disposed between the data driver 110 and the data lines 102 using a plurality of switch elements to distribute the data voltage Vdata output from the data driver 110 to the data lines 102. do. Since the data voltage Vdata output from one channel of the data driver 110 by the demultiplexer 112 is divided in time to a plurality of data lines, the number of channels of the data driver 110 can be reduced.

The gate driver 120 may be implemented as a gate in panel (GIP) circuit formed directly on the display panel 100 together with the pixel array in the active area AA. The GIP circuit may be disposed on a bezel area of the display panel 100 outside the pixel array. The gate driver 120 outputs gate signals to the gate lines 104 under the control of the timing controller 130 . The gate driver 120 may sequentially supply the gate signals to the gate lines 104 by shifting the gate signals using a shift register. The gate signal may include a scan signal SCAN and a sensing signal SENSE, but is not limited thereto. The scan signal SCAN and the sensing signal SENSE may be synchronized with the data voltage Vdata.

The timing controller 130 controls operation timings of the display panel driving circuits 110, 112, and 120 in the normal driving mode and the sensing mode. The timing controller 130 receives pixel data (digital data A) of an input image and a timing signal synchronized therewith from a host system (not shown). The timing signal received by the timing controller 130 may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal CLK, and a data enable signal DE. One cycle of the vertical synchronization signal Vsync is one frame period. One period of the horizontal synchronization signal Hsync and the data enable signal DE is one horizontal period (1H). A pulse of the data enable signal DE is synchronized with pixel data of one pixel line to be displayed on the pixels of the active area AA. Since the frame period and the horizontal period can be known by counting the data enable signal DE, the vertical sync signal Vsync and the horizontal sync signal Hsync can be omitted.

The host system may be any one of a television (TV) system, a set top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a wearable device.

The timing controller 130 may adjust the frame rate to a frequency higher than the input frame frequency. For example, the timing controller 130 multiplies the input frame frequency by i to determine the operation timing of the display panel drivers 110, 112, and 120 at a frame frequency of frame frequency × i (i is a positive integer greater than 0) Hz. can control. The frame frequency is 60 Hz in the National Television Standards Committee (NTSC) method and 50 Hz in the Phase-Alternating Line (PAL) method.

The timing controller 130 generates data timing control signals for controlling the operation timing of the display panel driving circuits 110, 112, and 120 based on the timing signals Vsync, Hsync, CLK, and DE received from the host system. The display panel driving circuits 110, 112, and 120 are controlled. The voltage level of the gate timing control signal output from the timing controller 130 may be converted into a gate-on voltage and a gate-off voltage through a level shifter (not shown) and supplied to the gate driver 120 .

As shown in FIG. 2 , the external compensation circuit receives the sensing line 103 connected to the pixel circuit in each of the sub-pixels 101, the sensing unit 111, and the digital data ADC OUT output from the sensing unit 111. It includes a compensation unit 131 for receiving. The sensing unit 111 may sense electrical characteristics of the driving element DT by sensing the current flowing through the OLED. The DAC and the sensing unit 111 may be integrated into an integrated circuit (IC) of the data driver 110 . The compensator 131 may be built into the timing controller 130 .

The external compensation circuit initializes the source voltage Vs of the sensing line 103 and the driving element DT, that is, the voltage of the second node n2, with a reference voltage, and then senses the source voltage of the driving element DT. Electrical characteristics of the driving element DT may be sensed. Electrical characteristics of the driving element DT include a threshold voltage (Vth) and mobility (Vth, μ).

The sensing unit 111 samples the voltage on the sensing line 103 connected to the pixel circuit in the sensing mode and outputs digital data ADC OUT through the ADC.

Compensation values for compensating the threshold voltage Vth and mobility μ of the driving element DT for each sub-pixel are stored in the look-up table of the compensator 131 . The compensation unit 131 modulates the pixel data by adding or multiplying the compensation value output from the look-up table by inputting the sensing data received through the ADC into the look-up table, thereby controlling the change in electrical characteristics of the driving element DT. compensate The pixel data modulated by the compensator 131 is transmitted to the data driver 110, converted into a data voltage Vdata by the DAC of the data driver 110, and supplied to the data line 102. The driving element DT of the pixel circuit is driven by the data voltage Vdata supplied through the data line 102 to generate current. A current flowing through the driving element DT to the light emitting element OLED is determined according to the gate-source voltage Vgs of the driving element DT.

As in the example of FIG. 2 , the pixel circuit includes an OLED, a driving element DT connected to the OLED, a plurality of switch TFTs M1 and M2, and a capacitor Cst. The driving element DT and the switch TFTs M1 and M2 may be implemented as n-channel transistors (NMOS), but are not limited thereto.

The OLED emits light with current generated according to the gate-source voltage Vgs of the driving element DT, which varies according to the data voltage Vdata. An OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode of the OLED is connected to the driving element DT through the second node n2, and the cathode of the OLED is connected to the VSS electrode to which the low potential power supply voltage VSS is applied. In FIG. 2, “Coled” is the capacitance of OLED.

The first switch TFT (M1) is turned on according to the gate-on voltage of the scan signal (SCAN) and connects the data line 102 to the first node (n1) to supply the data voltage (Vdata) to the first node (n1). is supplied to the gate of the driving element DT connected to . The first switch TFT (M1) has a gate connected to the first gate line 1041 to which the first scan signal SCAN is applied, a first electrode connected to the data line 102, and a first node connected to the first node n1. Contains 2 electrodes.

The second switch TFT M2 is turned on according to the sensing signal SENSE and supplies the reference voltages VPRES and VPRER to the second node n2. The second switch TFT (M2) includes a gate connected to the second gate line 1042 to which the sensing signal SENSE is applied, a first electrode connected to the sensing line 103 to which the reference voltages VPRES and VPRER are applied, and a second switch TFT M2. 2 includes a second electrode connected to the node n2.

The driving element DT drives the OLED by supplying current to the OLED according to its gate-source voltage Vgs. The driving element DT is an OLED through a gate connected to the first node n1, a first electrode (or drain) connected to the VDD line 105 to which the pixel driving voltage VDD is supplied, and a second node n2. and a second electrode (or source) connected to the anode of The capacitor Cst is connected between the first node n1 and the second node n2. The capacitor Cst charges the gate-source voltage Vgs of the driving element DT.

3 and 4 are diagrams showing a sensing mode. 5 is a diagram showing an active period (AT) and a vertical blank period (VB) in detail.

Referring to FIGS. 3 to 5 , the sensing mode is divided into before product shipment and after product shipment. Before product shipment, the electrical characteristics (Vth, μ) of the driving element DT are sensed in each sub-pixel through an external compensation circuit connected to the pixels, and the electrical characteristics (Vth, μ) of the driving element DT for each sub-pixel Variations or deviations in Vth, μ) are compensated for.

After product shipment, the sensing modes are ON RF mode performed in the power ON sequence, RT MODE performed in the vertical blank (VB) during the display driving period, and power OFF sequence. It can be divided into OFF RS mode that is implemented.

In the ON RF mode, when the power of the field emission display device is turned on, the mobility (μ) of the driving element (DT) is sensed in each pixel, and the mobility sensing value is measured by the driving element (DT) measured for each sub-pixel before product shipment. Compared with the mobility compensation value of , the mobility compensation value is updated based on the difference. In the sensing mode before product shipment, the threshold voltage and mobility of the driving element for each sub-pixel are sensed, and the threshold voltage compensation value and mobility compensation value of the driving element are set in a look-up table. The mobility μ of the driving element is compensated for by a mobility compensation value reflecting the mobility sensing value of the driving element DT for each sub-pixel.

In the RT mode, the mobility μ of the driving element DT is sensed in real time in a vertical blank interval (VB) in every frame period during the display driving period when an image is displayed, and the sub-pixel is sensed according to the mobility sensing value. Each mobility compensation value is updated. The vertical blank period (VB) is allocated a predetermined time between the active period (AT) of the N−1th frame period and the active period (AT) of the Nth frame period.

In the OFF RS mode, when the power of the display device is turned off, each pixel senses the threshold voltage Vth of the driving element DT, and updates the threshold voltage compensation value for each sub-pixel according to the threshold voltage sensed value. In the OFF RS mode, the display panel driving circuits 110, 112, and 120 and an external compensation circuit are driven for a preset delay time before the power is completely turned off to set the threshold voltage (Vth) of the driving element in each of the sub-pixels. By sensing, the threshold voltage compensation value is updated for each sub-pixel. When the threshold voltage compensation value is updated at the Nth power-off time (OFF(N)), it may be maintained as it is in the ON RF mode and the RT mode, and then updated at the Nth power-off time (OFF(N)).

Meanwhile, electrical characteristics of the driving element DT may be sensed in a predetermined number of pixel lines in a predetermined order within an active period AT in which pixel data of an input image is written into pixels.

In FIG. 5, the vertical synchronization signal Vsync defines one frame period. One frame period is the sum of the active period (AT) and the vertical blank period (VB). The horizontal synchronization signal (Hsync) defines one horizontal period (Horizontal time). The data enable signal DE defines a valid data period including pixel data to be displayed on the screen.

The data enable signal DE is synchronized with valid data to be displayed on the pixel array of the display panel 100 . One pulse period of the data enable signal DE corresponds to one horizontal period, and a high logic period of the data enable signal DE indicates data input timing of one pixel line. One horizontal period is a time required to write data to pixels of one pixel line in the display panel 100 .

The timing controller 130 receives the data enable signal DE and data of the input image during the active period AT. There is no data enable signal DE and data of the input image in the vertical blank period VB. During the active period AT, one frame of data to be written in all pixels is received by the timing controller 130 .

As can be seen from the data enable signal DE, input data is not received by the display device during the vertical blank period VB. The vertical blank period VB includes a vertical sync time (VS), a vertical front porch (FP), and a vertical back porch (BP). The vertical sync time (VS) is the time from the falling edge of Vsync to the rising edge, and represents the start (or end) timing of the screen.

6 is a circuit diagram showing the sensing unit 111 in detail.

Referring to FIG. 6 , the sensing unit 111 includes switch elements SW1 to SW3 for switching the reference voltages VPRER and VPRES, a capacitor Csam, a sampling & scaler circuit 112, and an analog to digital converter (hereinafter referred to as “ADC”) and the like. In FIG. 6, “Csio” is a capacitor connected to the sensing line 103. The switch elements SW1 to SW3 may be implemented as n-channel transistors (NMOS).

The reference voltages VPRER and VPRES are divided into a first reference voltage VPRES for initializing the pixel circuit and a second reference voltage VPRER set to a higher voltage than the first reference voltage VPRES. The first reference voltage VPRES is set as a voltage for initializing the driving element DT and the OLED in the sensing mode. The second reference voltage VPRER charges the source voltage Vs of the driving element DT to a voltage higher than 0V in the normal driving mode. The second reference voltage VPRER is a voltage margin for setting the compensation voltage of the data voltage Vdata when the threshold voltage shifts in the negative polarity direction due to gate bias stress of the driving element DT. ) can be set to a voltage higher than 0V to provide VPRES = 0V, VPRER = 3V, but is not limited thereto.

The first switch element SW1 is turned on according to the high logic voltage of the first switch control signal SPRE to apply the first reference voltage VPRES to the sensing line 103. supply The second switch element SW2 is turned on according to the high logic voltage of the second switch control signal RPRE to supply the second reference voltage VPRER to the sensing line 103 . The third switch element M3 is turned on according to the high logic voltage of the third switch control signal SAM and connects the sensing line 103 to the capacitor Csam. The capacitor Csam is formed between the reference voltage terminal EVREF2 and a node between the third switch element SW3 and the input terminal of the sample & scaler circuit 112 . The reference voltage terminal EVREF2 may be set to GND = OV.

The sampling & scaler circuit 112 includes a fourth switch and a voltage scaler (not shown). The fourth switch is turned on alternately with the third switch M3 to supply the sampling voltage charged in the capacitor Csam to the voltage scaler. A voltage scaler adjusts the sampling voltage to within the ADC's input voltage range. The ADC converts the input voltage into digital data and outputs digital data (ADC OUT) indicating the sensed value. When a low voltage below the input voltage range of the ADC is input to the ADC, the electrical characteristics of the driving element are not accurately sensed.

7 shows the voltage for each gradation when the input voltage range of the ADC is 3V. In FIG. 7, the x-axis is the gray level of pixel data, and the y-axis is the input voltage (Vin) of the ADC. 8 is a diagram showing an example in which a sensing error occurs when the input voltage (Vin) of the ADC is low. In FIG. 8 , the y-axis represents the voltage difference (ΔV) between gray levels. 8, 0.003V is the voltage between gradations 44 and 45, and 0.01V is the voltage between gradations 120 and 121.

When the input voltage range of the ADC is 3V, 3/1024 = 0.0003V per bit based on 10 bits. However, as can be seen in FIG. 7, if the current flowing through the OLED is small in the case of the lower gradation, the voltage sensed at the gradation in the lower gradation range is input to the ADC as the minimum voltage in the input voltage range of the ADC, although there is a gradation difference. In the data output from the ADC, there is an example in which gray levels cannot be distinguished. For example, as shown in FIGS. 7 and 8 , since ΔV of a sensing voltage in a lower grayscale range of 45 or less is 0.003V or less, it is converted into the same digital data through an ADC, resulting in a sensing error.

9 is a flowchart illustrating a pixel sensing method according to an embodiment of the present invention. The sensing method of the present invention may be implemented as a pixel sensing device shown in FIG. 10 . In order to increase the resolution of the ADC for the lower gradation voltage, which cannot be distinguished between gradations in the prior art, as shown in FIG. 10, the sensing voltage received from the pixel circuit, that is, the ADC input voltage, is converted into digital data using two ADCs. .

Referring to FIG. 9 , the current or voltage is sensed from the pixel circuit (S1). The sensed current is converted into a voltage. Subsequently, the present invention inputs the current or voltage sensed from the pixel circuit to the ADC, and compares the ADC input voltage (Vin) with a predetermined gray level division reference voltage (Vref) (S2 and S3).

The gradation discrimination reference voltage Vref may be set to a lower gradation voltage at which it is difficult to distinguish gradations in an input voltage range of the ADC. The gradation division reference voltage Vref may be appropriately set between a voltage of 1/2 or less within the input voltage range between the maximum voltage and minimum voltage of the input voltage Vin and a voltage higher than the minimum voltage of the input voltage range. there is. For example, the gradation period reference voltage Vref may be selected from 0.003V to 1.5V in the case of a 10-bit ADC having an input voltage range of 3V.

In the present invention, when the ADC input voltage (Vin) is determined to be an upper gray level voltage higher than the gray level division reference voltage (Vref), the sensing value output from the first ADC, that is, the digital data (ADC OUT) is selected and transmitted to the compensation unit 131 (S3 and S4). On the other hand, in the present invention, if the ADC input voltage (Vin) is a lower gradation voltage lower than the gradation division reference voltage (Vref), digital data (ADC OUT) output from the second ADC is selected and transmitted to the compensation unit 131 ( S3 and S4). An ADC input voltage smaller than the gray level division reference voltage Vref may be amplified and input to the second ADC within an input voltage range of the second ADC.

Referring to FIG. 10 , the pixel sensing device of the present invention includes a comparator 10 , a first ADC 12 , an amplifier 14 , a second ADC 16 , and a selector 18 .

The comparator 10 compares the input voltage Vin obtained from the pixel circuit with a predetermined grayscale division reference voltage to generate a selection signal for distinguishing an upper grayscale voltage equal to or higher than the grayscale division reference voltage and a lower grayscale voltage smaller than the grayscale division voltage. . The comparator 10 transmits the input voltage Vin obtained from the pixel circuit to the first and second ADCs 12 and 16 . The voltage level of the ADC input voltage Vin varies according to the gradation of the data voltage supplied to the pixel circuit. The amplifier 14 amplifies the input voltage Vin of the second ADC 16 .

The comparator 10 selects the digital data ADC OUT output from the first ADC 12 as the final ADC data when the ADC input voltage Vin is higher than the gray level division reference voltage Vref. On the other hand, the comparator 10 converts digital data (ADC OUT) output from the second ADC 16 as final ADC data when the ADC input voltage (Vin) is a lower gradation voltage lower than the gradation division reference voltage (Vref). choose

The first ADC 12 may be implemented as an M (M is a positive integer greater than or equal to 4) bit ADC. The first ADC 12 converts the input voltage Vin input from the comparator 10 into digital data. The first ADC 12 converts an input voltage Vin of an upper gray level voltage equal to or higher than the gray level division reference voltage Vref into digital data ADC OUT. The second ADC 16 may be implemented as an N bit ADC (where N is a positive integer less than or equal to M) bit ADC. The second ADC 16 converts the input voltage Vin of a lower grayscale voltage smaller than the grayscale division reference voltage Vref into digital data ADC OUT.

The selector 18 selects one of the output data of the first ADC 12 and the output data of the second ADC 16 under the control of the comparator 10 . The comparator 10 generates a selection signal as a first logic voltage when the ADC input voltage Vin is an upper gradation voltage, and generates a selection signal as a second logic voltage when the ADC input voltage Vin is a lower gradation voltage. do. The selection unit 18 selects output data of the first ADC 12 in response to the first logic voltage of the selection signal and transmits it to the compensation unit 131 . The selection unit 18 selects output data of the second ADC 14 in response to the second logic voltage of the selection signal and transmits it to the compensation unit 131 .

11 is a diagram showing an example in which a lower grayscale ADC input voltage is amplified. 12 is a diagram showing amplified voltage in a lower gray level.

The ADC applied to the conventional sensing unit could obtain a sensing value as digital data through a 10-bit ADC or a 12-bit ADC, but in the case of a lower gray level, it could not be distinguished by ADC output data. In the present invention, the ADC input voltage range is expanded by separating the upper grayscale voltage and the lower grayscale voltage with the reference voltage and reducing the ADC input voltage by dividing the ADC into binary with the first and second ADCs 12 and 16 . Therefore, according to the present invention, the bit expansion effect of the ADC can be obtained by increasing the resolution of the ADC even in the low current and low voltage range, and the bit expansion effect can be obtained with an ADC having a smaller number of bits than the conventional ADC, so the size of the ADC can be reduced.

13 is a circuit diagram showing the first and second ADCs 12 and 16 in detail. In FIG. 13, each of the first and second ADCs is exemplified as a 10 bit ADC, but is not limited thereto.

Referring to FIG. 13 , the first ADC 12 includes a reference voltage generator 30 that generates a plurality of reference voltages, a comparator 32 that compares the input voltage Vin and the reference voltage, and a comparator 32 ) and an encoder 34 for outputting digital data (ADC OUT) by encoding the output.

The comparator 30 divides the highest reference voltage (3V) and the gray level division reference voltage (Vref) using a voltage divider circuit in which resistors are connected in series to obtain the highest level reference voltage (3V) and the gray level division reference voltage ( Vref) outputs reference voltages having different voltage levels. The reference voltages may be input to the comparator 32 through an amplifier (not shown).

The comparator 32 includes a plurality of comparators that compare the input voltage Vin with reference voltages. Each of the comparators outputs a low logic (low = 0) when the input voltage Vin is greater than the reference voltage, while outputs a high logic (high = 1) when the reference voltage is greater than the input voltage Vin. The output of the comparator 32 indicates a boundary between '1' and '0' according to the comparison result of the input voltage and the reference voltages, and is known as a so-called “thermometer code”. The encoder 34 selects the digital code of the upper grayscale voltage corresponding to the thermometer code from the comparator 32 and outputs digital data ADC OUT.

The second ADC 16 includes a reference voltage generator 36 generating a plurality of reference voltages, a comparator 38 comparing the input voltage Vin and the reference voltage, and encoding the output of the comparator 38. It includes an encoder 40 that outputs digital data (ADC OUT).

The comparator 30 divides the highest reference voltage (3V) and the gray level division reference voltage (Vref) using a voltage divider circuit in which resistors are connected in series, and divides the gray level division reference voltage (Vref) and the lowest gray level division reference voltage (Vref) from each of the voltage dividing nodes. 0V) to output reference voltages with different voltage levels. Reference voltages may be input to the comparator 38 through an amplifier (not shown).

The comparator 38 includes a plurality of comparators that compare the input voltage Vin with reference voltages and outputs a thermometer code. Each of the comparators outputs a low logic (low = 0) when the input voltage Vin is greater than the reference voltage, while outputs a high logic (high = 1) when the reference voltage is greater than the input voltage Vin. The encoder 40 selects a digital code of a lower grayscale voltage corresponding to the thermometer code from the comparator 38 and outputs digital data ADC OUT.

As shown in FIG. 14, the first ADC 12 may be implemented as an 11-bit ADC and the second ADC 16 may be implemented as a 9-bit ADC. As another example, the first ADC 12 may be implemented as a 13-bit ADC and the second ADC 16 may be implemented as a 12-bit ADC.

Another embodiment of the present invention removes the quantization error of the data (ADC OUT) output from the second ADC using a feedback compensation loop as shown in FIG. can be corrected. The feedback compensation loop converts the input voltage (Vin) into digital data in the primary loop, inverts and amplifies the value by feeding back the value, adds the inverted and amplified voltage to the input voltage (Vin), and adds the digital data output from the second ADC 12. Remove the error of (ADC OUT).

15 is a circuit diagram showing a pixel sensing device according to another embodiment of the present invention. In FIG. 15, the same reference numerals are assigned to substantially the same components as those of the above-described embodiment, and detailed descriptions thereof will be omitted.

Referring to FIG. 15, the pixel sensing device includes a comparator 10, a first ADC 12, an amplifier 14, a feedback compensator 20, a second ADC 16, a selector 18, and a DAC. (22).

The first ADC 12 converts an input voltage Vin of an upper gray level voltage equal to or higher than the gray level division reference voltage Vref into digital data ADC OUT. The second ADC 12 converts an input voltage Vin of a lower grayscale voltage smaller than the grayscale division reference voltage Vref into digital data ADC OUT.

The output data ADC of the second ADC 16 is converted into an analog voltage through the DAC 22 and input to the non-inverting input terminal (-) of the feedback compensator 20 . The DAC 22 may be implemented as a 10-bit DAC when the second ADC 16 is a 10-bit ADC.

The operational amplifier of the feedback compensator 20 has a non-inverting input terminal (+) connected to the output node of the amplifier 14 through a resistor, an inverting input terminal (-) connected to the output node of the DAC 22 through a resistor, and It includes an output terminal connected to the input node of the second ADC 16 and connected to the inverting input terminal (-) through a resistor. The feedback compensator 20 adds the inverted voltage of the difference voltage between the feedback voltage from the DAC 22 and the input voltage to the input voltage Vin, thereby reducing the error of the digital data ADC OUT output from the second ADC 16. Remove.

The selector 18 selects one of the output data of the first ADC 12 and the output data of the second ADC 16 under the control of the comparator 10 . The comparator 10 generates a selection signal as a first logic voltage when the ADC input voltage Vin is an upper gradation voltage, and generates a selection signal as a second logic voltage when the ADC input voltage Vin is a lower gradation voltage. do. The selection unit 18 selects output data of the first ADC 12 in response to the first logic voltage of the selection signal and transmits it to the compensation unit 131 . The selection unit 18 selects output data of the second ADC 14 in response to the second logic voltage of the selection signal and transmits it to the compensation unit 131 .

When Vin = 2.99395V is input to the second ADC 16 and the digital data (ADC OUT) output from the second ADC 16 is converted into an analog voltage through the DAC 22, if it is 2.991V, the second ADC (16 ) causes a difference between the input voltage (Vin) and the feedback voltage from the DAC. In this example, the feedback compensator 20 compensates for the quantization error of the second ADC 16 as follows.

2.99395V + 0.00295V = 2.9969V

Here, 2.99395V is the input voltage (Vin) and 0.00295V is 2.99395-2.991 = 0.00295 obtained by inverting and amplifying the DAC conversion voltage of the output data (ADC OUT) of the second ADC 16.

Through the above description, those skilled in the art will understand that various changes and modifications are possible without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

10: comparison unit 12: first ADC
14: amplifier 16: second ADC
18: selection unit 20: feedback compensation unit
22: DAC 30, 36: reference voltage generator
32, 38: comparison unit 34, 40: encoder
100: display panel 110: data driving unit
120: gate driver 130: timing controller
111: sensing unit 131: compensation unit

Claims (8)

a comparator which compares the input voltage obtained from the pixel circuit with one gray level division reference voltage and generates a selection signal that distinguishes between an upper gray level voltage equal to or greater than the gray level division reference voltage and a lower gray level voltage lower than the gray level division reference voltage;
a first analog-to-digital converter converting the upper grayscale voltage into digital data;
a second analog-to-digital converter converting the lower grayscale voltage into digital data;
an amplifier that amplifies the input voltage input to the second analog-to-digital converter; and
In response to the selection signal, the output of the first analog-to-digital converter is selected when the upper grayscale voltage is input to the comparator, and the second analog-to-digital converter is selected when the lower grayscale voltage is input to the comparator. Including a selection unit for selecting the output of,
The input voltage is input to the first analog-to-digital converter and the second analog-to-digital converter, respectively;
The pixel sensing device of claim 1 , wherein the input voltage is input without amplification to the first analog-to-digital converter and amplified and input to the second analog-to-digital converter. According to claim 1,
a digital-to-analog converter converting the digital data output from the second analog-to-digital converter into an analog voltage; and
and a feedback compensator configured to receive the lower grayscale voltage from the digital-to-analog converter and remove an error in digital data output from the digital-to-analog converter. According to claim 1,
The first analog-to-digital converter includes an M (M is a positive integer greater than or equal to 4) bit analog-to-digital converter;
The second analog-to-digital converter includes an N (N is a positive integer less than or equal to M) bit analog-to-digital converter. According to claim 3,
The number of bits of the second analog-to-digital converter is smaller than the number of bits of the first analog-to-digital converter. According to any one of claims 1 to 4,
The grayscale division reference voltage is set between a voltage of 1/2 or less within an input voltage range between a maximum voltage and a minimum voltage of the input voltage and a voltage higher than the minimum voltage of the input voltage range. a display panel in which data lines and gate lines intersect and sub-pixels are disposed; and
a sensing unit that senses electrical characteristics of the sub-pixels;
a compensation unit modulating pixel data of an input image based on the digital data received from the sensing unit; and
a display panel driving circuit that writes the pixel data modulated by the compensator into the sub-pixels;
Each of the sub-pixels is
A pixel circuit including a light emitting element and a driving element for driving the light emitting element,
the sensing unit
a comparator which compares the input voltage obtained from the pixel circuit with one gray level division reference voltage and generates a selection signal that distinguishes between an upper gray level voltage equal to or greater than the gray level division reference voltage and a lower gray level voltage lower than the gray level division reference voltage;
a first analog-to-digital converter converting the upper grayscale voltage into digital data;
a second analog-to-digital converter converting the lower grayscale voltage into digital data;
an amplifier that amplifies the input voltage input to the second analog-to-digital converter; and
In response to the selection signal, the output of the first analog-to-digital converter is selected when the upper grayscale voltage is input to the comparator, and the second analog-to-digital converter is selected when the lower grayscale voltage is input to the comparator. Including a selection unit for selecting the output of,
The input voltage is input to the first analog-to-digital converter and the second analog-to-digital converter, respectively;
wherein the input voltage is input without amplification to the first analog-to-digital converter and amplified and input to the second analog-to-digital converter. delete According to claim 6,
a digital-to-analog converter converting the digital data output from the second analog-to-digital converter into an analog voltage; and
and a feedback compensator configured to receive the lower grayscale voltage from the digital-to-analog converter and remove an error in digital data output from the digital-to-analog converter.

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