JPH0666927B2 - Video signal A / D conversion method - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a video signal A / D conversion method in a television receiver using a panel type display unit.

[Prior Art and its Problems] In recent years, a portable small-sized television receiver using a liquid crystal display panel for a display unit has been put into practical use. In this type, a conventional television receiver using a liquid crystal display panel converts a video signal amplified by a video amplifier circuit into a digital signal corresponding to a plurality of gradations from a maximum gradation to a minimum gradation by an A / D conversion circuit. The digital signal is converted and the liquid crystal display panel is driven by the digital signal. However, the liquid crystal display panel has a problem in that a gradation range from a white (bright) level to a black (dark) level is narrow due to its characteristics, and it is difficult to obtain an image with good contrast. In order to solve such a problem, recently, the average value of the television video signal is detected, and the reference voltage of the A / D conversion circuit is set accordingly to obtain a good contrast. That is, the video signal does not always change from the white level to the black level, and it is not necessary to A / D convert the entire range of the video signal. Therefore, the conversion level of the A / D conversion circuit depends on the video signal. It is possible to improve the contrast by varying. Although it is possible to improve the contrast as described above, conventionally, it is completely unclear what level the reference voltage should be specifically set, and there is a problem that the specificity is lacking.

[Object of the Invention] The present invention has been made in view of the above points, and an object of the present invention is to provide a video signal A / D conversion method capable of obtaining an optimum contrast and always displaying a beautiful screen.

[Points of the Invention] The present invention adjusts the upper and lower reference voltages so that the data of perfect white (maximum gradation) and perfect black (minimum gradation) on one screen is approximately 10 to 15% of the total. This is to ensure that a beautiful screen is always obtained.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. First, the overall schematic configuration will be described with reference to FIG. The video signal sent from the video amplifier circuit (not shown) via the signal line DL is input to the video signal A / D conversion circuit 1 and the reference level A / D conversion circuit 2. The reference level A / D conversion circuit 2 is supplied with an upper limit reference voltage V _RH and an adjustable reference voltage V _{RL that} are set to predetermined values from a control unit (not shown), and is sampled at, for example, 3.12 MHz. The clock ψ _S is input. The reference level A / D conversion circuit 2 compares the video signal with the upper limit reference voltage V _RH and the lower limit reference voltage V _RL, and if the image signal is equal to or higher than the upper limit reference voltage V _RH , it is determined to be a white level. The white digital signal W synchronized with the sampling clock ψ _S is output, and if the video signal is equal to or lower than the lower limit reference voltage V _{RL, the} black level is determined and the black digital signal _B is output. The white level signal W output from the reference level A / D conversion circuit 2 is input to the pulse creating circuit 3, and the black level signal B is input to the pulse creating circuit 4. In addition, the above-mentioned palace creation circuits 3 and 4 have clock pulses from the control unit. Is entered. The clock pulse φ ₂ is output about 50,000 times in one field. Is also a clock pulse when the field changes The output is delayed by several H (H is a horizontal period). The outputs of the pulse generation circuits 3 and 4 are sent to the integration circuits 5 and 6, respectively. Operating voltages V ₁ and V ₂ are supplied to the integrating circuit 5, and operating voltages V ₁ ′ and V ₂ ′ are supplied to the integrating circuit 6. Then, the integration circuit 5 integrates the voltages V ₁ and V ₂ in accordance with the signal from the pulse generation circuit 3, and outputs the integrated output to the video signal A / D conversion circuit 1 as the upper limit reference voltage V _H ,
The integrating circuit 6 produces a voltage according to the signal from the pulse creating circuit 4.
V ₁ ′ and V ₂ ′ are integrated and the integrated output is output to the video signal A / D conversion circuit 1 as the lower limit reference voltage V _L. The video signal A / D conversion circuit 1 converts the video signal from the video amplification circuit into a 4-bit digital signal according to the upper limit reference voltage V _H and the lower limit reference voltage V _L given by the integrating circuits 5 and 6, and a liquid crystal display Liquid crystal display circuit using panel (not shown)
Output to.

Next, details of the reference level A / D conversion circuit 2, the pulse generation circuit 3, and the integration circuit 5 will be described with reference to FIG.
The reference level A / D conversion circuit 2 includes an A / D conversion circuit 21 and a decoder 22. The video signal from the video amplification circuit is input to the A / D conversion circuit 21 and the upper limit reference voltage V _RH and the lower limit reference voltage are input. V _RL is input. Then, the A / D conversion circuit 21 converts the white level signal of the upper reference voltage V _RH or more into a 4-bit digital signal (all “1”), and the black level signal of the lower reference voltage V _RL or less of the 4-bit digital signal. Convert to digital signal (all “0”) and output. The output signal of the A / D conversion circuit 21 is decoded by the decoder 22 in synchronization with the sampling clock φ _S and output as the white level signal W and the black level signal B. Then, the white level signal W is sent to the pulse creating circuit 3 and the black level signal B is sent to the pulse creating circuit 4.

The pulse generation circuit 3 includes an AND circuit 31, for example, a 4096-ary counter 32, a data latch circuit 33, a D / D converter.
The white level signal W from the reference level A / D conversion circuit 2 is input to the clock terminal of the counter 32 via the AND circuit 31. Further, the latch output of the latch circuit 35 is input to the AND circuit 31. This latch circuit 35 has a clock pulse Are latched by and are reset by the carry signal of the counter 32. Also, the above clock pulse Is input to the reset terminal of the counter 32. The count output of the counter 32 is the clock pulse. The data is latched by the data latch circuit 33 in synchronization with, and sent to the D / D converter 34. This D / D converter 34 clocks the latch data of the data latch circuit 33 into a clock pulse. D / D conversion is performed in synchronism with, and the converted output is output to the integrating circuit 5.

The integration circuit 5 includes a time constant circuit 51 including an integration resistor R and an integration capacitor C, a gate circuit 52 that controls the supply of the operating voltage V ₁ to the time constant circuit 51, and a gate circuit 53 that controls the supply of the operating voltage V _2. The output signal of the D / D converter 34 is directly input to the gate terminal of the gate circuit 53 and is also input to the gate terminal of the gate circuit 52 via the inverter 54. The time constant circuit 51 has a time constant set to about 2 ms, and its output is sent to the video signal A / D conversion circuit 1 as the upper limit reference voltage V _H.

On the other hand, the pulse creating circuit 4 and the integrating circuit 6 for processing the black level signal are configured in the same manner as the pulse creating circuit 3 and the integrating circuit 5, and the details thereof will be omitted.

Next, the operation of the above embodiment will be described with reference to the timing charts of FIGS. In this example,
The number of dots on the liquid crystal display panel is "120 x 160 = 19200", and the ideal numbers of perfect white and perfect black are "2300". When the video signal shown in FIG. 3 is sent from the video amplification circuit to the reference level A / D conversion circuit 2, the reference level A / D conversion circuit 2 converts the video input signal into the upper limit reference voltage V _RH , Lower reference voltage V _RL compared to upper reference voltage V
_The A / D conversion circuit 21 outputs a 4-bit digital signal of all "1" for a white level signal of _RH or more and all "0" for a black level signal of a lower limit reference voltage V _RL or less. . Then, the white level and black level digital signals output from the A / D conversion circuit 21 are decoded by the decoder 22 and output as the white level signal W and the black level signal B as shown in FIG. Then, the white level signal W output from the decoder 22 is sent to the pulse creating circuit 3, and the black level signal B is sent to the pulse creating circuit 4.

The pulse generation circuit 3 is a clock pulse The counter 32 is reset in synchronization with Are latched by the latch circuit 35. Clock pulse to this latch circuit 35 Is latched, its output becomes "1" and the AND circuit
31 gates are opened. As a result, the white level signal W output from the decoder 22 is countered via the AND circuit 31.
It is sent to 32, and the count up operation of the counter 32 is started. The counter 32 counts the white level signal W sent from the decoder 22 for one field,
The count content is clock pulse when moving to the next field. The data is latched by the data latch circuit 33 in synchronization with, and sent to the D / D converter 34. In this case, when a signal of "4096" or more is sent from the decoder 22 to the counter 32 in one field, the carry signal is output from the counter 32 and the latch circuit 35 is reset. This closes the gate of the AND circuit 31 and prohibits subsequent inputs. The D / D converter 34 performs the D / D conversion operation shown in FIG. 4 according to the contents of the data latch circuit 33. FIG. 4 shows the D / D converter 34 when the count value “1000” is latched by the data latch circuit 33 from the counter 32.
It shows the operation of. The D / D converter 34 is reset by the clock pulse φ ₂ when the field changes, and changes each field from the first block to the thirteenth block.
The blocks are equally divided into 13 blocks, and the time width of each block is obtained by counting 4096 clock pulses φ ₂ . The first to thirteenth blocks are equally divided into 16 blocks from the first small block to the sixteenth small block, and each small block corresponds to 256 clock pulses φ ₂ . And D
The / D converter 34 outputs a pulse signal having a time width according to the latch data of the data latch circuit 33 in the first to 16th small blocks. For example, when the count value "1000" is latched in the data latch circuit 33 as described above, the first to eighth small blocks are pulse signals with a time width of clock pulse φ ₂ 63 shots, and the ninth to ninth small blocks. 16th
A pulse signal with a time width of φ ₂ 62 clock pulses up to a small block is output. That is, the count value “10
00 "is averaged and divided in the first to 16th small blocks. Then, the signals of the first to 16th small blocks are sent to the integrating circuit 5 as the output of the D / D converter 34.

In the integration circuit 5, in the first to sixteenth small blocks from the D / D converter 34, the gate of the gate circuit 53 is opened while the high level signal is given, and the voltage V ₂ is supplied to the time constant circuit 51. The gate of the gate circuit 52 is opened by the output of the inverter 54 while the low level signal is being output, and the voltage V ₁ is output to the time constant circuit 51. This time constant circuit
The reference numeral 51 integrates the voltages V ₂ and V ₁ given to the input point a via the gate circuit 53 or the gate circuit 52, and the integrated voltage is used as the upper limit reference voltage V _H in the video signal A / D conversion circuit 1. give. The upper voltage V ₁ is a lower limit value of the video signal with respect to its own signal, and the voltage V ₂ is an upper limit value thereof. Then, when the latch data of the data latch circuit 33 in the pulse generation circuit 3 is "0", the output of the D / D converter 34 is at a low level all the time, and therefore the output of the gate circuit 52 becomes "1". As a result, the gate of the gate circuit 52 is opened, and the voltage V ₁ is output as the upper limit reference voltage V _H. If the latched data of the data latch circuit 33 is "4096", the output of the D / D converter 34 is at a high level all the time, so that the gate of the gate circuit 53 opens and the voltage V ₂ becomes the upper limit reference voltage V _H. Is output as. Accordingly, the latch data of the data latch circuit 33 is the output of the integration circuit 5 every time decreased "1", "| V ₂ -V ₁ | / 4096" decreases by one. Data latch circuit 33
If the latched data of 2 is “2300”, the upper limit reference voltage V _H output from the integrating circuit 5 is at a level approximately between the voltages V ₁ and V ₂ .

On the other hand, also in the pulse generation circuit 4 and the integration circuit 6 which process the black level signal B output from the reference level A / D conversion circuit 2, the same processing as that for the white level signal W is performed, and the integration circuit 6 The lower limit reference voltage V _L is output from the above and sent to the video signal A / D conversion circuit 1.

Then, the video signal A / D conversion circuit 1 converts the video signal sent from the video amplifier circuit into a 4-bit digital signal 160 times within 1H according to the upper limit reference voltage V _H and the lower limit reference voltage V _L. D-convert and output to liquid crystal display circuit.

When the video signal for a general screen is output from the video amplifier circuit, the screen looks most beautiful because the white level signal W output from the reference level A / D conversion circuit 2 during one field and The black level signal B, that is, the number of all "1s" and all "0s" is approximately "2300".
It is time for Then, based on the white level signal W and the black level signal B output from the reference level A / D conversion circuit 2, the pulse creating circuit 3 and the pulse creating circuit 4 create a pulse signal as described above. Accordingly, the upper limit reference voltage V _H and the lower limit reference voltage V _L are created from the integrating circuit 5 and the integrating circuit 6, and are sent to the video signal A / D conversion circuit 1. The video signal A / D conversion circuit 1 performs A / D conversion processing according to the upper limit reference voltage V _H and the lower limit reference voltage V _L, but in the case of a basic screen as described above, white and black Adjust each circuit so that the signal is approximately "2300" for each screen.

Next, if a sufficiently white screen is input as the input video signal and the number of all "1s" output from the reference level A / D conversion circuit 2 becomes "2300 + n", the pulse generation circuit 3
The signal time width in the first to 16th small blocks output from the D / D converter 34 of the above becomes longer, and the upper limit reference voltage V _H output from the integrating circuit 5 becomes “(| V ₁ −V ₂ | / 4096)・ N ”(V) rises. As the upper limit reference voltage V _H rises, all “1” s output from the video signal A / D conversion circuit 1, that is, the number of white level signals W becomes sufficiently close to “2300”, and a beautiful screen is obtained. To be Further, the black level signal B is similarly processed by the pulse generation circuit 4 and the integration circuit 6.

However, when using a liquid crystal display panel as described above, the data of completely white and completely black is 10% or more on the screen.
Through experiments, we were able to confirm that it looks most beautiful when it is about 15%. Therefore, the number of perfect whites and blacks that looks most beautiful is calculated from the total number of dots, and is set as X. If the number of perfect whites and perfect blacks is within the range of "Xa to X + a", it is beautiful. And Assuming that the number of dots on the liquid crystal display panel is “120 × 160 = 19200”, the data for full white and full black is 12%, and the value of a is 3%, then X≈120 × 160 × 0.12≈2300 ≈120 × 160 × 0.03 ≈ 600, and the data of completely white and completely black is "2300-600 to 2300".
The screen looks beautiful in the range of “+600”. Therefore,
By changing the upper limit reference voltage V _H and the lower limit reference voltage V _L of the video signal A / D conversion circuit 1 according to the video signal, and bringing the number of completely white and completely black on the screen close to the value of X, a beautiful screen can be obtained. Can be obtained.

Although the reference level A / D conversion circuit independent of the video signal A / D conversion circuit is provided in the above embodiment, it can be realized by only the video signal A / D conversion circuit.

[Effects of the Invention] As described in detail above, according to the present invention, the upper and lower reference voltages _VL are adjusted so that the data of completely white and completely black on one screen are approximately 10 to 15%, respectively. Therefore, it is possible to provide a video signal A / D conversion method that can obtain an optimum contrast and can always display a beautiful screen.

[Brief description of drawings]

The drawings show one embodiment of the present invention. FIG. 1 is a block diagram showing a schematic configuration of the whole, FIG. 2 is a circuit configuration diagram showing details of a main part of FIG. 1, FIG. 3 and FIG. The figure is a timing chart for explaining the operation. 1 ... video signal A / D conversion circuit, 2 ... reference level A /
D conversion circuit, 3, 4 ... Pulse generation circuit, 5, 6 ... Integration circuit, 21 ... A / D conversion circuit, 22 ... Decoder, 32 ...
... Counter, 33 ... Data latch circuit, 34 ... D / D converter, 35 ... Latch circuit, 51 ... Time constant circuit, 52 ...
… Gate circuit, 53 …… Gate circuit.

Claims (1)

[Claims] 1. A liquid crystal display panel having a plurality of pixels, and A / D converting a video signal to output a digital signal corresponding to a plurality of gradations from a maximum gradation to a minimum gradation, and outputting the digital signal to the liquid crystal display panel. A video signal A / D conversion method that includes an A / D conversion circuit for supplying the video signal, detects the level of the video signal, and changes the A / D conversion level of the A / D conversion circuit according to the detection result. Means for detecting the amount of light level and amount of dark level in each field included in the video signal, and output from the A / D conversion circuit according to the amount of light level and amount of dark level detected by this means. Means for changing the A / D conversion level of the A / D conversion circuit so that the data corresponding to the maximum gradation and the minimum gradation of the digital signal becomes about 10 to 15% of the number of pixels of the liquid crystal display panel. Equipped with A video signal A / D conversion method characterized by the above.