KR20190118438A - Fingerprint sensing module and lectronic device comprising the same - Google Patents

Abstract

According to an embodiment of the present invention, provided is a fingerprint recognition module, which comprises: a substrate; a conductive pattern unit disposed on the substrate; a protective layer partially disposed in one region on the conductive pattern unit; a first connecting unit disposed on the first conductive pattern unit exposed through a first open area of the protective layer; a first chip disposed on the first connecting unit; and a protective pattern unit disposed on the substrate exposed through the first open region of the protective layer. The first chip includes a fingerprint recognition sensor, and the protective pattern unit is disposed in a vibration space of a fingerprint recognition sensor between an upper surface of the substrate and the first chip.

Description

Fingerprint recognition module and electronic device including same {FINGERPRINT SENSING MODULE AND LECTRONIC DEVICE COMPRISING THE SAME}

The present invention relates to a fingerprint recognition module, and more particularly, to a fingerprint recognition module having a bending structure and an electronic device including the same.

The fingerprint sensor is a sensor for detecting a human finger fingerprint. Recently, the fingerprint sensor is widely used as a means for reinforcing security in portable electronic devices such as smartphones and tablet computers. That is, by performing a user registration or security authentication process through the fingerprint sensor, it is possible to protect the data stored in the portable electronic device, and to prevent security incidents in advance. In general, the home key is provided at the bottom front of the smartphone. The home key implements various functions of the smartphone in a one-touch manner, thereby improving usability. On the other hand, the tablet computer is provided with a home key in the lower front of the body similar to the above-described smartphone. As such, the home key in a smartphone and a tablet computer allows a user to implement a set operation through a portable electronic device. For example, when the user presses or touches the home key while using the portable electronic device, the home key returns to an initial screen. to provide.

Meanwhile, the fingerprint recognition module has a structure in which a fingerprint recognition sensor and an application specific integrated circuit (ASIC) are mounted on a substrate. However, the fingerprint module as described above cannot be directly connected to the motherboard. That is, a printed circuit board is required between the fingerprint recognition module and the main board.

An electronic device having a display unit has a problem that thickness is increased as a plurality of printed circuit boards are required. In addition, the sizes of the plurality of printed circuit boards may be limited to the miniaturization of the electronic device. In addition, poor bonding of a plurality of printed circuit boards can reduce the reliability of the electronic device.

Therefore, there is a need for a fingerprint recognition module having a new structure that can solve such a problem.

Embodiments provide a fingerprint recognition module including a flexible circuit board for chip-on-film that can be directly connected to a main board of an electronic device while a fingerprint sensor and an ASIC are mounted on one substrate, and an electronic device including the same.

In addition, an embodiment is to provide a fingerprint recognition module including a flexible circuit board for chip on film that can minimize the noise generated on the bonding sensor connected to the fingerprint sensor, the ASIC and the main board and an electronic device including the same. do.

In addition, an embodiment is to provide a fingerprint recognition module including a flexible circuit board for a chip on film that can prevent the conductive adhesive layer from invading into the vibration space of the fingerprint sensor and an electronic device including the same.

In addition, an embodiment is to provide a fingerprint recognition module and an electronic device including the same that can minimize the bending of the central portion of the fingerprint sensor.

In addition, an embodiment is to provide a fingerprint recognition module including a flexible circuit board for a chip on film that can discharge the gas generated in the vibration space of the fingerprint sensor to the outside and an electronic device including the same.

The technical problems to be achieved in the proposed embodiment are not limited to the technical problems mentioned above, and other technical problems not mentioned above are clear to those skilled in the art to which the proposed embodiments belong from the following description. Can be understood.

A fingerprint recognition module according to an embodiment includes a substrate; A conductive pattern portion disposed on the substrate; A protective layer partially disposed in one region on the conductive pattern portion; A first connecting portion disposed on the first conductive pattern portion exposed through the first open area of the protective layer; A first chip disposed on the first connection portion; And a protective pattern part disposed on the substrate exposed through the first open area of the protective layer, wherein the first chip includes a fingerprint sensor, and the protective pattern part includes an upper surface of the substrate and the first material. It is disposed in the vibration space of the fingerprint recognition sensor between one chip.

In addition, the height of the protective pattern portion is lower than the height of the first conductive pattern portion.

Further, the height of the first conductive pattern portion satisfies the range of 7 μm to 13 μm, and the height of the protective pattern portion satisfies the range of 6 μm to 11 μm.

In addition, the protective pattern portion is disposed adjacent to the first conductive pattern portion, the first protective pattern portion disposed in the outer region of the vibration space, and the central region of the vibration space excluding the outer region of the vibration space It includes a second protective pattern portion disposed in the.

The horizontal cross-sectional shape of the first protective pattern portion is different from the horizontal cross-sectional shape of the second protective pattern portion.

The apparatus may further include a through hole formed in the region between the first protective pattern portion and the second protective pattern portion to communicate with the vibration space.

In addition, a second connecting portion disposed on the second conductive pattern portion exposed through the second open area of the protective layer; And a second chip disposed on the second connection portion, wherein the second chip includes an application specific integrated circuit.

In addition, the substrate may include a first non-bended region positioned at one end and disposed with the first chip, a second non-bended region positioned at the other end opposite to the one end and disposed with the second chip, and the first And a bending area positioned between the two non-bending areas, wherein an adhesive layer is disposed between the first non-bending area and the second non-bending area, and the first non-bending area is formed around the adhesive layer. 2 are placed facing the non-bent area.

In addition, the substrate may be positioned above the adhesive layer, and may include an upper part including the first non-bended region and a portion of the bent region, a lower part of the adhesive layer, and the second non-bended region and the bent portion. A lower part including the remaining part of the area is included, and the ratio of the upper surface area of the first chip and the upper surface area of the upper part is 1: 2 or less.

The first conductive pattern portion may include a plurality of grooves recessed at a predetermined depth from an upper surface thereof in a lower surface direction, spaced apart from each other by a predetermined interval, and having the first connecting portion disposed thereon, and an upper surface of the first conductive pattern portion disposed at a center thereof. A first area | region toward the said vibration space toward a center and a 2nd area | region except the said 1st area are included, The 1st opening ratio by the said some groove | channel in the said 1st area is the said 2nd area | region in the said 2nd area | region Is larger than the second opening ratio due to the groove.

The semiconductor device may further include at least one third chip disposed on the conductive pattern portion exposed through the third open area of the protective layer, wherein the at least one third chip includes a diode chip, an MLCC chip, a BGA chip, and a chip. At least one of the capacitors, wherein the interval between the area between the second open area and the third open area is smaller than the interval between the area between the first open area and the second open area.

On the other hand, an electronic device according to the embodiment includes a substrate; A conductive pattern portion disposed on the substrate; A protective layer partially disposed in one region on the conductive pattern portion; A first connecting portion disposed on the first conductive pattern portion exposed through the first open area of the protective layer; A first chip disposed on the first connection portion; A second connecting portion disposed on the second conductive pattern portion exposed through the second open area of the protective layer; A second chip disposed on the second connection portion; And a protective pattern portion disposed on the substrate exposed through the first open area of the protective layer, wherein the first chip includes a fingerprint sensor, and the second chip includes an application specific integrated circuit; The substrate includes a first non-bent region positioned at one end, a second non-bent region positioned at the other end opposite to the one end, and a bent region positioned between the first and second non-bent regions, The first open area is located on the first non-bent area, the second open area is located on the second non-bent area, and the protective pattern part is the fingerprint between the upper surface of the substrate and the first chip. A fingerprint recognition module disposed in a vibration space of a recognition sensor, wherein a height of the protection pattern portion is lower than a height of the first conductive pattern portion; A display unit attached to the first chip; And a main board connected to the conductive pattern part positioned on the second non-bending area of the fingerprint recognition module.

The display unit may further include a display panel; And a cover window positioned on the display panel, wherein the first chip is attached to a bottom surface of the display panel or a bottom surface of the cover window.

According to an exemplary embodiment of the present invention, a flexible circuit board for a chip-on-film having a two-layer structure is applied as a substrate of a fingerprint recognition module, and the substrate area can be significantly reduced in response to a fine pitch. In addition, the embodiment can implement a fine pitch (line / Space = 10um or less / 15um or less) by using a polyimide substrate can reduce the size of the fingerprint recognition module.

In addition, according to an embodiment of the present invention, it is possible to mount different types of first chip, second chip and third chip on a single substrate to provide a fingerprint recognition module having improved reliability.

In addition, according to an embodiment of the present invention, the height of the inner lead pattern portion on which the fingerprint sensor is mounted is formed to be 7 μm or more, thereby ensuring a vibration space of the fingerprint sensor, and thus operating reliability of the fingerprint sensor. Can improve.

In addition, according to an embodiment of the present disclosure, the fingerprint recognition module and the main board may be directly connected. Accordingly, the size and thickness of the flexible circuit board for transmitting the signal sensed through the fingerprint recognition module to the main board can be reduced. In addition, the signal distance from the signal generated from the fingerprint chip to the main board can be shortened, so that fingerprint recognition can be accelerated.

Accordingly, the fingerprint recognition module and the electronic device including the same may expand the space of another component and / or the battery space.

In addition, since the connection of the plurality of printed circuit boards is not required, the convenience of the process and the reliability of the electrical connection may be improved. Accordingly, the fingerprint recognition module and the electronic device including the same according to the embodiment may be suitable for an electronic device having a high resolution display unit.

In addition, according to an embodiment of the present invention, by adding a side molding portion around the first chip and the second chip, it is possible to protect the first chip and the second chip from invasion or impact, thereby improving operation reliability Can be improved.

In addition, according to an embodiment of the present invention, the distance between the first chip and the second chip centered on the bending line is at least 1.6 mm. Therefore, when bending the fingerprint recognition module, it is possible to prevent cracking of the bonding part due to the bending external force.

In addition, according to the embodiment of the present invention, the distance between the second chip and the third chip as close as possible, so as to be at least 1.0mm. Therefore, the signal loss caused by the distance between the second chip and the third chip can be minimized. In addition, the position shift of the third chip, which occurs as the distance between the second chip and the third chip is closer than 1.0 mm, can be prevented.

In addition, according to an embodiment of the present invention, the flexible circuit board constituting the fingerprint recognition module has a bending structure. Accordingly, the total length of the fingerprint recognition module can be reduced.

In addition, in the embodiment according to the present invention, a plurality of grooves recessed in the thickness direction of the inner lead pattern portion are formed on the inner lead pattern portion on which the first chip C1 is disposed. The groove is filled by a connection portion formed for mounting the first chip C1 on the inner lead pattern portion. That is, the connection part may penetrate into the effective part corresponding to the vibration space during the mounting process of the first chip C1. Therefore, in the present invention, a part of the penetrating connection portion can fill the inside of the groove. According to this, it is possible to solve the operation reliability problem that occurs as the connection portion penetrates into the effective portion.

In addition, according to the embodiment of the present invention, a protective pattern portion having a height lower than that of the inner lead pattern portion is formed on the upper surface of the substrate corresponding to the vibration space of the first chip C1. A predetermined space exists between the upper surface of the protective pattern portion and the lower surface of the first chip C1. In addition, the first chip C1 may operate by vibrating in the separation space. In addition, the protective pattern part may prevent the first chip C1 from vibrating violently in the downward direction, thereby improving the operational reliability of the first chip C1. On the other hand, the first chip (C1) is mounted on the inner lead pattern portion by the connection portion, the outer region can be supported by the inner lead pattern portion. Alternatively, the central region of the first chip C1 is positioned in a floating state on the substrate. In this case, the protective pattern part may prevent the central area of the first chip C1 from sagging below the outer area, thereby minimizing the warpage of the first chip C1.

The protective pattern part may include a second protective pattern part disposed in a central area of the effective part, and a first protective pattern part surrounding the second protective pattern part and disposed in an outer area of the effective part. In this case, the first protective pattern portion and the second protective pattern portion may have different shapes or different sizes. As described above, the second protective pattern portion may function to prevent sagging of the central region of the first chip C1. In addition, the first protective pattern part may further prevent the connection part from penetrating into the effective part.

In addition, in an embodiment according to the present invention, an outer lead pattern portion connected to a main board and a lower surface of a substrate facing the area between the first chip and the second chip, a lower surface of the substrate facing the mounting area, and the second chip; A ground pattern is formed on the bottom surface of the opposing substrate. Accordingly, according to the embodiment of the present invention, it is possible to shield the electromagnetic interference noise generated in the region between the first chip and the second chip. In addition, according to an embodiment of the present invention, it is possible to shield the electromagnetic interference noise generated in the second chip. In addition, according to an embodiment of the present invention, it is possible to shield the electromagnetic interference noise generated between the fingerprint recognition module and the main board. On the other hand, the ground pattern has a mesh shape. Accordingly, according to an embodiment of the present invention, it is possible to minimize the increase in linear resistance in the ground pattern, and to minimize the increase in the line width of other conductive patterns generated during plating thereof.

In addition, the embodiment according to the present invention forms a gas outlet communicating with the vibration space of the first chip on the substrate, the conductive pattern portion, the protective layer and the adhesive layer. Accordingly, according to the embodiment of the present invention, it is possible to solve the problem that the substrate expands due to the gas present in the vibration space and the problem that the operation reliability is lowered.

1A is a cross-sectional view of an electronic device having a display unit including a conventional printed circuit board.
1B is a plan view of the printed circuit board of FIG. 1A.
2A is a cross-sectional view of an electronic device having a display unit including a fingerprint recognition module according to an embodiment.
FIG. 2B is a cross-sectional view of the flexible circuit board for chip on film of the fingerprint recognition module according to FIG.
FIG. 2C is a plan view of the flexible circuit board for chip on film of the fingerprint recognition module according to FIG.
3A is a cross-sectional view illustrating a flexible circuit board of a fingerprint recognition module according to an embodiment of the present invention.
FIG. 3B is a cross-sectional view illustrating a fingerprint recognition module including the flexible circuit board of FIG. 3A.
FIG. 4A is an enlarged view of a region in which the first chip is mounted in FIG. 3A.
4B is a view illustrating a modified example of the groove of FIG. 4.
5 is an enlarged view of a portion A of FIG. 3B.
6A to 6D are plan views illustrating a protection pattern unit according to an exemplary embodiment of the present invention.
FIG. 7A illustrates a bent form of the fingerprint recognition module of FIG. 3B.
7B is a plan view illustrating a fingerprint recognition module before bending and a fingerprint recognition module after bending according to an embodiment of the present disclosure.
8 is a plan view of the adhesive layer of FIG. 7A.
9 is another cross-sectional view of a flexible circuit board for a chip on film according to an embodiment.
10 is another cross-sectional view of a fingerprint recognition module including a flexible circuit board for on film according to an embodiment.
11 is an enlarged cross-sectional view of a region of a flexible circuit board for a chip on film according to an embodiment.
12A is a cross-sectional view of an electronic device including a fingerprint recognition module according to an embodiment.
12B is another cross-sectional view of an electronic device including a fingerprint recognition module according to an embodiment.
12C is another cross-sectional view of an electronic device including a fingerprint recognition module according to an embodiment.
13 through 17 are diagrams of various electronic devices including a fingerprint recognition module.

In the description of embodiments, each layer, region, pattern, or structure may be “on” or “under” the substrate, each layer, region, pad, or pattern. Substrate formed in ”includes all formed directly or through another layer. Criteria for the top / bottom or bottom / bottom of each layer will be described with reference to the drawings.

In addition, when a part is "connected" with another part, this includes not only the case where it is "directly connected" but also the case where it is "indirectly connected" with the other member in between. In addition, when a part is said to "include" a certain component, this means that it may further include other components, without excluding the other components unless otherwise stated.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1B, a printed circuit board according to a comparative example will be described.

An electronic device having a display unit requires at least two substrates in addition to the main board 40 to implement a fingerprint recognition function.

At least two substrates may be included in the electronic device including the display unit according to the comparative example.

An electronic device including a display unit according to a comparative example may include a first substrate 10 and a second substrate 20.

As the first substrate 10, a flexible printed circuit board (FPCB) or a silicon wafer was used.

As the second substrate 20, a flexible printed circuit board (FPCB) was used.

In the electronic device having the display unit according to the comparative example, since the first and second substrates are required between the display panel and the main board, the overall thickness of the electronic device may increase. In detail, since the electronic device having the display unit according to the comparative example requires the first and second substrates to be stacked up and down, the overall thickness of the electronic device may increase.

The first substrate 10 and the second substrate 20 are formed by different processes. For example, the first substrate 10 is manufactured by a general lamination process, and the second substrate 20 is manufactured by a sheet method.

Since the first and second substrates according to the comparative example are formed in different processes, the process efficiency may be reduced.

In addition, since a chip package including a substrate according to a comparative example has a difficulty in disposing different types of chips on one substrate, separate first and second substrates are required.

In addition, the chip package including the substrate according to the comparative example has a problem that it is difficult to connect different types of chips on one substrate.

The first substrate 10 is connected to the second substrate 20, and the second substrate 20 is connected to the main board 40 so as to recognize and process or transfer a fingerprint from an object approaching the upper portion of the display panel 30. Is connected to.

An electronic device having a display unit according to a comparative example may include a cover window 70 and the first substrate 10, between the first substrate 10 and the second substrate 20, and the second substrate ( A separate adhesive layer 50 may be required between the 20 and the main board 40. That is, since the electronic device having the display unit according to the comparative example requires a plurality of adhesive layers, there is a problem that the reliability of the electronic device may be degraded due to the poor connection of the adhesive layers. In addition, an adhesive layer disposed between the first substrate 10 and the second substrate 20 connected up and down may increase the thickness of the electronic device.

Referring to FIG. 1B, since a plurality of substrates are required in the comparative example, the length L1 in one direction is the sum of the lengths of the first substrate 10 and the second substrate 20, respectively. Normally, the length L1 is about 300 mm. As the electronic device according to the comparative example requires a plurality of substrates, a space for mounting another component or a space for arranging the battery 60 may be reduced. In addition, since the fingerprint recognition component is mounted outside the display unit, there is a problem that the size of the entire device must be increased.

Recently, electronic devices such as smart phones have been added with components having various functions to enhance user convenience and security. For example, an electronic device such as a smart phone or a smart watch may be equipped with several camera modules (dual camera module) or parts having various functions such as iris recognition and virtual reality (VR). Being added. Accordingly, it is important to secure space for mounting additional components.

In addition, various electronic devices including wearable devices require expansion of battery space in order to improve user convenience.

Therefore, as a plurality of printed circuit boards used in existing electronic devices are replaced with a single printed circuit board, the importance of securing a space for mounting a new component or securing a space for expanding a battery size is increasing.

In an electronic device according to a comparative example, different types of first, second, and third chips may be disposed on separate first and second substrates 10 and 30, respectively. Accordingly, the thickness of the adhesive layer 50 and the thickness of the second substrate 30 between the first substrate 10 and the second substrate 30 have a problem of increasing the thickness of the electronic device.

In addition, there is a problem in that a space for mounting a battery space or another component is reduced by the size of the second substrate 30.

In addition, poor bonding between the first and second substrates has a problem of lowering the reliability of the electronic device.

The embodiment can provide a fingerprint recognition module including a flexible circuit board for chip-on-film having a new structure capable of mounting a plurality of chips on one substrate, and an electronic device including the same.

Like reference numerals in the embodiments and the comparative examples denote the same components, and descriptions overlapping with the comparative examples described above are omitted.

2A to 2C, an electronic device equipped with a fingerprint recognition module including a flexible circuit board for a chip on film according to an embodiment will be described.

The electronic device according to the embodiment may use a single printed circuit board to transfer a fingerprint recognition signal obtained from an object approaching one side of the display panel to the main board.

The printed circuit board included in the electronic device including the display unit according to the embodiment may be one flexible printed circuit board. Accordingly, the fingerprint recognition module 100 including the flexible circuit board for the chip on film according to the embodiment may be bent between the display unit and the main board facing each other and be connected to the display unit and the main board. Can be.

In detail, the fingerprint recognition module 100 including the flexible circuit board for the chip on film according to the embodiment may be one substrate for arranging a plurality of chips of different types.

The fingerprint recognition module 100 including a flexible circuit board for a chip on film according to an embodiment may include different types of first chips c1, second chips c2, and third chips c3. It may be a substrate for placement.

The thickness t2 of the flexible circuit board for the chip on film of the fingerprint recognition module 100 according to the embodiment may be 20 μm to 100 μm before bending. For example, the thickness t2 before bending of the flexible circuit board for the chip on film according to the embodiment may be 30 μm to 80 μm. For example, the thickness t2 before bending of the flexible circuit board for the chip on film according to the embodiment may be 70 μm to 75 μm.

The thickness t2 before bending of the flexible circuit board for the chip on film of the fingerprint recognition module 100 according to the embodiment is 1/5 to 1 of the total thickness t1 of the plurality of substrates according to the comparative example. It may have a thickness of 1/2 level. That is, the thickness t2 before bending of the flexible circuit board for the chip on film according to the embodiment may have a thickness of 20% to 50% of the thickness t1 of the plurality of substrates according to the comparative example. Can be. For example, the thickness t2 before bending of the flexible circuit board for the chip on film according to the embodiment is 25% to 40% of the thickness t1 of the plurality of substrates according to the comparative example. Can have a level thickness. For example, the thickness t2 before bending of the flexible circuit board for the chip on film according to the embodiment may be 25% to 35% of the thickness t1 of the plurality of substrates according to the comparative example. Can have a level thickness.

The electronic device having the display unit according to the embodiment can reduce the overall thickness of the electronic device because only one flexible circuit board for a chip on film is required between the display panel and the main board.

In addition, the embodiment may omit the adhesive layer 50 between the first substrate and the second substrate included in the comparative example, the overall thickness of the chip package and the electronic device including the flexible circuit board for chip on film Can be reduced.

In addition, the embodiment may omit the adhesive layer 50 between the first substrate and the second substrate, thereby solving the problem caused by poor adhesion, thereby improving the reliability of the electronic device.

In addition, the bonding process of the plurality of substrates can be omitted, so that the process efficiency can be increased and the process cost can be reduced.

In addition, by replacing the substrate that was managed in a separate process with one process, it is possible to improve the process efficiency and product yield.

The flexible circuit board for the chip on film of the fingerprint recognition module 100 according to the embodiment may include a bent region and a non-bent region. The fingerprint recognition module 100 including a flexible circuit board for a chip on film according to an embodiment includes a bent region, and thus the display panel 30 and the main board 40 are disposed to face each other. A fingerprint recognition module 100 including a flexible circuit board for a chip on film may be disposed therebetween.

Non-bending areas of the fingerprint recognition module 100 including the flexible circuit board for a chip on film according to the embodiment may be disposed to face the display panel 30. The first chip C1 may be disposed on the non-bending region of the fingerprint recognition module 100 including the flexible circuit board for the chip on film according to the embodiment. Accordingly, the fingerprint recognition module 100 including the flexible circuit board for the chip on film according to the embodiment may be capable of stably mounting the first chip c1. In addition, the second chip C2 and the third chip C3 may be disposed on the non-bended region of the fingerprint recognition module 100 including the flexible circuit board for the chip on film according to the embodiment. Accordingly, the fingerprint recognition module 100 including the flexible circuit board for the chip on film according to the embodiment may be capable of stably mounting the second chip c2 and the third chip C3.

FIG. 2C is a plan view from the bottom of FIG. 2B.

Referring to FIG. 2C, since one embodiment requires one substrate, the length L2 in one direction may be the length of one substrate. The length L2 in one direction of the fingerprint recognition module 100 including the flexible circuit board for the chip on film according to the embodiment is a flexible circuit board for the chip on film according to the embodiment. It may be the length of the fingerprint recognition module 100 including. For example, the length L2 in one direction of the fingerprint recognition module 100 including the flexible circuit board for the chip on film according to the embodiment may be 10 mm to 50 mm. For example, the length L2 in one direction of the fingerprint recognition module 100 including the flexible circuit board for the chip on film according to the embodiment may be 5 mm to 30 mm. For example, the length L2 in one direction of the fingerprint recognition module 100 including the flexible circuit board for the chip on film according to the embodiment may be 7 mm to 25 mm. For example, the length L2 in one direction of the fingerprint recognition module 100 including the flexible circuit board for the chip on film according to the embodiment may be 10 mm to 15 mm.

However, the embodiment is not limited thereto and may be designed in various sizes according to the type and / or number of chips to be arranged and the type of electronic device.

In addition, a separate fingerprint recognition space is not required, and the display area can be widely used in the entire device because it is formed to overlap the display unit, thereby increasing user convenience.

The length L2 in one direction of the fingerprint recognition module 100 including the flexible circuit board for a chip on film according to the embodiment is 10 of the length L1 in one direction of the substrate according to the comparative example. It may have a length in the range of% to 70%.

Accordingly, the embodiment can reduce the size of the fingerprint recognition module 100 including the flexible circuit board for a chip on film in the electronic device, eliminating the need for a separate fingerprint recognition space of the comparative example As a result, not only can the entire display area be enlarged, but also the space for disposing the battery 60 can be enlarged. In addition, the fingerprint recognition module 100 including the flexible circuit board for the chip on film according to the embodiment may be reduced in planarity, thereby securing space for mounting other components.

Hereinafter, a flexible circuit board and a fingerprint recognition module including the same according to an embodiment of the present invention will be described in detail with reference to FIGS. 3 to 12.

3A is a cross-sectional view illustrating a flexible circuit board of a fingerprint recognition module according to an embodiment of the present invention, FIG. 3B is a cross-sectional view illustrating a fingerprint recognition module including the flexible circuit board of FIG. 3A, and FIG. 4A is a first view in FIG. 3A. 4B is an enlarged view showing an area where a chip is mounted, FIG. 4B is a view illustrating a modified example of the groove of FIG. 4, FIG. 5 is an enlarged view of a portion A of FIG. 3B, and FIGS. 7A is a plan view illustrating a bent form of the fingerprint recognition module of FIG. 3B, and FIG. 7B is a plan view of a fingerprint recognition module before bending and a fingerprint recognition module after bending according to an embodiment of the present invention. FIG. 8 is a plan view of the adhesive layer of FIG. 7A, and FIG. 9 is another cross-sectional view of the flexible circuit board for the chip on film according to the embodiment, and FIG. 10 is a fingerprint including the flexible circuit board for the on film according to the embodiment. 11 is an enlarged cross-sectional view of a region of a flexible circuit board for a chip on film according to an embodiment, and FIG. 12A is a cross-sectional view of an electronic device including a fingerprint recognition module according to an embodiment. 12B is another cross-sectional view of an electronic device including a fingerprint recognition module according to an embodiment, and FIG. 12C is another cross-sectional view of an electronic device including a fingerprint recognition module according to an embodiment.

In the flexible circuit board for a chip on film according to the embodiment, the substrate 110, the wiring pattern layer 120, the plating layer 130, and the protection pattern portion 190 disposed on the substrate 110 may be protected. It may include layer 140.

Herein, in the flexible circuit board for an all-in-one chip on film, the first chip C1, the second chip C2, and the third chip C3 constituting the fingerprint recognition module 100 are mounted. It is a board before it becomes.

The substrate 110 may be a support substrate supporting the wiring pattern layer 120, the plating layer 130, the protection pattern unit 190, and the protection layer 140.

The substrate 110 may include a bent region and a region other than the bent region. That is, the substrate 110 may include a bending area where bending is performed and a non-bending area other than the bending area. The bent region may be an area between the first chip C1 and the second chip C2 on the upper surface of the substrate 110. The bent area may be an area excluding a chip arrangement area in which the first chip C1, the second chip C2, and the third chip C3 are disposed. The non-bending region may be a region other than the bending region. The non-bending region may include a first chip arrangement region in which the first chip C1 is disposed, a second chip arrangement region in which the second chip C2 is arranged, and a third chip arrangement in which the third chip C3 is disposed. It may include a chip arrangement area.

The substrate 110 may be a flexible substrate. Accordingly, the substrate 110 may be partially bent. That is, the substrate 110 may include a flexible plastic. For example, the substrate 110 may be a polyimide (PI) substrate. However, the embodiment is not limited thereto and may be a substrate made of a polymer material such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN). Accordingly, the flexible circuit board including the substrate 110 may be used in various electronic devices having a curved display device. For example, the flexible circuit board including the substrate 110 may be suitable for mounting a semiconductor chip of a wearable electronic device because of its excellent flexibility. In detail, embodiments may be suitable for electronic devices that include curved displays.

The substrate 110 may be an insulating substrate. That is, the substrate 110 may be an insulating substrate supporting various wiring patterns.

The substrate 110 may have a thickness of 20 μm to 100 μm. For example, the substrate 110 may have a thickness of 25 μm to 50 μm. For example, the substrate 100 may have a thickness of 30 μm to 40 μm. When the thickness of the substrate 100 is greater than 100 μm, the thickness of the entire flexible printed circuit board may increase. When the thickness of the substrate 100 is less than 20 μm, it may be difficult to simultaneously arrange the first chip C1, the second chip C2, and the third chip C3. When the thickness of the substrate 110 is less than 20 μm, the substrate 110 may be vulnerable to heat / pressure in a process of mounting a plurality of chips, and thus it may be difficult to simultaneously arrange a plurality of chips.

Wiring may be disposed on the substrate 110. The wiring may be a plurality of patterned wiring. For example, the plurality of wires may be spaced apart from each other on the substrate 110. That is, the wiring pattern layer 120 may be disposed on one surface of the substrate 110.

Preferably, wiring layers may be disposed on both surfaces of the substrate 110, respectively. That is, the upper wiring pattern layer may be disposed on the upper surface of the substrate 110, and the lower wiring pattern layer may be disposed on the lower surface of the substrate 110. In addition, an upper plating layer may be disposed on the upper wiring pattern layer. In addition, an upper protective layer may be disposed on the upper wiring pattern layer. In addition, a lower plating layer may be disposed under the lower wiring pattern layer. A lower protective layer may be disposed below the lower wiring pattern layer.

The wiring pattern layer 120 may include a conductive material.

For example, the wiring pattern layer 120 may include a metal material having excellent electrical conductivity. In more detail, the wiring pattern layer 120 may include copper (Cu). However, embodiments are not limited thereto, and copper (Cu), aluminum (Al), chromium (Cr), nickel (Ni), silver (Ag), and molybdenum (Mo). Of course, it may include at least one metal of gold (Au), titanium (Ti), and alloys thereof.

The wiring pattern layer 120 may be disposed to have a thickness of 1 μm to 15 μm. For example, the wiring pattern layer 120 may be disposed to have a thickness of about 4 μm to about 10 μm. For example, the wiring pattern layer 120 may be disposed to have a thickness of 6 μm to 9 μm.

When the thickness of the wiring pattern layer 120 is less than 1 μm, the resistance of the wiring pattern layer may increase. When the thickness of the wiring pattern layer 120 is greater than 15 μm, it is difficult to use a mask when the side etching and the printing method are used when the lithography method is used, and in the case of the sputtering method, the deposition is performed for a long time to implement a fine pattern. It can be difficult.

The plating layer 130 may be disposed on the wiring pattern layer 120. The plating layer 130 may include a first plating layer 131 and a second plating layer 132.

The first plating layer 131 may be disposed on the wiring pattern layer 120, and the second plating layer 132 may be disposed on the first plating layer 131. The first plating layer 131 and the second plating layer 132 may be formed in two layers on the wiring pattern layer 120 to prevent whisker formation. Accordingly, a short circuit between the patterns of the wiring pattern layer 120 may be prevented. In addition, as two plating layers are disposed on the wiring pattern layer 120, bonding characteristics with a chip may be improved. When the wiring pattern layer includes copper (Cu), the wiring pattern layer may not be directly bonded to the first chip C1, and a separate process for adhesion may be required. On the other hand, in the case where the plating layer disposed on the wiring pattern layer is formed as a single layer, copper (Cu) of the wiring pattern layer may be diffused into the plating layer in the plating process, thereby causing defects in bonding with the chip. By further forming two plating layers on the one plating layer, chip bonding may be facilitated by reducing or reducing the amount of copper (Cu) on the surface to be bonded with the chip. When the plating layer includes tin (Sn), the surface of the plating layer may be a pure tin layer, so that bonding with the first chip C1 may be easy.

The region where the first plating layer 131 is disposed may correspond to the region where the second plating layer 132 is disposed. That is, an area in which the first plating layer 131 is disposed may correspond to an area in which the second plating layer 132 is disposed.

In addition, an area in which the first plating layer 131 is disposed may be larger than an area in which the second plating layer 132 is disposed. After forming the first plating layer 131, the protective layer 140 is formed, and the whisker phenomenon and the copper are formed even when the second plating layer 132 is formed on the first plating layer 131 where the protective layer is not formed. (Cu) Diffusion can be prevented.

The plating layer 130 may include tin (Sn). For example, the first plating layer 131 and the second plating layer 132 may include tin (Sn).

For example, the wiring pattern layer 120 may be disposed of copper (Cu), and the first plating layer 131 and the second plating layer 132 may be disposed of tin (Sn). When the plating layer 130 includes tin, since the corrosion resistance of tin (Sn) is excellent, oxidation of the wiring pattern layer 120 can be prevented.

Meanwhile, the material of the plating layer 130 may have a lower electrical conductivity than the material of the wiring electrode layer 120. The plating layer 130 may be electrically connected to the wiring electrode layer 120.

The first plating layer 131 and the second plating layer 132 are formed of the same tin (Sn), but may be formed by a separate process.

When the manufacturing process of the flexible circuit board according to the embodiment includes a heat treatment process such as thermal curing, the diffusion action of copper (Cu) of the wiring pattern layer 120 or tin (Sn) of the plating layer 130 Can happen. In detail, the hardening of the protective layer 140 may cause diffusion of copper (Cu) of the wiring pattern layer 120 or tin (Sn) of the plating layer 130.

Accordingly, as the diffusion concentration of copper (Cu) decreases from the first plating layer 131 to the surface of the second plating layer 132, the content of copper (Cu) may be continuously decreased. Meanwhile, the tin (Sn) content may increase continuously from the first plating layer 131 to the surface of the second plating layer 132. Accordingly, the top of the plating layer 130 may include pure tin.

That is, the wiring pattern layer 120 and the plating layer 130 may be an alloy of tin and copper by at least a portion of the plating layer 130 by a chemical reaction at a laminated interface. After curing the protective layer 140 on the plating layer 130 than the thickness of the alloy of tin and copper after forming the plating layer 130 on the wiring pattern layer 120 of the alloy of tin and copper The thickness can increase.

An alloy of tin and copper included in at least a portion of the plating layer 130 may have a chemical formula of Cu _x Sn _y and may be 0 <x + y <12. For example, in the above formula, the sum of x and y may be 4 ≦≦ x + y ≦≦ 11. For example, the alloy of tin and copper contained in the plating layer 130 is Cu ₃ Sn and Cu ₆ Sn ₅ It may include at least one of. In detail, the first plating layer 131 may be an alloy layer of tin and copper.

In addition, the first plating layer 131 and the second plating layer 132 may have different contents of tin and copper. The first plating layer 131 in direct contact with the copper wiring pattern layer may have a greater copper content than the second plating layer 132.

The second plating layer 132 may have a greater content of tin than the first plating layer 131. The second plating layer 132 may include pure tin. Here, pure tin may mean that the content of tin (Sn) is 50 atomic% or more, 70 atomic% or more, and 90 atomic% or more. In this case, elements other than tin may be copper. For example, the second plating layer 132 may have a content of tin (Sn) of 50 atomic% or more. For example, the second plating layer 132 may have a content of tin (Sn) of 70 atomic% or more. For example, the second plating layer 132 may have a content of tin (Sn) of about 90 atomic% or more. For example, the second plating layer 132 may have a content of tin (Sn) of 95 atomic% or more. For example, the second plating layer 132 may have a content of tin (Sn) of 98 atomic% or more.

Due to the diffusion phenomenon of Cu / Sn, the plating layer according to the embodiment prevents electrochemical migration resistance, thereby preventing short circuit defects due to metal growth.

However, the embodiment is not limited thereto, and the plating layer 130 may be formed of Ni / Au alloy, gold (Au), electroless nickel immersion gold (ENIG), Ni / Pd alloy, or organic compound plating (Organic). Of course, it may include any one of the Solderability Preservative (OSP).

The first plating layer 131 and the second plating layer 132 may correspond to each other or may have different thicknesses. The overall thickness of the first plating layer 131 and the second plating layer 132 may be 0.07 μm to 1 μm. The overall thickness of the first plating layer 131 and the second plating layer 132 may be 0.15 μm to 0.7 μm. The overall thickness of the first plating layer 131 and the second plating layer 132 may be 0.3 μm to 0.5 μm. The plating layer of any one of the first plating layer 131 and the second plating layer 132 may have a thickness of 0.05 μm to 0.15 μm or less. For example, the plating layer of any one of the first plating layer 131 and the second plating layer 132 may have a thickness of 0.07 μm to 0.13 μm or less.

The protective layer 140 may be partially disposed on the wiring pattern layer 120. For example, the protective layer 140 may be disposed on the plating layer 130 on the wiring pattern layer 120. The protective layer 140 may cover the plating layer 130 to prevent damage or film removal due to oxidation of the wiring pattern layer 120 and the plating layer 130.

The protective layer 140 may include the wiring pattern layer 120 and / or the plating layer 130 as the main board 40, the first chip C1, the second chip C2, or the third chip C3. It may be partially disposed in an area except for an area to be electrically connected.

Accordingly, the protective layer 140 may partially overlap the wiring pattern layer 120 and / or the plating layer 130.

The area of the protective layer 140 may be smaller than the area of the substrate 110. The protective layer 140 may be disposed in an area excluding the end of the substrate, and may include a plurality of open areas.

The protective layer 140 may include a first open area OA1 having a hole-like shape. The first open area OA1 may be a non-arranged area of the protective layer 140 in which the wiring pattern layer 120 and / or the plating layer 130 are electrically connected to the first chip C1.

The protective layer 140 may include a second open area OA2 having a hole-like shape. The second open area OA2 may be a non-arranged area of the protective layer 140 for electrically connecting the wiring pattern layer 120 and / or the plating layer 130 to the second chip C2. . Accordingly, in the second open region OA2, the plating layer 130 may be exposed to the outside.

In the second open region OA2, the copper content of the plating layer 130 may be 50 atomic% or more. For example, the copper content in the plating layer 130 may be 60 atomic% or more. For example, the copper content in the plating layer 130 may be 60 atomic% to 80 atomic%. In detail, the copper content of the first plating layer 131 measured in the second open region OA2 may be 60 atomic% to 80 atomic%.

The protective layer 140 may include a third open area OA3 having a hole-like shape. The third open area OA3 may be a non-arranged area of the protective layer 140 for electrically connecting the wiring pattern layer 120 and / or the plating layer 130 to the third chip C3. . Accordingly, in the third open area OA3, the plating layer 130 may be exposed to the outside.

The protective layer 140 may not be disposed on the conductive pattern part for electrically connecting with the main board 40. The embodiment may include a fourth open area OA4, which is a non-located area of the protective layer 140 on the conductive pattern part to be electrically connected to the main board 40. Accordingly, in the fourth open area OA4, the plating layer 130 may be exposed to the outside.

In the fourth open region OA4, the copper content of the plating layer 130 may be 50 atomic% or more. Alternatively, in the third open region OA3, the copper content of the plating layer 130 may be less than 50 atomic%. The fourth open area OA3 may be located outside the substrate than the first open area OA1. In addition, the fourth open area OA4 may be located outside the substrate than the second open area OA2. In addition, the fourth open area OA4 may be located outside the substrate than the third open area OA3.

The first open area OA1, the second open area OA2, and the third open area OA3 may be located in a central area of the substrate rather than the fourth open area OA4.

In this case, at least one of the two outermost regions in the longitudinal direction of the substrate may be covered by the protective layer 140. In other words, the substrate 110 may include a first outer region and a second outer region. The first outer region may be a left end region of the substrate 110. The second outer region may be a right end region of the substrate 110. As described above, a fourth open area OA4 is connected to the main board as described above. Alternatively, the first outer region does not have an open region. In other words, the first outer region may include a protective part PP on which the protective layer 140 is formed.

The protective layer 140 may be disposed in the bending area BP. Accordingly, the protective layer 140 may disperse the stress that may occur when bending. Therefore, the reliability of the flexible circuit board for the chip-on-film according to the embodiment can be improved.

In addition, since the protective layer is formed on the first outer region, wear of the first outer region of the fingerprint recognition module 100 including the flexible circuit board for the chip on film may be prevented. In the case of a flexible circuit board for chip-on-film mounting a conventional drive IC, a terminal connected to a display is formed at a portion corresponding to the first outer region, and thus the first outer region is a display panel. The exposed portion of the first outer region was protected by an adhesive material such as ACF to prevent wear of the first outer region. However, in the case of the present invention, since there is no part connected to the first outer region, a separate protection part PP may be formed in the first outer region to prevent wear.

The protective layer 140 may include an insulating material. The protective layer 140 may be coated to protect the surface of the conductive pattern portion, and may include various materials that may be cured by heating. The protective layer 140 may be a resist layer. For example, the protective layer 140 may be a solder resist layer including an organic polymer material. For example, the protective layer 140 may include an epoxy acrylate-based resin. In detail, the protective layer 140 may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, and the like. However, the embodiment is not limited thereto, and the protective layer 140 may be any one of a photo solder resist layer, a cover-lay, and a polymer material.

The protective layer 140 may have a thickness of about 1 μm to about 20 μm. The protective layer 140 may have a thickness of 5 μm to 15 μm. For example, the thickness of the protective layer 140 may be 7㎛ to 12㎛. When the thickness of the protective layer 140 is greater than 20 μm, the thickness of the flexible circuit board for the chip on film may increase. When the thickness of the protective layer 140 is less than 1 μm, the reliability of the conductive pattern part included in the flexible circuit board for the chip on film may be reduced.

After the wiring pattern layer 120, the plating layer 130, and the protective layer 140 are disposed on one surface of the substrate 110, the wiring pattern layer 120 and the plating layer are formed on the other surface opposite to the one surface. 130 and the protective layer 140 may be disposed.

That is, the upper wiring pattern layer, the upper plating layer, and the upper protective layer may be disposed on one surface of the substrate 110 according to the embodiment, and the lower wiring pattern layer, the lower plating layer, and the lower protective layer on the other surface opposite to the one surface. This can be arranged.

The upper wiring pattern layer may include a lower wiring pattern layer and a metal material corresponding to each other. Accordingly, process efficiency can be improved. However, the embodiment is not limited thereto and may include other conductive materials.

The thickness of the upper wiring pattern layer may correspond to the thickness of the lower wiring pattern layer. Accordingly, process efficiency can be improved.

The upper plating layer may include a metal material corresponding to the lower plating layer. Accordingly, process efficiency can be improved. However, the embodiment is not limited thereto and may include other conductive materials.

The thickness of the upper plating layer may correspond to the thickness of the lower plating layer. Accordingly, process efficiency can be improved.

The substrate 110 may include a through hole. The substrate 110 may include a plurality of through holes. The plurality of through holes of the substrate 110 may be respectively formed at the same time or by a mechanical process or a chemical process. For example, the plurality of through holes of the substrate 110 may be formed by a drill process or an etching process. For example, the through hole of the substrate may be formed through a punching and desmear process through a laser. The desmear process may be a process of removing a polyimide smear attached to an inner side surface of the through hole. By the desmear process, the inner surface of the polyimide substrate may have an inclined surface similar to a straight line.

The wiring pattern layer 120, the plating layer 130, the protection pattern unit 190, and the protection layer 140 may be disposed on the substrate 110. In detail, the wiring pattern layer 120, the plating layer 130, and the protective layer 140 may be sequentially disposed on both surfaces of the substrate 110.

The wiring pattern layer 120 may be formed by at least one of evaporation, plating, and sputtering.

In one example, the wiring layer for forming the circuit may be formed by electroplating after sputtering. In one example, the wiring layer for forming the circuit may be a copper plating layer formed by electroless plating. Alternatively, the wiring layer may be a copper plating layer formed by electroless plating and by electrolytic plating.

Next, after laminating the dry film on the wiring layer, a patterned wiring layer may be formed on both surfaces, that is, the upper and lower surfaces of the flexible circuit board, through an exposure, development, and etching process. Accordingly, the wiring pattern layer 120 may be formed.

A conductive material may be filled in the via holes V1, V2, V3, and V4 penetrating the substrate 110. The conductive material filled in the via hole may correspond to the wiring pattern layer 120 or may be different conductive materials from each other. For example, the conductive material filled in the via hole is copper (Cu), aluminum (Al), chromium (Cr), nickel (Ni), silver (Ag), molybdenum (Mo). Gold (Au), titanium (Ti) and their alloys may include at least one metal. The electrical signal of the conductive pattern portion CP of the upper surface of the substrate 110 may be transmitted to the conductive pattern portion CP of the lower surface of the substrate 110 through the conductive material filled in the via hole.

In addition, since the via is formed on the substrate and the wiring is formed, the same material as the wiring may be formed in the via in the same process. This eliminates the process of separately filling the vias with conductive material, and also reduces signal transmission / distortion due to material differences between vias and interconnects.

Next, a plating layer 130 may be formed on the wiring pattern layer 120.

After that, the protective part PP may be screen printed on the conductive pattern part CP.

The conductive pattern part CP may include the wiring pattern layer 120 and the plating layer 130. The area of the wiring pattern layer 120 may correspond to or different from the plating layer 130. An area of the first plating layer 131 may correspond to or different from an area of the second plating layer 132.

Referring to FIG. 3A, an area of the wiring pattern layer 120 may correspond to the plating layer 130. An area of the first plating layer 131 may correspond to an area of the second plating layer 132.

9, an area of the wiring pattern layer 120 may be different from that of the plating layer 130. An area of the wiring pattern layer 120 may correspond to an area of the first plating layer 131. An area of the first plating layer 131 may be different from an area of the second plating layer 132. For example, an area of the first plating layer 131 may be larger than an area of the second plating layer 132.

Referring to FIG. 10, an area of the wiring pattern layer 120 may correspond to the plating layer 130.

Referring to FIG. 11, an area of the wiring pattern layer 120 on one surface of the substrate 110 is different from that of the plating layer 130, and an area of the wiring pattern layer 120 on the other surface of the substrate 110. Silver may correspond to the plating layer 130.

The protective layer 140 may be disposed in direct contact with the substrate 110, may be disposed in direct contact with the wiring pattern layer 120, or may be disposed in direct contact with the first plating layer 131. The second plating layer 132 may be disposed in direct contact with each other.

3A and 3B, the first plating layer 131 is disposed on the wiring pattern layer 120, and the second plating layer 132 is formed on the first plating layer 131. The protective layer 140 may be partially disposed on the second plating layer 132.

9, the first plating layer 131 may be disposed on the wiring pattern layer 120, and the protective layer 140 may be partially disposed on the first plating layer 131. The second plating layer 132 may be disposed in a region other than the region where the protective layer 140 is disposed on the plating layer 131.

The first plating layer 131 contacted by the lower surface of the protective layer 140 may be an alloy layer of copper and tin. The second plating layer 132 in contact with the side surface of the protective layer 140 may include pure tin. Accordingly, it is possible to prevent the removal of the protective layer due to the cavity formed between the protective layer 140 and the first plating layer 131, to prevent the formation of a whisker, to increase the adhesion of the protective layer. have. Therefore, the embodiment may include two plating layers, thereby providing a highly reliable electronic device.

In addition, when only a single tin plating layer 131 is disposed on the wiring pattern layer 120, and the protective layer 140 is disposed on one tin plating layer 131, thermal curing of the protective layer 140 is performed. As the tin plating layer 131 is heated at the time, copper may be diffused in the tin plating layer 131. Accordingly, since the tin plating layer 131 may be an alloy layer of tin and copper, there is a problem in that the mounting of the first chip having gold bumps cannot be made firmly. Therefore, the plating layer 130 according to the embodiment requires the first plating layer 131 and the second plating layer 132 which can continuously increase the tin concentration as the distance from the substrate.

9, the first plating layer 131 may be disposed on the wiring pattern layer 120, and the protective layer 140 may be partially disposed on the first plating layer 131. The second plating layer 132 may be disposed in a region other than the region where the protective layer 140 is disposed on the plating layer 131.

Referring to FIG. 10, the wiring pattern layer 120 may include a first wiring pattern layer 121 and a second wiring pattern layer 122. That is, a plurality of wiring pattern layers may be disposed on the substrate.

Although not illustrated, a metal seed layer may be formed between the substrate 110 and the first wiring pattern layer 121 to improve adhesion between the substrate 110 and the first wiring pattern layer 121. It may further include. In this case, the metal seed layer may be formed by sputtering. The metal seed layer may comprise copper.

The first wiring baton layer 121 and the second wiring pattern layer 122 may be formed to correspond to each other or different processes.

The first wiring baton layer 121 may be formed by sputtering copper to a thickness of 1 μm to 15 μm. The first wiring baton layer 121 may be disposed on upper, lower, and inner surfaces of the through hole of the substrate. At this time, since the thickness of the first wiring baton layer 121 is thin, the inner surfaces of the through holes may be spaced apart from each other.

Next, the second wiring pattern layer 122 may be disposed on the first wiring pattern layer 121. In addition, the second wiring pattern layer 122 may be entirely filled in the through hole by plating.

Since the first wiring pattern layer 121 is formed by sputtering, the first wiring pattern layer 121 has an advantage of excellent adhesion to the substrate 110 or the metal seed layer. However, since the manufacturing cost is high, the first wiring pattern layer ( By forming the second wiring pattern layer 122 by plating again on 121, the manufacturing cost can be reduced. In addition, since the second wiring pattern layer 122 is disposed on the first wiring pattern layer 121 and copper is filled in the via hole without separately filling the through hole of the substrate, the process is performed. The efficiency can be improved. In addition, it is possible to prevent the formation of voids in the via hole, it is possible to provide a fingerprint recognition module including a highly reliable chip-on-film flexible circuit board and an electronic device including the same.

Referring to FIG. 11, a plurality of protective layers 140 may be disposed on one surface of the substrate. The protective layer may include a first protective layer 141 and a second protective layer 142.

For example, the first protective layer 141 may be partially disposed on one surface of the substrate, and the wiring pattern layer 120 may be disposed on a region other than the region where the protective layer 141 is disposed. .

The second protective layer 142 may be disposed on the protective layer 141. The second passivation layer 142 may cover the first passivation layer 141 and the wiring pattern layer 120 and may be disposed in an area larger than the first passivation layer 141.

The protective layer 142 may be disposed on an area corresponding to the protective layer 141 while surrounding the upper surface of the first protective layer 141. The width of the second passivation layer 142 may be larger than the passivation layer 141. Accordingly, the lower surface of the second protective layer 142 may contact the wiring pattern layer 120 and the first protective layer 141. Accordingly, the second protective layer 142 may alleviate concentration of stress at an interface between the first protective layer 141 and the wiring pattern layer 120. Therefore, it is possible to reduce the occurrence of film removal or cracks that may occur when bending the flexible circuit board for the chip-on-film according to the embodiment.

The first and second passivation layers may use the same material. The passivation layer may be formed to have a step on the plating layer. Since the step is formed, it is possible to prevent the removal of the protective layer due to the formation of the cavity between the protective layer 140 and the first plating layer 131, and to prevent the formation of a whisker, the adhesion of the protective layer Can increase.

The plating layer 130 may be disposed in a region other than the region in which the second protective layer 142 is disposed. In detail, the first plating layer 131 is disposed on the wiring pattern layer 120 and the first plating layer 131 on the wiring pattern layer 120 in a region other than the region where the second protective layer 142 is disposed. The second plating layer 132 may be arranged in sequence.

The wiring pattern layer 120 may be disposed on the other surface opposite to the one surface of the substrate. The plating layer 130 may be disposed on the wiring pattern layer 120. The protective layer 140 may be partially disposed on the plating layer 130.

Widths of the protective layer disposed on one surface of the substrate and the protective layer disposed on the other surface of the substrate may correspond to each other or may be different from each other.

Although the drawings show that a plurality of protective layers are disposed only on one surface of the substrate, the embodiment is not limited thereto, and a plurality of protective layers may be included on both surfaces of the substrate, of course. In addition, a plurality or one protective layer may be disposed on only one surface of the substrate.

On the other hand, the fingerprint recognition module 100 including a flexible circuit board for a chip-on-film according to such an embodiment is a substrate 110, a conductive pattern portion (CP) disposed on one surface of the substrate and the conductive pattern portion (CP) The protective layer 140 may be partially disposed on one region of the upper surface of the protective layer 140.

The conductive pattern part CP may include the wiring pattern layer 120 and the plating layer 130.

The protection part PP may not be disposed on an area different from one area on the conductive pattern part CP. Accordingly, the substrate 110 between the conductive pattern portion CP and the spaced apart conductive pattern portion CP may be exposed on one region and the other region on the conductive pattern portion CP. The first connection part 150, the second connection part 160, and the third connection part 170 may be disposed on one area different from the one area on the conductive pattern part CP. In detail, the first connection part 150, the second connection part 160, and the third connection part 170 may be disposed on an upper surface of the conductive pattern part CP on which the protection part PP is not disposed.

Each of the first connector 150, the second connector 160, and the third connector 170 may have a different shape. For example, the first connector 150 may have a hexahedron shape. In detail, the cross section of the first connector 150 may include a quadrangular shape. In more detail, the cross section of the first connector 150 may have a rectangular or square shape. For example, the second connector 160 may have a spherical shape. The cross section of the second connector 160 may have a circular shape. Alternatively, the second connector 160 may have a rounded shape partially or entirely. For example, the cross-sectional shape of the second connection portion 160 may include a flat surface on one side and a curved surface on the other side opposite to the one side.

The third connector 170 may have a spherical shape. The cross section of the third connection unit 170 may include a circular shape. Alternatively, the third connector 170 may include a rounded shape partially or entirely. For example, the cross-sectional shape of the third connection unit 170 may include a flat surface on one side and a curved surface on the other side opposite to the one side.

The first connector 150, the second connector 160, and the third connector 170 may have different sizes. Widths of the first connector 150, the second connector 160, and the third connector 170 may be different from each other. The first chip C1 may be disposed on the first connector 150. The first connector 150 may include a conductive material. Accordingly, the first connector 150 is disposed on the upper surface of the first connector 150 and the conductive pattern portion CP disposed on the lower surface of the first connector 150. Can be electrically connected.

The second chip C2 may be disposed on the second connector 160. The second connector 160 may include a conductive material. Accordingly, the second connecting portion 160 is disposed on the top surface of the second connecting portion 160 and the conductive pattern portion CP disposed on the bottom surface of the second connecting portion 160. Can be electrically connected.

The third chip C3 may be disposed on the third connector 170. The third connector 170 may include a conductive material. Accordingly, the third connecting portion 170 is disposed on the upper surface of the third connecting portion 170 and the conductive pattern portion CP disposed on the lower surface of the third chip C3 and the third connecting portion 170. Can be electrically connected.

Different types of first chips C1, second chips C2, and third chips C3 may be disposed on the same surface of the flexible circuit board for the chip-on-film according to the embodiment. In detail, one first chip C1, one second chip C2, and a plurality of third chips C3 may be disposed on the same surface of the flexible circuit board for the chip-on-film according to the embodiment. Thereby, the efficiency of a chip packaging process can be improved.

The first chip C1 may include a fingerprint recognition sensor. Preferably, the first chip C1 may include an ultrasonic fingerprint recognition sensor. Preferably, the first chip C1 may include a transducer. The transducer constitutes an ultrasonic fingerprint sensor, which is a kind of fingerprint recognition sensor, and its principle is to obtain an image of a fingerprint by converting sound waves reflected by an ultrasonic wave onto a finger placed on a contact surface into an electrical signal. Therefore, the first chip C1 may include a transducer for converting sound waves reflected by the finger into an electrical signal.

The second chip C2 may include an application specific integrated circuit (ASIC). The application specific integrated circuit (ASIC) receives a control signal transmitted through the main board 40 and transmits it to the first chip C1, or analogizes a signal obtained through the first chip C1 to perform the analog processing. The main board 40 may be transferred.

The third chip C3 may include at least one of a diode chip, an MLCC chip, a BGA chip, and a chip capacitor.

The plurality of third chips C3 disposed on the flexible circuit board for the chip on film may mean that at least one of a diode chip, an MLCC chip, a BGA chip, and a chip capacitor is disposed. For example, several MLCC chips may be disposed on the flexible circuit board for the chip on film.

In addition, the third chip C3 may include at least two of a diode chip, an MLCC chip, a BGA chip, and a chip capacitor. That is, a plurality of third chips C3a and C3b of different types may be disposed on the flexible circuit board for the chip on film. For example, a third chip C3a of any one of a diode chip, an MLCC chip, a BGA chip, and a chip capacitor and a diode chip, an MLCC chip, a BGA chip, and a chip capacitor may be formed on the flexible circuit board for the chip on film. Another third chip C3b may be included.

In an embodiment, the type of the third chip is not limited thereto, and various sub-chips for reliability of the operations of the first chip C1 and the second chip C2 may be included therein.

The first chip C1 may be mounted on the first connector 150. In this case, the first connector 150 may include gold (Au). The first connector 150 may be a gold bump. In order to arrange one first chip C1 on the chip warm flexible circuit according to the embodiment, a plurality of first connection parts 150 may be disposed between the first chip C1 and the second plating layer 132. Can be arranged.

Since the second plating layer 132 of the first open region OA1 has a content of tin (Sn) of 50 atomic% or more, the second plating layer 132 has excellent adhesion property with the first connection portion 150 including gold (Au). can do. The fingerprint recognition module 100 including the flexible circuit board for the chip on film may have excellent electrical connection between the first chip C1 and the conductive pattern through the first connection part 150, thereby improving reliability. Can be.

Alternatively, the first connector 150 may include an anisotropic conductive paste (ACP), so that the conductive pattern portion exposed through the terminal of the first chip (C1) and the first open area (OA1). Can be electrically connected

On the other hand, a patterned groove (PG: Patterning Groove) for preventing the flow of the first connecting portion 150 is formed in the conductive pattern portion CP on which the first connecting portion 150 is disposed. A portion of the conductive pattern portion CP on which the first connection portion 150 is disposed may include a first inner lead pattern portion I1 connected to the first chip C1 and a second inner lead pattern portion I2. ). The grooves PG are formed in the first inner lead pattern portion I1 and the second inner lead pattern portion I2, respectively.

Referring to FIG. 4A, a plurality of grooves PG are formed on one inner lead pattern portion at a predetermined interval. The groove PG is formed to prevent the first connector 150 from penetrating into the vibration space of the first chip C1 during the heat treatment of the first connector 150. That is, in order to mount the first chip C1, a process of thermally treating the first connector 150 must be performed. At this time, in the heat treatment process, at least a part of the first connection part 150 may flow in the vibration space direction, and thus may penetrate into the vibration space.

Therefore, in the present invention, the first inner lead pattern portion I1 and the second inner lead pattern to block the flow of a part of the first connecting portion 150 moving in the vibration space direction in the heat treatment process. A plurality of grooves PG are formed in the portion I2, respectively. That is, a part of the first connection part 150 moving in the vibration space direction in the heat treatment process moves inside the plurality of grooves PG, thereby preventing penetration into the vibration space direction. have.

In this case, at least a portion of the first and inner lead pattern portions I1 and I2 may be covered by an upper passivation layer. The upper protective layer may serve as a dam that prevents the first connection portion 150 from moving in the first direction (the direction opposite to the vibration space direction) in the heat treatment process. However, the upper protective layer is not disposed in the second direction (direction toward the vibration space) opposite to the first direction, and thus there is no configuration that functions as the dam. Therefore, the groove PG may be selectively formed only on a region facing the second direction, centering on the centers of the first and second inner lead pattern portions I1 and I2.

For example, in FIG. 4A, an upper passivation layer is disposed on the left side of the first inner lead pattern portion I1 located on the left side. Therefore, the groove PG may not be formed in the left region around the center of the first inner lead pattern portion I1. In addition, the vibration space is formed on the right side of the center of the first inner lead pattern portion I1. Therefore, a plurality of grooves PG spaced at regular intervals may be disposed in the right region around the center of the first inner lead pattern portion I1.

Therefore, in the embodiment according to the present invention, the groove PG is not formed in the first region (the region located in the first direction about the center) of the first inner lead pattern portion I1. 1 to allow the connection part 150 to be stably seated. In addition, the first movement of the first inner lead pattern part I1 may be performed in the second direction by selectively forming the groove PG only in the second region (the region located in the second direction with the center as the center). The flow of the connection unit 150 may be blocked.

Meanwhile, referring to FIG. 4B, the groove PG may be formed under various conditions. The condition may be an interval between a plurality of grooves and a width of each of the grooves.

Referring to FIG. 4B (a), the distance between the plurality of grooves PG may gradually decrease toward the second direction. That is, it is necessary to completely block the flow of the first connecting portion in the edge region of the first and second inner lead pattern portions I1 and I2 closest to the vibration space. Therefore, by reducing the arrangement interval of the grooves PG closer to the vibration space, it is possible to prevent the situation that the first connecting portion can penetrate into the vibration space in advance.

In addition, referring to FIG. 4B (b), the widths of the plurality of grooves PG may be different from each other. That is, each width of the plurality of grooves PG may gradually increase in width in the second direction. In other words, the width of each angle of the plurality of grooves PG may be larger as it is adjacent to the vibration space. Therefore, by increasing the width of the groove PG closer to the vibration space, a situation in which the first connection part 150 can penetrate into the vibration space can be prevented in advance.

Meanwhile, the first and second inner lead pattern parts I1 and I2 are disposed on the first open area OA1 of the upper surface of the substrate 110. In this case, the first and second inner lead pattern parts I1 and I2 may be disposed in an edge area of the first open area OA1. The remaining area except for the edge area of the first open area OA1 forms a vibration space of the first chip C1.

In this case, in the present invention, the protective pattern part 190 is formed in the vibration space, and the penetration of the first connection part 150 and the stable vibration of the first chip C1 are formed through the formed protective pattern part 190. Let the action take place.

That is, the protective pattern part 190 is disposed on the upper surface of the substrate 110 corresponding to the vibration space.

The protection pattern unit 190 may be spaced apart from each other by a predetermined interval, and may include a plurality of protection patterns having a columnar shape.

The protective pattern part 190 may be formed of a non-conductive material. Preferably, the protective pattern portion 190 may be formed of an insulating material. Preferably, the protective pattern portion 190 may be formed of a photosensitive resin. For example, the protection pattern unit 190 may be a photo resist (PR).

In this case, the protection pattern part 190 may include a first protection pattern part 191 disposed in the outer region of the effective part corresponding to the vibration space, and a second protection pattern part 192 disposed in the center area of the effective part. It may include.

The first protective pattern portion 191 may be disposed adjacent to the first inner lead pattern portion I1 and the second inner lead pattern portion I2. The first protective pattern portion 191 may be spaced apart from the first inner lead pattern portion I1 and the second inner lead pattern portion I2 by a predetermined interval.

The first protection pattern portion 191 includes the grooves PG formed in the first inner lead pattern portion I1 and the second inner lead pattern portion I2, and the first connection portion 150 vibrates. Penetration into the effective portion of the space can be prevented.

In other words, the first protective pattern portion 191 is disposed in an outer region of the effective portion of the vibration space among the upper surfaces of the substrate 110 to prevent the first connection portion 150 from penetrating into the effective portion. Can act as a bulkhead.

That is, according to the amount of the first connecting portion 150, a portion of the first connecting portion 150 is formed in the first inner lead pattern portion I1 and the second inner lead pattern portion I2. The flow is not blocked by), and can penetrate into the effective portion of the vibration space.

Accordingly, the first protective pattern part 191 may further prevent the first connection part 150 from penetrating into the effective part of the vibration space.

In this case, the first protective pattern portion 191 may be formed to have a height lower than that of the first inner lead pattern portion I1 and the second inner lead pattern portion I2. Preferably, the first protective pattern portion 191 may have a height lower than that of the conductive pattern portion CP.

Therefore, an upper surface of the first protective pattern unit 191 may have a predetermined distance and may be spaced apart from a lower surface of the first chip C1. In addition, the first chip C1 may perform a vibration within the formed separation distance to obtain a detection signal accordingly.

Preferably, a chip protection layer 153 is formed on the bottom surface of the first chip C1 to protect the bottom surface of the first chip C1. In this case, the chip protection layer 153 may be formed of a photoresist such as SU8.

The upper surface of the first protective pattern part 191 may be spaced apart from the lower surface of the chip protection layer 153 by a predetermined distance in the vibration space.

The second protective pattern part 192 may be disposed in a central area of the effective part of the vibration space. Accordingly, the first protective pattern portion 191 may be disposed to surround the second protective pattern portion 192.

The second protective pattern portion 192 may be formed to ensure the stability of the vibration operation of the first chip (C1). That is, the first chip C1 may vibrate more than normal due to various factors in the use environment. In addition, when the first chip C1 vibrates with a width larger than normal, damage may occur to the first chip C1, and thus, an accurate sensing signal may not be obtained. Accordingly, the second protection pattern unit 192 may prevent abnormal vibration of the first chip C1 in the effective part.

In addition, a pad PAD is electrically connected to the first inner lead pattern portion I1 and the second inner lead pattern portion I2 through the first connection portion 150 on the bottom surface of the first chip C1. ) Is formed. In this case, the pad PAD may be disposed in an outer region of the bottom surface of the first chip C1. Preferably, the pad PAD may be disposed in an edge region of the bottom surface of the first chip C1. Accordingly, the outer region of the first chip C1 may be supported and disposed by the first inner lead pattern portion I1 and the second inner lead pattern portion I2. Alternatively, the central region of the first chip C1 is disposed in a floating state spaced apart from the upper surface of the substrate 110 by a predetermined distance. Accordingly, the first chip C1 may cause a bending phenomenon in which the central region sags downward. Accordingly, the second protective pattern unit 192 can prevent the deflection of the central region of the first chip C1, thereby improving the operational reliability of the first chip C1. Meanwhile, a part of the second protection pattern part 192 may perform a function of preventing the first connection part 150 from penetrating into the effective part together with the first protection pattern part 191.

Referring to FIG. 5, the conductive pattern part CP constituting the first inner lead pattern part I1 and the second inner lead pattern part I2 may have a first height H1. In addition, the substrate 110 may have a second height H2. In addition, the first connection part 150 disposed on the conductive pattern part CP may have a third height H3. In addition, the first chip C1 may have a fourth height H4. In addition, the pad PAD disposed on the bottom surface of the first chip C1 may have a fifth height H5. In addition, the chip protection layer 153 disposed on the bottom surface of the first chip C1 may have a sixth height H6. In addition, the protection pattern part 190 may have a seventh height H7.

The first height H1 of the conductive pattern part CP may satisfy a range between 7 μm and 13 μm.

The second height H2 of the substrate 110 may satisfy a range of 15 μm to 50 μm. For example, the second height H2 of the substrate 110 may satisfy a range between 25 μm and 40 μm. For example, the second height H2 of the substrate 110 may be 30 μm to 35 μm.

In addition, the third height H3 of the first connection part 150 may satisfy a range between 1 μm and 4 μm.

In addition, the fourth height H4 of the first chip C1 may satisfy a range of 50 μm to 70 μm. Preferably, the fourth height H4 of the first chip C1 may be 60 μm.

In addition, the fifth height H5 of the pad PAD disposed on the bottom surface of the first chip C1 may satisfy a range between 1 μm and 3 μm. Preferably, the fifth height H5 of the pad PAD may be 2 μm.

In addition, the sixth height H6 of the chip protection layer 153 disposed on the bottom surface of the first chip C1 may satisfy a range between 2 μm and 10 μm. Preferably, the sixth height H6 of the chip protection layer 153 may satisfy a range between 4 μm and 5 μm.

Meanwhile, the seventh height H7 of the protective pattern unit 190 may satisfy a range between 4 μm and 12 μm. Preferably, the seventh height H7 of the protective pattern part 190 may satisfy a range between 6 μm and 11 μm.

In this case, the first protective pattern portion 191 and the second protective pattern portion 192 may have the same height as the seventh height H7 and may be disposed on the substrate 110. However, the embodiment is not limited thereto, and the heights of the first protective pattern portion 191 and the second protective pattern portion 192 may be different from each other. That is, any one of the first protective pattern portion 191 and the second protective pattern portion 192 may have the seventh height H7. In addition, the other of the first protective pattern portion 191 and the second protective pattern portion 192 may have an eighth height smaller than the seventh height H7.

In addition, the height of each of the first protective pattern part 191 and the second protective pattern part 192 may be smaller than the first height H1 of the conductive pattern part CP.

As described above, in the embodiment according to the present disclosure, a protective pattern portion having a height lower than that of the inner lead pattern portion is formed on the upper surface of the substrate 110 corresponding to the vibration space of the first chip C1. A predetermined space exists between the upper surface of the protective pattern portion and the lower surface of the first chip C1. In addition, the first chip C1 may operate by vibrating in the separation space. In addition, the protective pattern part may prevent the first chip C1 from vibrating violently in the downward direction, thereby improving the operational reliability of the first chip C1. On the other hand, the first chip (C1) is mounted on the inner lead pattern portion by the connection portion, the outer region can be supported by the inner lead pattern portion. Alternatively, the central region of the first chip C1 is positioned in a floating state on the substrate. In this case, the protective pattern part may prevent the central area of the first chip C1 from sagging below the outer area, thereby minimizing the warpage of the first chip C1.

The protective pattern part may include a second protective pattern part disposed in a central area of the effective part, and a first protective pattern part surrounding the second protective pattern part and disposed in an outer area of the effective part. In this case, the first protective pattern portion and the second protective pattern portion may have different shapes or different sizes. As described above, the second protective pattern portion may function to prevent sagging of the central region of the first chip C1. In addition, the first protective pattern part may further prevent the first connection part from penetrating into the effective part.

6A to 6D, the protective pattern part 190 may have various shapes and may be disposed on an effective part corresponding to the vibration space among the upper surfaces of the substrate 110.

Referring to FIG. 6A, the first protective pattern portion 191 may be disposed in an outer region of the effective portion of the upper surface of the substrate 110. In this case, the first protection pattern unit 191 may include a plurality of first protection patterns spaced apart from each other by a predetermined interval. The first protective pattern may have a quadrangular cross section. In addition, the overall shape of the first protective pattern portion 191 connecting the plurality of first protective patterns may also have a square shape. However, the embodiment is not limited thereto, and the first protective pattern part 191 may have a triangular shape or a polygonal shape.

The second protective pattern part 192 may be surrounded by the first protective pattern part 191, and may be disposed in a central area of the effective part. In this case, the second protection pattern unit 192 may include a plurality of second protection patterns that are spaced apart from each other by a predetermined interval in the central region of the effective part. In this case, the second protection pattern may have a circular cross section. However, the embodiment is not limited thereto, and the second protection pattern may be modified into an ellipse shape, a heart shape, and a fan shape.

That is, the first protective pattern portion 191 and the second protective pattern portion 192 may have different horizontal cross-sectional shapes. This is because the functions of the first protective pattern part 191 and the second protective pattern part 192 are different from each other.

The first protective pattern part 191 performs a function of preventing penetration of the first connection part 150. In this case, when the vertical cross section of the first protective pattern portion 191 has a curved surface, a portion of the first connection portion 150 may penetrate into the effective portion through the curved surface. Therefore, the first protective pattern portion 191 preferably has a rectangular shape as described above to completely block the penetration of the first connection portion 150.

In addition, the second protective pattern unit 192 prevents the lower surface of the first chip C1 from sagging. Therefore, the second protective pattern unit 192 may contact the lower surface of the first chip C1 (more specifically, the lower surface of the chip protective layer). Accordingly, the second protective pattern constituting the second protective pattern part 192 has a cross-sectional shape like a circle, so that damage to the bottom surface of the first chip C1 can be minimized.

Meanwhile, referring to FIG. 6B, the first protective pattern portion 191 may be arranged in a plurality of rows in the outer region of the effective portion.

That is, in FIG. 6A, the first protective pattern part 191 is illustrated as being arranged in one row in the outer region of the effective part.

Alternatively, referring to FIG. 6B, the first protective pattern portion 191 may be disposed in two rows in the outer region of the effective portion. However, this is only an example, and the first protective pattern portion 191 may be arranged in three rows, four rows, or more rows.

That is, the first protection pattern part 191 may protect the first row of protection patterns 191a disposed in the outermost region of the effective part and the second row of protection patterns 191a of the first row. It may include patterns 191b. The protection patterns 191a in the first column and the protection patterns 191b in the second column may include a plurality of protection patterns spaced apart from each other by a predetermined interval.

In this case, the protection patterns 191a of the first column are spaced apart from each other as described above, so that an open area OR exists between the protection patterns 191a of each first column. In this case, a situation may occur in which the first connection unit 150 penetrates through the open area OR. Accordingly, in the present invention, additional protective patterns 191b of the second column are formed in addition to the protective patterns 191a of the first column. In this case, the protective patterns 191a of the first column and the protective patterns 191b of the second column may be arranged in a zigzag form in each column. In other words, the protection patterns 191b of the second column may be disposed on the open area OR between the protection patterns 191a of the first column within the second column. Accordingly, even if the first connection part 150 penetrates through the open area OR between the protection patterns 191a of the first row, the flow may be blocked by the protection patterns 191b of the second row. Can be.

6C, the first protection pattern unit 191 may include the protection patterns 191a in the first column and the protection patterns 191b in the second column as described above.

In addition, the second protection pattern part 192 may be disposed in the protection patterns 191 of the second row. In this case, the second protective pattern portion 192 may have a square cross-sectional shape different from the shape shown in the previous drawing.

Meanwhile, as shown in FIG. 6D, the first protection pattern unit 191 may include only one protection pattern in one column.

In this case, as in the previous embodiment, the first protection pattern unit 191 may not include the plurality of first protection patterns spaced apart from each other by a predetermined interval, but may include a single protection pattern. Preferably, the first protective pattern portion 191 may have a single closed curve shape surrounding an outer region of the effective portion. Accordingly, the first connection portion 150 may be completely blocked flow by the first protective pattern portion 191 of the single closed curve shape.

The first side molding part 155 may be disposed around the first chip C1. The first side molding part 155 may ensure the operational reliability of the first chip C1 from various contamination factors in the environment of using the fingerprint recognition module. In this case, the first side molding part 155 is not disposed in the lower region of the first chip C1. Preferably, the first side molding part 155 is disposed surrounding the outer region of the terminal of the first chip C1, thereby sealing the circumference of the lower region of the first chip C1. Therefore, a space is formed between the substrate 110 and the first chip C1 in the lower region of the first chip C1. The space is formed for vibration generated during the operation of the first chip C1. That is, the first chip C1 is an ultrasonic fingerprint sensor, and thus vibration occurs during operation. Therefore, the space ensures a space for stable vibration of the first chip (C1).

At this time, if the space is too large, there is a problem that the total volume of the fingerprint recognition module accordingly increases, and if the space is too narrow, the first chip C1 and the substrate 110 during the operation of the fingerprint recognition sensor. Problems may arise in the operation reliability of the first chip (C1) according to the contact therebetween.

Therefore, the height of the space to have a 7㎛ ~ 13㎛. In addition, the height of the space is to have between 8㎛ ~ 11㎛. Preferably, the height of the space is to be at least 7㎛. That is, when the height of the space is smaller than 7 μm, a problem may occur due to insufficient vibration space of the first chip C1. Accordingly, in the present invention, the thickness of the wiring pattern layer 120, the thickness of the first plating layer 131, and the thickness range of the second plating layer 132 are adjusted so that the height of the conductive pattern portion is at least 7 μm. do.

Meanwhile, a chip protection layer is disposed on the bottom surface of the first chip C1. The chip protection layer is formed between the first chip C1 and the substrate to protect the first chip C1 due to contact between the first chip C1 and the substrate.

In addition, at least one vent path (VP) is formed on a region vertically overlapping the region where the first chip C1 is disposed. The vent path (VP) communicates with the vibration space. The vent path (VP) forms a gas discharge path for discharging the gas filled in the vibration space to the outside.

To this end, the vent path (VP) communicates with the vibration space to form a path for discharging the gas filled in the vibration space to the outside. In other words, the vent path (VP) is formed through the substrate 110, the lower conductive pattern portion CP, and the lower protective layer PP positioned on a region vertically overlapping the vibration space. . In this case, a plurality of vent paths (VP) may be disposed at positions spaced apart from each other by a predetermined interval. For example, the vent paths (VP) may be disposed at edge regions of the vibration space, respectively.

Preferably, the through hole VP may pass through the substrate 110 in a region between the first protective pattern portion 191 and the second protective pattern portion 192.

In conclusion, the operation of the first chip C1 is performed by vertical vibration in the vibration space. At this time, the moisture penetrating into the vibration space or foreign matter such as the first connection portion 150 may interfere with the vibration of the first chip (C1), thereby reducing the operational reliability of the first chip (C1) Problems may arise.

Accordingly, in the present invention, a plurality of grooves are formed on the inner lead pattern portion on which the first chip C1 is mounted, so that part of the first connection portion vibrates during the heat treatment of the first connection portion. Prevents penetration into space. In addition, the first side molding part 155 is disposed around the first chip C1, thereby preventing the penetration of moisture or foreign matter into the vibration space. In addition, a through hole (VP) is formed on the substrate in communication with the vibration space, thereby solving the reliability problem caused by the gas is filled in the vibration space.

On the other hand, the second connection portion 160 is disposed in the second open area OA2 of the flexible circuit board for chip on film.

In order to arrange the second chip C2 on the flexible circuit board for the chip-on-film according to the embodiment, heat is selectively provided only to a portion corresponding to an area where the second connection portion 160 is disposed through a mask (not shown). Can supply In detail, the embodiment may selectively supply heat to a region where the second connector 160 for connecting the second chip C2 is disposed through a selective reflow process. In detail, the flexible circuit board for the chip-on-film according to the embodiment may be a part through a selective reflow process even when the second chip C2 is disposed after the first chip C1 is mounted. Heat supply may be possible.

That is, the manufacturing process according to the embodiment may prevent the heat of the first open region OA from being exposed through the mask. Accordingly, the second plating layer disposed in the first open region OA1 can be prevented from being denatured from pure tin to an alloy layer of tin and copper by heat supply. Accordingly, even when different first chips C1 and second chips C2 are mounted on one chip-on-film flexible circuit board 100, the second plating layer 132a in the first open area. The tin (Sn) content of) may be 50 atom% or more, so that the assembly of the first chip C1 may be excellent.

The second connector 160 may include gold (Au), but preferably, the second connector 160 may include a metal other than gold (Au). Accordingly, the second connector 160 has excellent assembly performance with the second chip C2 even when the second plating layer 132 disposed below the second connector 160 is not pure tin. can do. In addition, the second connection part 160 may include a metal other than gold (Au), thereby reducing manufacturing costs.

For example, the second connector 160 may include copper (Cu), tin (Sn), aluminum (Al), zinc (Zn), indium (In), lead (Pb), antimony (Sb), and bismuth (bi). ), Silver (Ag), and nickel (Ni).

The second connector 160 may be a solder bump. The second connector 160 may be a solder ball. At the temperature of the reflow process, the solder ball may be melted.

In order to arrange one second chip C2 on the flexible circuit board for chip-on-film according to the embodiment, a plurality of second connection portions 160 are disposed between the second chip C2 and the second plating layer 132. Can be placed in.

At the temperature of the reflow process, the second chip C2 may be capable of excellent bonding with the second plating layer 132 on the second open area OA2 through the second connector 160.

In the flexible circuit board for chip-on-film according to the embodiment, the connection of the first chip C1 is excellent through the first connection part 150 in the first open area, and the second connection part 160 in the second open area. Through the connection of the second chip (C2) may be excellent.

Meanwhile, a second side molding part 164 may be disposed around the second chip C2. The second side molding part 164 may ensure operational reliability of the second chip C2 from various contamination factors. In this case, the second side molding part 164 may not be disposed in the lower region of the second chip C2. Alternatively, the second side molding part 164 may be disposed to fill all the lower regions of the second chip C2. Therefore, the second side molding part 164 may improve the mounting robustness of the second chip C2.

On the other hand, a third connecting portion 170 is disposed in the third open area OA3 of the flexible circuit board for chip on film.

In order to arrange the third chip C3 on the flexible circuit board for the chip-on-film according to the embodiment, heat is selectively provided only to a portion corresponding to an area where the third connection unit 170 is disposed through a mask (not shown). Can supply In detail, the embodiment may selectively supply heat to a region where the third connector 170 for connecting the third chip C3 is disposed through a selective reflow process.

The third connector 170 may include a metal other than Au. Accordingly, the third connector 170 has excellent assembly performance with the third chip C3 even when the second plating layer 132 disposed below the third connector 170 is not pure tin. can do. In addition, the third connection portion 170 may include a metal other than gold (Au), thereby reducing the manufacturing cost.

For example, the third connector 170 may include copper (Cu), tin (Sn), aluminum (Al), zinc (Zn), indium (In), lead (Pb), antimony (Sb), and bismuth (bi). ), Silver (Ag), and nickel (Ni).

Meanwhile, a distance between the first chip C1 and the second chip C2 is separated by a first distance W1, and a second distance between the second chip C2 and the third chip C3 ( Spaced apart by W2). That is, the first chip C1 and the second chip C2 are spaced apart by the first distance W1, thereby minimizing the possibility of cracking occurring during bending.

That is, a bending region is included between the first chip C1 and the second chip C2. More specifically, between the first chip C1 and the second chip C2, a first non-bending region adjacent to the first chip C1 and a second ratio adjacent to the second chip C2 are provided. A bent region and a bent region between the first non-bended region and the second non-bended region.

In this case, the width of the bent region may be determined by the thickness of the substrate 110 or the thickness of the conductive pattern portion CP. In this case, if the interval between the first chip C1 and the second chip C2 is too narrow, the widths of the first and second non-bended regions may be narrowed. In this case, damage may be applied to the mounted first chip C1 or the second chip C2 when the substrate is bent, and cracking of the bonding part may occur.

Therefore, referring to FIG. 7A, the distance between the first chip C1 and the second chip C2 should have a minimum distance at which the crack may not occur. At this time, after bending, the distance (W3) between the bent end and the first chip (C1) should be at least 1.6mm to prevent the occurrence of cracks. In addition, after bending, the distance between the bent end and the second chip (C2) should be at least 1.6mm to prevent the occurrence of the crack. Therefore, the distance W1 between the first chip C1 and the second chip C2 is set to be at least 3.2 mm.

Herein, the distance between the bent end and the first chip C1 may mean a distance from the end of the rightmost substrate to the right end of the first chip C1 after bending of the substrate. have. Herein, the distance between the bent end and the second chip C2 may mean a distance from the end of the rightmost substrate to the left end of the second chip C2 after bending of the substrate. have. In addition, when the distance W1 between the first chip C1 and the second chip C2 exceeds 10 mm, the output signal of the first chip C1 received by the second chip C2 may be applied to the output signal. Losses may occur. The distance W1 between the first chip C1 and the second chip C2 is in a range of 3.2 mm to 10 mm. For example, the distance W1 may be between 3.2 mm and 5 mm. For example, the distance W1 may be between 3.2 mm and 3.6 mm.

In addition, the closer the distance between the second chip (C2) and the third chip (C3), the better the signal processing. That is, when the distance between the second chip C2 and the third chip C3 increases, the length of the signal wire becomes longer, and signal transmission loss occurs due to an increase in the wire resistance. However, when the distance between the second chip and the third chip C3 is too close, a reliability problem may occur in the mounting process between the second chip C2 and the third chip C3. That is, generally, the mounting process of the third chip C3 is performed after the second chip C2 is mounted. In this case, when the distance between the second chip C2 and the third chip C3 is too close, when the bonding of the third chip C3, the second connection portion 160 that has completed the bonding is melted. This occurs, thereby causing a problem in that the position of the second chip C2 is changed. Therefore, the distance W2 between the second chip C2 and the third chip C3 is set to be at least 1.0 mm, thereby solving the problem that may occur.

In addition, when the distance W2 between the second chip C2 and the third chip C3 exceeds 5 mm, a loss in the signal between the second chip C2 and the third chip C3 may occur. May occur. The distance W2 between the second chip C2 and the third chip C3 is in a range of 1.0 mm to 5 mm. For example, the distance W2 may be between 1.0 mm and 3 mm. For example, the distance W2 may be between 1.0 mm and 1.5 mm.

That is, the distance W2 may be smaller than the distance W1 between the first chip C1 and the second chip C2. This allows a flexible circuit board that can be bent while minimizing signal loss.

Meanwhile, referring to FIG. 7B, the upper surface of the flexible circuit board before the bending may satisfy a range of 14 mm to 26 mm in a length in the first direction. Preferably, the length of the flexible circuit board in the first direction may be 19.96 mm. In addition, the length of the second direction perpendicular to the first direction of the upper surface of the associative circuit board may be 10mm to 15mm. Preferably, the length of the second direction of the flexible circuit board may be 12.1 mm.

On the other hand, after bending the flexible circuit board as described above, the length of the second direction is maintained as it is, the length of the first direction may be 1/2 of the length before bending. Preferably, the length in the first direction after the bending may be 7 mm to 13 mm. Preferably, the length of the first direction after the bending may be 10 mm.

Accordingly, the length in the first direction of the flexible circuit board after the bending may be 10 mm, and the length in the second direction may be 12.1 mm.

Meanwhile, the first chip C1 is disposed above the flexible circuit board after the bending, and the second chip C2 and the third chip C3 are disposed below. In this case, an upper surface area of the flexible circuit board after the bending may be determined according to an area of the first chip C1.

In this case, an upper surface of the first chip C1 may satisfy a range between 7 mm and 8 mm in the first direction and the second direction. Preferably, the length in the first direction of the upper surface of the first chip C1 may be 7.43 mm, and the length in the second direction may be 7.83 mm.

Accordingly, the area of the upper surface of the first chip C1 and the area of the upper surface of the flexible circuit board after the bending may satisfy a ratio of 1: 2 or less. Preferably, the area of the upper surface of the first chip C1 and the area of the upper surface of the flexible circuit board after the bending may satisfy a ratio of 1: 1.8 or less. Preferably, the area of the upper surface of the first chip C1 and the area of the upper surface of the flexible circuit board after the bending may satisfy a ratio of 1: 1.5 or less. That is, the upper surface area of the flexible circuit board after the bending is about 1.5 times the upper surface area of the first chip C1.

On the other hand, as described above, the flexible circuit board includes a bent region. Accordingly, the flexible circuit board includes a first non-bending area of the flexible circuit board located on one side of the bent area and a second non-bending area of the flexible circuit board located on the other side of the bent area. In this case, the adhesive layer 180 may be disposed between the first non-bending area and the second non-bending area. The adhesive layer 180 maintains the bending form of the flexible circuit board. In addition, a shielding film (not shown) may be disposed on the surface of the adhesive layer 180 to shield electromagnetic waves. The shielding film may be configured to prevent signal interference between the first chip C1 disposed in the first non-bent region, the second chip C2 and the third chip C3 disposed in the second non-bent region. Electromagnetic waves can be shielded while being suppressed.

On the other hand, as described above, a hole (VP: Vent Path) is formed on the flexible circuit board. In this case, when the flexible circuit board is bent, the lower portion of the vent path (VP) is blocked by the adhesive layer 180. Accordingly, an additional gas discharge path is formed in the adhesive layer 180 to communicate with a vent path (VP) formed on the flexible circuit board. That is, the vent path (VP) may be divided into a first part and a second part. The first part may be formed on the flexible circuit board in communication with the vibration space. In addition, the second part may be formed on the adhesive layer 180 while communicating with the first part.

Referring to FIG. 8, a second part of a vent path (VP) is formed in the adhesive layer 180. In this case, the second part may include a first sub part 141 having a same horizontal cross-section as the first part, and an agent extending from the first sub part 141 to at least one end of the adhesive layer 180. It may include two sub-parts 142. In this case, the second sub part 142 may be formed by bending at least once. However, this is only an example, and the second sub part 142 may connect the end portion of the adhesive layer 180 and the first part in a straight line without a bent portion.

Meanwhile, a main wiring connecting the first chip C1 and the second chip C2 may be located on an upper surface of the substrate 110. The main wiring may be a signal transmission line through which a detection signal obtained from the first chip C1 is transferred to the second chip C2.

In this case, the conductive pattern portions CP disposed on the upper surface of the substrate 110 do not overlap each other in a vertical direction. That is, since the main wirings are located only on the upper surface of the substrate 110, the respective main wirings cannot overlap each other in the vertical direction. In this case, when the main wires overlap each other in the vertical direction, signal transmission efficiency may decrease due to signal interference between the main wires.

Meanwhile, the main wiring includes a plurality of signal lines spaced apart from each other, and accordingly, the main wiring has a form in which at least one bend (including both bent and acute angles) is bent on the upper surface of the substrate 110 rather than in a straight line shape. Have

At this time, the main wirings do not overlap each other in the vertical direction before bending the flexible circuit board. However, after bending the flexible circuit board, the main wirings overlap each other in the vertical direction. Accordingly, after bending, mutual signal interference may occur in the main wiring.

Therefore, in the present invention, a plurality of ground patterns GP are formed on the substrate 110. The ground pattern is connected to a ground terminal (not shown), thereby removing noise or electromagnetic interference noise generated on a chip or a signal wire.

The plurality of ground patterns GP may include a first ground pattern GP1, a second ground pattern GP2, and a third ground pattern GP3. In this case, signal lines between the first chip C1, the second chip C2, and the third chip C3 are mainly disposed on the upper surface of the substrate 110. This is to minimize the length of the signal line and to increase the signal transmission efficiency accordingly.

Therefore, the plurality of ground patterns GP according to the present invention are formed in the dummy region of the lower surface of the substrate 110.

In this case, arrangement positions of the first ground pattern GP1, the second ground pattern GP2, and the third ground pattern GP3 are different from each other.

The first ground pattern GP1 is positioned on a bottom surface of the substrate 110 that vertically overlaps an area between the first chip C1 and the second chip C2. The region between the first ground pattern GP1 and the second chip C2 is a bent region as described above. In the bending region, as described above, the main wirings have a structure in which they overlap each other in the vertical direction. Therefore, the first ground pattern GP1 is disposed on the bottom surface of the bent region of the substrate 110. The first ground pattern GP1 removes signal interference or electromagnetic interference between the first chip C1 and the second chip C2.

The second ground pattern GP2 is disposed in an area of the lower surface of the substrate 110 that vertically overlaps with an area where the second chip C2 is disposed. That is, when the flexible circuit board is bent, the first ground pattern GP1 and the second chip C2 are disposed to face each other, which may cause reliability problems due to signal interference or electromagnetic interference noise. have. Therefore, the second ground pattern GP2 is disposed in a region of the lower surface of the substrate 110 that vertically overlaps with the region where the second chip C2 is disposed, thereby generating the second chip C2. Eliminate electromagnetic interference.

The third ground pattern GP3 is disposed on the bottom surface of the substrate 110 that vertically overlaps the fourth open area OA4. That is, a fourth open area OA4 is formed on the upper surface of the substrate 110, and an outer lead pattern part connected to the main board is exposed through the fourth open area OA4.

The main board is bonded to the outer lead pattern portion. In this case, after the main board is bonded, signal interference between the flexible circuit board and the main board may occur. Therefore, the third ground pattern GP3 is disposed on the bottom surface of the substrate 110 that vertically overlaps the outer lead pattern portion. The third ground pattern GP3 blocks signal interference or electromagnetic interference noise generated between the flexible circuit board and the main board.

Meanwhile, each of the first ground pattern GP1, the second ground pattern GP2, and the third ground pattern GP3 has a mesh pattern shape. That is, the conductive pattern part CP in the present invention is a fine pattern. In this case, when the first ground pattern GP1, the second ground pattern GP2, and the third ground pattern GP3 have a stripe shape having a width larger than that of the fine pattern, a line in the stripe ground pattern There is a problem of increasing resistance. In addition, since the width of the stripe-shaped pattern is larger than the width of the fine pattern, the width of the fine pattern may increase due to the difference in width between the patterns. Similarly, when the ground pattern is formed in a plate shape having an area of a predetermined level or more, the width of the fine pattern may be affected during the manufacturing process of the plate pattern. Therefore, in the present invention, the first ground pattern GP1, the second ground pattern GP2, and the third ground pattern GP3 have a mesh pattern shape, thereby making it possible to obtain an optimal signal without affecting a fine pattern. Allows you to remove interference or electromagnetic interference.

Referring to FIG. 12A, the first chip C1 mounted on the chip on film flexible circuit board may contact the display panel 30. Preferably, the adhesive layer 50 may be disposed on the top surface of the first chip C1. The first chip C1 may be attached to the bottom surface of the display panel 30 by the adhesive layer 50. This makes it possible to fabricate a device that maximizes the effective area of the display.

Alternatively, referring to FIG. 12B, the first chip C1 mounted on the flexible circuit board for the chip on film may contact the cover window 70 positioned on the display panel 30. Preferably, at least one area of the cover window 70 may not vertically overlap with the display panel 30. Preferably, at least one area of the cover window 70 may include an invalid area in which an image is not displayed, so that the first chip C1 is disposed below the invalid area of the cover window 70. Can be attached.

Accordingly, the display panel 30 or the curve window 70 and the flexible circuit board for chip on film (obviously, the first chip) may be bonded up and down with the adhesive layer 50 interposed therebetween. have. This can minimize the distortion of the fingerprint signal transmitted through the display.

Meanwhile, the cover window 70 may be a glass film.

One end of the flexible circuit board 100 for the chip on film may include a protection part PP. In other words, one end of the flexible circuit board 100 for chip-on-film does not need to be connected to an external substrate or a chip, and thus one end may be covered by a protective layer, and thus the conductive pattern part is not exposed to the outside. Since the terminal exposing the conductive pattern portion is not required at one end, the length of the flexible circuit board 100 for the chip on film may be minimized, and space for mounting other components such as a battery may be secured.

The other end opposite to the one end of the flexible circuit board 100 for the chip on film may be connected to the main board 40. The other end opposite to the one end of the flexible circuit board 100 for the chip on film may be connected by the main board 40 and the adhesive layer 50. In detail, the main board 40 may be disposed on the upper surface of the adhesive layer 50, and the flexible circuit board for the chip on film may be disposed on the lower surface of the adhesive layer 50. Accordingly, the main board 40 and the flexible circuit board for the chip on film may be bonded up and down with the adhesive layer 50 interposed therebetween. The adhesive layer 50 disposed between the main board 40 and the flexible circuit board for the chip on film may include a conductive material. The adhesive layer 50 may be one in which conductive particles are dispersed in an adhesive material. For example, the adhesive layer 50 may be an anisotropic conductive film (ACF). Accordingly, the adhesive layer 50 may transmit an electrical signal between the flexible circuit board for the chip on film and the main board 40 and may stably connect separate components.

Alternatively, the adhesive layer 50 disposed on the first chip C1 may include a PET-based transparent adhesive layer as an optical clear adhesive (OCA).

Meanwhile, as shown in FIG. 10C, a second substrate 20 may be additionally disposed between the flexible circuit board for the chip on film and the main board 40. The second substrate 20 may provide additional functions other than the fingerprint recognition function, such as additional signal processing, a function of recognizing a touch signal according to movement of a stylus pen or a hand on a display, or a drive IC that processes a signal of a display. To this end, the main board and the flexible circuit board for the chip-on film may be disposed. The second substrate 20 may have a structure including an insulating substrate 21, a conductive pattern portion 22, a protective layer 23, and a reinforcing portion 24 for securing strength. Through this, the substrate for processing the fingerprint recognition signal and the touch myth or the display signal can be processed on one substrate.

Meanwhile, referring to FIGS. 3 to 12, a connection relationship with the main board 40 will be described.

The flexible circuit board 100 for a chip on film according to the embodiment may include a substrate 100 including a through hole; A wiring pattern layer 120 disposed on both surfaces of the substrate including the through holes; A first plating layer 131 disposed on the wiring pattern layer 120; A second plating layer 132 disposed on the first plating layer 131; And a protective layer 140 partially disposed on the wiring pattern layer.

By forming the wiring pattern layer 120 on both sides of the substrate, a substrate having a size substantially similar to that of a fingerprint chip can be formed.

An area of the protective layer 140 on which the protective layer 140 is formed may be the protective part PP. The conductive pattern part CP may be exposed to the outside in a region other than the protective part PP in which the protective layer is not formed. That is, in the open area of the protective layer or the area in which the protective part is not disposed on the conductive pattern part, the conductive pattern part CP includes the first chip C1, the second chip C2, the third chip C3, and the like. It may be electrically connected to the main board 40.

The lead pattern portion of the flexible circuit board for the chip on film according to the embodiment may not overlap with the protective portion. That is, the lead pattern part may mean a conductive pattern part located in an open area not covered by the protective layer, and may be classified into an inner lead pattern part and an outer lead pattern part according to a function. In addition, although not shown in the drawings, a test pattern part (not shown) may be further located in an area that does not overlap with the protection part. The test pattern unit is a pattern for testing whether a signal is normally transmitted through each conductive pattern unit. That is, the test pattern unit may mean a conductive pattern unit for confirming whether the flexible circuit board for the chip on film and the fingerprint recognition module including the same are defective.

The lead pattern part may mean a conductive pattern part for connecting to the first chip, the second chip, the third chip C3, and the main board.

The lead pattern portion may be classified into an inner lead pattern portion and an outer lead pattern portion according to a position. One region of the conductive pattern portion which is relatively close to the first chip C1 and is not overlapped by the protective layer may be represented as an inner lead pattern portion. One region of the conductive pattern portion, which is relatively far from the first chip C1 and is not overlapped by the protective layer, may be represented by an outer lead pattern portion.

The flexible circuit board for the chip on film may include a first inner lead pattern portion I1, a second inner lead pattern portion I2, a third inner lead pattern portion I3, a fourth inner lead pattern portion I4, and a fifth The inner lead pattern portion I5 and the sixth inner lead pattern portion I6 may be included.

The flexible circuit board for the chip on film according to the embodiment may include an outer lead pattern part OP.

The first inner lead pattern portion I1, the second inner lead pattern portion I2, the third inner lead pattern portion I3, and the fourth portion are formed on one surface of the flexible circuit board 100 for chip on film according to the embodiment. The inner lead pattern portion I4, the fifth inner lead pattern portion I5, the sixth inner lead pattern portion I6, and the outer lead portion OP may be disposed.

Meanwhile, the position of the outer lead part OP may be changed. That is, the position of the outer lead part OP may be located on the bottom surface of the substrate 110. In this case, the test pattern part may be located on an upper surface of the substrate 110.

That is, although the test pattern portion and the outer lead pattern portion OP are illustrated as being formed on the lower surface and the upper surface of the substrate, some or all of the plurality of patterns may be formed on the upper surface and the lower surface in accordance with design efficiency. .

Preferably, when the flexible circuit board for the chip-on-film is bent and attached to the main board, the upper surface is formed by the outer lead pattern part OP and the lower surface is formed by the test pattern part, thereby eliminating space constraints due to the plurality of pattern parts. have.

The first chip C1 disposed on one surface of the flexible circuit board for the chip-on-film according to the embodiment may be formed through the first connection part 150 and the first inner lead pattern part I1 and the second inner lead. It may be connected to the pattern portion I2.

The first connector 150 may include a first sub-first connector 151 and a second sub-first connector 152 according to a location and / or a function.

The first chip C1 disposed on one surface of the flexible circuit board 100 for chip-on-film according to the embodiment is the first inner lead pattern part I1 through the first sub-first connection part 151. And may be electrically connected with.

The first inner lead pattern part I1 may transmit an electrical signal to the first via hole V1 along the upper surface of the substrate 110. The first via hole V1 and the first inner lead pattern portion I1 may be electrically connected to each other.

In addition, the first inner lead pattern part I1 may be electrically connected to the first via hole V1 along the upper surface of the substrate 110, and the substrate may be filled with a conductive material filled in the first via hole V1. An electrical signal may be transmitted to the third via hole V3 along the bottom surface of the 110. In this case, the signal transmitted through the first via hole V1 and the third via hole V3 may be a signal transmitted between the second chip C2 and the first chip C1. Preferably, the signal transmitted through the first via hole V1 and the third via hole V3 may be a control signal of the first chip C1 transmitted through the main board 40.

In other words, the signal transmission line from the first chip C1 may be disposed on the bottom surface of the substrate 110 through the via hole.

Through this, the outgoing signal Tx for fingerprint recognition is formed on the lower surface of the flexible circuit board 100 for chip-on-film, so that the signal transmission line is relatively long, and the received signal Rx returned after the fingerprint is recognized on the upper surface. By forming shorter than the outgoing signal transmission line, it can recognize the fingerprint more clearly. Preferably, the number of transmission signal Tx signal transmission lines may be greater on the bottom surface of the flexible circuit board 100 for chip-on-film than the number of transmission signal Rx signal transmission lines.

The first chip C1 disposed on one surface of the flexible circuit board 100 for chip-on-film according to the embodiment is the second inner lead pattern portion I2 through the second sub-first connection portion 152. And may be electrically connected with.

The second inner lead pattern portion I2 disposed on the upper surface of the substrate 110 may be formed of a conductive material filled in a second via hole V2 disposed under the second inner lead pattern portion I2. It may be connected to the fourth via hole V4 along the bottom surface of 110.

In addition, if the test pattern unit is formed, the test pattern unit may identify a failure of an electrical signal that may be transmitted through the first via holes V1, V2, V3, and V4. For example, the accuracy of the signal transmitted to the first inner lead pattern unit I1 may be confirmed through the test pattern unit. In detail, as the voltage or current is measured by the test pattern unit, whether or not a short circuit or a short circuit occurs in the conductive pattern unit positioned between the first chip and the second chip can be confirmed, thereby improving product reliability. You can.

Meanwhile, a plurality of grooves PG as described above are formed on the first inner lead pattern portion I2 and the second inner lead pattern portion I2, and the first groove lead PG is formed through the plurality of grooves PG. The connection part 150 can be prevented from penetrating into the vibration space.

In addition, the protective pattern part 190 is disposed on an effective part corresponding to the vibration space among the upper surfaces of the substrate 110. The protection pattern unit 190 may include a first protection pattern unit 191 that additionally blocks the flow of the first connection unit 150 that is not completely blocked through the plurality of grooves PG. Accordingly, the first protective pattern portion 191 may be disposed in the outer region of the effective portion adjacent to the first inner lead pattern portion I2 and the second inner lead pattern portion I2.

In addition, the protection pattern unit 190 may include a second protection pattern unit 192 disposed in the central area of the effective unit. The second protective pattern unit 192 prevents the first chip C1 from sagging and enables the first chip C1 to stably vibrate.

In addition, the second chip C2 may be connected to the third inner lead pattern part I3 through the first sub second connection part 161, the second sub second connection part 162, and the third sub second connection part 163, respectively. The fourth inner lead pattern portion I4 and the fifth inner lead pattern portion I5 are electrically connected to each other. In this case, the third inner lead pattern portion I3 may be directly connected to the second inner lead pattern portion I2 through a wire disposed on the upper surface of the substrate without passing through the via hole. In this case, a signal transmitted from the first chip C1 to the second chip C2 is transmitted to the third inner lead pattern part I3 and the second inner lead pattern part I2. May be a line.

That is, the second chip C2 performs analog signal processing, and accordingly, the accuracy of the output signal is determined according to the accuracy of the received signal. In this case, the longer the transmission line of the received signal is, the greater the loss of the signal is, thereby reducing the accuracy of the signal received by the second chip (C2). Therefore, in the present invention, between the first chip C1 and the second chip C2, the signal receiving line of the second chip C2 is positioned on the upper surface of the substrate, so that the length of the signal transmission line Minimize signal loss.

The display panel 30 may include a lower substrate and an upper substrate.

When the display panel is a liquid crystal display panel, the display panel 30 is a lower substrate including a thin film transistor (TFT) and a pixel electrode and an upper substrate including color filter layers are bonded to each other with the liquid crystal layer interposed therebetween. It can be formed into a structure.

In addition, the display panel 30 has a thin film transistor, a color filter, and a black matrix formed on the lower substrate, and the upper substrate is bonded to the lower substrate with the liquid crystal layer interposed therebetween. It may be a panel.

In addition, when the display panel 30 is a liquid crystal display panel, the display panel 30 may further include a backlight unit configured to provide light under the display panel 30.

When the display panel 30 is an organic light emitting display panel, the display panel 30 includes a self-light emitting device that does not require a separate light source. The display panel 30 has a thin film transistor formed on a lower substrate, and an organic light emitting element in contact with the thin film transistor is formed. The organic light emitting diode may include an anode, a cathode, and an organic light emitting layer formed between the anode and the cathode. In addition, the organic light emitting device may further include an upper substrate serving as an encapsulation substrate / barrier substrate for encapsulation. The upper substrate may be rigid or flexible.

In addition, the cover window 70 may further include a polarizing plate. The polarizing plate may be a linear polarizing plate or an external light reflection preventing polarizing plate. For example, when the display panel 30 is a liquid crystal display panel, the polarizing plate may be a linear polarizing plate. In addition, when the display panel 30 is an organic light emitting display panel, the polarizing plate may be an anti-reflective polarizing plate.

Due to the presence of such layers between the fingerprint recognition module and the hand of the person providing the fingerprint, the received signal may be weak. Therefore, the signal receiving line of the fingerprint recognition module is located on the upper surface of the substrate, thereby minimizing the length of the signal transmission line, thereby minimizing the reception signal loss.

Meanwhile, the third chip C3 is electrically connected to the sixth inner lead pattern part I6 through the third connection part 170. The sixth inner lead pattern part I6 may be electrically connected to the fourth inner lead pattern part I4 or the fourth inner lead pattern part I5.

The fingerprint recognition module 100 including the flexible circuit board for the chip on film according to the embodiment may implement a conductive pattern part having a fine pitch on both surfaces thereof, and thus may be suitable for an electronic device having a high resolution display unit.

In addition, since the fingerprint recognition module 100 including the flexible circuit board for the chip-on-film according to the embodiment is flexible, small in size, and thin in thickness, it can be used in various electronic devices.

For example, referring to FIG. 13, the fingerprint recognition module 100 including the flexible circuit board for the chip on film according to the embodiment may reduce the bezel and thus may be used for the edge display.

For example, referring to FIG. 14, the fingerprint recognition module 100 including the flexible circuit board for the chip on film according to the embodiment may be included in a flexible flexible electronic device. Therefore, the touch device device including the same may be a flexible touch device device. Thus, the user can bend or bend by hand. The flexible touch window may be applied to a wearable touch or the like.

For example, referring to FIG. 15, the fingerprint recognition module 100 including the flexible circuit board for the chip on film according to the embodiment may be applied to various electronic devices to which the foldable display device is applied. 15A to 15C, the foldable cover window may be folded in the foldable display device. The foldable display device may be included in various portable electronic products. In detail, the foldable display device may be included in a mobile terminal (mobile phone), a notebook computer (portable computer), and the like. As a result, the display area of the portable electronic product can be increased, and the size of the device can be reduced during storage or movement, thereby improving portability. Therefore, the convenience of the user of the portable electronic product can be improved. However, the embodiment is not limited thereto, and the foldable display device may be used in various electronic products.

Referring to FIG. 15A, the foldable display device may include one folded area in the screen area. For example, the foldable display device may have a C shape in a folded form. That is, one end of the foldable display device and the other end opposite to the one end may be stacked on each other. In this case, the one end and the other end may be disposed close to each other. For example, the one end and the other end may be disposed facing each other.

Referring to FIG. 15B, the foldable display device may include two folded areas in the screen area. For example, the foldable display device may have a G shape in a folded form. That is, the foldable display device may be folded as one end and the other end opposite to the one end are folded in directions corresponding to each other. In this case, the one end and the other end may be spaced apart from each other. For example, the one end and the other end may be arranged parallel to each other.

Referring to FIG. 15C, the foldable display device may include two folded areas in the screen area. For example, the foldable display device may have an S shape in a folded form. That is, one end of the foldable display device and the other end opposite to the one end may be folded in different directions. In this case, the one end and the other end may be spaced apart from each other. For example, the one end and the other end may be arranged parallel to each other.

In addition, although not shown in the drawings, the fingerprint recognition module 100 including the flexible circuit board for the chip-on-film according to the embodiment may be applied to the rollable display.

Referring to FIG. 16, the fingerprint recognition module 100 including the flexible circuit board for the chip on film according to the embodiment may be included in various wearable touch devices including a curved display. Therefore, the electronic device including the fingerprint recognition module 100 including the flexible circuit board for the chip-on-film according to the embodiment can be made slim, small or light.

Referring to FIG. 17, the fingerprint recognition module 100 including the flexible circuit board for the chip on film according to the embodiment may be used in various electronic devices having display parts such as a TV, a monitor, and a notebook.

However, the embodiment is not limited thereto, and the fingerprint recognition module 100 including the flexible circuit board for the chip on film according to the embodiment may be used in various electronic devices having a flat or curved display portion.

Features, structures, effects, and the like described in the above embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. In addition, the features, structures, effects, and the like illustrated in each embodiment may be combined or modified with respect to other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be interpreted that the contents related to such a combination and modification are included in the scope of the present invention.

In addition, the above description has been made with reference to the embodiments, which are merely examples and are not intended to limit the present invention, and those skilled in the art to which the present invention pertains may be illustrated in the above without departing from the essential characteristics of the present embodiment. It will be appreciated that various modifications and applications are possible. For example, each component specifically shown in the embodiments may be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

10: first printed circuit board
20: second printed circuit board
C1: first chip
C2: second chip
30: display panel
40: mainboard
50: adhesive layer
60: battery
100: fingerprint recognition module
110: substrate
120: wiring pattern layer
130: plating layer
140: protective layer
CP: conductive pattern
PP: protector
OA1, OA2, OA3, OA4, OA5: open area
V1, V2, V3: Via Hole
OP: outer lead pattern part
I1, I2, I3, I4, I5, I6: inner lead pattern portion
150: first connection part
160: second connection portion
170: third connection part
180: adhesive layer
190: protective pattern portion

Claims (14)

Board;
A conductive pattern portion disposed on the substrate;
A protective layer partially disposed in one region on the conductive pattern portion;
A first connecting portion disposed on the first conductive pattern portion exposed through the first open area of the protective layer;
A first chip disposed on the first connection portion; And
A protective pattern portion disposed on the substrate exposed through the first open region of the protective layer,
The first chip,
Includes a fingerprint sensor,
The protective pattern portion,
Disposed in a vibration space of the fingerprint recognition sensor between an upper surface of the substrate and the first chip.
Fingerprint Recognition Module. The method of claim 1,
The height of the protective pattern portion,
Lower than the height of the first conductive pattern portion
Fingerprint Recognition Module. The method of claim 2,
The height of the first conductive pattern portion,
Satisfies a range of 7 μm to 13 μm,
The height of the protective pattern portion,
Satisfying the range of 6 μm to 11 μm
Fingerprint Recognition Module. The method of claim 1,
The protective pattern portion,
A first protective pattern portion disposed adjacent to the first conductive pattern portion and disposed in an outer region of the vibration space;
And a second protective pattern part disposed in the central area of the vibration space except for the outer area of the vibration space.
Fingerprint identification module The method of claim 4, wherein
The horizontal cross-sectional shape of the first protective pattern portion is
Different from the horizontal cross-sectional shape of the second protective pattern portion
Fingerprint Recognition Module. The method of claim 4, wherein
A through hole formed in a region between the first protective pattern portion and the second protective pattern portion and communicating with the vibration space;
Fingerprint Recognition Module. The method of claim 1,
A second connecting portion disposed on the second conductive pattern portion exposed through the second open area of the protective layer; And
Further comprising a second chip disposed on the second connecting portion,
The second chip,
Including application specific integrated circuits
Fingerprint Recognition Module. The method of claim 7, wherein
The substrate,
A first non-bending region located at one end and arranged with the first chip,
A second non-bending region positioned on the other end opposite to the one end and on which the second chip is disposed;
A bending region located between the first and second non-bending regions,
An adhesive layer is disposed between the first non-bent region and the second non-bent region,
The first non-bending area,
It is disposed facing the second non-bent region around the adhesive layer.
Fingerprint Recognition Module. The method of claim 8,
The substrate,
An upper part positioned above the adhesive layer, the upper part including the first non-bending area and a part of the bending area;
Located below the adhesive layer, and includes a lower part including the second non-bending area and the remaining part of the bending area,
The ratio of the upper surface area of the first chip and the upper surface area of the upper part is
Less than 1: 2
Fingerprint Recognition Module. The method of claim 1,
The first conductive pattern portion,
It includes a plurality of grooves recessed in a predetermined depth in the lower surface in the upper surface, spaced apart from each other, the first connecting portion is disposed,
The upper surface of the first conductive pattern portion,
A first region facing the vibration space around a center and a second region except the first region,
The first aperture ratio due to the plurality of grooves in the first region is
Greater than a second aperture ratio due to the plurality of grooves in the second region
Fingerprint Recognition Module. The method of claim 7, wherein
At least one third chip disposed on the conductive pattern portion exposed through the third open region of the protective layer,
The at least one third chip,
At least one of a diode chip, MLCC chip, BGA chip, chip capacitor,
An interval of an area between the second open area and the third open area is
Less than an interval of an area between the first open area and the second open area
Fingerprint Recognition Module. The method according to claim 1, wherein
The protective pattern portion,
Containing photoresist
Fingerprint Recognition Module. Board;
A conductive pattern portion disposed on the substrate;
A protective layer partially disposed in one region on the conductive pattern portion;
A first connecting portion disposed on the first conductive pattern portion exposed through the first open area of the protective layer;
A first chip disposed on the first connection portion;
A second connecting portion disposed on the second conductive pattern portion exposed through the second open area of the protective layer;
A second chip disposed on the second connection portion; And
A protective pattern portion disposed on the substrate exposed through the first open region of the protective layer,
The first chip,
Includes a fingerprint sensor,
The second chip,
Includes application specific integrated circuits,
The substrate,
A first non-bending region located at one end,
A second non-bending area positioned at the other end opposite to the one end;
A bending region located between the first and second non-bending regions,
The first open area is located on the first non-bended area,
The second open area is located on the second non-bent area,
The protective pattern portion,
Disposed in a vibration space of the fingerprint sensor between an upper surface of the substrate and the first chip,
The height of the protective pattern portion,
A fingerprint recognition module lower than a height of the first conductive pattern portion;
A display unit attached to the first chip; And
A main board connected to the conductive pattern part disposed on the second non-bending area of the fingerprint recognition module;
Electronic device. The method of claim 13,
The display unit,
Display panel; And
A cover window positioned on the display panel;
The first chip is attached to a bottom surface of the display panel or a bottom surface of the cover window.
Electronic device.

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