KR20190054500A - Hybrid flexible circuit board and chip package comprising the same - Google Patents

Abstract

An integrated flexible printed circuit board according to an embodiment comprises: a first insulating layer including a first region and a second region; a first circuit pattern layer disposed on the first region and the second region of the first insulating layer; a first protective layer disposed on the first region of the first insulating layer and including at least one open region; a second insulating layer disposed on the second region of the first insulating layer; a second circuit pattern layer disposed on the second insulating layer; and a second protective layer disposed on the second insulating layer and including at least one open region. The first circuit pattern layer includes a plurality of first conductive patterns disposed on the first region of the first insulating layer and a plurality of second conductive patterns disposed on the second region of the first insulating layer. The first conductive pattern has the width smaller than the second conductive pattern. Different types of first and second chips can be mounted on one substrate, thereby improving reliability.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a flexible circuit board,

Embodiments relate to an integrated flexible circuit board and a chip package including the same, and an electronic device including the same.

In detail, the integrated flexible circuit board includes a flexible circuit board for a chip-on-film connected to a display panel, a light-flexible printed circuit board connected to the main board, and a chip package including the integrated flexible circuit board Lt; / RTI >

Recently, a variety of electronic products are becoming thinner, smaller, and lighter. Accordingly, various studies for mounting a semiconductor chip at a high density in a narrow region of an electronic device have been carried out.

Among them, since a COF (Chip On Film) method uses a flexible substrate, it can be applied to both a flat panel display and a flexible display. That is, the COF method is attracting attention because it can be applied to various wearable electronic devices. Further, since the COF method can realize a fine pitch, it can be used to realize a display of high resolution (QHD) as the number of pixels increases.

COF (Chip On Film) is a method of mounting a semiconductor chip on a flexible circuit board in the form of a thin film. For example, the semiconductor chip may be an integrated circuit (IC) chip or a large scale integrated circuit (LSI) chip.

However, the COF flexible circuit board can not be directly connected between the display panel and the main board.

That is, at least two printed circuit boards are required between the display panel and the main board.

An electronic device having a display portion has a problem in that the thickness thereof increases as a plurality of printed circuit boards are required. In addition, the size of a plurality of printed circuit boards may be a limitation to miniaturization of electronic devices. In addition, poor bonding of a plurality of printed circuit boards may lower the reliability of the electronic device.

Therefore, a new flexible circuit board capable of solving such a problem is required.

An embodiment provides an integrated flexible circuit board having a novel structure in which a flexible circuit board for a chip-on-film connected to a display panel and a printed circuit board connected to a main board are integrated into one, a chip package including the integrated flexible circuit board, ≪ / RTI >

It is to be understood that the technical objectives to be achieved by the embodiments are not limited to the technical matters mentioned above and that other technical subjects not mentioned are apparent to those skilled in the art to which the embodiments proposed from the following description belong, It can be understood.

An integrated flexible printed circuit board according to an embodiment includes a first insulation layer including a first region and a second region; A first circuit pattern layer disposed on the first region and the second region of the first insulating layer; A first passivation layer disposed on the first region of the first insulating layer and including at least one open region; A second insulating layer disposed on the second region of the first insulating layer; A second circuit pattern layer disposed on the second insulating layer; And a second protective layer disposed on the second insulating layer and including at least one open region, wherein the first circuit pattern layer includes a plurality of first insulating layers disposed on the first region of the first insulating layer A first conductive pattern and a plurality of second conductive patterns disposed on the second region of the first insulating layer, wherein the first conductive pattern has a smaller width than the second conductive pattern.

Further comprising at least one first via passing through the second insulating layer, wherein the second conductive pattern comprises a second-1 conductive pattern in direct contact with the via, and a second-1 conductive pattern in direct contact with the via, And the second-1 conductive pattern has a greater width than the first conductive pattern.

The 2-2 conductive pattern is the same as either the width of the first conductive pattern or the width of the 2-1 conductive pattern.

The second-2 conductive pattern is larger than the width of the first conductive pattern and has a width smaller than the width of the second-1 conductive pattern.

The first conductive pattern may include a first conductive pattern disposed on the first open region of the first protective layer and on which the first chip is mounted and a second conductive pattern on the second open region of the first protective layer, And a 1-2 conductive pattern connected to the display panel, wherein the 1-1 conductive pattern has a smaller width than the 1-2 conductive pattern.

The second circuit pattern layer may include a third conductive pattern disposed on a third open region of the second protective layer and having a second chip different from the first chip mounted thereon, And a fourth conductive pattern disposed on the fourth open area and connected to the main board.

A first plating layer disposed on the first conductive pattern; And a second plating layer disposed on the third and fourth conductive patterns.

The first and second plating layers may be formed of the same metal material selected from Sn, Au, Ag, Ni, and Ni-Cr.

The first and second plating layers include different metal materials, and the different metal materials include Au / Sn, Ag / Sn, Ni / (Sn), nickel-chromium alloy (Ni-Cr) / tin (Sn), nickel (Ni) / chromium (Cr), gold (Au) / silver (Ag) Nickel-chromium alloy (Ni-Cr) / gold (Au).

The first circuit pattern layer may be disposed on the upper surface and the lower surface of the first insulating layer and may extend through the first insulating layer and may be disposed on the upper surface and the lower surface of the first insulating layer, And a second via connecting the pattern layer, wherein the second via has a smaller width than the first via.

The first region includes a first outer region of the first insulating layer and a second outer region opposite to the first outer region, and the first 1-1 conductive pattern and the 1-2 first conductive pattern Wherein the first conductive pattern is disposed on the second outer area and is exposed through a third open area of the first protective layer, and the first conductive pattern is disposed on the first outer area, 3 < / RTI > conductive pattern.

According to another aspect of the present invention, there is provided a chip package including: a first insulating layer including a first region and a second region; A first circuit pattern layer disposed on the first region and the second region of the first insulating layer; A first passivation layer disposed on the first region of the first insulating layer and including at least one open region; A second insulating layer disposed on the second region of the first insulating layer; A second circuit pattern layer disposed on the second insulating layer; An integrated flexible printed circuit board disposed on the second insulating layer and including a second protective layer including at least one open area; A first chip disposed on a first open region of the first passivation layer; And a second chip disposed on a second open region of the second passivation layer and different from the first chip, wherein the first circuit pattern layer is formed on the first region of the first insulation layer And a plurality of second conductive patterns disposed on the second region of the first insulating layer, wherein the first conductive pattern has a width smaller than the width of the second conductive pattern I have.

The first conductive pattern may have a first connection portion, the second circuit pattern layer may have a second connection portion, the first chip may be disposed on the first connection portion, 2 connection.

The first chip may be a drive IC chip, and the second chip may be at least one of a diode chip, a power IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor.

An electronic device according to an embodiment includes a first insulating layer including a first region and a second region; A first circuit pattern layer disposed on the first region and the second region of the first insulating layer; A first passivation layer disposed on the first region of the first insulating layer and including at least one open region; A second insulating layer disposed on the second region of the first insulating layer; A second circuit pattern layer disposed on the second insulating layer; An integrated flexible printed circuit board disposed on the second insulating layer and including a second protective layer including at least one open area; A display panel connected to one end of the integrated flexible printed circuit board; And a main board connected to the other end of the integrated flexible printed circuit board, wherein the first circuit pattern layer includes: a plurality of first conductive patterns disposed on the first region of the first insulation layer; And a plurality of second conductive patterns disposed on the second region of the insulating layer, wherein the first conductive pattern has a smaller width than the second conductive pattern.

The first conductive pattern may include a first conductive pattern disposed on the first open region of the first protective layer and on which the first chip is mounted and a second conductive pattern on the second open region of the first protective layer, And a second conductive pattern connected to the display panel, wherein the second circuit pattern layer is disposed on a third open region of the second passivation layer, And a fourth conductive pattern disposed on the fourth open region of the second passivation layer and connected to the main board.

In addition, the first region may include a first outer region of the first insulating layer and a second outer region opposite to the first outer region, and the first conductive pattern may be disposed on the first outer region A first conductive pattern on which a first chip is mounted; a first conductive pattern disposed on the first outer conductive area and connected to the display panel; and a second conductive pattern disposed on the second outer conductive area, And a third conductive pattern connected to the main board.

The integrated flexible printed circuit board according to the embodiment can mount different types of first chip and second chip on one substrate, thereby providing an integrated flexible circuit board chip package with improved reliability.

In addition, one integrated flexible circuit board according to the embodiment can directly connect the display panel and the main board. Accordingly, the size and thickness of the flexible circuit board for transmitting signals generated from the display panel to the main board can be reduced.

Accordingly, the integrated flexible circuit board according to the embodiment, and the chip package including the same, and the electronic device including the same can expand the space and / or the battery space of other parts.

In addition, since the integrated flexible printed circuit board according to the embodiment does not require connection of a plurality of printed circuit boards between the main board and the display panel in the electronic device, the convenience of the process and the reliability of the electrical connection can be improved.

Accordingly, the integrated flexible printed circuit board, the chip package including the integrated flexible circuit board, and the electronic device including the integrated flexible circuit board according to the embodiments may be suitable for an electronic device having a high-resolution display portion.

1A is a cross-sectional view of an electronic device having a display portion including a conventional printed circuit board.
FIG. 1B is a cross-sectional view of the printed circuit board according to FIG. 1A in a bent form. FIG.
1C is a plan view of the printed circuit board according to FIG. 1A in a bent form.
2A is a cross-sectional view of an electronic device having a display portion including an integrated flexible circuit board according to an embodiment.
FIG. 2B is a cross-sectional view of the integrated flexible printed circuit board according to FIG. 2A in a bent form. FIG.
FIG. 2C is a sectional view of the display portion shown in FIG. 2A in a folded form. FIG.
FIG. 2D is a plan view of the integrated flexible circuit board according to FIG. 2A in a bent form. FIG.
3 is a cross-sectional view of an integrated flexible printed circuit board according to a first embodiment of the present invention.
4A is an enlarged cross-sectional view of the soft region FA of FIG.
4B is an enlarged cross-sectional view of the hard area RA of FIG.
5A to 5J are cross-sectional views showing the manufacturing method of the integrated flexible circuit board 300 shown in FIG. 3 in the order of process.
FIG. 6 is a cross-sectional view of an integrated flexible printed circuit board according to a second embodiment of the present invention, and FIG. 7 is a simplified plan view of the integrated flexible printed circuit board shown in FIG.
8 is a cross-sectional view of an integrated flexible printed circuit board according to a third embodiment of the present invention.
9A is a cross-sectional view of an integrated flexible printed circuit board according to a fourth embodiment of the present invention.
FIG. 9B is a cross-sectional view showing a modified example of the integrated flexible circuit board shown in FIG. 9A.
9C is a cross-sectional view showing another modified example of the integrated flexible circuit board shown in FIG. 9A.
10 is a cross-sectional view of an integrated flexible printed circuit board according to a fifth embodiment of the present invention.
11 to 15 are views of various electronic devices including an integrated flexible circuit board.

In the description of the embodiments, it is to be understood that each layer (film), area, pattern or structure may be referred to as being "on" or "under / under" Quot; includes all that is formed directly or through another layer. The criteria for top / bottom or bottom / bottom of each layer are described with reference to the drawings.

Also, when a part is referred to as being "connected" to another part, it includes not only a case of being "directly connected" but also a case of being "indirectly connected" with another member in between. Also, when an element is referred to as " comprising ", it means that it can include other elements, not excluding other elements unless specifically stated otherwise.

The thickness or the size of each layer (film), region, pattern or structure in the drawings may be modified for clarity and convenience of explanation, and thus does not entirely reflect the actual size.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

A printed circuit board according to a comparative example will be described with reference to Figs. 1A to 1C.

An electronic device having a display portion requires at least two printed circuit boards in order to transmit signals of the display panel to the main board.

The electronic device including the display unit according to the comparative example may have at least two printed circuit boards.

The electronic device including the display unit according to the comparative example may include the first printed circuit board 10 and the second printed circuit board 20. [

The first printed circuit board 10 may be a flexible printed circuit board. In detail, the first printed circuit board 10 may be a flexible printed circuit board for a chip on film (COF). The first printed circuit board 10 may be a COF flexible printed circuit board on which the first chip C1 is mounted. More specifically, the first printed circuit board 10 may be a flexible printed circuit board for a COF for disposing a drive IC chip.

The second printed circuit board 20 may be a printed circuit board. In detail, the second printed circuit board 20 may be a printed circuit board for disposing a second chip C2 of a different kind from the first chip C1. Here, the second chip C2 may be a device other than a drive IC chip, and may be electrically connected to a printed circuit board such as another chip, a semiconductor device, or a socket except a drive IC chip May refer to the various chips being deployed. The second printed circuit board 20 may be a printed circuit board for disposing a plurality of second chips C2. For example, the second printed circuit board 20 may be a printed circuit board for disposing a plurality of second chips C2a and C2b of different kinds.

Since the first and second printed circuit boards are required between the display panel and the main board, the electronic device having the display unit according to the comparative example can increase the overall thickness of the electronic device. In detail, since the electronic device having the display portion according to the comparative example requires the first and second printed circuit boards stacked on and under, the overall thickness of the electronic device can be increased.

The first printed circuit board 10 and the second printed circuit board 20 may be formed in different processes. For example, the first printed circuit board 10 may be manufactured by a roll-to-roll process. The second printed circuit board 20 may be manufactured by a sheet method.

Different types of chips may be disposed on the first printed circuit board 10 and the second printed circuit board 20 and pitches of the conductive pattern portions to be connected to the respective chips may be different from each other. For example, the pitch of the conductive pattern portions disposed on the second printed circuit board 20 may be greater than the pitch of the conductive pattern portions disposed on the first printed circuit board 10. For example, the pitch of the conductive pattern portions disposed on the second printed circuit board 20 is 100 탆 or more, the pitch of the conductive pattern portions disposed on the first printed circuit board 10, May be less than 100 mu m.

In detail, the first printed circuit board 10 having a conductive pattern portion arranged at a fine pitch can be manufactured through a roll-to-roll process, which is process efficient and can reduce the process cost. On the other hand, since the second printed circuit board 20 having the conductive pattern portion disposed at intervals of 100 mu m or more is difficult to be handled by the roll-to-roll process, it is common to use the sheet process.

Since the first and second printed circuit boards according to the comparative example are formed by different processes, the process efficiency may be lowered.

In addition, since the chip package including the flexible circuit board according to the comparative example has a difficulty in arranging different types of chips on one substrate, separate first and second printed circuit boards are required.

In addition, the chip package including the flexible circuit board according to the comparative example has a problem that it is difficult to connect different kinds of chips on one substrate.

That is, the first and second printed circuit boards may be disposed between the conventional display panel and the main board.

The first printed circuit board 10 is connected to the display panel 30 to control, process, or transfer the R, G, and B signals generated from the display panel 30, And the second printed circuit board 20 may be connected to the main board 40. The second printed circuit board 20 may be connected to the second printed circuit board 20,

One end of the first printed circuit board 10 may be connected to the display panel 30. The display panel 30 may be connected to the first printed circuit board 10 by an adhesive layer 50.

The other end opposite to the one end of the first printed circuit board 10 may be connected to the second printed circuit board 20. The first printed circuit board 10 may be connected to the second printed circuit board 20 by the adhesive layer 50.

One end of the second printed circuit board 20 is connected to the first printed circuit board 10 and the other end opposite to the one end of the second printed circuit board 20 is connected to the main board 40 have. The second printed circuit board (20) may be connected to the main board (40) by the adhesive layer (50).

The electronic device having the display unit according to the comparative example is disposed between the display panel 30 and the first printed circuit board 10 and between the first printed circuit board 10 and the second printed circuit board 20 A separate adhesive layer 50 may be required between the second printed circuit board 20 and the main board 40, respectively. That is, since the electronic device having the display unit according to the comparative example requires a plurality of adhesive layers, the reliability of the electronic device may deteriorate due to poor connection of the adhesive layer. In other words, since the electronic device having the display unit according to the comparative example requires a plurality of adhesive layers 50, the signal performance can be reduced by the noise generated in the adhesive layer. In addition, the adhesive layer disposed between the first printed circuit board 10 and the second printed circuit board 20 connected in an up-and-down direction can increase the thickness of the electronic device.

1B and 1C, a first printed circuit board 10, a second printed circuit board 20, a display panel 30, and a main board 40 housed in an electronic device according to a comparative example Explain.

FIG. 1B is a cross-sectional view of the printed circuit board according to FIG. 1A in a bent form, and FIG. 1C is a plan view of the lower surface of FIG. 1B.

The display panel 30 and the main board 40 may be disposed to face each other. A first printed circuit board 10 including a bending area may be disposed between the display panel 30 and the main board 40 which are disposed facing each other.

The first printed circuit board 10 is bent in one area, and the first chip C1 may be disposed in a region where the first printed circuit board 10 is not bent.

The second printed circuit board 20 may be disposed facing the display panel 30. And the second chip C2 may be disposed in an unbending region of the second printed circuit board 20. [

Referring to FIG. 1C, since a plurality of substrates are required in the comparative example, the length L1 in one direction is the sum of the lengths of the first printed circuit board 10 and the second printed circuit board 20 . The length L1 of the first printed circuit board 10 and the second printed circuit board 20 in one direction is determined by the length of the short side of the first printed circuit board 10 and the length of the first printed circuit board 10 20). ≪ / RTI > For example, the length L1 of the first printed circuit board 10 and the second printed circuit board 20 in one direction may be 30 mm to 40 mm. However, the length L1 of the first printed circuit board 10 and the second printed circuit board 20 in one direction may vary according to the type of chip to be mounted and the type of the electronic device.

As the electronic device according to the comparative example requires a plurality of printed circuit boards, the space for mounting other components or the space for arranging the battery 60 can be reduced.

2. Description of the Related Art [0002] In recent years, electronic devices such as smart phones have been added with various functions to enhance user convenience and security. For example, electronic devices such as smart phones and smart watches are equipped with a plurality of camera modules (dual camera module, dual camera module) or components having various functions such as iris recognition and virtual reality (VR) Has been added. Accordingly, it is important to secure a space for mounting additional components.

In addition, various electronic devices including a wearable device are required to have an expanded battery space for the convenience of the user.

Therefore, replacing a plurality of printed circuit boards used in existing electronic devices with a single printed circuit board, the importance of securing a space for mounting new components or securing a space for enlarging the battery size becomes important.

In the electronic device according to the comparative example, the first chip and the second chip of different kinds may be disposed on the first printed circuit board 10 and the second printed circuit board 30, respectively. The thickness of the adhesive layer 50 between the first printed circuit board 10 and the second printed circuit board 30 and the thickness of the second printed circuit board 30 increase the thickness of the electronic device .

In addition, there is a problem that the space for mounting the battery space or other parts is reduced by the size of the second printed circuit board 30.

In addition, defective junctions of the first and second printed circuit boards have a problem of lowering the reliability of the electronic device.

In order to solve this problem, the embodiment can provide an integrated flexible circuit board having a novel structure capable of mounting a plurality of chips on one substrate, a chip package including the same, and an electronic device including the same. The same reference numerals in the embodiment and the comparative example denote the same components, and the description overlapping with the comparative example described above is excluded.

Referring to Figs. 2A to 2D, an electronic device including an integrated flexible circuit board according to an embodiment will be described.

The electronic device according to the embodiment may use one printed circuit board to transmit signals of the display panel to the main board. The printed circuit board included in the electronic device including the display unit according to the embodiment may be one flexible printed circuit board. Accordingly, the integrated flexible printed circuit board 300 according to the embodiment is bended between the display part and the main board facing each other to connect the display part and the main board.

In detail, the integrated flexible printed circuit board 300 according to the embodiment may be a single substrate for arranging a plurality of chips of different kinds.

Integrated Flexible Circuit Substrate 300 According to the Embodiment The flexible circuit board 100 may be a substrate for disposing first and second chips c1 and c2 of different kinds.

The electronic device having the display unit according to the embodiment can reduce the overall thickness of the electronic device because only one integrated flexible circuit board 300 is required between the display panel and the main board.

In addition, the embodiment can omit the adhesive layer 50 between the first printed circuit board and the second printed circuit board included in the comparative example, so that the chip package including the integrated flexible circuit board 300 and the electronic package The overall thickness of the device can be reduced.

In addition, the embodiment can omit the adhesive layer 50 between the first printed circuit board and the second printed circuit board, thereby solving the problem caused by poor adhesion, thereby improving the reliability of the electronic device.

Further, since the step of adhering a plurality of printed circuit boards can be omitted, the process efficiency can be increased and the process cost can be reduced.

In addition, by replacing the substrate that has been managed as a separate process with one process, the process efficiency and product yield can be improved.

The integrated flexible printed circuit board 300 according to an embodiment may include a bent region and a non-bent region. The flexible circuit board 100 for a chip on film according to the embodiment includes the bending regions and can connect the display panel 30 and the main board 40 which are disposed facing each other .

The non-bending region of the integrated flexible printed circuit board 300 according to the embodiment may be disposed facing the display panel 30 with respect to each other. The first chip C1 and the second chip C2 may be disposed on the non-bending region of the integrated flexible circuit board 300 according to the embodiment. Accordingly, the integrated flexible circuit board 300 according to the embodiment can stably mount the first chip c1 and the second chip c2.

The display panel 30 according to the embodiment may include a bending region and a non-bending region. The display panel 30 may include a first substrate portion 31 and a second substrate portion 32. The second substrate portion 32 includes a first region disposed on a lower surface of the first substrate portion 31 and a second region extending from the first region and being bent at a second Region. ≪ / RTI >

An adhesive layer 50 is disposed under the second region of the second substrate portion 32 and an integrated flexible printed circuit board 300 according to an embodiment of the present invention is disposed below the adhesive layer 50 .

FIG. 2D is a plan view of the bottom of FIG. 2B.

Referring to FIG. 2D, since the embodiment requires one substrate, the length L2 in one direction may be the length of one substrate. The length L2 in one direction of the integrated flexible printed circuit board 300 according to the embodiment may be the length of the short side of the integrated flexible printed circuit board 300 according to the embodiment. For example, the length L2 in one direction of the integrated flexible printed circuit board 300 according to the embodiment may be 10 mm to 50 mm. For example, the length L2 in one direction of the integrated flexible printed circuit board 300 according to the embodiment may be 10 mm to 30 mm. For example, the length L2 in one direction of the integrated flexible printed circuit board 300 according to the embodiment may be 15 mm to 25 mm. However, the embodiment is not limited thereto, and it is of course possible to design various sizes according to the type and / or number of chips to be arranged and the type of electronic device.

The length L2 in one direction of the integrated flexible printed circuit board 300 according to the embodiment is 50% to 70% of the length L1 in one direction of the plurality of first and second printed circuit boards according to the comparative example, Level length. ≪ / RTI > For example, the length L2 in one direction of the integrated flexible printed circuit board 300 according to the embodiment may be equal to or greater than the length L2 of the first and second printed circuit boards 100, % ≪ / RTI > to 150%. The length L2 in one direction of the integrated flexible printed circuit board 300 according to the embodiment is 60% to 70% of the length L1 in one direction of the first and second printed circuit boards according to the comparative example, Level length. ≪ / RTI >

Accordingly, the embodiment can reduce the size of the chip package including the integrated flexible circuit board 300 in the electronic device, so that the space for disposing the battery 60 can be enlarged. In addition, the chip package including the integrated flexible circuit board 300 according to the embodiment can be reduced in planarity, and space for mounting other components can be secured.

Hereinafter, an integrated flexible printed circuit board and its chip package according to an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 3 is a cross-sectional view of the integrated flexible circuit board according to the first embodiment of the present invention, FIG. 4A is an enlarged cross-sectional view of the soft region FA of FIG. 3, Fig.

3, 4A and 4B, the integrated flexible printed circuit board 300 includes a flexible circuit board 100 for a chip-on film, a laminated board 200 disposed on the chip-on-film flexible circuit board 100, ).

Here, the chip-on-film flexible circuit board 100 and the laminate board 200 may have different thicknesses.

The thickness of the chip-on-film flexible circuit board 100 may be smaller than the thickness of the laminated board 200.

For example, the chip-on-film flexible printed circuit board 100 may have a thickness of about 10 μm to 100 μm. The laminated substrate 200 may have a thickness of about 100 μm to 300 μm. For example, the total thickness t1 of the integrated soft circuit board including the chip-on-film flexible circuit board 100 and the laminate board 200 may be 100 to 400 mu m.

Preferably, the integrated flexible printed circuit board 300 is divided into a first area and a second area, and the laminated board 200 is stacked on the upper and lower surfaces of the second area of the integrated flexible printed circuit board 300.

The chip-on-film flexible circuit board 100 includes a first insulation layer 110, a first circuit pattern layer 120 disposed on one side of the first insulation layer 110, a first circuit pattern layer 120, And a first passivation layer 140 disposed on the first circuit pattern layer 120 and / or the first plating layer 130. The first plating layer 130 may be disposed on the first circuit pattern layer 120 and /

The chip-on-film flexible circuit board 100 included in the integrated flexible circuit board 300 in the first embodiment of the present invention may be a flexible circuit board for chip-on-film having an electrode pattern on one side.

The first insulating layer 110 may be a supporting substrate for supporting the first circuit pattern layer 120, the first plating layer 130, and the first passivation layer 140.

The first insulating layer 110 may include a region other than the bending region and the bending region. That is, the substrate 110 may include a bending region where bending is performed and a non-bending region other than the bending region.

The first insulating layer 110 may be a flexible substrate. Accordingly, the first insulating layer 110 may be partially bendable. That is, the first insulating layer 110 may include a soft plastic. For example, the first insulating layer 110 may be a polyimide (PI) substrate. However, the embodiment is not limited thereto, and may be a substrate made of a polymer material such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN). Accordingly, the chip-on-film flexible circuit board 100 including the first insulation layer 110 can be used in various electronic devices having a curved display device. For example, since the flexible circuit board for a chip-on film including the first insulating layer has excellent flexibility, it can be suitable for mounting a semiconductor chip of a wearable electronic device. In particular, embodiments may be suitable for electronic devices including a curved display.

The first insulating layer 110 may be an insulating substrate. That is, the first insulating layer 110 may be an insulating substrate supporting various wiring patterns.

The first insulating layer 110 may have a thickness of about 20 탆 to about 100 탆. For example, the first insulating layer 110 may have a thickness of 25 to 50 탆. For example, the first insulating layer 100 may have a thickness of 30 to 40 탆. When the thickness of the first insulating layer 100 is more than 100 mu m, the overall thickness of the flexible circuit board may increase. If the thickness of the first insulating layer 100 is less than 20 mu m, it may be difficult to dispose the first chip C1. When the thickness of the first insulating layer 110 is less than 20 탆, the first insulating layer 110 may be vulnerable to heat / pressure during the step of mounting the chip, It may be difficult to arrange the first chip C1. Wiring may be disposed on the first insulating layer 110. [ The wiring may be a plurality of patterned wirings. For example, the plurality of wirings on the first insulating layer 110 may be spaced apart from each other. That is, the first circuit pattern layer 120 may be disposed on one side of the substrate 110.

The area of the first insulating layer 110 may be larger than the area of the first circuit pattern layer 120. In detail, the planar area of the first insulation layer 110 may be larger than the planar area of the first circuit pattern layer 120. That is, the first circuit pattern layer 120 may be partially disposed on the first insulating layer 110. For example, the lower surface of the first circuit pattern layer 120 may be in contact with the first insulating layer 110, and the first insulating layer 110 may be exposed between the plurality of wirings. The first circuit pattern layer 120 may include a conductive material.

For example, the first circuit pattern layer 120 may include a metal material having excellent electrical conductivity. More specifically, the first circuit pattern layer 120 may include copper (Cu). However, the embodiment is not limited thereto, and copper, aluminum, chromium, nickel, silver and molybdenum may be used. And may include at least one of gold (Au), titanium (Ti), and alloys thereof.

The first circuit pattern layer 120 may be arranged to have a thickness of 1 탆 to 15 탆. For example, the first circuit pattern layer 120 may be arranged to have a thickness of 1 탆 to 10 탆. For example, the first circuit pattern layer 120 may have a thickness of 2 to 10 탆.

If the thickness of the first circuit pattern layer 120 is less than 1 mu m, the resistance of the first circuit pattern layer may increase. When the thickness of the first circuit pattern layer 120 is more than 10 mu m, it may be difficult to realize a fine pattern.

A first plating layer 130 may be disposed on the first circuit pattern layer 120. The first plating layer 130 may include a plurality of plating layers. In other words, the first plating layer 130 may include a 1-1 plating layer disposed on the first circuit pattern layer 120 and a 1-2 plating layer disposed on the 1-1 plating layer.

The first plating layer 130 including the first 1-1 plating layer and the 1-2 first plating layer may be formed as two layers on the first circuit pattern layer 120 to prevent formation of a whisker (kr00000374075b1) . Thus, it is possible to prevent a short circuit between the patterns of the first circuit pattern layer 120. In addition, since the two layers of plating layers are disposed on the first circuit pattern layer 120, the bonding characteristics with the chips can be improved. In the case where the first circuit pattern layer 120 includes copper (Cu), the first circuit pattern layer 120 can not be directly bonded to the first chip C1, . On the other hand, when one of the plurality of layers of the first plating layer 130 disposed on the first circuit pattern layer 120 includes tin (Sn), the surface of the first plating layer 130 is pure Tin layer, so that bonding with the first chip C1 can be facilitated. At this time, the wire connected to the first chip (C1) can be easily connected to the pure tin layer only by heat and pressure, so that the accuracy of the chip wire bonding and the convenience of the manufacturing process can be improved.

The region where the 1-1 plating layer is disposed may correspond to the region where the 1-2 plating layer is disposed. That is, the area where the 1-1 coating layer is disposed may correspond to the area where the 1-2 coating layer is disposed.

The first plating layer 130 may include tin (Sn). For example, the first 1-1 plating layer and the 1-2 first plating layer may include tin (Sn).

For example, the first circuit pattern layer 120 may be formed of copper (Cu), and the first 1-1 plating layer and the 1-2 plating layer may be formed of tin (Sn). When the first plating layer 130 includes tin, oxidation of the first circuit pattern layer 120 can be prevented because tin (Sn) has excellent corrosion resistance. The first plating layer 130 may include gold (Au), silver (Ag), nickel (Ni), and nickel-chromium alloy (Ni-Cr) in addition to the tin And may be disposed on the first circuit pattern layer 120 using electrolytic plating, electroless plating, or the like.

Meanwhile, the material of the first plating layer 130 may be lower in electric conductivity than the material of the first circuit pattern layer 120. The first plating layer 130 may be electrically connected to the first circuit pattern layer 120.

The first 1-1 plating layer and the first 1-2 plating layer are formed of the same tin (Sn), but they may be formed by a separate process.

When the process of manufacturing the integrated flexible circuit board 300 according to the embodiment includes a heat treatment process such as thermal curing, the copper (Cu) of the first circuit pattern layer 120 or the copper (Cu) of the first plating layer 130 A diffusion action of tin Sn may occur. In detail, diffusion of copper (Cu) of the first circuit pattern layer 120 or tin (Sn) of the first plating layer 130 may occur through curing of the first protective layer 140.

Accordingly, as the diffusion concentration of copper (Cu) decreases from the first 1-1 plating layer toward the surface of the 1-2 plating layer, the content of copper (Cu) can be continuously reduced. On the other hand, the content of tin (Sn) may continuously increase from the first 1-1 plating layer toward the surface of the 1-2 plating layer. Accordingly, the top of the first plating layer 130 may include pure tin.

That is, at least a part of the first plating layer 130 may be an alloy of tin and copper due to a chemical action at the lamination interface of the first circuit pattern layer 120 and the first plating layer 130. The first protective layer 140 is hardened on the first plating layer 130 to a thickness of the tin and copper alloy after the first plating layer 130 is formed on the first circuit pattern layer 120 The thickness of the alloy of tin and copper may increase.

The alloy of tin and copper contained in at least a part of the first plating layer 130 has a chemical formula of Cu _x Sn _y , and 0 <x + y <12. For example, in the above formula, the sum of x and y may be 4? X + y? 11. For example, the tin and copper alloy contained in the plating layer 130 may be Cu ₃ Sn and Cu ₆ Sn ₅ Or the like. In detail, the first-1-1 plating layer may be an alloy layer of tin and copper.

In addition, the content of tin and copper may be different in the first 1-1 plating layer and the 1-2 first plating layer. The first 1-1 plating layer directly contacting the copper wiring pattern layer may have a copper content higher than that of the first 1-2 plating layer.

The first 1-2 plating layer may have a tin content higher than that of the first 1-1 plating layer. The first 1-2 plating layer may include pure tin. Here, pure tin may mean that the content of tin (Sn) is 50 atomic% or more, 150 atomic% or more, and 90 atomic% or more. At this time, the element other than tin may be copper. For example, the content of tin (Sn) may be 50 atomic% or more in the 1-2 plating layer. For example, the content of tin (Sn) in the first 1-2 plating layer may be 150 atomic% or more. For example, the tin (1-2) plating layer may have a tin (Sn) content of 90 atomic% or more. For example, the content of tin (Sn) may be 95 atomic% or more in the 1-2 coating layer. For example, the content of tin (Sn) may be 98 atomic% or more in the 1-2 coating layer.

The first plating layer 130 according to the embodiment can prevent an electrochemical migration resistance due to the diffusion phenomenon of Cu / Sn and can prevent a short-circuit defect due to metal growth.

However, the present invention is not limited to this example, and the first plating layer 130 may be formed of Ni / Au alloy, Au, electroless nickel immersion gold (ENIG), Ni / Pd alloy, (Organic Solderability Preservative, OSP).

The 1-2 plating layer may correspond to the first 1-2 plating layer, or may have different thicknesses. The total thickness of the first 1-1 plating layer and the 1-2 first plating layer may be 0.3 탆 to 1 탆. The total thickness of the first 1-1 plating layer and the 1-2 first plating layer may be 0.3 탆 to 0.7 탆. The total thickness of the first 1-1 plating layer and the 1-2 first plating layer may be 0.3 탆 to 0.5 탆. The plating layer of any one of the first 1-1 plating layer and the 1-2 first plating layer may have a thickness of 0.05 탆 to 0.15 탆 or less. For example, the plating layer of any one of the 1-1 plating layer and the 1-2 plating layer may have a thickness of 0.07 탆 to 0.13 탆 or less.

The first passivation layer 140 may be partially disposed on the first circuit pattern layer 120. For example, the first passivation layer 140 may be disposed on the first plating layer 130 on the first circuit pattern layer 120. The first protective layer 140 may cover the first plating layer 130 to prevent damage or de-filming due to oxidation of the first circuit pattern layer 120 and the first plating layer 130 .

The first passivation layer 140 may be formed on the first circuit pattern layer 120 and / or the first plating layer 130 to be electrically connected to the display panel 30, the main board 40, And may be partially disposed in an area other than the area to be connected.

Accordingly, the first passivation layer 140 may be partially overlapped with the first circuit pattern layer 120 and / or the first plating layer 130.

The area of the first passivation layer 140 may be smaller than the area of the first insulation layer 110. The first passivation layer 140 may be disposed in a region other than an end of the substrate, and may include a plurality of open regions.

The first passivation layer 140 may include a first open region OA1 having the same shape as a hole. The first open area OA1 is formed in a region where the first circuit layer 120 and / or the first plating layer 130 are electrically connected to the first chip C1, May be a placement area.

The first passivation layer 140 may not be disposed on the first circuit pattern layer 120 to be electrically connected to the display panel 30. The embodiment may include a second open area OA2 that is a non-layout area of the first passivation layer 140 on the first circuit pattern layer 120 to be electrically connected to the display panel 30. [ Accordingly, in the second open area OA2, the first plating layer 130 disposed on the first circuit pattern layer 120 may be exposed to the outside.

In the second open region OA2, the content of copper in the first plating layer 130 may be 50 atomic% or more. Alternatively, in the second open area OA2, the content of copper in the first plating layer 130 may be less than 50 atomic%. The second open area OA2 may be located on the outer side of the substrate than the first open area OA1.

The first open area OA1 may be located in a central area of the substrate than the second open area OA2.

The first passivation layer 140 may be disposed in the bending region. Accordingly, the first passivation layer 140 can disperse stress that may occur during bending. Therefore, the reliability of the integrated flexible printed circuit board 300 according to the embodiment can be improved.

The first passivation layer 140 may include an insulating material. The first passivation layer 140 may include various materials that are applied to protect the surface of the first circuit pattern layer 120 and then cured by heating. The first passivation layer 140 may be a resist layer. For example, the first passivation layer 140 may be a solder resist layer containing an organic polymer material. For example, the first passivation layer 140 may include an epoxy acrylate resin. In detail, the first passivation layer 140 may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic based monomer, or the like. However, the present invention is not limited thereto, and the first passivation layer 140 may be a photo-solder resist layer, a cover-lay, or a polymer material.

The thickness of the first passivation layer 140 may be between 1 탆 and 20 탆. The thickness of the first passivation layer 140 may be 1 탆 to 15 탆. For example, the first passivation layer 140 may have a thickness of 5 to 20 占 퐉. If the thickness of the first passivation layer 140 is more than 20 μm, the thickness of the chip-on-film flexible circuit board 100 may increase. If the thickness of the first passivation layer 140 is less than 1 탆, the reliability of the first circuit pattern layer 120 included in the chip-on-film FPCB 100 may be reduced.

The chip-on-film flexible printed circuit board 100 may include a conductive pattern portion CP disposed on one side of the first insulating layer 110 and a conductive pattern portion CP partially disposed on one side of the conductive pattern portion CP, And a protective portion PP where the layer 140 is disposed and inspired.

The conductive pattern portion CP may include the first circuit pattern layer 120 and the first plating layer 130.

The protective portion PP may not be disposed on a region other than one region on the conductive pattern portion CP. Accordingly, the first insulating layer 110 between the conductive pattern CP and the spaced conductive pattern CP can be exposed on a region other than the one region on the conductive pattern CP. The first connection part 150 may be disposed on the conductive pattern part CP and on the other area. In detail, the first connection part 150 may be disposed on the upper surface of the conductive pattern part CP in which the protection part PP is not disposed.

The first chip C1 may be disposed on the first connection unit 150. [ The first connection part 150 may include a conductive material. The first connection part 150 may include the first chip C1 disposed on the upper surface of the first connection part 150 and the conductive pattern part CP disposed on the lower surface of the first connection part 150, Can be electrically connected.

The first chip C1 may include a drive IC chip.

One end of the flexible circuit board 100 for the chip-on-film may be connected to the display panel 30. One end of the chip-on-film flexible circuit board 100 may be connected to the display panel 30 by an adhesive layer 50. The display panel 30 may be disposed on the upper surface of the adhesive layer 50 and the flexible circuit board 100 may be disposed on the lower surface of the adhesive layer 50. Accordingly, the display panel 30 and the flexible circuit board 100 for the chip-on-film can be bonded up and down with the adhesive layer 50 interposed therebetween.

The adhesive layer 50 may include a conductive material. The adhesive layer 50 may be one in which the conductive particles are dispersed in the adhesive material. For example, the adhesive layer 50 may be an anisotropic conductive film (ACF).

Accordingly, the adhesive layer 50 transmits electrical signals between the display panel 30 and the integrated flexible circuit board 300 including the chip-on-film flexible circuit board 100, .

On the other hand, the chip-on-film flexible circuit board 100 may be divided into a first area and a second area.

The first region may include a region where the first chip C1 is disposed and a region where a conductive pattern portion connected to the display panel 30 is formed. The second region may be a region other than the first region.

The first circuit pattern layer 120 may include a conductive pattern disposed in the first region and a conductive pattern disposed in the second region.

At this time, the conductive patterns constituting the first circuit pattern layer 120 may have different widths depending on the regions. Preferably, the first circuit pattern layer 120 disposed on the first region includes a first conductive pattern CP1 to which the first chip C1 is attached, and a second conductive pattern CP1 to which the first conductive pattern CP1 is connected, And a second conductive pattern CP2 for signal transmission between the first conductive pattern CP1 and the third conductive pattern CP3.

At this time, the first to third conductive patterns CP1, CP2, and CP3 may all have the same width. However, the third conductive pattern CP3 may have a width different from that of the first conductive pattern CP1 and the second conductive pattern CP2 according to the embodiment.

Wherein the first conductive pattern CP1 has a first width D1 and the second conductive pattern CP2 has a second width D2 and the third conductive pattern CP3 has a third width D3 ). At this time, the first width D1 and the second width D2 may be equal to each other. Preferably, the first width D1 and the second width D2 may be between 5 and 20 um. More preferably, the first width D1 and the second width D2 may be between 8 and 12 um.

The third width D3 of the third conductive pattern CP3 may be greater than the first width D1 and the second width D2. Preferably, the third width (D3) Can be from 5 to 20 um. More preferably, the third width D3 may be between 8 and 12 um. In this case, the third width D3 is preferably larger than the first width D1 and the second width D2 within the above range.

That is, the first conductive pattern CP1 and the second conductive pattern CP2 are implemented at a fine pitch for mounting a display driver IC such as an LCD or a p-OLED in the chip-on-film flexible circuit board 100 . However, the third conductive pattern CP3 may have the same width as the first conductive pattern CP1 and the second conductive pattern CP2. However, in the embodiment of the present invention, the first conductive pattern CP1 and the second conductive pattern CP2 may have a greater width than the first conductive pattern CP1 and the second conductive pattern CP2 in order to increase the reliability of connection with the display panel.

The first circuit pattern layer 120 disposed on the second region of the chip-on-film flexible circuit board 100 may include a fourth conductive layer (not shown) directly connected to the via V1 disposed on the layered substrate 200, A pattern CP4, and a fifth conductive pattern CP5 for signal transmission.

At this time, the fourth conductive pattern CP4 has a fourth width D4, and the fifth conductive pattern CP5 has a fifth width D5. At this time, the fourth width D4 and the fifth width D5 may be equal to each other. If the fourth width D4 and the fifth width D5 are equal to each other, the fourth width D4 and the fifth width D5 may be equal to each other between the first width D1 and the second width D5, Is greater than the width (D2).

Meanwhile, the fourth width D4 and the fifth width D5 may be different from each other. Here, if the fourth width D4 and the fifth width D5 are different from each other, the fourth width D4 is larger than the fifth width D5. The fifth width D5 may be the same as the first width D1 and the second width D2.

In other words, the laminated substrate 200 is disposed in the second region of the chip-on-film flexible circuit board 100. At this time, a plurality of vias V1 are arranged in the laminated substrate 200. [ The chip-on-film flexible circuit board 100 may be manufactured by a roll-to-roll process. The laminated board 200 may be manufactured by laminating a second region of the chip-on-film flexible circuit board 100 manufactured by the roll-to-roll method in a sheet manner.

The pitch of the conductive patterns disposed on the chip-on-film flexible circuit board 100 may be a pitch of the conductive patterns or pitches of the vias V1 disposed on the laminate substrate 200, .

At this time, if the conductive pattern disposed in the second region of the chip-on-film flexible printed circuit board 100 is formed at a fine pitch such as a conductive pattern disposed in the first region, in the laminating process of the laminated substrate, The conductive pattern in the region and the alignment between the vias V1 are difficult, which may cause a problem in reliability.

In other words, the minimum width that the vias can have is considerably larger than the width that the conductive pattern of the chip-on-film flexible circuit board 100 can have, so that the gap between the via V1 and the conductive pattern Mismatching may cause a problem such as a circuit short circuit.

Accordingly, in the present invention, the width of the fourth conductive pattern D4 disposed in the second region is greater than the width of the first conductive pattern D1 or the second conductive pattern D2, So that there is no problem in alignment with the vias V1.

Preferably, the fourth width of the fourth conductive pattern CP4 may be 20 to 50 mu m. More preferably, the fourth width of the fourth conductive pattern CP4 may be 20 to 35 um.

Meanwhile, the width of the fifth conductive pattern CP5 may be selectively formed. Preferably, the fifth conductive pattern CP5 is not directly connected to the via V1 and therefore has a fifth width D2 equal to the first width D1 and the second width D2 for fine pitch implementation D5).

Alternatively, the fifth conductive pattern CP5 may have a fifth width D5 that is the same as the fourth width D4, for the uniformity of the conductive patterns disposed on the second region.

Alternatively, the fifth conductive pattern CP5 may have an impedance problem for signal transmission due to the difference between the first width D1 and the fourth width D4, (D5) that is greater than the first width (D1) but less than the fourth width (D4).

On the other hand, a laminated board 200 is disposed on the upper and lower surfaces of the second region of the chip-on-film flexible circuit board 100.

The laminated substrate 200 includes a second insulating layer 210 disposed on upper and lower surfaces of the second region of the first insulating layer 110 and a second insulating layer 210 disposed on the second insulating layer 210, A third insulating layer 220 disposed on the second insulating layer 210, a fourth insulating layer 230 disposed on the third insulating layer 220, a second circuit pattern layer 240 disposed on the second insulating layer 210, A third circuit pattern layer 250 disposed on the surface of the third insulating layer 230, a second protective layer 260 partially disposed on the third circuit pattern layer 250, And a second plating layer 2150 disposed on the three-circuit pattern layer 250.

In this case, the chip-on-film flexible circuit board 100 is divided into a first region and a second region as described above, and the first region is divided into a soft region FA, And the second region may be referred to as a hard region RA as the laminated substrate 200 is disposed.

The second insulating layer 210 and the fourth insulating layer 230 may be prepregs and the third insulating layer 220 may be a flexible copper clad laminate (FCCL).

The prepreg (PPG) is a molding material preliminarily impregnated with a matrix resin in a reinforcing fiber, which is excellent in flowability and adhesiveness in a semi-cured state, and is used as an intermediate substrate for a fiber reinforced composite material used as an adhesive layer and an insulating material layer . These prepregs are laminated and heated / pressed to cure the resin to form a molded article. That is, a prepreg is a material that is impregnated with a glass fiber (BT / Epoxy, FR4, FR5, etc.) and cured to a B-stage

The FCCL refers to a flexible copper-clad laminate, which is a composite film in which a heat-resistant flame-retardant epoxy adhesive is coated on a polyimide film and a copper foil is laminated on the polyimide film, and a circuit board It is used as a material.

Also, a via V1 is disposed through at least one of the first to fourth insulating layers 110, 210, 220, and 230. The via V1 includes a first circuit pattern layer 120 disposed on a surface of the first insulation layer 110 and a second circuit pattern layer 240 disposed on a surface of the third insulation layer 220. [ And the third circuit pattern layer 250 disposed on the surface of the fourth insulating layer 230 are electrically connected to each other.

The via V1 may be formed by filling a conductive material into a via hole passing through at least one of the first to fourth insulating layers 110, 210, 220, and 230. The conductive material filled in the via hole may be a conductive material corresponding to or different from the circuit pattern layers. For example, the conductive material filled in the via hole may be copper (Cu), aluminum (Al), chromium (Cr), nickel (Ni), silver (Ag), molybdenum (Mo). Gold (Au), titanium (Ti), and alloys thereof.

The second plating layer 2150 may include a plurality of layers (a second-1-plated layer and a second-2-plated layer) like the first plating layer 130.

Meanwhile, the second plating layer 2150 may be formed by dissimilar metal plating of a material different from that of the first plating layer 130. That is, the metal material constituting the second plating layer 2150 / the first plating layer 130 may be at least one selected from the group consisting of gold / tin, silver / tin, nickel / tin, nickel-chromium / tin, nickel / chrome, Copper, and nickel-chromium / gold.

The second passivation layer 260 may include a third open area OA3 having the same shape as a hole. The third open area OA3 may be formed in a region where the third circuit pattern layer 250 and / or the second plating layer 2150 are electrically connected to the second chip C2, May be a placement area.

The copper content of the first plating layer 140 disposed on the first open area OA1 and the copper content of the second plating layer 2150 disposed on the third open area OA3 are different from each other .

In the third open area OA3, the content of copper in the second plating layer 2150 may be 50 atomic% or more. For example, the content of copper in the second plating layer 2150 may be 60 atomic% or more. For example, the content of copper in the second plating layer 2150 may be 60 atom% to 280 atom%. In detail, the content of copper in the second-1 plated layer measured in the third open area OA3 may be 60 atom% to 280 atom%.

The second passivation layer 260 may not be disposed on the conductive pattern portion to be electrically connected to the main board 40. The embodiment may include a fourth open area OA4 that is a non-layout area of the second protective layer 260 on the conductive pattern part to be electrically connected to the main board 40. [ Accordingly, in the fourth open area OA4, the second plating layer 2150 may be exposed to the outside.

In the fourth open area OA4, the copper content of the second plating layer 2150 may be 50 atomic% or more. Alternatively, in the fourth open area OA4, the content of copper in the second plating layer 2150 may be less than 50 atomic%. The fourth open area OA4 may be located on the outer side of the substrate than the first open area OA1 and the third open area O3.

The first open area OA1 and the third open area OA3 may be located in a central area of the substrate than the fourth open area OA4.

The second passivation layer 260 may be disposed in the bending region. Accordingly, the second passivation layer 260 can disperse stress that may occur during bending. Therefore, the reliability of the integrated flexible printed circuit board 300 according to the embodiment can be improved.

The second plating layer 2150 in the fourth open region OA4 exposed in the laminated substrate 200 may be connected to the main board 40. [ The other end opposite to the one end of the integrated flexible printed circuit board 300 may be connected to the main board 40 by an adhesive layer 50. The main board 40 may be disposed on the upper surface of the adhesive layer 50 and the integrated flexible printed circuit board 300 may be disposed on the lower surface of the adhesive layer 50. Accordingly, the main board 40 and the integrated flexible printed circuit board 300 may be bonded up and down with the adhesive layer 50 therebetween.

On the other hand, the second connection part 2280 may be disposed on the third open area OA3. At this time, the first connection part 150 and the second connection part 280 may have different shapes. For example, the first connection part 150 may have a hexahedral shape. In detail, the cross section of the first connection part 150 may include a rectangular shape. More specifically, the cross section of the first connection part 150 may include a rectangular or square shape. For example, the second connection portion 280 may include a spherical shape. The cross section of the second connection part 280 may include a circular shape. Alternatively, the second connection portion 280 may include a partially or entirely rounded shape. For example, the cross-sectional shape of the second connection part 280 may be a flat surface on one side and a curved surface on the other side opposite to the one side surface.

The first connection part 150 and the second connection part 280 may have different sizes. The first connection unit 150 may be smaller than the second connection unit 280.

The widths of the first connection part 150 and the second connection part 280 may be different from each other. For example, the width D6 between both sides of one first connection part 150 may be smaller than the width D7 between both sides of one second connection part 280. [

And the second chip C2 may be disposed on the second connection unit 280. [ The second connection part 280 may include a conductive material. The second connection part 280 is electrically connected to the third circuit pattern layer 241 disposed on the lower surface of the second chip C2 and the second connection part 280 disposed on the upper surface of the second connection part 280, 250 and the second conductive layer 260 may be electrically connected to each other.

In the integrated flexible printed circuit board 300 according to the embodiment, the first chip C1 is disposed on the soft region FA of the chip-on-film flexible circuit board 100 and the first chip C1 is disposed on the hard region RA. A second chip C2 of a different type from the first chip C2 may be disposed.

In detail, one of the first chip C1 and the plurality of second chips C2 may be disposed on the integrated flexible circuit board 300 according to the embodiment. Thus, the efficiency of the chip packaging process can be improved.

The second chip C2 may refer to a chip other than a drive IC chip. The second chip C2 may refer to various chips including a socket or a device other than a drive IC chip. For example, the second chip C2 may include at least one of a diode chip, a power IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor.

The plurality of second chips C2 disposed on the integrated flexible circuit board 300 mean that at least one of a diode chip, a power IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor is disposed can do. For example, a plurality of MLCC chips may be disposed on the integrated flexible circuit board 300.

The second chip C2 may include at least two of a diode chip, a power IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor. That is, a plurality of second chips C2a and C2b of different kinds may be disposed on the integrated flexible circuit board 300. [ For example, a second chip (C2a) of any one of a diode chip, a power IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor and a diode chip, a power IC chip, A touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor, and one second chip C2b.

A plurality of second chips (C2a) of a diode chip, a power IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor may be arranged on the integrated flexible circuit board 300 in detail. , A power IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor, and a second chip (C2b) different from the first chip (C2b). For example, the integrated flexible circuit board 300 may include a plurality of MLCC chips C2a and a plurality of power IC chips C2b. For example, the integrated flexible circuit board 300 may include a plurality of MLCC chips C2a and a plurality of diode chips C2b. For example, the integrated flexible circuit board 300 may include a plurality of MLCC chips C2a and a plurality of BGA chips C2b.

It is needless to say that the second chip is not limited to two types in the embodiment, and various chips other than the driving IC chip may be included in the second chip.

Hereinafter, a method of manufacturing the integrated flexible printed circuit board 300 shown in FIG. 3 will be described with reference to FIGS. 5A to 5J.

5A, a first circuit pattern layer 120 is formed on one surface of a first insulating layer 110, a first circuit pattern layer 120 is formed on one surface of the first circuit pattern layer 120, 1 &lt; / RTI &gt; protection layer 140 can be prepared.

As described above, the first insulating layer 110 is divided into a first region and a second region, and the width of the first circuit pattern layer 120 disposed in the first region and the width of the second circuit pattern layer 120, The widths of the first circuit pattern layers 120 disposed in the regions are different from each other. In other words, the fourth conductive pattern CP4 connected to the via V1 of the laminated substrate 200 among the first circuit pattern layers 120 disposed in the second region is formed to have a greater width than the other conductive patterns do. Preferably, the fourth conductive pattern CP4 has a width corresponding to the width of the ratio V1.

Next, as shown in FIG. 5B, a second insulating layer 210 covering only the second region is formed on the second region of the first insulating layer 110. Next, as shown in FIG. At this time, the second insulating layer 210 may be formed of a prepreg.

The FCCL covering the upper region of the first region of the first insulating layer 110 is formed while covering the upper surface of the first insulating layer 210 on the second insulating layer 210. At this time, the FCCL includes a third insulating layer 220 and a copper foil layer 235 disposed on the third insulating layer 220.

Next, as shown in FIG. 5C, the copper foil layer 235 is patterned to form a second circuit pattern layer 240 disposed on the surface of the third insulating layer 220.

A via V1 is formed through at least two of the first insulating layer 110, the second insulating layer 210, and the third insulating layer 220. At this time, the vias V1 are disposed to penetrate the first insulating layer 110, the second insulating layer 210, and the third insulating layer 220 in common, and the first circuit pattern layer 120 And the second circuit pattern layer 240 can be electrically connected to each other. The vias V1 may pass through the second insulating layer 210 and the third insulating layer 220 to electrically connect the first circuit pattern layer 120 and the second circuit pattern layer 240 to each other. .

5D, a fourth insulating layer 230 is formed on the third insulating layer 220, and a copper foil layer 245 is formed on the fourth insulating layer 230. Next, as shown in FIG.

5E, the copper foil layer 245 is patterned to form a third circuit pattern layer 250 disposed on the fourth insulating layer 230. Next, as shown in FIG.

The second circuit pattern layer 240 and the third circuit pattern layer 250 may be formed by filling the via hole formed through the fourth insulating layer 230 with the metal material, Thereby forming electrically connecting vias.

Next, as shown in FIG. 5F, a second passivation layer 260 including a third open region OA3 and a fourth open region OA4 is formed on the fourth insulating layer 230. Referring to FIG.

Next, as shown in FIG. 5G, a portion of the third insulating layer 220 and the fourth insulating layer 230 located above the first region of the first insulating layer 110 is removed. At this time, the removal may be performed by a laser drill.

5H, the first circuit pattern layer 120 and the third circuit pattern layer 250, which are exposed through the first passivation layer 140 and the second passivation layer 260, A first plating layer 130 and a second plating layer 2150 are formed.

At this time, the first plating layer 130 and the second plating layer 2150 may be simultaneously formed by metal plating, or they may be formed of different metal materials by different metal plating. The one kind of plating may include tin (Sn) and may include gold (Au), silver (Ag), nickel (Ni) and nickel-chromium alloy (Ni-Cr) Electroplating, electroless plating, or the like.

The dissimilar metal plating may also include gold / tin, silver / tin, nickel / tin, nickel-chromium / tin, nickel / chrome, gold / silver, gold / copper, nickel-chrome / gold.

Next, as shown in FIGS. 5I and 5J, the first connection part 150 is formed on the exposed conductive pattern part through the first open area OA1 of the first passivation layer 140. Next, as shown in FIGS. The second connection part 280 is formed on the conductive pattern part exposed through the third open area OA3 of the second passivation layer 260. [

That is, the first connection part 150 may be disposed in the first open area OA1. The content of tin (Sn) in the first plating layer (130) in the first open area (OA1) may be 50 atomic% or more. In the first open area OA1, the first plating layer 130 may include pure tin. For example, the content of tin (Sn) in the first plating layer 130 in the first open area OA1 may be 150 atomic% or more. For example, the content of tin (Sn) in the first plating layer 130 in the first open area OA1 may be 90 atomic% or more. For example, the content of tin (Sn) in the first plating layer 130 in the first open area OA1 may be 95 atomic% or more. For example, the content of tin (Sn) in the first plating layer 130 in the first open area OA1 may be 98 atomic% or more. When the content of tin (Sn) in the first plating layer 130 in the first open region OA1 is less than 50 atomic%, the first plating layer 130 and the first chip 130, (C1) may be difficult to connect. When the content of tin (Sn) in the first plating layer 130 in the first open area OA1 is less than 50 atomic%, the first plating layer 130 and the first plating layer 130 The connection by the bonding of the chip C1 may be difficult.

The first connection part 150 may include gold (Au). The first connection part 150 may be a gold bump.

A plurality of the first connection parts 150 may be formed between the first chip C1 and the first plating layer 130 in order to dispose one first chip C1 on the integrated flexible circuit board 300 according to the embodiment. As shown in FIG.

A second connection part 280 is disposed in the third open area OA3 of the second passivation layer 260. [

In order to arrange the second chip C2 on the integrated flexible printed circuit board 300 according to the embodiment, only the portion H corresponding to the region where the second connection portion 280 is arranged is selectively opened through the mask M, Can be supplied. In detail, the embodiment can selectively supply heat to an area where the second connection part 280 for connecting the second chip C2 is disposed through an optional reflow process.

In detail, the integrated flexible circuit board 300 according to the embodiment has a function of preventing the portion (s) through selective reflow process even when the second chip C2 is disposed after mounting the first chip C1. Heat supply can be possible.

That is, the fabrication process according to the embodiment can prevent heat from being exposed to the first open region OA through the mask. Thus, the first plating layer disposed in the first open region OA can be prevented from being transformed from pure tin into an alloy layer of tin and copper by heat supply. Accordingly, even when the first chip C1 and the second chip C2, which are different from each other, are mounted on one integrated flexible circuit board 300, the tin of the first plating layer 130 in the first open region (Sn) may be 50 atomic% or more, and the assembly of the driving IC chip may be excellent.

On the other hand, a hole of a mask may be disposed in an area corresponding to the third open area OA3. Accordingly, the plating layer exposed by heat in the third open area OA3 may be denatured as an alloy layer of tin and copper.

In detail, a part of the second plating layer 270 exposed by the heat through the hole of the mask may further undergo diffusion of tin / copper. Accordingly, the content of tin (Sn) in the second plating layer 280 in the third open area OA3 may be less than 50 atomic%. In the third open area OA3, the second plating layer 280 may be an alloy layer of copper (Cu) and tin (Sn).

The second connection unit 280 may include a metal other than Au. Therefore, even when the second plating layer 280 located below the second connection part 280 is not pure tin, the second connection part 280 can be easily assembled with the second chip C2 can do. In addition, the second connection portion 280 may include a metal other than gold (Au), so that the manufacturing cost can be reduced.

For example, the second connection unit 280 may include at least one of copper (Cu), tin (Sn), aluminum (Al), zinc (Zn), indium (In), lead (Pb), antimony (Sb), bismuth (bi ), Silver (Ag), and nickel (Ni).

The second connection unit 280 may be a solder bump. The second connection unit 280 may be a solder ball. The solder ball can be melted at the temperature of the reflow process.

A plurality of second connection portions 280 may be formed between the second chip C2 and the second plating layer 280 so as to arrange one second chip C2 on the integrated flexible circuit board 300 according to the embodiment. As shown in FIG.

At the temperature of the reflow process, the second chip C2 can be bonded with the second plating layer 280 on the third open area OA3 through the second connection part 280. [

The integrated flexible printed circuit board 300 according to the embodiment is excellent in the connection of the first chip C1 through the first connection part 150 in the first open area and the second connection part 280 in the third open area, The connection of the second chip C2 may be excellent.

As in the comparative example, after the first chip is mounted on the first printed circuit board and the second chip is mounted on the second printed circuit board, the first printed circuit board having the first chip and the second chip are provided In the case of bonding a second printed circuit board to an adhesive layer, there may be no problem caused by thermal degeneration of the first chip.

However, when the first and second chips different from each other are mounted on one integrated flexible circuit board 300 as in the embodiment, a second plating layer is formed in the first open area of the protective layer for connecting the first chip, There is a problem that it is difficult to assemble the first chip by the first connection portion.

In order to solve such a problem, the inventors arranged the first chip and the second chip sequentially on the integrated flexible circuit board 300 through an optional reflow process. Accordingly, the integrated flexible printed circuit board 300 according to the embodiment and the chip package including the same can be manufactured by a combination of the tin content of the first plated layer in the first open area and the tin content of the tin of the second plated layer in the third open area. Content may vary. Therefore, the chip package including the integrated flexible printed circuit board 300 according to the embodiment can enable excellent electrical connection between the first chip C1 and the second chip C2, which are different from each other.

The first plating layer including pure tin in the first open region can be stably mounted on the first chip, which is a driving IC chip, through a first connection portion including gold (Au). The second plating layer including the copper and tin alloy layer in the third open region is electrically connected to the diode chip, the power IC chip, the touch sensor IC chip, the MLCC A stable mounting of a second chip, which is at least one of a chip, a BGA chip, and a chip capacitor, may be possible.

Accordingly, the integrated flexible printed circuit board 300 according to the embodiment and the chip package including the integrated flexible circuit board 300 can be mounted on one integrated flexible circuit board 300 with excellent yields of first and second chips of different kinds .

In addition, since a plurality of existing printed circuit boards can be replaced with one integrated flexible circuit board 300, the integrated flexible circuit board 300 for connecting the display panel and the main board can be downsized and thinned.

Therefore, the electronic device including the integrated flexible circuit board 300 of the embodiment can easily mount various functional parts such as a camera module, an iris recognition module, and the like. Further, the electronic device including the integrated flexible printed circuit board 300 of the embodiment can expand the battery space.

FIG. 6 is a cross-sectional view of an integrated flexible printed circuit board according to a second embodiment of the present invention, and FIG. 7 is a simplified plan view of the integrated flexible printed circuit board shown in FIG.

Referring to FIG. 6, the integrated flexible printed circuit board differs from the integrated flexible circuit board shown in FIG. 3 only in the structure in which the laminated board is disposed, and the other parts are the same.

Therefore, in the description of FIG. 6, only the lamination structure of the laminated substrate will be described in detail.

Referring to FIG. 1, the chip-on-film flexible circuit board 100 is divided into a first region and a second region, and the chip-on-film flexible circuit board 100 is divided into a first region and a second region, 2 area. The area exposed by the first passivation layer 140 in the chip-on-film flexible printed circuit board 100 may include a first open area OA1 where the first chip C1 is disposed, And a second open area OA1 in which the pattern is disposed. At this time, the laminated substrate 200 is not disposed in a region between the first open area OA1 and the second open area OA2.

6, in the integrated flexible printed circuit board according to the second embodiment of the present invention, in the area between the first open area OA1 and the second open area OA2, 200 are disposed.

In other words, the laminated substrate 200 is disposed so as to surround the first open area OA1 while exposing the second open area OA2.

That is, the laminated substrate 200 includes the cavity C that exposes the first open area OA1, so that the periphery of the area where the first chip C1 is disposed is the same as that of the laminated substrate 200, . Therefore, in the present invention, the strength around the area where the first chip (C1) is arranged can be secured, and thus the operation reliability can be further improved.

Therefore, according to the second embodiment of the present invention, the integrated flexible circuit board includes the first hard area RA1, the second hard area RA2, the first soft area FA1, and the second soft area FA2. . &Lt; / RTI &gt;

The first hard area RA1 is a first area of the chip-on-film flexible circuit board 100 and is a left area of the integrated flexible circuit board on which the laminated board 200 is disposed. As shown in FIG. 3, a conductive pattern connected to the main board is disposed in the first hard area RA1.

The second hard area RA2 is a region between the area where the first chip C1 is arranged in the chip-on-film flexible circuit board 100 and the area where the conductive pattern connected with the display panel is arranged. In the first embodiment, the second chip C2 is disposed in a region adjacent to the conductive pattern connected to the main board. And may be disposed on the second hard area RA2 in the second embodiment. Accordingly, the interval between the first chip C1 and the second chip C2 can be minimized, thereby minimizing signal attenuation.

The first soft region FA1 is a region where the first chip C1 is disposed on the chip-on-film flexible circuit board 100. [ At this time, the first soft region FA1 is formed as a soft region at the center portion, and the third hard region RA3 is formed at the edge portion thereof.

And the second soft area FA2 is a region where a conductive pattern connected to the display panel in the chip-on-film flexible circuit board 100 is disposed.

As described above, in the second embodiment of the present invention, the laminated substrate 200 is disposed to surround the periphery of the region where the first chip C1 is disposed, and thereby the strength of the integrated flexible circuit board is ensured .

3 and 6, the integrated flexible printed circuit board includes a chip-on-film flexible printed circuit board 100, wherein the chip-on-film flexible printed circuit board 100 is formed on only one of the upper surface and the lower surface On-film flexible circuit board (100) in which a conductive pattern is disposed. However, such a flexible chip for a chip-on-film substrate may be difficult to realize a circuit having a high resolution (QHD).

2. Description of the Related Art Recently, various electronic devices having a display portion such as a smart phone, a television, a monitor, an electronic paper, and a wearable device are required to realize a high resolution display. Accordingly, the integrated flexible circuit board according to the embodiment may include a flexible circuit board for a double-sided chip-on film.

At this time, in the flexible circuit board for a double-sided chip-on-film, a conductive pattern layer may be disposed on both sides of the substrate to realize a high-resolution display.

8 is a cross-sectional view of an integrated flexible printed circuit board according to a third embodiment of the present invention.

In this case, the integrated flexible printed circuit board of FIG. 8 is different from that of FIG. 1 only in the structure of the chip-on-film flexible circuit board, and the structure of the laminated board disposed on the chip-on film flexible circuit board is the same. Accordingly, the double-sided chip-on-film flexible circuit board 400 constituting the integrated flexible circuit board will be described in detail below.

The chip-on-film flexible circuit board 400 may be a flexible circuit board for a double-sided chip-on-film having electrode pattern portions on both sides.

A flexible circuit board 400 for a chip on film constituting an integrated flexible circuit board according to an embodiment includes a first insulation layer 410, a circuit pattern layer 400 disposed on the first insulation layer 410, A metal layer 420, a plating layer 430, and a protective layer 440.

The chip on film flexible circuit board 400 according to the embodiment may be manufactured by disposing the circuit pattern layer 420, the plating layer 430 and the protection layer 440 on one surface of the first insulating layer 410, And the circuit pattern layer 420, the plating layer 430, and the protective layer 440 may be additionally disposed on the opposite surface.

That is, the circuit pattern layer 420 may include an upper circuit pattern layer and a lower circuit pattern layer, and the upper circuit pattern layer and the lower circuit pattern layer may include metal materials corresponding to each other. Thus, the process efficiency can be improved. However, it should be understood that the embodiments are not limited thereto and may include other conductive materials.

The thickness of the upper circuit pattern layer may correspond to the thickness of the lower circuit pattern layer. Thus, the process efficiency can be improved.

The upper plating layer may include a metal material corresponding to the lower plating layer. Thus, the process efficiency can be improved. However, it should be understood that the embodiments are not limited thereto and may include other conductive materials.

The thickness of the upper plating layer may correspond to the thickness of the lower plating layer. Thus, the process efficiency can be improved.

The first insulating layer 410 may include through holes. The first insulating layer 410 may include a plurality of through holes. The plurality of through holes of the first insulating layer 410 may be formed by a mechanical process or a chemical process, respectively, or simultaneously. For example, the plurality of through holes of the first insulating layer 410 may be formed by a drilling process or an etching process. For example, the through holes may be formed through laser punching and desmearing processes. The desmearing step may be a step of removing the polyimide smear attached to the inner surface of the through hole. The inner wall of the through hole formed in the first insulating layer 410 may have an inclined surface similar to a straight line by the desmearing process.

A circuit pattern layer 420, a plating layer 430, and a protective layer 440 may be disposed on the first insulating layer 410. In detail, the circuit pattern layer 420, the plating layer 430, and the protective layer 440 may be sequentially disposed on both surfaces of the first insulating layer 410.

The circuit pattern layer 420 may be formed by at least one of evaporation, plating, and sputtering.

As an example, a pattern layer for forming a circuit can be formed by electroplating after sputtering. In one example, the pattern layer for forming the circuit may be a copper plated layer formed by electroless plating. Alternatively, the pattern layer may be a copper-plated layer formed by electroless plating and electroplating.

Next, a patterned wiring layer can be formed on both sides of the flexible circuit board, that is, on the upper and lower surfaces of the flexible circuit board through the exposure, development and etching processes after laminating the dry film on the pattern layer. Thus, the circuit pattern layer 120 can be formed.

Vias (V1, V2, V3) passing through the first insulating layer 410 may be filled with a conductive material. The conductive material filled in the via hole may be a conductive material corresponding to or different from the circuit pattern layer 420. For example, the conductive material filled in the via hole is copper (Cu), aluminum (Al), chromium (Cr), nickel (Ni), silver (Ag), molybdenum (Mo). Gold (Au), titanium (Ti), and alloys thereof. The electrical signal of the conductive pattern on the upper surface of the first insulating layer 410 may be transmitted to the conductive pattern of the lower surface of the first insulating layer 410 through the conductive material filled in the via hole.

Next, a plating layer 430 may be formed on the circuit pattern layer 420.

Thereafter, the protective portion PP may be screen printed on the circuit pattern layer 420 and / or the plating layer 430.

The protective layer 440 may be disposed in direct contact with the first insulating layer 410 or in direct contact with the circuit pattern layer 420 or may be disposed in direct contact with the plating layer 430 .

The first insulating layer 410 and the circuit pattern layer 420 may be formed of a metal material for enhancing adhesion between the first insulating layer 410 and the circuit pattern layer 420, And a seed layer. At this time, the metal seed layer can be formed by sputtering. The metal seed layer may comprise copper.

Meanwhile, a plurality of protection layers 440 may be disposed on one surface of the first insulation layer 410. The protective layer may include a first protective layer and a second protective layer. For example, the first protective layer may be partially disposed on one surface of the first insulating layer 410, and the circuit pattern layer 420 may be disposed on a region other than a region where the protective layer is disposed. The second passivation layer may be disposed on the first passivation layer. In other words, the protective layer 440 disposed on the chip-on-film flexible circuit board 400 may be composed of a plurality of layers.

The second passivation layer covers the first passivation layer and the circuit pattern layer 420 and may be disposed in a region larger than the first passivation layer.

The second protective layer may be disposed on a region corresponding to the first protective layer while covering an upper surface of the first protective layer. The width of the second protective layer may be larger than that of the protective layer. Accordingly, the lower surface of the second protective layer can contact the circuit pattern layer 420 and the first protective layer. Accordingly, the second protective layer can relieve the stress concentration at the interface between the first passivation layer and the circuit pattern layer 420. Accordingly, it is possible to reduce the occurrence of a film or crack that may occur when bending the double-sided chip-on-film flexible circuit board 400 included in the integrated flexible circuit board according to the embodiment.

On the other hand, in the chip-on-film flexible circuit board 400, the protection region 440 may be formed of the protective portion PP. The conductive pattern may be exposed to the outside in a region other than the protective portion PP where the protective layer is not formed. That is, the conductive pattern may be electrically connected to the first chip (C1) and the display panel (30) in a region where the protection portion is not disposed on the open region or the conductive pattern of the protection layer.

The lead pattern portion and the test pattern portion of the flexible circuit board for a chip on film according to the embodiment may not overlap with the protective portion. That is, the lead pattern portion and the test pattern portion may be a conductive pattern located in an open region not covered by a protective layer, and may be distinguished as a lead pattern portion and a test pattern portion according to functions.

The lead pattern portion may refer to a conductive pattern to be connected to the first chip and the display panel.

The test pattern portion may mean a conductive pattern for confirming whether or not a product of the chip-on-film flexible circuit board and the chip package including the same is defective.

The lead pattern portion can be distinguished as an inner lead pattern portion and an outer lead pattern portion depending on the position. One region of the conductive pattern which lies relatively close to the first chip (C1), and which is not overlapped by the protective layer, can be represented by the inner lead pattern portion. One region of the conductive pattern that is relatively far from the first chip C1 and is not overlapped by the protective layer may be represented by an outer lead pattern portion.

The first chip C1 disposed on one surface of the flexible circuit board 100 for a chip on film according to the embodiment may be connected to the inner lead pattern portion through a first connection portion 450. [ The inner lead pattern portion may include a first inner lead pattern portion, a second inner lead pattern portion, and a third inner lead pattern portion.

The first connection unit 450 includes a first sub second connection unit 451, a second sub first connection unit 452, and a third sub first connection unit 453 according to the position and / .

The first chip C1 according to the embodiment may be electrically connected to the first inner lead pattern portion through the first sub first connection portion 451. [

The first inner lead pattern portion may transmit an electrical signal to a conductive pattern adjacent to the second via hole V2 along the upper surface of the first insulating layer 410. [

The first inner lead pattern portion is electrically connected to the second via hole V2 along the upper surface of the first insulating layer 410 and electrically connected to the first via hole V2 through the conductive material filled in the second via hole V2. And may transmit an electrical signal to the conductive pattern adjacent to the second via hole V2 along the lower surface of the insulating layer 410. [

The first chip C1 according to the embodiment may be electrically connected to the second inner lead pattern portion via the second sub first connection portion 452. [

The second inner lead pattern portion disposed on the upper surface of the first insulating layer 410 is electrically connected to the first insulating layer 410 through a conductive material filled in the first via hole V1 located below the second inner lead pattern portion (V1) and the conductive pattern along the lower surface of the first via hole (V1). At this time, at least a test pattern among the conductive patterns disposed on the lower surface of the first insulating layer 410 is included, so that a signal transmitted through the first via hole can be transferred to the test pattern.

In addition, the test pattern can confirm the failure of an electrical signal that can be transmitted through the first via hole V1. For example, the accuracy of a signal transmitted through the test pattern can be confirmed. In detail, by measuring a voltage or a current in the test pattern, it is possible to confirm whether or not a short circuit or a short-circuit occurs in the conductive pattern portion located between the first chip and the display panel, thereby improving the reliability of the product have.

The first chip C1 disposed on one surface of the chip-on-film flexible circuit board 400 according to the embodiment is electrically connected to the third inner lead pattern portion through the third sub first connection portion 453 Can be connected.

The third inner lead pattern portion may transmit an electrical signal to the outer lead pattern portion adjacent to the third via hole V3 along the upper surface of the first insulating layer 410. [ The outer lead pattern portion may be a pattern portion connected to the display panel.

The third inner lead pattern portion is electrically connected to the third via hole V3 along the upper surface of the substrate 110 and electrically connected to the first insulating layer V3 through the conductive material filled in the third via hole V3. 410 to transmit an electrical signal.

As described above, in the embodiment of the present invention, the chip-on-film flexible circuit board 400 is formed as a chip-on-film flexible circuit board 400 having a double-sided structure, so that a circuit having a high resolution (QHD) can be easily implemented.

Meanwhile, the via-holes formed on the first insulating layer 410 and the via-holes formed on the laminated substrate 200 have different shapes and sizes. In other words, the via hole formed on the first insulating layer 410 may have an inclined surface whose side is similar to a straight line. On the other hand, the via holes formed on the laminated substrate 200 have a predetermined inclination angle with respect to the main surface, and thus can have a trapezoidal shape.

The via hole formed on the first insulating layer 410 may have a width that satisfies a range of 15 to 50 um. The via hole formed on the first insulating layer 410 may have a width that satisfies the range of 20 to 35 um.

On the other hand, the via-holes formed on the laminated substrate 200 may have a width that satisfies the range of 50 to 200 um. Preferably, the via-holes formed on the laminated substrate 200 may have a width that satisfies the range of 70 to 100 um.

Meanwhile, a via hole may be formed in the second region of the first insulating layer 410. At this time, the width of the directly connected circuit pattern layer 420 connected to the via hole disposed in the first insulating layer 410 may be determined depending on whether or not there is an additional via connected directly. In other words, when the circuit pattern layer 420 is directly connected to the via hole disposed on the laminate substrate 200, the circuit pattern layer 420 may be formed corresponding to the width of the via hole disposed on the laminate substrate 200. On the other hand, when the circuit pattern layer 420 is not directly connected to the via hole disposed on the laminated substrate 200, the circuit pattern layer 420 may have a width corresponding to the via hole disposed in the first insulating layer 410 have.

9A is a cross-sectional view of an integrated flexible printed circuit board according to a fourth embodiment of the present invention.

Referring to FIG. 9A, the integrated flexible printed circuit board differs from the integrated flexible printed circuit shown in FIG. 8 in the position in which the conductive pattern (which may be referred to as an outer lead) is arranged to be connected to the main board. That is, in FIG. 8, a conductive pattern connected to the main board is disposed on the laminated board 200. On the other hand, in the integrated flexible printed circuit board shown in FIG. 9A, a conductive pattern connected to the main board can be disposed on the chip-on-film flexible circuit board 400.

That is, the chip-on-film flexible circuit board 400 may be divided into a first region, a second region, and a third region.

In addition, the laminated substrate 200 may be disposed in the second region. In this case, the second region may be a region between the first region and the third region.

That is, in the previous embodiment, the laminated board 200 covers all the remaining areas except for the first area of the chip-on-film flexible circuit board 400. On the other hand, in the present embodiment, the laminated substrate 200 is disposed so as to cover only the remaining region of the second region except the edge region.

In other words, the area connected to the main board has flexibility according to the position of the main board or the specification of the device. At this time, when the conductive pattern connected to the main board is disposed on the laminated board 200 as described above, it may be difficult to apply to all devices. Accordingly, in the embodiment, a conductive pattern connected to the main board is disposed on the chip-on-film flexible circuit board 400.

Accordingly, the integrated flexible printed circuit board includes a first soft region FA1 including a region where the first chip C1 is disposed, a region to which the display panel is connected, and a hard region RA And a second soft area FA2 including an area to which the main board is connected.

The conductive pattern connected to the display panel is disposed on one end of the chip-on-film flexible circuit board 400, and the conductive pattern connected to the other end of the chip-on-film flexible circuit board 400, And a conductive pattern connected to the main board is disposed. Accordingly, the second flexible region FA2 is bent according to the specification of the device to which the integrated flexible circuit board is applied and the position of the main board, thereby improving the connectivity with the main board.

9B and 9C are views showing a modified example of the integrated flexible circuit board shown in FIG. 9A.

9B, a reinforcing portion 460 may be further disposed under the second soft region FA2 of the chip-on-film flexible circuit board 400. In addition, as shown in FIG. That is, the second soft area FA2 is connected to the main board and has a curvature according to the position of the main board. At this time, if the strength of the second soft area FA2 is weak, a short circuit may occur after connection with the main board. Further, if the strength of the second soft region FA2 is weak, a problem such as breakage of the circuit may occur. Accordingly, in the present invention, the reinforcing portion 460 is further disposed under the second soft region FA2, and the gkse

Further, as shown in FIG. 9C, the chip-on-film flexible circuit board 400 may form another layer without forming the core layer of the integrated flexible circuit board. In other words, as shown in FIG. 9C, the chip-on-film flexible circuit board 400 is disposed at the center of the integrated flexible circuit board, And may be disposed in an area other than the center of the substrate.

Referring to FIG. 9C, the laminated substrate 200 may be disposed only on the upper portion of the chip-on-film flexible circuit substrate 400, and the laminated substrate may not be disposed on the lower portion.

Alternatively, the laminated boards may be disposed on the upper and lower sides of the chip-on-film flexible circuit board 400, respectively. The number of the laminated boards disposed on the upper portion and the laminated board disposed on the lower portion, May be different from each other.

10 is a cross-sectional view of an integrated flexible printed circuit board according to a fifth embodiment of the present invention.

Referring to FIG. 10, the integrated flexible printed circuit board differs from the integrated flexible printed circuit board shown in FIG. 9 in the insulation layer material of the laminated board 200 disposed on the chip-on-film flexible printed circuit board 400. That is, in the previous embodiment including FIG. 9, at least one of the second insulating layer, the third insulating layer, and the fourth insulating layer constituting the laminated substrate 200 is formed of the rigid substrate.

However, in Fig. 10, all of the insulating layers constituting the laminated substrate may be a flexible substrate.

The laminated substrate 500 includes a first adhesive insulating layer 510 disposed on the upper surface and a lower surface of the first insulating layer 410 and a second adhesive insulating layer 510 disposed on the first adhesive insulating layer 510. A second insulating layer 530 disposed on the second insulating layer 520 and a third insulating layer 540 disposed on the second insulating layer 530. The second insulating layer 530 may be formed on the second insulating layer 520, . &Lt; / RTI &gt;

The first adhesive insulating layer 510 and the second adhesive insulating layer 530 may be an adhesive film for laminating the second insulating layer 520 and the third insulating layer 540.

The second insulating layer 520 and the third insulating layer 540 may be flexible polyimide films. That is, the second insulating layer 520 and the third insulating layer 540 may include the same material as the first insulating layer 410.

Therefore, according to the fifth embodiment of the present invention, the integrated flexible printed circuit board may be a softened area in which the laminated board 500 is disposed.

In addition, the laminated board 500 may be disposed only on the upper portion of the chip-on-film flexible circuit board 400, or may not be disposed on the lower portion thereof.

Alternatively, the laminated boards may be disposed on the upper and lower portions of the chip-on-film flexible circuit board 500, respectively. The number of the laminated boards disposed on the upper portion and the laminated board disposed on the lower portion, May be different from each other.

The integrated flexible printed circuit board according to the embodiment can realize a fine pitch conductive pattern on both sides of the chip on film flexible circuit board and can be suitable for an electronic device having a high resolution display portion.

In addition, the integrated flexible circuit board is flexible, small in size, and thin in thickness, so that it can be used in various electronic devices.

For example, referring to Fig. 11, the integrated flexible printed circuit board according to the embodiment can be used in an edge display since it can shrink the bezel.

For example, referring to FIG. 12, an integrated flexible circuit board according to an embodiment may be included in a flexible electronic device that is bent. Accordingly, the touch device device including the same may be a flexible touch device device. Therefore, the user can bend or bend by hand. Such a flexible touch window can be applied to a wearable touch or the like.

For example, referring to FIG. 13, an integrated flexible circuit board according to an embodiment can be applied to various electronic devices to which a foldable display device is applied. 13A to 13C, the folder-type display device can fold the folder-cover window. Foldable display devices can be included in a variety of portable electronic products. In detail, the folder-type display device can be included in a mobile terminal (mobile phone), a notebook (portable computer), and the like. Accordingly, while the display area of the portable electronic product is large, it is possible to reduce the size of the device when storing or moving the portable electronic device, thereby increasing the portability. Therefore, the convenience of the user of the portable electronic device can be improved. However, the embodiment is not limited thereto, and it goes without saying that the folder-type display device can be used for various electronic products.

Referring to FIG. 13A, the foldable display device may include one folded area in the screen area. For example, the foldable display device may have a C-shape in a folded configuration. That is, the folder-type display device may have one end and the other end opposite to the end. At this time, the one end and the other end may be disposed close to each other. For example, the one end and the other end may be disposed facing each other.

Referring to FIG. 13B, the foldable display device may include two folding regions in the screen region. For example, the foldable display device may have a G shape in a folded form. That is, the foldable display device can be superposed on each other as the one end and the other end opposite to the one end are folded in the directions corresponding to each other. At this time, the one end and the other end may be spaced apart from each other. For example, the one end and the other end may be arranged parallel to each other.

Referring to FIG. 13C, the foldable display device may include two folding regions in the screen region. For example, the foldable display device may have an S-shaped configuration in a folded configuration. That is, the folder-type display device can be folded at one end and the other end opposite to the one end in different directions. At this time, the one end and the other end may be spaced apart from each other. For example, the one end and the other end may be arranged parallel to each other.

In addition, although not shown in the drawing, it goes without saying that the integrated flexible printed circuit board according to the embodiment can be applied to a rollerable display.

Referring to FIG. 14, the integrated flexible circuit board according to the embodiment may be included in various wearable touch devices including a curved display. Therefore, the electronic device including the integrated flexible circuit board according to the embodiment can be made slimmer, smaller, or lighter.

Referring to FIG. 15, the integrated flexible circuit board according to the embodiment can be used in various electronic devices having a display portion such as a TV, a monitor, and a notebook.

However, the embodiment is not limited thereto, and it goes without saying that the integrated flexible circuit board according to the embodiment can be used in various electronic devices having a flat or curved display portion.

The integrated flexible printed circuit board according to the embodiment can mount different types of first chip and second chip on one substrate, thereby providing an integrated flexible circuit board chip package with improved reliability.

In addition, one integrated flexible circuit board according to the embodiment can directly connect the display panel and the main board. Accordingly, the size and thickness of the flexible circuit board for transmitting signals generated from the display panel to the main board can be reduced.

Accordingly, the integrated flexible circuit board according to the embodiment, and the chip package including the same, and the electronic device including the same can expand the space and / or the battery space of other parts.

In addition, since the integrated flexible printed circuit board according to the embodiment does not require connection of a plurality of printed circuit boards between the main board and the display panel in the electronic device, the convenience of the process and the reliability of the electrical connection can be improved.

Accordingly, the integrated flexible printed circuit board, the chip package including the integrated flexible circuit board, and the electronic device including the integrated flexible circuit board according to the embodiments may be suitable for an electronic device having a high-resolution display portion.

The features, structures, effects and the like described in the foregoing embodiments are included in at least one embodiment of the present invention and are not necessarily limited to one embodiment. Further, the features, structures, effects and the like illustrated in the embodiments can be combined and modified by other persons skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be construed as limiting the scope of the present invention. It can be seen that various modifications and applications are possible. For example, each component specifically shown in the embodiments may be modified and implemented. It is to be understood that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof.

Claims (15)

A first insulating layer including a first region and a second region;
A first circuit pattern layer disposed on the first region and the second region of the first insulating layer;
A first passivation layer disposed on the first region of the first insulating layer and including at least one open region;
A second insulating layer disposed on the second region of the first insulating layer;
A second circuit pattern layer disposed on the second insulating layer;
And a second protective layer disposed on the second insulating layer and including at least one open region,
Wherein the first circuit pattern layer comprises:
A plurality of first conductive patterns disposed on the first region of the first insulating layer,
And a plurality of second conductive patterns disposed on the second region of the first insulating layer,
The first conductive pattern may include:
A second conductive pattern having a smaller width than the second conductive pattern
Integrated flexible printed circuit board. The method according to claim 1,
The first conductive pattern may include:
Has a width that satisfies a range of 5 mu m or more and less than 20 mu m,
Wherein the second conductive pattern comprises a first conductive pattern,
Having a width satisfying the range of 20 or more and less than 50um
Integrated flexible printed circuit board. The method of claim 1,
Further comprising at least one first via penetrating said second insulating layer,
Wherein the second conductive pattern comprises a first conductive pattern,
A second-1 conductive pattern in direct contact with the via,
And a second-2 conductive pattern excluding the second-first conductive pattern,
The second conductive pattern (2-1)
The first conductive pattern having a width larger than that of the first conductive pattern
Integrated flexible printed circuit board. The method of claim 3,
The second conductive pattern (2-2)
Is equal to either the width of the first conductive pattern or the width of the second-1 conductive pattern
Integrated flexible printed circuit board. The method of claim 3,
The second conductive pattern (2-2)
A width of the second conductive pattern is larger than a width of the first conductive pattern,
Integrated flexible printed circuit board. The method according to claim 1,
The first conductive pattern may include:
A first conductive pattern disposed on the first open region of the first protective layer and on which the first chip is mounted,
A first conductive pattern disposed on a second open region of the first passivation layer and connected to the display panel,
The 1-1 conductive pattern may be formed by patterning,
And a second conductive pattern having a width smaller than the first conductive pattern
Integrated flexible printed circuit board. The method according to claim 6,
Wherein the second circuit pattern layer comprises:
A third conductive pattern disposed on a third open region of the second passivation layer and on which a second chip different from the first chip is mounted,
And a fourth conductive pattern disposed on a fourth open region of the second passivation layer and connected to the main board,
Integrated flexible printed circuit board. 8. The method of claim 7,
A first plating layer disposed on the first conductive pattern; And
And a second plating layer disposed on the third and fourth conductive patterns
Integrated flexible printed circuit board. 9. The method of claim 8,
Wherein the first and second plating layers are formed on the substrate,
(Au), silver (Ag), nickel (Ni), and nickel-chromium alloy (Ni-Cr)
Integrated flexible printed circuit board. 9. The method of claim 8,
Wherein the first and second plating layers comprise different metal materials,
The different metal materials may be,
(Ag) / tin (Sn), nickel (Ni) / tin (Sn), nickel-chromium alloy (Ni-Cr) / tin (Sn), nickel (Ni) (Au), gold (Au) / chrome (Cr), and a nickel-chromium alloy (Ni-Cr)
Integrated flexible printed circuit board. The method of claim 3,
Wherein the first circuit pattern layer comprises:
A first insulating layer disposed on the upper surface and the lower surface of the first insulating layer,
Further comprising second vias passing through the first insulating layer and connecting the first circuit pattern layers disposed on the top and bottom surfaces of the first insulating layer,
Wherein the second via comprises:
And a second via having a width smaller than that of the first via
Integrated flexible printed circuit board. 12. The method of claim 11,
Wherein the first via comprises:
Having a width that satisfies the range of 15um to less than 50um,
Wherein the second via comprises:
Having a width that satisfies the range of 50um or more and less than 200um
Integrated flexible printed circuit board. A first insulating layer including a first region and a second region; A first circuit pattern layer disposed on the first region and the second region of the first insulating layer; A first passivation layer disposed on the first region of the first insulating layer and including at least one open region; A second insulating layer disposed on the second region of the first insulating layer; A second circuit pattern layer disposed on the second insulating layer; An integrated flexible printed circuit board disposed on the second insulating layer and including a second protective layer including at least one open area;
A first chip disposed on a first open region of the first passivation layer; And
A second chip disposed on a second open region of the second protective layer and different from the first chip,
Wherein the first circuit pattern layer comprises:
A plurality of first conductive patterns disposed on the first region of the first insulating layer,
And a plurality of second conductive patterns disposed on the second region of the first insulating layer,
The first conductive pattern may include:
A second conductive pattern having a smaller width than the second conductive pattern
Chip package. 14. The method of claim 13,
A first connection portion is disposed on the first conductive pattern,
A second connection portion is disposed on the second circuit pattern layer,
Wherein the first chip is disposed on the first connection portion,
And the second chip is disposed on the second connection portion
Chip package. 15. The method of claim 14,
The first chip is a drive IC chip,
The second chip may be at least one of a diode chip, a power IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor
Chip package.

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