CN117651457A

CN117651457A - Display device and method of manufacturing the same

Info

Publication number: CN117651457A
Application number: CN202311138236.7A
Authority: CN
Inventors: 金桢晧; 康斯坦丁米什奇; 金亨植; 刘炅翰; 张昇勋; 黄势沿
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2022-09-05
Filing date: 2023-09-05
Publication date: 2024-03-05

Abstract

The present disclosure relates to a display device and a method of manufacturing a display device. The display device includes: a glass substrate comprising: a first surface; a second surface opposite to the first surface; and a side surface disposed between the first surface and the second surface; an outermost structure disposed on the first surface of the glass substrate and adjacent to an edge of the glass substrate; and a display layer including a plurality of emission regions on the first surface of the glass substrate, the plurality of emission regions being spaced apart from the edge. The side surface has a curved shape with an edge protruding to an outermost side of the glass substrate, the side surface includes a first side surface and a second side surface, the first side surface is disposed between the edge and the first surface, the second side surface is between the edge and the second surface and has a different curvature from the first side surface, and the glass substrate includes an edge region on the first surface adjacent to the edge and leaving a processing trace in the edge region.

Description

Display device and method of manufacturing the same

Technical Field

The present disclosure relates to a display device and a method of manufacturing a display device.

Background

As information society has developed, demands for display devices for displaying images have been diversified. Display devices have been applied to various electronic devices such as smart phones, digital cameras, notebook computers, navigation systems, and smart televisions. Here, the display device may be a flat panel display device such as a liquid crystal display ("LCD") device, a field emission display ("FED") device, or an organic light emitting diode ("OLED") display device. A light emitting display device among such flat panel display devices includes a light emitting element capable of causing pixels of the display device to emit light, and can thereby display an image without a backlight unit for supplying light to a display panel.

The display device includes a display area that displays an image, and a peripheral area (such as a non-display area surrounding the display area) around the display area. The width of the non-display area may be reduced to increase the immersion of the display area and the aesthetic appeal of the display device.

The display device may be obtained by cutting a mother substrate including a plurality of display units along the display units.

The non-display region of the display device may include a first non-display region in which wiring and circuits for driving the display region of the display device are disposed, and a second non-display region corresponding to a margin region for a cutting process during fabrication of the display device. Since there is a limitation in reducing wiring and circuits in the first non-display area, studies have been made to reduce the width of the second non-display area.

Disclosure of Invention

Features of the present disclosure provide a display device capable of minimizing a width of a non-display area and a method of fabricating the display device.

Features of the present disclosure also provide a display device capable of improving mechanical strength and a method of manufacturing the display device.

However, the features of the present disclosure are not limited to those set forth herein. The above and other features of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

In an embodiment of the present disclosure, a display device includes: a glass substrate comprising: a first surface; a second surface opposite the first surface; and a side surface disposed between the first surface and the second surface; an outermost structure disposed on the first surface of the glass substrate and adjacent to an edge of the glass substrate; and a display layer including a plurality of emissive regions on the first surface of the glass substrate, the plurality of emissive regions being spaced apart from the edge. The side surface has a curved shape, and the edge protrudes toward the outermost side of the glass substrate, the side surface includes a first side surface and a second side surface, the first side surface is disposed between the edge and the first surface, the second side surface is between the edge and the second surface and has a different curvature from the first side surface, and the glass substrate includes an edge region in the first surface, adjacent to the edge, and a processing trace is left in the edge region.

In an embodiment, the second side surface may have a radius of curvature of about 200 micrometers (μm) to about 300 μm.

In an embodiment, the length of the first side surface may be smaller than the length of the second side surface, and the second side surface may have a curvature that is gentler than the curvature of the first side surface.

In an embodiment, the width of the second side surface protruding from the end of the second side surface toward the edge may be about 10% to about 20% of the total thickness of the glass substrate.

In an embodiment, the width of the second side surface protruding from the end of the second side surface toward the edge may be about 20 μm to about 40 μm.

In an embodiment, the diameter of the glass hole defined in the first side surface may be smaller than the diameter of the glass hole defined in the second side surface.

In an embodiment, the diameter of the glass hole defined in the first side surface may be about 5 μm to about 30 μm, and the diameter of the glass hole defined in the second side surface may be about 30 μm to about 50 μm.

In embodiments, the vertical distance between the second surface and an imaginary plane passing through the edge and parallel to the second surface may be about 50% to about 60% of the total thickness of the glass substrate.

In an embodiment, the vertical distance may be about 100 μm to about 120 μm.

In an embodiment, the minimum distance between the edge of the glass substrate and the outermost structure may be about 130 μm or less.

In an embodiment, the width of the edge region may be about 50 μm or less.

In an embodiment, the display device may further include: and the packaging layer covers the display layer and the outermost structure. The encapsulation layer may include a first encapsulation inorganic film, an encapsulation organic film, and a second encapsulation inorganic film, the encapsulation organic film being disposed on the first encapsulation inorganic film, the second encapsulation inorganic film being disposed on the encapsulation organic film, and the first encapsulation inorganic film and the second encapsulation inorganic film may cover the outermost structure.

In an embodiment of the present disclosure, a method of fabricating a display device includes: preparing a mother substrate and forming a plurality of display units on a first surface of the mother substrate; defining cutting lines along the plurality of display elements by applying a laser to a second surface of the mother substrate, the second surface being opposite the first surface; and separating the substrate having the plurality of display units formed thereon by etching the second surface of the mother substrate along the cutting lines. The laser defines a plurality of laser points spaced apart from one another between the first and second surfaces of the master substrate, and the plurality of laser points define a trajectory having a curvature in a three-dimensional ("3D") space of the master substrate.

In an embodiment, the track may have a radius of curvature of about 500 μm.

In an embodiment, the processing region defining the plurality of laser spots may be formed in the mother substrate in a thickness direction of the mother substrate and may occupy about 95% to about 100% of the thickness of the mother substrate.

In an embodiment, the outermost curvature laser spot is a laser spot of the plurality of laser spots at an outermost portion of the track, which may be disposed from the second surface at a depth corresponding to about 30% of the thickness of the mother substrate.

In an embodiment, the processing region may be in a range of a depth of about 450 μm to about 500 μm in the thickness direction, the plurality of laser spots may be formed along the thickness direction, and the outermost curvature laser spot may be separated from the second surface by about 150 μm.

In an embodiment, the angle of incidence between the second surface and an imaginary line connecting the four laser points closest to the second surface may be 70 ° to 90 °, and the angle of emission between the first surface and an imaginary line connecting the four laser points closest to the first surface may be 35 ° to 40 °.

In an embodiment, a horizontal distance between the outermost curvature laser spot and a laser spot closest to the second surface of the four laser spots closest to the second surface may be about 10 μm to about 20 μm, and a horizontal distance between the outermost curvature laser spot and a laser spot closest to the first surface of the four laser spots closest to the first surface may be about 120 μm to about 150 μm.

In an embodiment, the laser may have a pulse energy of about 10 microjoules (μj) to about 500 μj, and each of the plurality of laser spots may have a length in a thickness direction of about 20 μm to about 25 μm.

According to the above and other embodiments of the present disclosure, unnecessary regions in the outer portion of the display panel may be minimized.

The fabrication of the display device includes a laser irradiation process and an etching process, and can thereby improve manufacturing efficiency.

It should be noted that the effects of the present disclosure are not limited to the effects described above, and other effects of the present disclosure will be apparent from the following description.

Drawings

The above and other features and aspects of the present disclosure will become more apparent by describing in detail embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a perspective view of an embodiment of a display device according to the present disclosure;

FIG. 2 is a plan view of an embodiment of a display panel according to the present disclosure;

FIG. 3 is a cross-sectional view taken along line I-I' of FIG. 1;

fig. 4 is a cross-sectional view of the display device of fig. 3 showing bending of a circuit board thereof;

FIG. 5 is a cross-sectional view of a display area of the display panel of FIG. 2;

fig. 6 is a plan view of region a of fig. 2;

FIG. 7 is a plan view of region B of FIG. 2;

FIG. 8 is a cross-sectional view taken along line II-II' of FIG. 6;

FIG. 9 is a cross-sectional view taken along line III-III' of FIG. 7;

fig. 10 is a cross-sectional view illustrating an edge portion of the substrate of fig. 8 or 9;

fig. 11 is a photomicrograph showing an edge portion of a substrate of the display panel of fig. 2;

fig. 12 is a photomicrograph showing a cut surface on an edge portion of a substrate of the display panel of fig. 11;

fig. 13 is an enlarged view of region C of fig. 8;

fig. 14 is an enlarged view of region D of fig. 9;

FIG. 15 is a flow chart illustrating an embodiment of a method of fabricating a display device according to the present disclosure;

fig. 16 to 20 are perspective views illustrating an embodiment of a method of manufacturing a display device according to the present disclosure of fig. 15;

fig. 21 and 22 are cross-sectional views showing an embodiment of a laser irradiation process as performed in the method of manufacturing a display device according to the present disclosure of fig. 15;

FIG. 23 is a graph illustrating an embodiment of a laser spot trajectory defined by a method of fabricating a display device according to the present disclosure;

fig. 24 is a photomicrograph showing laser spots formed on a master substrate along the laser spot trajectories of fig. 23;

fig. 25 to 27 are sectional views showing embodiments of an etching process and a cutting process as performed in the method of manufacturing a display device according to the present disclosure of fig. 15;

FIG. 28 is a cross-sectional view of another embodiment of a display panel according to the present disclosure;

fig. 29 is a cross-sectional view showing an embodiment of an etching process as performed during the fabrication of the display device of fig. 28;

FIG. 30 is a cross-sectional view of another embodiment of a display panel according to the present disclosure;

fig. 31 is a photomicrograph showing an edge portion of a substrate of the display panel of fig. 30;

fig. 32 is a plan view showing another embodiment of a non-display area of a display panel according to the present disclosure;

FIG. 33 is a cross-sectional view taken along line IV-IV' of FIG. 32; and

fig. 34 is a cross-sectional view of another embodiment of a display panel according to the present disclosure.

Detailed Description

Embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

It will also be understood that when a layer or substrate is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers or substrates may also be present. Like reference numerals refer to like components throughout the specification.

It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element discussed below could be termed a second element without departing from the teachings of the present invention. Similarly, a second element may also be referred to as a first element.

In view of the measurements in question and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), as used herein, "about" or "approximately" includes the stated values and is intended to be within the scope of acceptable deviation for the particular value as determined by one of ordinary skill in the art. For example, the term "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

Embodiments of the present disclosure will be described hereinafter with reference to the accompanying drawings.

Fig. 1 is a perspective view of an embodiment of a display device according to the present disclosure. Fig. 2 is a plan view of an embodiment of a display panel according to the present disclosure.

Referring to fig. 1 and 2, a display device 10 displaying a moving image or a still image may be used not only for portable electronic devices such as a mobile phone, a smart phone, a tablet personal computer ("PC"), a smart watch, a watch phone, a mobile communication terminal, an electronic notepad, an electronic book, a portable multimedia player ("PMP"), a navigation device, or an ultra mobile PC ("UMPC"), but also for various other products such as a television ("TV"), a notebook computer, a monitor, a billboard, or an internet of things ("IoT") device.

The display device 10 may be an organic light emitting display device using an organic light emitting diode ("OLED"), a quantum dot light emitting display device including a quantum dot light emitting layer, an inorganic light emitting display device including an inorganic semiconductor, or a subminiature light emitting diode ("LED") (such as a micro LED or nano LED) display device. The display device 10 will hereinafter be described as an organic light emitting display device, but the present disclosure is not limited thereto.

The display device 10 includes a display panel 100, a driver integrated circuit ("IC") 200, and a circuit board 300.

The display panel 100 may be formed in a quadrangular shape (e.g., a rectangular shape having a short side in a first direction (or X-axis direction) and a long side in a second direction (or Y-axis direction) in a plan view). The corners where the long sides and the short sides of the display panel 100 meet may be rounded to have a predetermined curvature, or the corners where the long sides and the short sides of the display panel 100 meet may be right-angled. The planar shape of the display panel 100 is not particularly limited, and the display panel 100 may be formed in various other shapes (such as another polygonal shape, a circular shape, or an elliptical shape).

The display panel 100 may be flat, but the present disclosure is not limited thereto. In one example, the display panel 100 may include curved portions disposed at opposite ends of the display panel 100 and having a uniform or varying curvature. The display panel 100 may be flexible (such as foldable, bendable, or rollable).

The display panel 100 may include a display area DA displaying an image and a non-display area NDA disposed around the display area DA.

The display area DA may define a large area of the display panel 100. The display area DA may be disposed in the middle of the display panel 100. Pixels including an emission area for displaying an image may be disposed in the display area DA.

The non-display area NDA may be disposed adjacent to the display area DA. The non-display area NDA may be an area outside the display area DA. The non-display area NDA may surround the display area DA. The non-display area NDA may be an edge area of the display panel 100.

The display pad PD may be disposed in the non-display area NDA to be connected to the circuit board 300. The display pad PD may be disposed along one edge of the display panel 100. In an embodiment, for example, the display pad PD may be disposed on the lower edge of the display panel 100.

The display pad PD may be an outermost structure disposed on an outermost portion of the display panel 100 along a lower edge of the display panel 100. The outermost structure may be a structure adjacent to an edge of the display panel 100. The outermost structure may be a structure for driving the display panel 100 or improving the function of the display panel 100.

The display panel 100 may include a first DAM1 (refer to fig. 6), a second DAM2 (refer to fig. 6), and a crack DAM CRD (refer to fig. 6).

The first DAM1 and the second DAM2 may be structures for preventing overflow of the encapsulation organic film (encapsulation organic film TFE2 of fig. 5) of the encapsulation layer (encapsulation layer ENC of fig. 4). The first DAM1 may surround the display area DA, and the second DAM2 may surround the first DAM1.

The crack dam CRD may be a structure for preventing propagation (propagation) of cracks in the inorganic film of the encapsulation layer ENC during cutting of the substrate SUB (refer to fig. 3) as performed during manufacturing of the display device 10. The slit dam CRD may be disposed along the left, upper and right edges of the display panel 100. The crack dam CRD may not be disposed on the lower edge of the display panel 100. The slit dam CRD may be an outermost structure disposed along the left, upper and right edges of the display panel 100.

The driver IC 200 may generate a data voltage, a power supply voltage, and a scan timing signal. The driver IC 200 may output a data voltage, a power supply voltage, and a scan timing signal.

The driver IC 200 may be disposed between the display pad PD and the display area DA. The driver ICs 200 may be attached to the non-display area NDA of the display panel 100 in a chip on glass ("COG") manner. In an alternative embodiment, the driver IC 200 may be attached to the non-display area NDA of the display panel 100 in a plastic flip chip ("COP") manner.

The circuit board 300 may be disposed on the display pad PD disposed along one edge of the display panel 100. The circuit board 300 may be attached to the display pad PD via a conductive adhesive member such as an anisotropic conductive film ("ACF") or an anisotropic conductive adhesive member. Accordingly, the circuit board 300 may be electrically connected to the signal wiring of the display panel 100. The circuit board 300 may be a flexible printed circuit board ("FPCB") or a flexible film such as a chip on film ("COF").

Fig. 3 is a sectional view taken along line I-I' of fig. 1. Fig. 4 is a cross-sectional view of the display device of fig. 3 showing bending of a circuit board thereof.

Referring to fig. 3 and 4, the display device 10 may include a display panel 100, a polarizing film PF, a cover window CW, and a panel bottom cover PB. The display panel 100 may include a substrate (e.g., a glass substrate) SUB, a display layer dis, an encapsulation layer ENC, and a sensor electrode layer SENL.

The substrate SUB may comprise or consist of glass.

The display layer dis may be formed on the first surface of the substrate SUB. The display layer dis may be a layer displaying an image. The display layer dis may include a thin film transistor layer TFTL (refer to fig. 5) in which a thin film transistor is formed and a light emitting element layer EML (refer to fig. 5) in which a light emitting element is disposed in an emission region.

Scan lines, data lines, and power lines for emitting light in the emission region may be disposed in the display region DA (refer to fig. 1) of the display layer dis. A scan driving circuit unit outputting a scan signal to a scan line, and a fanout line connecting a data line and the driver IC 200 may be disposed in the non-display area NDA (refer to fig. 1).

The encapsulation layer ENC may be a layer that encapsulates the light emitting element layer EML of the display layer dis to prevent oxygen or moisture from penetrating into the light emitting element layer EML of the display layer dis. The encapsulation layer ENC may be disposed on the display layer dis. The encapsulation layer ENC may be disposed on the upper surface and the side surfaces of the display layer dis. The encapsulation layer ENC may cover the display layer dis.

The sensor electrode layer SENL may be disposed on the display layer dis. The sensor electrode layer SENL may include a sensor electrode. The sensor electrode layer SENL may detect a touch input from a user through the sensor electrode.

The polarizing film PF may be disposed on the display panel 100 to reduce reflection of external light. The polarizing film PF may include a first base member, a linear polarizing plate, a phase retardation film such as a quarter wave (λ/4) plate, and a second base member. The first base member, the linear polarizing plate, the phase retardation film, and the second base member may be sequentially disposed on the display panel 100, but the present disclosure is not limited thereto. The polarizing film PF may be optional, and the display device 10 may include an antireflection structure including a color filter or a low reflection layer, or the like.

The cover window CW may be provided on the polarizing film PF. The cover window CW may be attached to the polarizing film PF via a transparent adhesive member such as an optically clear adhesive ("OCA") film.

The panel bottom cover PB may be disposed under the second surface of the substrate SUB of the display panel 100. The second surface of the substrate SUB may be opposite to the first surface of the substrate SUB. The panel bottom cover PB may be attached to the second surface of the substrate SUB of the display panel 100 via an adhesive member. The adhesive member may be a pressure sensitive adhesive ("PSA") member.

The panel bottom cover PB may include at least one of a light blocking member for absorbing light incident thereon from the outside, a buffer member for absorbing impact from the outside, and a heat dissipating member for effectively releasing heat from the display panel 100.

The light blocking member may be disposed under the display panel 100. The light blocking member may block transmission of light, and may thereby prevent components (such as the circuit board 300) disposed below the light blocking member from being visible from above the display panel 100. The light blocking member may include a light absorbing material such as a black pigment or a black dye.

The buffer member may be disposed under the light blocking member. The buffer member may absorb external impact and may thus prevent breakage of the display panel 100. The cushioning member may be formed as a single layer or as multiple layers. In an embodiment, the cushioning member may include or consist of a polymer resin (such as polyurethane, polycarbonate, polypropylene, or polyethylene) or an elastic material (such as a sponge obtained by foam molding a rubber, urethane-based material, or acrylic material), or a polymer resin (such as polyurethane, polycarbonate, polypropylene, or polyethylene) or an elastic material (such as a sponge obtained by foam molding a rubber, urethane-based material, or acrylic material).

The heat dissipation member may be disposed under the buffer member. The heat dissipation member may include a first heat dissipation layer including graphite or carbon nanotubes, and a second heat dissipation layer including or consisting of a metal capable of blocking electromagnetic waves and having excellent thermal conductivity, such as copper (Cu), nickel (Ni), ferrite, or silver (Ag).

As shown in fig. 4, the circuit board 300 may be bent toward the bottom of the display panel 100. The circuit board 300 may be attached to the lower surface of the panel bottom cover PB via an adhesive member 310. Adhesive member 310 may be a PSA member.

Fig. 5 is a cross-sectional view of a display area of the display panel of fig. 2.

Referring to fig. 5, the display panel 100 may be an organic light emitting display panel including a light emitting element LEL including an organic light emitting layer 172. Here and hereinafter, the display panel 100 may refer to fig. 2, for example.

The display layer dis may include a thin film transistor layer TFTL including a thin film transistor TFT and a light emitting element layer EML including a light emitting element LEL.

The first buffer film BF1 may be disposed on the substrate SUB. The first buffer film BF1 may include or consist of an inorganic material such as silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, or aluminum oxide. In an alternative embodiment, the first buffer film BF1 may be formed as a multi-layer film in which more than one layer among a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer is alternately stacked.

An active layer including a channel region TCH, a source region TS, and a drain region TD of the thin film transistor TFT may be disposed on the first buffer film BF 1. The active layer may include or consist of polysilicon, monocrystalline silicon, substantially low temperature polysilicon, amorphous silicon, or an oxide semiconductor material. In the case where the active layer includes polysilicon or an oxide semiconductor material, the source and drain regions TS and TD may be conductive regions doped with ions or impurities.

The gate insulating film 130 may be disposed on the active layer. The gate insulating film 130 may be formed as an inorganic film including a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

A first gate metal layer including the gate electrode TG of the thin film transistor TFT, the first capacitor electrode CAE1 of the capacitor Cst, and the scan line may be disposed on the gate insulating film 130. The gate electrode TG of the thin film transistor TFT may overlap the channel region TCH in the third direction (or the Z-axis direction). The first gate metal layer may be formed to include a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), ni, neodymium (Nd), cu, and any alloy thereof.

The first interlayer insulating film 141 may be disposed on the first gate metal layer. The first interlayer insulating film 141 may be formed as an inorganic film including a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first interlayer insulating film 141 may include a plurality of inorganic films.

A second gate metal layer including a second capacitor electrode CAE2 of the capacitor Cst may be disposed on the first interlayer insulating film 141. The second capacitor electrode CAE2 may overlap the first capacitor electrode CAE1 in a third direction (or Z-axis direction). Thus, the capacitor Cst may be formed of the first capacitor electrode CAE1, the second capacitor electrode CAE2, and an inorganic insulating dielectric film disposed between the first capacitor electrode CAE1 and the second capacitor electrode CAE 2. The second gate metal layer may be formed as a single layer or multiple layers including one of Mo, al, cr, au, ti, ni, nd, cu and any alloys thereof.

The second interlayer insulating film 142 may be disposed on the second gate metal layer. The second interlayer insulating film 142 may be formed as an inorganic film including a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating film 142 may include a plurality of inorganic films.

A first data metal layer including the first connection electrode CE1 and the data line may be disposed on the second interlayer insulating film 142. The first connection electrode CE1 may be connected to the drain region TD through a first contact hole CT1 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The first data metal layer may be formed as a single layer or multiple layers including one of Mo, al, cr, au, ti, ni, nd, cu and any alloys thereof.

The first organic film 160 may be disposed on the first connection electrode CE1 to planarize a step difference formed by the thin film transistor TFT. The first organic film 160 may be formed as an organic film including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

A second data metal layer including a second connection electrode CE2 may be disposed on the first organic film 160. The second data metal layer may be connected to the first connection electrode CE1 through the second contact hole CT2 penetrating the first organic film 160. The second data metal layer may be formed as a single layer or multiple layers including one of Mo, al, cr, au, ti, ni, nd, cu and any alloys thereof.

The second organic film 180 may be disposed on the second connection electrode CE2. The second organic film 180 may be formed as an organic film including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

The second data metal layer and the second organic film 180 may be optional.

The light emitting element layer EML is disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include light emitting elements LEL and banks 190.

Each of the plurality of light emitting elements LEL may include a pixel electrode 171, a light emitting layer 172, and a common electrode 173. The emission region EA refers to a region in which the pixel electrode 171, the light emitting layer 172, and the common electrode 173 are sequentially stacked such that holes from the pixel electrode 171 and electrons from the common electrode 173 are combined together in the light emitting layer 172 to emit light. In this case, the pixel electrode 171 may be an anode, and the common electrode 173 may be a cathode.

A pixel electrode layer including the pixel electrode 171 may be formed on the second organic film 180. The pixel electrode 171 may be connected to the second connection electrode CE2 through a third contact hole CT3 penetrating the second organic film 180. The pixel electrode layer may be formed as a single layer or a plurality of layers including one of Mo, al, cr, au, ti, ni, nd, cu and any alloy thereof.

In the top emission structure in which light is emitted in a direction from the light emitting layer 172 to the common electrode 173, the pixel electrode 171 may be formed as a single layer including Mo, ti, cu, or Al, or as a stack of Al and indium tin oxide ("ITO") (e.g., ITO/Al/ITO), a stack of silver (Ag) -palladium (Pd) -copper (Cu) ("APC") alloy, or a stack of APC alloy and ITO (e.g., ITO/APC/ITO).

The banks 190 define an emission area EA. For this, on the second organic film 180, the bank 190 may expose a portion of the pixel electrode 171. The bank 190 may cover an edge of each of the plurality of pixel electrodes 171. The bank 190 may be disposed in the third contact hole CT 3. That is, the third contact hole CT3 may be filled with the bank 190. The bank 190 may be formed as an organic film including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

Spacers 191 may be disposed on the banks 190. The spacers 191 may support the mask during formation of the light emitting layer 172. The spacer 191 may be formed as an organic film including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

The light emitting layer 172 is formed on the pixel electrode 171. The light emitting layer 172 may include an organic material, and may thus emit light of a specific color. In an embodiment, for example, the light emitting layer 172 may include a hole transporting layer, an organic material layer, and an electron transporting layer. The organic material layer may include a host and a dopant. The organic material layer may include a material capable of emitting light of a specific color, and may include or consist of a phosphorescent material or a fluorescent material.

The common electrode 173 is formed on the light emitting layer 172. The common electrode 173 may cover the light emitting layer 172. The common electrode 173 may be a common layer commonly formed in the plurality of emission areas EA. The capping layer may be formed on the common electrode 173.

In the top emission structure, the common electrode 173 may include or consist of a transparent conductive oxide ("TCO") (such as ITO or indium zinc oxide ("IZO")) or a semi-transmissive metal material (such as magnesium (Mg), ag, or any alloy thereof). In the case where the common electrode 173 includes or is composed of a semi-transmissive metal material, the emission efficiency of the light emitting element LEL may be improved due to the microcavity.

The encapsulation layer ENC may be formed on the light emitting element layer EML. The encapsulation layer ENC may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light emitting element layer EML. The encapsulation layer ENC may further include at least one organic film to protect the light emitting element layer EML from foreign substances such as dust. In an embodiment, for example, the encapsulation layer ENC may include a first encapsulation inorganic film TFE1, an encapsulation organic film TFE2, and a second encapsulation inorganic film TFE3.

The first encapsulation inorganic film TFE1 may be disposed on the common electrode 173, the encapsulation organic film TFE2 may be disposed on the first encapsulation inorganic film TFE1, and the second encapsulation inorganic film TFE3 may be disposed on the encapsulation organic film TFE 2. Each of the first and second encapsulation inorganic films TFE1 and TFE3 may be formed as a multilayer in which more than one layer among a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer is alternately stacked. The encapsulation organic film TFE2 may be formed as an organic film including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

The sensor electrode layer SENL is disposed on the encapsulation layer ENC. The sensor electrode layer SENL may include sensor electrodes TE and RE (i.e., drive electrodes TE and sense electrodes RE).

The second buffer film BF2 may be disposed on the encapsulation layer ENC. The second buffer film BF2 may include at least one inorganic film. In the embodiment, for example, the second buffer film BF2 may be formed as a multilayer in which more than one layer among a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer is alternately stacked. The second buffer film BF2 may be optional.

The first link BE1 may BE disposed on the second buffer film BF 2. The first connection BE1 may BE formed as a single layer including Mo, ti, cu, or Al, or as a stack of Al and ITO (e.g., ITO/Al/ITO), a stack of APC alloy, or a stack of APC alloy and ITO (e.g., ITO/APC/ITO).

The first sensor insulating film TINS1 may BE disposed on the first connection BE 1. The first sensor insulating film TINS1 may be formed as an inorganic film including a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

The sensor electrodes TE and RE (i.e., the driving electrode TE and the sensing electrode RE) may be disposed on the first sensor insulating film TINS 1. The dummy pattern may also be disposed on the first sensor insulating film TINS 1. In an embodiment, the test contact hole TCNT1 may be defined in the driving electrode TE.

The driving electrode TE, the sensing electrode RE, and the dummy pattern may not overlap the emission area EA. The driving electrode TE, the sensing electrode RE, and the dummy pattern may be formed as a single layer including Mo, ti, cu, or Al, or as a stack of Al and ITO (e.g., ITO/Al/ITO), a stack of APC alloy, or a stack of APC alloy and ITO (e.g., ITO/APC/ITO).

The second sensor insulating film TINS2 may be disposed on the driving electrode TE, the sensing electrode RE, and the dummy pattern. The second sensor insulating film TINS2 may include at least one of an inorganic film and an organic film. The inorganic film may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic film may include an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

Fig. 6 is a plan view of the area a of fig. 2. Fig. 6 shows a portion of the display area DA and the non-display area NDA on the right side of the display panel 100.

Referring to fig. 6, the display area DA may include a plurality of emission areas EA1, EA2, EA3, and EA4. The emission areas EA1, EA2, EA3, and EA4 may include a first emission area EA1 that emits light of a first color, second and fourth emission areas EA2 and EA4 that emit light of a second color, and a third emission area EA3 that emits light of a third color. In an embodiment, for example, the first color light may be red wavelength light in a wavelength range of about 600 nanometers (nm) to about 750nm, the second color light may be green wavelength light in a wavelength range of about 480nm to about 560nm, and the third color light may be blue wavelength light in a wavelength range of about 370nm to about 460 nm. However, the present disclosure is not limited to this example.

Fig. 6 shows that the second and fourth emission areas EA2 and EA4 emit light of the same color (i.e., second color light), but the present disclosure is not limited thereto. In alternative embodiments, the second and fourth emission areas EA2 and EA4 may emit different colors of light. In an embodiment, for example, the second emission area EA2 may emit the second color light, and the fourth emission area EA4 may emit the fourth color light.

Fig. 6 shows that the first, second, third, and fourth emission areas EA1, EA2, EA3, and EA4 have a quadrangular shape (e.g., a rectangular shape) in a plan view, but the present disclosure is not limited thereto. In alternative embodiments, the first, second, third, and fourth emission areas EA1, EA2, EA3, and EA4 may have various other shapes, such as polygonal shapes, circular shapes, or elliptical shapes other than quadrangular shapes (e.g., rectangular shapes).

The third emission area EA3 may have a maximum size, and the second emission area EA2 and the fourth emission area EA4 may have a minimum size. The second emission area EA2 and the fourth emission area EA4 may have the same size.

The second emission areas EA2 and the fourth emission areas EA4 may be alternately arranged in the first direction (or the X-axis direction). The second emission area EA2 may be arranged in a second direction (or Y-axis direction). The fourth emission area EA4 may be arranged in the second direction (or Y-axis direction). The fourth emission area EA4 may have a long side in the first oblique line direction and a short side in the second oblique line direction, and the second emission area EA2 may have a long side in the second oblique line direction and a short side in the first oblique line direction. The first diagonal direction may be a direction between the first direction (or X-axis direction) and the second direction (or Y-axis direction), and the second diagonal direction may be orthogonal to the first diagonal direction.

The first and third emission areas EA1 and EA3 may be alternately arranged in the first direction (or the X-axis direction). The first emission area EA1 may be arranged in the second direction (or Y-axis direction). The third emission area EA3 may be arranged in the second direction (or Y-axis direction). The first and third emission areas EA1 and EA3 may have square shapes in a plan view, but the present disclosure is not limited thereto. In this case, the first and third emission areas EA1 and EA3 may have two parallel sides in the first diagonal direction and two parallel sides in the second diagonal direction.

The non-display area NDA may include a first non-display area NDA1 and a second non-display area NDA2. The first non-display area NDA1 may be an area in which a structure for driving pixels in the display area DA is disposed. The second non-display area NDA2 may be disposed outside the first non-display area NDA 1. The second non-display area NDA2 may be an edge portion of the non-display area NDA. The second non-display area NDA2 may also be an edge portion of the display panel 100.

The scan driving circuit unit SDC, the first power line VSL, the first DAM1, and the second DAM2 may be disposed in the first non-display area NDA 1.

The scan driving circuit unit SDC may include a plurality of stages (stages) STA. The stage STA may be connected to a scan line extending in a first direction (or X-axis direction) in the display area DA. That is, the stages STA may be connected one-to-one to scan lines extending in the first direction (or X-axis direction) in the display area DA. The stage STA may sequentially apply a scan signal to the scan lines.

The first power line VSL may be disposed outside the scan driving circuit unit SDC. That is, the first power line VSL may be disposed closer to the edge EG of the display panel 100 than the scan driving circuit unit SDC. In the non-display area NDA of the left side of the display panel 100, the first power line VSL may extend in the second direction (or Y-axis direction).

The first power line VSL may be electrically connected to the common electrode 173 (refer to fig. 5), and thus, the common electrode 173 may receive the first power voltage from the first power line VSL.

The first DAM1 and the second DAM2 may be structures for preventing the encapsulation organic film TFE2 (refer to fig. 5) of the encapsulation layer ENC (refer to fig. 5) from overflowing the edge EG of the display panel 100. On the right side of the display panel 100, the first DAM1 and the second DAM2 may extend in a second direction (or Y-axis direction) in the non-display area NDA. The second DAM2 may be disposed outside the first DAM 1. The first DAM1 may be disposed closer to the scan driving circuit unit SDC than the second DAM2, and the second DAM2 may be disposed closer to the edge EG of the display panel 100 than the first DAM 1.

Fig. 6 illustrates that the first DAM1 and the second DAM2 are disposed on the first power line VSL, but the present disclosure is not limited thereto. In an embodiment, for example, one of the first DAM1 and the second DAM2 may not be disposed on the first power line VSL. In another embodiment, neither the first DAM1 nor the second DAM2 may be disposed on the first power line VSL, in which case the first DAM1 and the second DAM2 may be disposed outside the first power line VSL.

Fig. 6 illustrates that the display panel 100 includes two DAMs (i.e., a first DAM1 and a second DAM 2), but the present disclosure is not limited thereto. In alternative embodiments, the display panel 100 may include three or more dams in some embodiments.

The first power line VSL may be a first external structure disposed in the first non-display area NDA 1. The first external structure may be disposed farther from the edge EG of the display panel 100 than the outermost structure (e.g., the crack dam CRD). That is, the distance between the first power line VSL, which is the first external structure, and the edge EG of the display panel 100 may be greater than the distance between the outermost structure and the edge EG of the display panel 100.

The distance between the first power line VSL and the edge EG of the display panel 100 may be smaller at the left or right side of the display panel 100 than at the upper side of the display panel 100. In an embodiment, for example, the distance between the first power line VSL and the edge EG of the display panel 100 may be about 160 micrometers (μm) or less on the left or right side of the display panel 100, and about 445 μm or less on the upper side of the display panel 100.

The second DAM2 may be a second external structure disposed in the first non-display area NDA 1. The second external structure may be disposed closer to the edge EG of the display panel 100 than the first external structure. That is, the distance between the second DAM2 as the second external structure and the edge EG of the display panel 100 may be smaller than the distance between the first power line VSL as the first external structure and the edge EG of the display panel 100.

The distance between the second DAM2 and the edge EG of the display panel 100 may be smaller at the left or right side of the display panel 100 than at the upper side of the display panel 100. In an embodiment, for example, the distance between the second DAM2 and the edge EG of the display panel 100 may be about 220 μm or less at the left side of the display panel 100, and the distance between the second DAM2 and the edge EG of the display panel 100 may be about 445 μm or less at the upper side of the display panel 100.

The display device 10 may further include a crack dam CRD provided in the outermost portion of the display panel 100. The crack dam CRD may be a structure for preventing cracks during cutting of the substrate SUB (for example, refer to fig. 5) as performed during manufacturing of the display device 10. The crack dam CRD may be an outermost structure disposed at the outermost side of the display panel 100. At the outermost side of the display panel 100, the crack DAM CRD may surround the second DAM2. In an embodiment, for example, on the left side of the display panel 100, the crack dam CRD may extend in the second direction (or Y-axis direction) in the non-display area NDA. The crack DAM CRD in the second non-display area NDA2 may be disposed closer to the edge EG than the second DAM2, and may be disposed between the second DAM2 and the edge area EGA. Here and hereinafter, the display device 10 may refer to fig. 1, for example.

The second non-display area NDA2 may include an edge area EGA. The edge region EGA may be disposed along an edge EG of the display panel 100. The edge area EGA may be an area in which a processing trace is left from the dicing of the substrate SUB.

Fig. 7 is a plan view of region B of fig. 2. Fig. 7 shows a portion of the non-display area NDA of the lower side of the display panel 100.

Referring to fig. 7, the first non-display area NDA1 may include a plurality of display pads PD, a plurality of first driving pads DPD1, a plurality of second driving pads DPD2, a plurality of pad lines PDL, a plurality of fan-out lines FL, a first DAM1, and a second DAM2.

The display pad PD may be electrically connected to the circuit board 300 via a conductive adhesive member such as an ACF or an anisotropic conductive adhesive member (for example, refer to fig. 4). The display pad PD may be connected to a pad line PDL. The pad line PDL may connect the display pad PD and the first driving pad DPD1.

The first and second driving pads DPD1 and DPD2 may be electrically connected to the driver IC 200 (for example, refer to fig. 2) via a conductive adhesive member such as an ACF or an anisotropic conductive adhesive member. The first driving pad DPD1 may be an input pad for causing the driver IC 200 to receive a signal (e.g., digital video data or a data timing control signal) from the circuit board 300. The second driving pad DPD2 may be an output pad for outputting a signal (e.g., a data voltage) from the driver IC 200. The second driving pad DPD2 may be connected to the fanout line FL. The fanout line FL may connect the second driving pad DPD2 and the data line in the display area DA (for example, refer to fig. 2).

The first driving pad DPD1 may be disposed closer to the display area DA than the display pad PD in the second direction (or Y-axis direction). That is, the display pad PD connected to the first driving pad DPD1 may be disposed closer to the edge EG of the display panel 100 than the first driving pad DPD1 in the second direction (or Y-axis direction).

The second driving pad DPD2 may be disposed closer to the display area DA than any one of the plurality of first driving pads DPD1 in the second direction (or Y-axis direction). That is, the first driving pad DPD1 may be disposed closer to the edge EG of the display panel 100 than any one of the plurality of second driving pads DPD2 in the second direction (or Y-axis direction).

The first DAM1 and the second DAM2 may intersect the fan-out line FL. On the lower side of the display panel 100, the first DAM1 and the second DAM2 may extend in a first direction (or X-axis direction) in the non-display area NDA. The second DAM2 may be disposed outside the first DAM 1. The first DAM1 may be disposed closer to the display area DA than the second DAM2, and the second DAM2 may be disposed closer to the edge EG of the display panel 100 than the first DAM 1.

Fig. 8 is a sectional view taken along line II-II' of fig. 6. Fig. 9 is a sectional view taken along line III-III' of fig. 7.

Fig. 8 and 9 show a cross section of the display panel 100 when the substrate SUB of the display panel 100 is cut by applying strong light (e.g., laser) and spraying an etchant during manufacturing of the display panel 100.

Referring to fig. 8 and 9, the edge area EGA may be an area in which a processing trace is defined by a laser applied to cut the substrate SUB. In cross section, the edge region EGA may have a width of about 50 μm in the horizontal direction. An edge region EGA having a width of about 50 μm may be formed along an edge EG of the display panel 100.

The substrate SUB of the display panel 100 may have an upper surface (first surface) US, a lower surface (second surface) BS opposite to the upper surface US, and side surfaces SS1 and SS2, the light emitting element layer EML being disposed on the upper surface US, the side surfaces SS1 and SS2 extending to or from the upper surface US and the lower surface BS and being curved. The substrate SUB of the display panel 100 may include an edge EG, which is an outermost protruding portion on the side surfaces SS1 and SS2, and the side surfaces SS1 and SS2 may include a first side surface SS1 and a second side surface SS2, the first side surface SS1 being between the edge EG and the upper surface US, and the second side surface SS2 being between the edge EG and the lower surface BS.

The substrate SUB may be cut out from a mother substrate (mother substrate MSUB of fig. 16) by a laser irradiation process and an etching process during fabrication of the display device 10. Here, the shape of the side surfaces SS1 and SS2 of the substrate SUB of the display panel 100 may be controlled by designing the position of the laser SPOT (laser SPOT of fig. 22) to which the laser on the mother substrate MSUB is applied. During cutting of the substrate SUB from the mother substrate MSUB, the laser spot may form a curved shape in a three-dimensional ("3D") space, and as a result, the side surfaces SS1 and SS2 of the substrate SUB may have a curved shape.

The laser irradiation process and the etching process may be performed from one side of the mother substrate MSUB. The side surfaces SS1 and SS2 of the substrate SUB may include a side surface adjacent to a surface of the substrate SUB on which the laser irradiation process and the etching process are performed and a side surface adjacent to another surface of the substrate SUB on which the laser irradiation process and the etching process are not performed. During manufacturing of the display device 10, a laser irradiation process and an etching process may be performed on the lower surface BS of the substrate SUB, and the side surfaces SS1 and SS2 of the substrate SUB may include first and second side surfaces SS1 and SS2 of the substrate SUB adjacent to the upper and lower surfaces US and BS, respectively. During cutting of the substrate SUB, the first and second side surfaces SS1 and SS2 may have different exposed levels for the laser irradiation process and the etching process, and both the first and second side surfaces SS1 and SS2 may have curvatures, but have shapes different from each other.

Fig. 10 is a cross-sectional view illustrating an edge portion of the substrate of fig. 8 or 9. Fig. 11 is a photomicrograph showing an edge portion of a substrate of the display panel of fig. 2.

Referring to fig. 10 and 11 and further referring to fig. 8 and 9, the substrate SUB of the display panel 100 may include an edge EG as an outermost portion of the substrate SUB, and may have a first side surface SS1 and a second side surface SS2, the first side surface SS1 being between the edge EG and the upper surface US, and the second side surface SS2 being between the edge EG and the lower surface BS. The first and second side surfaces SS1 and SS2 may have curvature, and the first and second side surfaces SS1 and SS2 may be curved from the end of the upper surface US or the lower surface BS toward the edge EG. The curvatures of the first side surface SS1 and the second side surface SS2 may vary according to the design of the laser SPOT (refer to fig. 22) in the laser irradiation process (e.g., the position of the laser SPOT and the distance between the laser SPOTs). The edge EG may not be provided at the center (in the thickness direction) of the substrate SUB, but may be closer to the upper surface US than to the lower surface BS. As a result, the first side surface SS1 and the second side surface SS2 may have lengths different from each other. In an embodiment, for example, the length of the first side surface SS1 may be smaller than the length of the second side surface SS2, and the curvature of the first side surface SS1 may be greater than the curvature of the second side surface SS 2. That is, the second side surface SS2 may have a gentle curvature than the first side surface SS 1.

The second side surface SS2 may have a radius of curvature of about 200 μm to about 300 μm, about 220 μm to about 260 μm, or about 240 μm. The width W1 of the second side surface SS2 protruding from the end of the lower surface BS (i.e., the lower end of the second side surface SS 2) toward the edge EG may be about 10% to about 20% of the total thickness of the substrate SUB. In embodiments where the total thickness of the substrate SUB is about 200 μm, the width W1 may be about 20 μm to about 40 μm or about 30 μm. In some embodiments, the width W1 may be about 27.01 μm. The second side surface SS2 adjacent to the lower surface BS where the display unit DPC is not provided (for example, refer to fig. 17) may have a gentle curvature than the first side surface SS1, and may reinforce the impact resistance of the substrate SUB.

When the side surfaces SS1 and SS2 are not parallel to the upper and lower surfaces US and BS, but are orthogonal to or inclined with respect to the upper and lower surfaces US and BS, the substrate SUB of the display panel 100 may weakly resist external impact. To solve this problem, the display device 10 may have side surfaces SS1 and SS2 having relatively gentle curvatures with respect to the upper surface US and the lower surface BS, and may thus be robustly resistant to external impact. The shape of the side surfaces SS1 and SS2 may vary depending on the conditions for the laser irradiation process and the etching process. As will be described later.

The vertical distance H1 between the lower surface BS and an imaginary plane passing through the edge EG and parallel to the lower surface BS may be about 50% to about 60% of the total thickness of the substrate SUB. In an embodiment, for example, in the case where the total thickness of the substrate SUB is about 200 μm, the vertical distance H1 may be about 100 μm to about 120 μm or about 110 μm. In an embodiment, for example, the vertical distance H1 may be about 109.2 μm. The position of the edge EG may vary depending on the design of the laser SPOT to which the laser is to be applied during cutting of the substrate SUB and the conditions for the etching process to be performed after the laser irradiation process.

During cutting of the substrate SUB, an etching process following the laser irradiation process may be performed on the lower surface BS of the substrate SUB. During the etching process, the substrate SUB may be cut out from the mother substrate MSUB along a region irradiated with the laser (for example, refer to fig. 16), and the surface shapes of the side surfaces SS1 and SS2 of the substrate SUB may vary depending on a direction in which the mother substrate MSUB is etched.

Fig. 12 is a photomicrograph showing a cut surface on an edge portion of a substrate of the display panel of fig. 11. Fig. 12 shows side surfaces SS1 and SS2 (refer to fig. 10, for example) as cut surfaces of the substrate SUB (refer to fig. 10, for example).

Referring to fig. 12 in combination with fig. 1, 8, 9, 10 and 16, the substrate SUB of the display panel 100 may be a glass substrate, and portions of the side surfaces SS1 and SS2 adjacent to the upper surface US or the lower surface BS may have different surface shapes. During cutting the substrate SUB, the etching process may cut the substrate SUB from the mother substrate MSUB along a region to which laser is applied during the laser irradiation process, and may form glass holes in the surface of the substrate SUB. The size (diameter) of the glass hole may be reduced depending on the direction in which the etching process is performed after the laser irradiation process.

The etching process may be performed in a direction from the lower surface BS to the upper surface US of the substrate SUB, and the size of the glass hole may be larger near the lower surface BS than near the upper surface US. In an embodiment, for example, the average size of the glass holes formed in the portion of the second side surface SS2 adjacent to the lower surface BS may be larger than the average size of the glass holes formed in the portion of the first side surface SS1 adjacent to the upper surface US.

The size of the glass hole in the portion of the second side surface SS2 adjacent to the lower surface BS may be larger than the size of the glass hole in the portion of the second side surface SS2 near the edge EG. In addition, the size of the glass hole in the portion of the first side surface SS1 near the edge EG may be larger than the size of the glass hole in the portion of the first side surface SS1 adjacent to the upper surface US. The size of the glass pores may increase in a direction from the upper surface US to the lower surface BS. The average size of the glass pores in the first side surface SS1 may be about 5 μm to about 30 μm, and the average size of the glass pores in the second side surface SS2 may be about 30 μm to about 50 μm. Referring to fig. 12, the substrate SUB may have a surface shape similar to that of the second side surface SS2 near the lower surface BS and a surface shape similar to that of the first side surface SS1 near the upper surface US. The substrate SUB may have curved side surfaces SS1 and SS2, and glass holes are formed in the curved side surfaces SS1 and SS2 as traces from the fabrication of the substrate SUB.

However, the present disclosure is not limited thereto. In an alternative embodiment, during cutting of the substrate SUB, an etching process may be performed on both the upper surface US and the lower surface BS. In this case, the lengths and curvatures of the first and second side surfaces SS1 and SS2 and the sizes of the glass holes formed in the first and second side surfaces SS1 and SS2 may be different from those of the first and second side surfaces SS1 and SS2 described above and the sizes of the glass holes formed in the first and second side surfaces SS1 and SS 2.

The crack dam CRD may be a structure for preventing cracks during cutting of the substrate SUB. The slit dam CRD may be an outermost structure disposed at the outermost side of the display panel 100 from the left side of the display panel 100. The distance between the crack dam CRD and the edge area EGA may be about 30 μm or less. The distance between the crack dam CRD and the edge area EGA may be about 0 μm.

The distance between the edge EG of the display panel 100 and the encapsulation layer ENC may be about 300 μm or less. In the case of cutting the substrate SUB by applying a laser and then spraying an etchant, the distance between the edge EG of the display panel 100 and the encapsulation layer ENC may vary depending on a unidirectional tolerance of the laser. In an embodiment, for example, when the unidirectional tolerance of the laser is about 50 μm, the distance between the edge EG of the display panel 100 and the encapsulation layer ENC may be about 200 μm or less, but the present disclosure is not limited thereto. In an alternative embodiment, the distance between the edge EG of the display panel 100 and the encapsulation layer ENC may be about 0 μm.

The distance D1 (refer to fig. 8) between the crack dam CRD and the edge EG may be about 130 μm, and the distance between the crack dam CRD and the edge area EGA may be about 80 μm. The minimum distance between the crack dam CRD as the outermost structure and the edge EG of the display panel 100 may vary depending on the width of the edge area EGA and the minimum distance between the crack dam CRD and the edge area EGA.

In the case of cutting the substrate SUB by applying a laser and then spraying an etchant, the distance D1 between the crack dam CRD and the edge EG of the display panel 100 may vary depending on a unidirectional tolerance of the laser. In this case, the distance D1 between the crack dam CRD and the edge EG of the display panel 100 may be the sum of the width of the edge area EGA, the minimum distance between the crack dam CRD and the edge area EGA, and the unidirectional tolerance of the laser. In an embodiment, for example, when the minimum distance between the crack dam CRD and the edge area EGA is designed to be about 30 μm or less, the minimum distance between the crack dam CRD and the edge area EGA may be at most about 80 μm or less because the unidirectional tolerance of the laser is about 50 μm. In an alternative embodiment, the minimum distance between the crack dam CRD and the edge area EGA may be about 0 μm.

Similarly, when the minimum distance between the crack dam CRD and the edge area EGA is designed to be about 30 μm or less and the width of the edge area EGA is designed to be about 50 μm, the distance D1 between the crack dam CRD and the edge EG may be at most about 130 μm or less because the unidirectional tolerance of the laser is about 50 μm. The distance D1 between the crack dam CRD and the edge EG will be described in further detail later in connection with how the display device 10 is fabricated.

The display pad PD may be an outermost structure provided at the outermost side of the display panel 100 at the lower side of the display panel 100. On the lower side of the display panel 100, a distance D2 (refer to fig. 9) between the edge EG of the display panel 100 and the encapsulation layer ENC may be about 300 μm or less. However, since the display pad PD is disposed at the lower side of the display panel 100, a distance D2 between the edge EG of the left side, the right side, or the upper side of the display panel 100 and the encapsulation layer ENC may be smaller than a distance D2 between the edge EG of the lower side of the display panel 100 and the encapsulation layer ENC. The minimum distance between the edge EG and the display pad PD may be about 80 μm or less.

The minimum distance between the edge EG of the substrate SUB and the display pad PD may be a sum of the width of the edge area EGA and the minimum distance between the edge area EGA and the display pad PD. In the case of cutting the substrate SUB by applying a laser and then spraying an etchant, the minimum distance between the edge EG of the substrate SUB and the display pad PD may vary depending on a unidirectional tolerance of the laser. In an embodiment, for example, when the minimum distance between the edge EG of the substrate SUB and the display pad PD is designed to be about 80 μm, the minimum distance between the edge EG of the substrate SUB and the display pad PD may be about 130 μm or less because the unidirectional tolerance of the laser is about 50 μm.

The substrate SUB of the display panel 100 may be cut by applying a laser and then spraying an etchant, and the first and second side surfaces SS1 and SS2 of the display panel 100 may be etched by the etchant. The first and second side surfaces SS1 and SS2 of the display panel 100 may have a roughness of about 0.5 μm or less. The roughness of the first and second side surfaces SS1 and SS2 of the display panel 100 may be smaller when the substrate SUB is cut by applying a laser and then spraying an etchant than when the substrate SUB is cut with a cutting member and then polished.

As already mentioned above, since the etching process is performed from the lower surface BS of the substrate SUB during the cutting of the substrate SUB, the first and second side surfaces SS1 and SS2 of the display panel 100 may have different levels of exposure to the etchant. As a result, the first side surface SS1 and the second side surface SS2 may have different roughness. In embodiments, for example, the roughness of the first side surface SS1 and the second side surface SS2 may differ by as much as about 1% to about 20%.

Fig. 13 is an enlarged view of the area C of fig. 8. Fig. 13 shows a sectional structure of the right side portion of the display panel 100.

Referring to fig. 13 and in combination with fig. 2, 5 and 8, the first power line VSL may include the same material as that of the first data metal layer including the first connection electrode CE1 and the data line, and may be disposed in the same layer as the first data metal layer. The first power line VSL may be disposed on the second interlayer insulating film 142. The first power line VSL may be formed as a single layer or a plurality of layers including one of Mo, al, cr, au, ti, ni, nd, cu and any alloy thereof.

The first DAM1 and the second DAM2 may be disposed on the first power line VSL. The first DAM1 may include a first sub-DAM SDAM1 and a second sub-DAM SDAM2, and the second DAM2 may include a first sub-DAM SDAM1, a second sub-DAM SDAM2, and a third sub-DAM SDAM3. The first sub-dam SDAM1 may include the same material as that of the first organic film 160, and may be disposed in the same layer as the first organic film 160. The second sub-dam SDAM2 may include the same material as that of the second organic film 180, and may be disposed in the same layer as the second organic film 180. The third sub-dam SDAM3 may include the same material as that of the bank 190, and may be disposed in the same layer as the bank 190.

The height of the first DAM1 may be smaller than the height of the second DAM2, but the present disclosure is not limited thereto. In alternative embodiments, the height of the first DAM1 may be substantially the same as the height of the second DAM2, or greater than the height of the second DAM 2.

The common electrode 173 may be connected to an uncovered portion of the first power line VSL but exposed by the first organic film 160, the second organic film 180, and the first DAM 1. Accordingly, the common electrode 173 may receive the first power supply voltage from the first power supply line VSL.

The first encapsulation inorganic film TFE1 may cover the first DAM1, the second DAM2, and the crack DAM CRD in a portion of the non-display area NDA of the left side of the display panel 100. The first encapsulation inorganic film TFE1 may extend from a portion of the non-display area NDA of the lower side of the display panel 100 to an edge EG of the display panel 100.

The encapsulation organic film TFE2 may cover the top surface of the first DAM1, but not the top surface of the second DAM2, but the disclosure is not limited thereto. In alternative embodiments, the encapsulation organic film TFE2 may not cover both the top surface of the first DAM1 and the top surface of the second DAM 2. The encapsulation organic film TFE2 may not overflow the edge EG of the display panel 100 due to the first DAM1 and the second DAM 2.

The second encapsulation inorganic film TFE3 may cover the first DAM1, the second DAM2, and the crack DAM CRD in a portion of the non-display area NDA of the left side of the display panel 100. The second encapsulation inorganic film TFE3 may extend to an edge EG of the display panel 100 in a portion of the non-display area NDA of the left side of the display panel 100.

The inorganic encapsulation area where the first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3 contact each other may range from the second DAM2 to the edge EG of the display panel 100. The inorganic encapsulation area may surround the second DAM2. Since the encapsulation layer ENC extends to the edge EG and the display panel 100 includes the crack dam CRD provided in the outer portion of the display panel 100, reliability can be ensured in the region where the inorganic film in the display panel 100 is directly provided on the substrate SUB. The first and second encapsulation inorganic films TFE1 and TFE3 of the encapsulation layer ENC may extend to an edge EG of the display panel 100, and the edge region EGA may overlap the encapsulation layer ENC.

The crack dam CRD may include the same material as that of the first organic film 160 and may be disposed on the first buffer film BF1, but the present disclosure is not limited thereto. In an alternative embodiment, the crack dam CRD may be disposed on the second interlayer insulating film 142 like the first organic film 160. The slit dam CRD may be formed as an organic film including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The width of the crack dam CRD may be about 30 μm.

Fig. 13 shows that the crack dam CRD includes one organic film, but the present disclosure is not limited thereto. In an alternative embodiment, the crack dam CRD may further include another organic film including the same material as that of the second organic film 180. In an alternative embodiment, the crack dam CRD may further include another organic film including the same material as that of the bank 190. In an alternative embodiment, the crack dam CRD may further include another organic film including the same material as that of the spacer 191.

Fig. 13 shows a scanning thin film transistor STFT of the scanning driving circuit unit SDC. In an embodiment, the scanning thin film transistor STFT may include a source region STS, a channel region STCH, a gate electrode STG, and a drain region STD. The scanning thin film transistor STFT is substantially the same as the thin film transistor TFT described above with reference to fig. 5, and thus, a detailed description thereof will be omitted.

Fig. 14 is an enlarged view of the area D of fig. 9. Fig. 14 shows a cross-sectional structure of a lower portion of the display panel 100.

Referring to fig. 14 and in combination with fig. 4, 5 and 6, each of the display pad PD, the first driving pad DPD1 and the second driving pad DPD2 may include a first sub-pad SPD1, a second sub-pad SPD2 and a third sub-pad SPD3.

The first sub-pad SPD1 may include the same material as that of the first gate metal layer including the gate electrode TG, the first capacitor electrode CAE1 of the capacitor Cst, and the scan line, and may be disposed in the same layer as the first gate metal layer. The first sub-pad SPD1 may be disposed on the gate insulating film 130. The first sub-pad SPD1 may be formed as a single layer or a plurality of layers including one of Mo, al, cr, au, ti, ni, nd, cu and any alloy thereof.

The second sub-pad SPD2 may include the same material as that of the second gate metal layer including the second capacitor electrode CAE2, and may be disposed in the same layer as the second gate metal layer. The second sub-pad SPD2 may be disposed on the first interlayer insulating film 141. The second sub-pad SPD2 may be formed as a single layer or a plurality of layers including one of Mo, al, cr, au, ti, ni, nd, cu and any alloy thereof.

The third sub-pad SPD3 may include the same material as that of the first data metal layer including the first connection electrode CE1 and the data line, and may be disposed in the same layer as the first data metal layer. The third sub-pad SPD3 may be disposed on the second interlayer insulating film 142. The third sub-pad SPD3 may be formed as a single layer or a plurality of layers including one of Mo, al, cr, au, ti, ni, nd, cu and any alloy thereof.

The third sub-pad SPD3 of the display pad PD may be electrically connected to the circuit board 300 via a conductive adhesive member such as an ACF or an anisotropic conductive adhesive member. The third sub-pad SPD3 of the first drive pad DPD1 may be electrically connected to the input bump of the driver IC 200 via a conductive adhesive member such as an ACF or an anisotropic conductive adhesive member. The third sub-pad SPD3 of the second drive pad DPD2 may be electrically connected to the output bump of the driver IC 200 via a conductive adhesive member such as an ACF or an anisotropic conductive adhesive member. For convenience, the driver IC 200 and the circuit board 300 are not shown in fig. 14.

On the lower side of the display panel 100, the first and second encapsulation inorganic films TFE1 and TFE3 may cover a portion of the first DAM1 and the second DAM 2. In an embodiment, for example, the first and second encapsulation inorganic films TFE1 and TFE3 may be disposed so as not to cover a portion of the top surface of the second DAM 2. In an alternative embodiment, the first and second encapsulation inorganic films TFE1 and TFE3 may cover the second DAM2, but not the third sub-pad SPD3 of the second drive pad DPD2. That is, on the lower side of the display panel 100, the first and second encapsulation inorganic films TFE1 and TFE3 may not extend to the display pad PD, the first and second driving pads DPD1 and DPD2 disposed adjacent to the edge EG of the display panel 100.

The fabrication of the display device 10 will be described hereinafter.

Fig. 15 is a flowchart illustrating an embodiment of a method of fabricating a display device according to the present disclosure.

Referring to fig. 15, the method may include: preparing a mother substrate (mother substrate MSUB of fig. 16) and forming a plurality of display units (display units DPC of fig. 16) on one surface (first surface) of the mother substrate (S100); forming cutting lines (cutting lines LS of fig. 17) along the plurality of display units by applying laser light (laser light LR of fig. 17) to the other surface (second surface) of the mother substrate (S200); and separating the substrate (substrate SUB of fig. 19) having the plurality of display units formed thereon by etching the other surface of the mother substrate along the cutting lines LS (S300).

The display device 10 may be formed by separating a substrate having the display units DPC formed thereon from a mother substrate MSUB forming a plurality of display units DPC. Separating the substrate SUB from the mother substrate MSUB may involve applying a laser and separating the substrate SUB by etching the mother substrate MSUB. The display device 10 can be manufactured by performing a laser irradiation process, and the size of the boundary portion of the substrate SUB where the display unit DPC is not provided can be minimized. The side surface of the substrate SUB cut out from the mother substrate MSUB may be curved by designing the position of a laser SPOT (laser SPOT of fig. 22) in the laser irradiation process. Accordingly, the substrate SUB of the display panel 100 of the display device 10 can resist external impact.

The fabrication of the display device 10 will be described in further detail below.

Fig. 16 to 20 are perspective views illustrating an embodiment of a method of manufacturing a display device according to the present disclosure of fig. 15. Fig. 21 and 22 are cross-sectional views illustrating an embodiment of a laser irradiation process as performed in the method of manufacturing a display device according to the present disclosure of fig. 15. Fig. 25 to 27 are sectional views illustrating embodiments of an etching process and a cutting process as performed in the method of manufacturing a display device according to the present disclosure of fig. 15.

Fig. 16 to 19 are perspective views of a mother substrate MSUB having a plurality of display units DPC disposed thereon, and fig. 20 is a perspective view of a plurality of substrates SUB having a plurality of display units DPC disposed thereon. Fig. 21, 22 and 25 to 27 are sectional views taken along the line VIII-VIII' of fig. 16 to 20, respectively.

Referring to fig. 16 and 21, a plurality of display units DPC are formed on a first surface (or upper surface) of a mother substrate MSUB, a plurality of first protective films PRF1 are attached on the display units DPC, and the display units DPC are inspected.

The display layer dis of the display unit DPC is formed on a first surface (or upper surface) of the mother substrate MSUB. Each of the plurality of display layers dis includes a thin film transistor layer TFTL, a light emitting element layer EML, an encapsulation layer ENC, and a sensor electrode layer SENL. The structure of the display layer dis is as already described above.

Thereafter, a first protective film layer is attached to cover the display unit DPC and a portion of the mother substrate MSUB between the display units DPC. Thereafter, a portion of the first protective film layer on the mother substrate MSUB is removed so that the first protective film PRF1 is disposed on the display unit DPC. The portion of the first protective film layer that is not removed may correspond to the first protective film PRF1. The first protective film PRF1 may be disposed on the display unit DPC. The first protective film PRF1 may correspond one-to-one to the display units DPC.

The first protective film PRF1 may be a buffer film for protecting the display unit DPC from external impact. The first protective film PRF1 may include or consist of a transparent material.

Thereafter, the display unit DPC is inspected with an inspection device. The probes are connected to a plurality of test pads provided in the display unit DPC, and an illumination test is performed on each of the plurality of display units DPC.

In the case where the illumination test is performed after the display unit DPC is separated from the mother substrate MSUB via the dicing process, an additional process for removing the test pads is required after the illumination test. In contrast, in the case of performing an illumination test on the mother substrate MSUB, the test pad is removed when the display unit DPC is separated from the mother substrate MSUB via the laser irradiation process and the etching process. In this case, an additional process for removing the test pad is not required.

Thereafter, referring to fig. 17 and 22, a laser SPOT is formed along the display unit DPC by applying laser light LR to a second surface (or lower surface) of the mother substrate MSUB opposite to the first surface (or upper surface) of the mother substrate MSUB.

Since the laser SPOT is defined by applying the laser LR along the display unit DPC, the cutting line LS can be delineated. The cutting line LS may be formed along the display unit DPC.

Various lasers may be used to apply the laser LR for delineating the cutting line LS. The laser LR may be an infrared Bessel beam (Bessel beam) having a wavelength of about 1030 nm. The laser LR may have a repetition rate of about 10 kilohertz (kHz) to about 1000kHz, a pulse duration of about 300 femtoseconds (fs) to about 10 picoseconds (ps), and a pulse energy of about 10 microjoules (μj) to about 500 μj. Here, the pulse energy per laser SPOT may be about 10 μj or less. Each of the plurality of laser SPOTs may have a length of about 20 μm to about 25 μm in the Z-axis direction.

The laser LR may be applied to the second surface (or lower surface) of the mother substrate MSUB, and a plurality of laser SPOTs SPOT may be formed in the 3D space of the mother substrate MSUB. The laser SPOTs SPOT may be spaced apart from each other in the X-axis direction, the Y-axis direction, and the Z-axis direction in the 3D space of the mother substrate MSUB. The laser light LR may be applied to the mother substrate MSUB by an optical device such as a diffractive optical element ("DOE") or a spatial laser modulator ("SLM"), and a plurality of laser points SPOT may be simultaneously formed in the 3D space of the mother substrate MSUB.

The plurality of laser SPOTs SPOT may have a predetermined trajectory in the 3D space of the mother substrate MSUB. The plurality of laser SPOTs may be separated from each other by a predetermined distance in the X-axis direction, the Y-axis direction, and the Z-axis direction, and may be formed along a predetermined trajectory. During the following etching process to apply the laser LR, the etchant may penetrate the laser SPOT, may thereby etch the mother substrate MSUB, and may cut the mother substrate MSUB along the trace of the laser SPOT. That is, the shape of the side surfaces SS1 and SS2 of the substrate SUB of fig. 8 cut out from the mother substrate MSUB may vary depending on the trajectory of the laser SPOT. According to the method of fig. 15, the laser SPOT formed in the process of applying the laser LR to the mother substrate MSUB may have a curved trajectory in the 3D space, and the substrate SUB cut out from the mother substrate MSUB may have curved side surfaces SS1 and SS2.

The laser LR may be applied along the Y-axis direction, and the laser SPOT may be designed to form a track satisfying a specific condition along the X-axis direction and the Z-axis direction.

Fig. 23 is a graph illustrating an embodiment of a laser spot trajectory defined by a method of fabricating a display device according to the present disclosure. Fig. 24 is a photomicrograph showing a laser spot formed on a mother substrate along the laser spot trajectory of fig. 23. Fig. 23 is a graph showing trajectories in the X-axis direction and the Z-axis direction defined by a plurality of laser points SPOT defined by applying laser light LR to the mother substrate MSUB. Here and hereinafter, the laser SPOT may refer to fig. 22 and the laser LR and the mother substrate MSUB may refer to, for example, fig. 17.

Referring to fig. 23 and 24, the thickness of the mother substrate MSUB may be about 400 μm to about 600 μm. When the thickness of the mother substrate MSUB is about 500 μm, the laser SPOT may be in a range of a depth of about 0 μm to about 500 μm in the mother substrate MSUB in the Z-axis direction. That is, in the thickness direction (or in the Z-axis direction) of the mother substrate MSUB, the depth (or thickness) of the processed region, which is the region processed with the laser LR, may be about 95% to about 100% of the thickness of the mother substrate MSUB. When the thickness of the mother substrate MSUB is about 500 μm, the processing region may be in a range of about 475 μm to about 500 μm in the thickness direction (or Z-axis direction) of the mother substrate MSUB. In the embodiment of fig. 23, the processing area ranges up to about 482.25 μm in the thickness direction (or Z-axis direction) of the master substrate MSUB.

The number of laser SPOTs formed throughout the thickness of the mother substrate MSUB may be 10 to 50. Specifically, referring to fig. 23 and in combination with fig. 22, the number of laser SPOTs spaced apart from each other in the Z-axis direction between the lower surface and the upper surface of the mother substrate MSUB may be 10 to 50. Fig. 23 shows that 20 laser SPOTs are formed, but the present disclosure is not limited thereto. In the case of forming the laser SPOT while moving the laser LR in the Y-axis direction, the laser SPOTs SPOT may be spaced apart from each other in the X-axis direction and the Z-axis direction in a cross-sectional view of the mother substrate MSUB taken along the X-axis direction. Here, the number of laser SPOTs measured from the cross section of the mother substrate MSUB may be 10 to 50.

The first horizontal distance DSP, which is a distance between the laser points SPOT in the X-axis direction, may be about 10 μm, and the second vertical distance HSP, which is a distance between the laser points SPOT in the Z-axis direction, may be about 7 μm. In the embodiment of fig. 23, the first horizontal distance DSP may be about 9.8 μm and the second vertical distance HSP may be about 7.05 μm. However, the present disclosure is not limited to the embodiment of fig. 23.

The trajectory formed by the laser SPOT on the X-axis and the Z-axis may have a curvature. As already mentioned above with respect to the shape of the side surfaces SS1 and SS2 of the substrate SUB of fig. 8, the outermost curvature laser spot SOT may be closer to the second surface (or lower surface) of the mother substrate MSUB than to the middle of the processing region in the Z-axis direction. That is, the outermost curvature laser spot SOT may be set closer to the lower surface of the mother substrate MSUB than to a depth corresponding to 1/2 of the thickness of the mother substrate MSUB.

The outermost curvature laser SPOT SOT of the track defined by the laser SPOT may be disposed at a depth corresponding to about 30% of the thickness of the mother substrate MSUB from the second surface (or lower surface) of the mother substrate MSUB. When the thickness of the mother substrate MSUB is about 500 μm, the outermost curvature laser SPOT SOT of the track defined by the laser SPOT may be at a position spaced apart from the second surface (or lower surface) of the mother substrate MSUB or the lower surface BS (for example, refer to fig. 8) of the substrate SUB of the display device 10 by about 150 μm. In the embodiment of fig. 23, the outermost curvature laser SPOT SOT of the track defined by the laser SPOT may be at a depth of about 148.8 μm. The radius of curvature of the track defined by the laser SPOT may be about 500 μm. "TS0" represents the vertical distance between the second surface (or lower surface) of the mother substrate MSUB and the outermost curvature laser spot SOT.

The laser SPOT may be continuously formed along a track having a curvature from the outermost curvature laser SPOT SOT. The laser SPOT within a range from the first laser SPOT S1 to the outermost curvature laser SPOT SOT may be formed outside the curvature center of the track defined by the laser SPOT, the first laser SPOT S1 being the second surface (or lower surface) on which the laser LR is irradiated, which is first formed by applying the laser LR and is closest to the mother substrate MSUB. In contrast, the laser SPOT in the range from the outermost curvature laser SPOT SOT to the nth laser SPOT Sn, which is the last laser SPOT defined by applying the laser LR and is closest to the first surface (or upper surface) of the mother substrate MSUB where the laser LR is not irradiated, may be oriented toward the center of curvature of the track defined by the laser SPOT.

The processing region in the X-axis direction may be defined by a trajectory defined by the laser SPOT starting from the outermost curvature laser SPOT SOT. In an embodiment, an X-axis machining region WCH and a Z-axis machining region VCH may be defined. The first X-axis machining region WCH1 of the X-axis machining region WCH (refer to fig. 22) may have a horizontal distance of about 10 μm to about 20 μm, which is a horizontal distance between the outermost curvature laser spot SOT and the first laser spot S1. The second X-axis machining region WCH2 of the X-axis machining region WCH may have a horizontal distance of about 120 μm to about 150 μm, which is a horizontal distance between the outermost curvature laser spot SOT and the nth laser spot Sn. Here, the term "horizontal distance" may refer to the difference in X-coordinate between the first laser point S1 and the nth laser point Sn. That is, the term "horizontal distance" may refer to a distance in the X-axis direction between an imaginary line passing through the outermost curvature laser spot SOT and the first laser spot S1 in the Z-axis direction or a distance in the X-axis direction between an imaginary line passing through the outermost curvature laser spot SOT and the nth laser spot Sn in the Z-axis direction. In the embodiment of fig. 23, the horizontal distance of the first X-axis machining region WCH1 may be about 16.47 μm, and the horizontal distance of the second X-axis machining region WCH2 may be about 139.61 μm.

Since the locus defined by the laser SPOT has curvature, angles α and β may be defined between the locus defined by the laser SPOT and the first and second surfaces (or the upper and lower surfaces) of the mother substrate MSUB. The incident angle α defined by an imaginary line connecting the first, second, third, and fourth laser spots S1, S2, S3, and S4 adjacent to the second (or lower) surface of the mother substrate MSUB and the second (or lower) surface of the mother substrate MSUB may be in a range from 70 ° to 90 °. The emission angle β defined by an imaginary line connecting the (n-3) th, (n-2) th, (n-1) th and nth laser spots Sn-3, sn-1 and Sn-th laser spots adjacent to the first surface (or upper surface) of the mother substrate MSUB, and the first surface (or upper surface) of the mother substrate MSUB may be in a range from 35 ° to 40 °. In the embodiment of fig. 23, the incident angle α may be 81.85 °, and the emission angle β may be 39.62 °.

As already mentioned above, the trajectory defined by the laser SPOT defined by applying the laser LR to the mother substrate MSUB may have a curved shape, and the distance between the laser SPOT and the processing region may be designed such that the side surfaces SS1 and SS2 of the substrate SUB of the display device 10 cut out from the mother substrate MSUB may also have a curved shape. The shape of the side surfaces SS1 and SS2 of the substrate SUB of the display device 10 can be determined by the position of the outermost curvature laser SPOT SOT in the track defined by the laser SPOT, the incident angle α, the emission angle β, and the size of the processing region. The trajectory defined by the laser SPOT may vary. According to the method of fig. 15, the side surfaces SS1 and SS2 of the substrate SUB of the display device 10 may be curved by applying the laser light LR such that the laser SPOT forms a track having a curvature, and the substrate SUB of the display device 10 may be resistant to external impact.

The unidirectional tolerance of the laser LR may be about 50 μm and the bidirectional tolerance of the laser LR may be about 100 μm. The unidirectional tolerance of the laser LR may be a cutting error in one direction (for example, in the X-axis direction) when the cutting line LS (refer to fig. 17) is delineated by forming the laser SPOT with the laser LR.

The distance from the encapsulation layer ENC (e.g., refer to fig. 9) to the edge EG (e.g., refer to fig. 9) of the display panel 100 may be affected by the unidirectional tolerance (SE 2) of the laser light LR. The distance between the encapsulation layer ENC and the laser SPOT when the laser LR is properly applied to each specified position may be defined as DCH.

In case the laser light LR is applied to the left with a maximum unidirectional tolerance of up to the laser light LR, the distance between the encapsulation layer ENC and the laser SPOT may be DCH-SE2. In contrast, in the case where the laser light LR is applied to the right side with a maximum unidirectional tolerance of up to the laser light LR, the distance between the encapsulation layer ENC and the laser SPOT may be dch+se2.

Since the substrate SUB of the display device 10 is separated from the mother substrate MSUB along the laser SPOT in the etching process after the application of the laser light LR, the distance between the encapsulation layer ENC and the laser SPOT may be similar to the minimum distance between the encapsulation layer ENC and the edge EG of the display panel 100 as shown in fig. 8. The distance between the encapsulation layer ENC and the laser SPOT may be slightly reduced in the etching process and may become a minimum distance between the encapsulation layer ENC and the edge EG of the display panel 100. The minimum distance between the encapsulation layer ENC and the edge EG of the display panel 100 may vary by up to twice the unidirectional tolerance of the laser LR (or up to the bi-directional tolerance of the laser LR) (e.g., about 100 μm).

Referring to fig. 8, the distance between the encapsulation layer ENC and the edge EG of the display panel 100 may be DCH-SE2 or dch+se2. In an embodiment, for example, when the Distance (DCH) between the encapsulation layer ENC and the laser SPOT is about 50 μm and the unidirectional tolerance of the laser LR is about 50 μm, the distance between the encapsulation layer ENC and the edge EG of the display panel 100 may be about 300 μm or less, but may vary up to about 100 μm depending on the unidirectional tolerance of the laser LR. The distance to the edge EG of the display panel 100 may be a minimum value of about 0 μm or a maximum value of about 300 μm.

The unidirectional tolerance of the laser light LR, which is about 50 μm, may be smaller than that of the cutting member when the substrate SUB of the display device 10 is cut with the cutting member. That is, since the unidirectional tolerance of the laser light LR is smaller than that of the cutting member, the distance between the encapsulation layer ENC and the edge EG of the display panel 100 may be reduced as compared with the case where the substrate SUB of the display device 10 is cut with the cutting member.

Thereafter, referring to fig. 18 and 25 to 27, the second protective film PRF2 is attached on the first protective film PRF1, and the mother substrate MSUB is etched by spraying an etchant onto the second surface (or lower surface) of the mother substrate MSUB without using a mask.

The second protective film PRF2 may be attached on the first protective film PRF1 and the portion of the mother substrate MSUB that is not covered but exposed by the first protective film PRF 1. The second protective film PRF2 may cover a region where the laser SPOT is formed. The second protective film PRF2 may be an acid-resistant film for protecting the display unit DPC from an etchant for etching the mother substrate MSUB.

The mother substrate MSUB may be etched by spraying an etchant onto the second surface (or lower surface) of the mother substrate MSUB without using a mask. As a result, the thickness of the mother substrate MSUB can be reduced, and the mother substrate MSUB can be cut along the laser SPOT. That is, the display unit DPC may be separated from the mother substrate MSUB.

In the case of spraying the etchant onto the second surface (or lower surface) of the mother substrate MSUB, the thickness of the mother substrate MSUB may be reduced from the first thickness T1 'to the second thickness T2'. Since the mother substrate MSUB is etched without using a mask, all regions on the second surface (or lower surface) of the mother substrate MSUB (even regions forming the laser SPOT) can be isotropically etched uniformly.

Since the etchant penetrates the laser SPOT defined by the laser LR, when the thickness of the mother substrate MSUB is being reduced by the etchant, a difference in etching rate may occur between a region where the laser SPOT is formed and a region where the laser SPOT is not formed.

Since the laser SPOT is formed in the region irradiated with the laser light LR, the surface area of the mother substrate MSUB may be increased in the region irradiated with the laser light LR than in the region not irradiated with the laser light LR. Since the region irradiated with the laser light LR has a surface area larger than that of the region not irradiated with the laser light LR, the region irradiated with the laser light LR may have an etching rate higher than that of the region not irradiated with the laser light LR because of a substantially relatively large contact area of the region irradiated with the laser light LR with the etchant. In addition, in the region irradiated with the laser light LR, the physical properties of the mother substrate MSUB may be changed. The mother substrate MSUB may have a higher reactivity to an etchant and a higher etching rate in the region irradiated with the laser light LR than in the region not irradiated with the laser light LR.

Accordingly, anisotropic etching may be performed on the mother substrate MSUB in which an etching rate may be higher in a region where the laser SPOT is formed than in a region where the laser SPOT is not formed. As a result, the side surfaces SS1 and SS2 (for example, refer to fig. 8) of the substrate SUB of the display device 10 separated from the mother substrate MSUB may have a curved shape similar to the trajectory defined by the laser SPOT, and may be etched more than the area where the laser SPOT is not formed. The curvature of the track defined by the laser SPOT may be different from the curvature of the side surfaces SS1 and SS2 of the substrate SUB of the display device 10 because the etching rate is different during etching of the mother substrate MSUB along the laser SPOT.

In addition, an etching process may be performed on the second surface (or lower surface) to which the laser LR of the mother substrate MSUB is applied. Therefore, a difference in etching rate may occur not only between the region where the laser SPOT is formed and the region where the laser SPOT is not formed, but also between the first surface (or upper surface) and the second surface (or lower surface) of the mother substrate MSUB. The etching rate may be higher on the second surface than on the first surface (or upper surface) of the mother substrate MSUB, and the mother substrate MSUB may be etched more along the laser SPOT than in other regions. That is, in connection with fig. 8, due to the difference in etching rate between the first side surface SS1 and the second side surface SS2 of the substrate SUB of the display device 10 adjacent to the upper surface US and the lower surface BS, respectively, of the substrate SUB, a difference in curvature on the surface of the substrate SUB of the display device 10 cut out from the mother substrate MSUB and a difference in size of the glass holes in the surface may occur. In an embodiment, for example, since the etchant penetrates the mother substrate MSUB from the second surface (or lower surface) of the mother substrate MSUB, the second side surface SS2 adjacent to the second surface (or lower surface) of the mother substrate MSUB or the lower surface BS of the substrate SUB of the display device 10 may have a curvature that is gentler than that of the first side surface SS1 adjacent to the first surface (or upper surface) of the mother substrate MSUB or the upper surface US of the substrate SUB of the display device 10. In addition, the size of the glass hole formed in the second side surface SS2 may be smaller than the size of the glass hole formed in the first side surface SS 1.

Since the first surface (or upper surface) of the mother substrate MSUB is not penetrated by the etchant due to the second protective film PRF2, but the second surface (or lower surface) of the mother substrate MSUB is etched by the etchant, differences in roughness, strength, light transmittance, light reflectance, local density, and surface chemical structure may occur between the first surface and the second surface (or upper surface and lower surface) of the mother substrate MSUB. In an embodiment, for example, due to the etchant, a dent may be formed in the mother substrate MSUB.

Once the etching process is completed, the second protective film PRF2 may be detached.

Thereafter, referring to fig. 20 and in combination with fig. 5 and 21, the driver IC 200 and the circuit board 300 may be attached to each of the plurality of display units DPC, the first protective film PRF1 may be detached from the display unit DPC, and the polarizing film PF and the cover window CW may be attached to the display unit DPC, thereby obtaining the display device 10.

According to the method of fig. 15, since the mother substrate MSUB is cut via etching, the distance between the display unit DPC and the display panel 100 of the display apparatus 10 can be minimized as compared with the case of cutting the mother substrate MSUB with the cutting member. That is, the size of any unnecessary space on the outermost side of the display panel 100 of the display device 10 can be minimized. In addition, since the thickness of the mother substrate MSUB can be reduced and the substrate SUB of the display device 10 can be separated from the mother substrate MSUB via etching, the manufacturing efficiency of the display device 10 can be improved.

Fabrication of the display device 10 may include forming a plurality of laser SPOTs SPOT arranged in the 3D space in the X-axis direction, the Y-axis direction, and the Z-axis direction by applying the laser LR and performing an etching process. During the etching process, the mother substrate MSUB may be etched along the laser SPOT, and the side surfaces SS1 and SS2 of the substrate SUB of the display device 10 cut out from the mother substrate MSUB may have a curved shape. Accordingly, the substrate SUB of the display device 10 may be resistant to external impact.

A display device according to other embodiments of the present disclosure will be described hereinafter.

Fig. 28 is a cross-sectional view of another embodiment of a display panel according to the present disclosure. Fig. 29 is a cross-sectional view showing an embodiment of an etching process as performed during the fabrication of the display device of fig. 28.

Referring to the display device 10_1 of fig. 28 and 29, the edge EG may be disposed at a depth corresponding to 1/2 of the thickness of the substrate SUB, and the first and second side surfaces SS1 and SS2 of the substrate SUB may have the same curvature and the same length. The first and second side surfaces SS1 and SS2 may be symmetrical with respect to the edge EG. Accordingly, the first side surface SS1 and the second side surface SS2 may have uniform curvature, and resistance to external impact of the display device 10_1 may be further improved.

The etching process for etching the mother substrate MSUB may be performed simultaneously on both the first and second surfaces (or the upper and lower surfaces) of the mother substrate MSUB. During the etching process, the second protective film PRF2 may expose a portion of the first surface (or upper surface) of the mother substrate MSUB. The etching process may be simultaneously performed on both the second surface (or lower surface) of the mother substrate MSUB where the second protective film PRF2 is not disposed and the portion of the upper surface of the mother substrate MSUB exposed by the second protective film PRF 2. The mother substrate MSUB may be etched along a trajectory defined by the laser SPOT, and since the etching process is simultaneously performed on both the upper and lower surfaces of the mother substrate MSUB, the etching rate for the mother substrate MSUB may be further improved. As a result, the amount of time taken to manufacture the display device 10_1 can be reduced, and the first side surface SS1 and the second side surface SS2 can be smoothed according to the conditions of the etching process.

Fig. 30 is a cross-sectional view of another embodiment of a display panel according to the present disclosure. Fig. 31 is a photomicrograph showing an edge portion of a substrate of the display panel of fig. 30.

Referring to the display device 10_2 of fig. 30 and 31, the substrate SUB of the display panel 100 may include a side surface SS and a first inclined surface IP1. The side surface SS and the first inclined surface IP1 may not be parallel or orthogonal to the upper surface US and the lower surface BS, but inclined with respect to the upper surface US and the lower surface BS. The side surface SS and the first inclined surface IP1 may overlap with the edge region EGA in which the processing trace is left in the thickness direction (or the Z-axis direction). In an embodiment, a distance D3 between the crack dam CRD and the edge EG may be similar to a distance D1 of the display device 10_1 shown in fig. 28.

The angle θ1 between the side surface SS and the upper surface US may be about 80 °. The angle θ2 between the side surface SS and the first inclined surface IP1 and the angle θ3 between the first inclined surface IP1 and the lower surface BS may be obtuse angles.

During fabrication of the display device 10_2 having the side surface SS and the first inclined surface IP1, an inclined locus may be defined by the laser SPOT. The track defined by the laser SPOT may not necessarily have a curved shape, and may be designed such that the substrate SUB cut along the laser SPOT may have a substantially high impact resistance. Accordingly, the shape of the side surface SS of the substrate SUB of the display device 10_2 may be modified in various ways.

Fig. 32 is a plan view illustrating another embodiment of a non-display area of a display panel according to the present disclosure. Fig. 33 is a sectional view taken along line IV-IV' of fig. 32.

Referring to fig. 32 and 33, the display device 10_3 may further include a heat dissipation layer IRL overlapping the crack dam CRD. The heat dissipation layer IRL may be disposed in an outer portion of the display panel 100 on an inside of the edge region EGA, and may overlap the crack dam CRD.

The heat dissipation layer IRL may release heat generated by the laser light applied during cutting of the mother substrate MSUB, or may minimize an influence of the laser light on the display panel 100 during cutting of the mother substrate MSUB by increasing an absorptivity of infrared light. In embodiments, for example, the heat dissipation layer IRL may comprise a metallic material having a substantially high thermal conductivity or a material having a substantially high infrared absorption rate. The heat sink layer IRL may be formed as a single layer or multiple layers including one of Mo, al, cr, au, ti, ni, nd, cu and any of their alloys.

The width of the heat sink layer IRL may be greater than the width of the edge region EGA. In an embodiment, for example, the width of the heat dissipation layer IRL may be about 50 μm to about 300 μm, but the present disclosure is not limited thereto.

Referring to fig. 34, the display device 10_4 may further include a passivation layer PL disposed on the edge EG of the display panel 100. The passivation layer PL may cover the first and second side surfaces SS1 and SS2 of the substrate SUB and a portion of the upper surface US and a portion of the lower surface BS of the substrate SUB. The passivation layer PL may overlap the edge region EGA and may partially cover the processing trace on the upper surface US of the substrate SUB.

During fabrication of the display device 10_4, a process of separating the substrate SUB from the mother substrate MSUB via laser irradiation and etching may be performed. As a result, an edge area EGA in which a processing trace is left may be formed on the substrate SUB of the display panel 100, and the first side surface SS1 and the second side surface SS2 may be inclined or curved. This type of display panel 100 may be relatively vulnerable to external impact. Thus, for protection, the display device 10_4 may further include a passivation layer PL disposed on the substrate SUB.

The passivation layer PL may be disposed on a cut surface of the substrate SUB defined by laser irradiation and etching during separation of the substrate SUB from the mother substrate MSUB as performed during manufacturing of the display device 10_4. The passivation layer PL is shown to cover the first and second side surfaces SS1 and SS2 and a portion of the upper surface US and a portion of the lower surface BS, but the present disclosure is not limited thereto. In alternative embodiments, in some embodiments, the passivation layer PL may cover the side surface SS (of fig. 30) and the first inclined surface IP1 of the substrate SUB, and another passivation layer PL may be further disposed on the lower surface BS of the substrate SUB.

At the conclusion of the detailed description, those skilled in the art will appreciate that many changes and modifications can be made to the preferred embodiments without substantially departing from the principles of the present invention. Accordingly, the disclosed preferred embodiments of the invention are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. A display device, wherein the display device comprises:

a glass substrate comprising:

a first surface;

a second surface opposite the first surface; and

A side surface disposed between the first surface and the second surface; an outermost structure disposed on the first surface of the glass substrate and adjacent to an edge of the glass substrate; and

a display layer comprising a plurality of emissive areas on the first surface of the glass substrate, the plurality of emissive areas spaced apart from the edge,

wherein,

the side surface has a curved shape, and the edge protrudes toward the outermost side of the glass substrate,

the side surfaces include a first side surface disposed between the edge and the first surface and a second side surface having a different curvature from the first side surface between the edge and the second surface, and

the glass substrate includes an edge region in the first surface adjacent to the edge and leaving a processing trace in the edge region.

2. The display device of claim 1, wherein the second side surface has a radius of curvature of 200 microns to 300 microns.

3. The display device according to claim 1, wherein,

The length of the first side surface is smaller than that of the second side surface, and

the second side surface has a gentle curvature than the first side surface.

4. The display device according to claim 1, wherein a width of the second side surface protruding from an end of the second side surface toward the edge is 10% to 20% of a total thickness of the glass substrate.

5. The display device of claim 4, wherein the width of the second side surface protruding from the end of the second side surface toward the edge is 20 micrometers to 40 micrometers.

6. The display device of claim 1, wherein a diameter of the glass aperture defined in the first side surface is smaller than a diameter of the glass aperture defined in the second side surface.

7. The display device according to claim 6, wherein,

the diameter of the glass hole defined in the first side surface is 5 to 30 micrometers, and

the diameter of the glass holes defined in the second side surface is 30 micrometers to 50 micrometers.

8. The display device of claim 1, wherein a vertical distance between the second surface and an imaginary plane passing through the edge and parallel to the second surface is 50% to 60% of a total thickness of the glass substrate.

9. The display device of claim 8, wherein the vertical distance is 100 micrometers to 120 micrometers.

10. The display device of claim 1, wherein a minimum distance between the edge of the glass substrate and the outermost structure is 130 microns or less.

11. The display device of claim 1, wherein the width of the edge region is 50 microns or less.

12. The display device according to claim 1, wherein the display device further comprises:

an encapsulation layer covering the display layer and the outermost structure,

wherein,

the encapsulation layer includes a first encapsulation inorganic film, an encapsulation organic film, and a second encapsulation inorganic film, the encapsulation organic film is disposed on the first encapsulation inorganic film, the second encapsulation inorganic film is disposed on the encapsulation organic film, and

the first and second encapsulating inorganic films cover the outermost structure.

13. A method of making a display device, wherein the method comprises:

preparing a mother substrate and forming a plurality of display units on a first surface of the mother substrate;

defining cutting lines along the plurality of display elements by applying a laser to a second surface of the mother substrate, the second surface being opposite the first surface; and

Separating the substrate having the plurality of display units formed thereon by etching the second surface of the mother substrate along the cutting lines,

wherein,

the laser defines a plurality of laser spots spaced apart from each other between the first and second surfaces of the mother substrate, an

The plurality of laser spots define a trajectory having a curvature in a three-dimensional space of the mother substrate.

14. The method of claim 13, wherein the trajectory has a radius of curvature of 500 microns.

15. The method of claim 14, wherein the processing region defining the plurality of laser spots is formed in the mother substrate along a thickness direction of the mother substrate and occupies 95% to 100% of a thickness of the mother substrate.

16. The method of claim 15, wherein an outermost curvature laser spot is a laser spot of the plurality of laser spots at an outermost portion of the track, the outermost curvature laser spot disposed from the second surface at a depth corresponding to 30% of the thickness of the master substrate.

17. The method of claim 16, wherein,

the processing region is in a depth range of 450 to 500 micrometers in the thickness direction, the plurality of laser spots are defined along the thickness direction, and

The outermost curvature laser spot is 150 microns apart from the second surface.

18. The method of claim 16, wherein,

the incident angle between the second surface and an imaginary line connecting four laser points nearest to the second surface is 70 DEG to 90 DEG, and

the emission angle between the first surface and an imaginary line connecting four laser points closest to the first surface is 35 deg. to 40 deg..

19. The method of claim 18, wherein,

the horizontal distance between the outermost curvature laser spot and the laser spot closest to the second surface of the four laser spots closest to the second surface is 10 micrometers to 20 micrometers, and

the horizontal distance between the outermost curvature laser spot and the laser spot closest to the first surface of the four laser spots closest to the first surface is 120 micrometers to 150 micrometers.

20. The method of claim 13, wherein,

the laser has a pulse energy of 10 microjoules to 500 microjoules, and

each of the plurality of laser spots has a length of 20 micrometers to 25 micrometers in a thickness direction.

21. The method of claim 13, wherein,

The substrate separated from the mother substrate includes a side surface disposed between the first surface and the second surface, and

the side surfaces of the substrate include a first side surface between the first surface and an edge of the substrate and a second side surface between the second surface and the edge of the substrate, and the second side surface and the first side surface have a symmetrical shape.

22. The method of claim 21, wherein,

in the etching of the mother substrate along the second surface and the cutting line, the first surface is etched together.

23. A display device, wherein the display device comprises:

a glass substrate comprising:

a first surface;

a second surface opposite the first surface; and

Wherein,

the side surfaces include a first side surface disposed between the edge and the first surface and a second side surface between the edge and the second surface and having a symmetrical shape with the first side surface, an

24. The display device of claim 23, wherein,

the length of the first surface is the same as the length of the second surface.

25. The display device of claim 23, wherein,

the width of the second side surface protruding from the end of the second side surface toward the edge is 10% to 20% of the total thickness of the glass substrate.

26. The display device of claim 25, wherein,

the width of the second side surface protruding from the end of the second side surface toward the edge is 20 micrometers to 40 micrometers.

27. The display device of claim 23, wherein a minimum distance between the edge of the glass substrate and the outermost structure is 130 microns or less.

28. The display device of claim 23, wherein the width of the edge region is 50 microns or less.