CN220986091U

CN220986091U - Display device

Info

Publication number: CN220986091U
Application number: CN202322407657.7U
Authority: CN
Inventors: 文孝英; 严理璱; 金完政; 南炅我; 朴镛昇; 尹大相; 李昭玲; 李荣勳
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2022-09-05
Filing date: 2023-09-05
Publication date: 2024-05-17
Anticipated expiration: 2033-09-05
Also published as: CN117651446A

Abstract

A display device is provided. The display device includes a substrate including an upper surface carrying a light emitting element, a bottom surface facing the upper surface, and a through hole penetrating the upper surface and the bottom surface, wherein the substrate includes: a side surface intersecting the upper surface in the through hole; a first surface intersecting the bottom surface; a second surface intersecting the side surface; and a third surface between the first surface and the second surface, and wherein the first surface and the second surface are spaced apart from each other, and the third surface is between the first surface and the second surface, and the first surface and the second surface are inclined surfaces. The display device can improve efficiency of a manufacturing process, improve impact resistance of a substrate, relatively easily separate the substrate from a mother substrate, and prevent or reduce damage to the vicinity of a through hole of the display device due to high heat of laser light.

Description

Display device

Technical Field

Aspects of some embodiments of the present disclosure relate to a display device.

Background

With the development of the information society, the demand for display devices is increasing. For example, display devices are being employed by a variety of electronic devices such as smartphones, digital cameras, laptop computers, navigation devices, and smart televisions. The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and an organic light emitting display device. Among such flat panel display devices, the light emitting display device includes a light emitting element that can emit light so that each of pixels of the display panel can emit light. Accordingly, the light emitting display device can display an image without a backlight unit that supplies light to a display panel.

The display device may include a display area displaying an image and a non-display area surrounding the display area. Recently, in order for viewers to be more immersed in contents displayed on a display area and to increase the aesthetic appearance of a display device, the width of a non-display area is continuously reduced.

Incidentally, in the process of manufacturing the display device, the display device may be formed by cutting the mother substrate along a plurality of display units formed on the mother substrate. For example, a through hole in the display device may be formed by cutting the display device on a mother substrate, with an optical device such as a camera positioned in the through hole. In the process of forming the through-hole, the film in the vicinity of the through-hole may be damaged, for example, delaminated, due to the high heat of the laser. Therefore, there is a method of reducing damage to such a display device.

The above information disclosed in this background section is only for enhancement of understanding of the background art and therefore the information discussed in this background section does not necessarily form the prior art.

Disclosure of utility model

The utility model aims to provide a display device which can reduce damage to the display device.

It should be noted that the characteristics according to the embodiments of the present disclosure are not limited to the above-described characteristics; and other features of the present disclosure will be apparent to those skilled in the art from the following description.

According to some embodiments, a display device includes a substrate including an upper surface carrying a light emitting element, a bottom surface facing the upper surface, and a through hole penetrating the upper surface and the bottom surface; wherein the substrate comprises: a side surface intersecting the upper surface in the through hole; a first surface intersecting the bottom surface; a second surface intersecting the side surface; and a third surface between the first surface and the second surface, and wherein the first surface and the second surface are spaced apart from each other, and the third surface is between the first surface and the second surface, and the first surface and the second surface are inclined surfaces.

According to some embodiments, one end of the third surface intersects the first surface and an opposite end of the third surface intersects the second surface.

According to some embodiments, the angle between the bottom surface and the first surface and the angle between the third surface and the second surface are obtuse angles.

According to some embodiments, the angle between the surface and the first surface is equal to, greater than or less than the angle between the third surface and the second surface.

According to some embodiments, the length of the first surface in the oblique direction is equal to, greater than or less than the length of the second surface in the oblique direction.

According to some embodiments, the third surface extends parallel to the bottom or upper surface; or the third surface is an inclined surface.

According to some embodiments, at least one of the first surface and the second surface is a flat surface or a curved surface.

According to some embodiments, a length between the bottom surface and the side surface on a plane formed by the first surface, the second surface, and the third surface is 100 μm to 500 μm.

According to some embodiments, a display device includes a substrate including an upper surface carrying a light emitting element, a bottom surface facing the upper surface, and a through hole penetrating the upper surface and the bottom surface, wherein the substrate includes: a side surface intersecting the upper surface in the through hole; a first surface intersecting the bottom surface; a second surface intersecting the side surface; and a third surface between the first surface and the second surface, wherein an angle between the bottom surface and the first surface and an angle between the third surface and the second surface are obtuse angles, and wherein the bottom surface and the third surface form a stepped edge.

According to some embodiments, the display device further comprises: an optical device is at least partially embedded in the through hole.

According to some embodiments of the present disclosure, a display device includes a substrate including an upper surface, a bottom surface facing the upper surface, and a through hole penetrating the upper surface and the bottom surface, and a light emitting element layer on the upper surface of the substrate, wherein the substrate includes: a side surface intersecting the upper surface in the through hole; a first surface intersecting the bottom surface; a second surface intersecting the side surface; and a third surface between the first surface and the second surface, and wherein the first surface and the second surface are spaced apart from each other, and the third surface is between the first surface and the second surface, and the first surface and the second surface are inclined surfaces.

According to some embodiments, the angle between the bottom surface and the first surface is equal to the angle between the third surface and the second surface.

According to some embodiments, the angle between the bottom surface and the first surface is greater than the angle between the third surface and the second surface.

According to some embodiments, the angle between the third surface and the second surface is greater than the angle between the bottom surface and the first surface.

According to some embodiments, the length of the first surface in the oblique direction is equal to the length of the second surface in the oblique direction.

According to some embodiments, the length of the first surface in the oblique direction is greater than the length of the second surface in the oblique direction.

According to some embodiments, the length of the second surface in the oblique direction is greater than the length of the first surface in the oblique direction.

According to some embodiments, the third surface extends parallel to the bottom or upper surface.

According to some embodiments, the third surface is an inclined surface.

According to some embodiments of the present disclosure, a display device includes a substrate including an upper surface, a bottom surface facing the upper surface, and a through hole penetrating the upper surface and the bottom surface, and a light emitting element layer on the upper surface of the substrate, wherein the substrate includes: a side surface intersecting the upper surface in the through hole; a first surface intersecting the bottom surface; a second surface intersecting the side surface; and a third surface between the first surface and the second surface, wherein an angle between the bottom surface and the first surface and an angle between the third surface and the second surface are obtuse angles, and wherein the bottom surface and the third surface form a stepped edge.

According to some embodiments, the display device further comprises: an optical device at least partially embedded in the via.

According to some embodiments of the present disclosure, a method of manufacturing a display device includes: forming a plurality of display units on a first surface of a mother substrate; forming a first laser irradiation area for cutting the plurality of display units by irradiating a first laser on a second surface of the mother substrate facing the first surface; irradiating a second laser and a third laser on the second surface of the mother substrate to form a second laser irradiation region and a third laser irradiation region along an edge of the through hole of each of the plurality of display units; and separating the plurality of display units by spraying an etchant on the second surface of the mother substrate and cutting the mother substrate along the first laser irradiation area and the second laser irradiation area of the mother substrate.

According to some embodiments, the third laser shot region is formed to surround the second laser shot region.

According to some embodiments, the second laser irradiated region is deeper from the first surface of the mother substrate than the third laser irradiated region is from the first surface of the mother substrate.

According to some embodiments, the repetition rate of the first laser light and the third laser light is in the range of 10kHz to 250kHz and the repetition rate of the second laser light is in the range of 1kHz to 50 kHz.

According to some embodiments, the processing speed of the first laser and the third laser is in the range of 10mm/s to 250mm/s and the processing speed of the second laser is in the range of 1mm/s to 50 mm/s.

According to some embodiments, the pulse energy of the first laser and the third laser and the pulse energy of the second laser are in the range of 10 μj to 300 μj.

According to some embodiments, the method further comprises: the fourth laser light irradiation region is formed by irradiating the fourth laser light at a position spaced apart from the second laser light irradiation region and on the inner side of the second laser light irradiation region along the edge of the through hole.

According to some embodiments of the present disclosure, by irradiating a laser and then spraying an etchant, the following may be possible: the thickness of the mother substrate is reduced, each of the plurality of display units is separated from the mother substrate, and a through hollow is formed. In this way, it may be possible to increase the efficiency of the manufacturing process.

In addition, by reducing the angle of the edge of the side surface of the substrate in the through hole of the display device, the impact resistance of the substrate can be improved.

In addition, the substrate may be relatively easily separated from the mother substrate at the through-hole of the display device, thereby preventing or reducing damage to the substrate.

In addition, it may be possible to prevent or reduce damage to the vicinity of the through hole of the display device due to high heat of the laser.

It should be noted that the characteristics of the embodiments according to the present disclosure are not limited to those described above, and other effects of the present disclosure will be apparent to those skilled in the art from the following description.

Drawings

The above and other aspects and features of embodiments according to the present disclosure will become more apparent by describing aspects of some embodiments according to the embodiments of the present disclosure in more detail with reference to the accompanying drawings.

Fig. 1 is a perspective view of a display device according to some embodiments of the present disclosure.

Fig. 2 is a plan view illustrating a display panel according to some embodiments of the present disclosure.

Fig. 3 is a cross-sectional view showing an example of the display device taken along the line I-I' of fig. 1.

Fig. 4 is a cross-sectional view showing an example of the display pixel of fig. 3 when the circuit board is bent.

Fig. 5 is a cross-sectional view illustrating an example of a display area of a display panel according to some embodiments of the present disclosure.

Fig. 6 is a layout diagram showing an example of the area a of fig. 2 in more detail.

Fig. 7 is a layout diagram showing an example of the region B of fig. 2 in more detail.

Fig. 8 is a layout diagram showing an example of the region D of fig. 2 in more detail.

Fig. 9 is a cross-sectional view illustrating an example of a display panel taken along line II-II' of fig. 6.

Fig. 10 is a cross-sectional view illustrating an example of a display panel taken along line III-III' of fig. 7.

Fig. 11 is a cross-sectional view illustrating an example of a display panel taken along the line IV-IV' of fig. 8.

Fig. 12 is an enlarged cross-sectional view showing an example of the region E of fig. 9 in more detail.

Fig. 13 is an enlarged cross-sectional view showing an example of the region F of fig. 10 in more detail.

Fig. 14 is an enlarged cross-sectional view showing an example of the region G of fig. 11 in more detail.

Fig. 15 is a layout diagram illustrating an example of a via hole, an inorganic package region, a wiring region, and a display region of the display panel of region I of fig. 2 according to some embodiments.

Fig. 16 is a cross-sectional view showing an example of the display panel taken along the line V-V' of fig. 15.

Fig. 17 is an enlarged cross-sectional view showing an example of the region K of fig. 16 in more detail.

Fig. 18 to 22 are enlarged cross-sectional views showing various examples of the region L of fig. 16.

Fig. 23 is a flowchart for illustrating a method of manufacturing a display device according to some embodiments of the present disclosure.

Fig. 24 to 39 are views for illustrating a method of manufacturing a display device according to some embodiments of the present disclosure.

Fig. 40 to 42 are cross-sectional views for illustrating methods of manufacturing a display device according to some embodiments of the present disclosure.

Fig. 43 is an image showing a through hole of the display device according to the comparative example.

Fig. 44 is an image illustrating a through hole of a display device according to some embodiments of the present disclosure.

Detailed Description

The present disclosure now will be described more fully hereinafter with reference to the accompanying drawings, in which aspects of some embodiments of the utility model are shown. This utility model may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the utility model to those skilled in the art.

It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like reference numerals refer to like elements throughout the specification.

It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure. Similarly, a second element may also be referred to as a first element.

Each of the features of the various embodiments of the present disclosure may be partially or fully combined or combined with each other, and various interlocks and drives are technically possible. Each embodiment may be implemented independently of the other or may be implemented together in association.

Aspects of some embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings.

Fig. 1 is a perspective view of a display device according to some embodiments of the present disclosure. Fig. 2 is a plan view illustrating a display panel according to some embodiments of the present disclosure.

Referring to fig. 1 and 2, a display apparatus 10 according to some embodiments of the present disclosure is used to display a moving image or a still image. The display device 10 may be used as a display screen of a portable electronic device such as a mobile phone, a smart phone, a tablet PC, a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a Portable Multimedia Player (PMP), a navigation device, and an Ultra Mobile PC (UMPC), and a display screen of various products such as a television, a notebook, a monitor, a billboard, and an internet of things device.

According to some embodiments of the present disclosure, the display device 10 may be a light emitting display device such as an organic light emitting display device using an organic light emitting diode, a quantum dot light emitting display device including a quantum dot light emitting layer, an inorganic light emitting display device including an inorganic semiconductor, and a micro LED display device using a micro or nano light emitting diode (micro LED or nano LED). In the following description, an organic light emitting display device is described as an example of the display device 10. However, it will be appreciated that embodiments according to the present disclosure are not limited thereto.

The display device 10 according to some embodiments includes a display panel 100, a driving Integrated Circuit (IC) 200, and a circuit board 300.

The display panel 100 may be formed as a rectangular plane having a long side in a first direction (X-axis direction) and a short side in a second direction (Y-axis direction) intersecting the first direction (X-axis direction). Each of the corners where the long side in the first direction (X-axis direction) meets the short side in the second direction (Y-axis direction) may be formed as a right angle, or may be a circle (rounded) having curvature. The shape of the display panel 100 is not limited to a quadrangular shape when viewed from the top, but may be formed in a different polygonal shape, a circular shape, or an elliptical shape.

The display panel 100 may be formed flat, but is not limited thereto. For example, the display panel 100 may be formed to include curved portions having a constant curvature or a varying curvature at left and right ends. In addition, the display panel 100 may be flexible such that it may be bent, folded, or curled.

The display panel 100 may include a display area DA displaying an image and a non-display area NDA disposed around the display area DA (e.g., in a peripheral area of the display area DA or outside a footprint of the display area DA).

The display area DA may occupy a large area of the display panel 100. The display area DA may be positioned at the center of the display panel 100. In the display area DA, pixels each including a plurality of emission areas may be formed to display an image.

The non-display area NDA may be positioned adjacent to the display area DA (e.g., outside the footprint of the display area DA or in the periphery of the display area DA). The non-display area NDA may be positioned on the outside of the display area DA. The non-display area NDA may surround the display area DA. The non-display area NDA may be defined as a boundary of the display panel 100.

In the non-display area NDA, a display pad (also referred to as a "pad" or "bonding pad") PD may be arranged to be connected to the circuit board 300. The display pad PD may be positioned at one edge of the display panel 100. For example, the display pad PD may be positioned at the lower edge of the display panel 100.

The driving Integrated Circuit (IC) 200 may generate a data voltage, a power supply voltage, a scan timing signal, and the like. The driving IC 200 may output a data voltage, a power supply voltage, a scan timing signal, etc.

The driving IC 200 may be positioned between the display pad PD and the display area DA in the non-display area NDA. Each of the driving ICs 200 may be attached to the non-display area NDA of the display panel 100 by a Chip On Glass (COG) technique. Alternatively, the driving ICs 200 may be attached to the circuit boards 300, respectively, by a chip-on-plastic (COP) technique.

The circuit board 300 may be positioned on the display pad PD positioned at one edge of the display panel 100. The circuit board 300 may be attached to the display pad PD using a conductive adhesive member such as an anisotropic conductive film and an anisotropic conductive adhesive. Accordingly, the circuit board 300 may be electrically connected to the signal lines of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a flexible film such as a chip-on-film.

The bending area BA may be positioned between the driving IC 200 and the display area DA in the non-display area NDA. The bending area BA may be bent such that the driving IC 200 and the circuit board 300 are positioned under the substrate SUB (see fig. 3).

The through holes TH may be formed at one side of the display area DA. The through holes TH may transmit light, and the optical device may be positioned in the through holes TH.

Fig. 3 is a cross-sectional view showing an example of the display device taken along the line I-I' of fig. 1. Fig. 4 is a cross-sectional view showing an example of the display pixel of fig. 3 when the circuit board is bent. Referring to fig. 3, the display device 10 according to some embodiments may include a display panel 100, a polarizing film PF, a cover window CW, and a panel bottom cover PB. The display panel 100 may include a substrate SUB, a display layer DISL, an encapsulation layer ENC, and a sensor electrode layer SENL.

The substrate SUB is a rigid substrate and may be, for example, a glass substrate.

The display layer DISL may be positioned on the first surface of the substrate SUB. The display layer DISL may display an image. The display layer DISL may include a thin film transistor layer TFTL (see fig. 5) in which a thin film transistor is formed and a light emitting element layer EML (see fig. 5) in which a light emitting element that emits light is positioned in an emission region.

In the display area DA of the display layer DISL, scan lines, data lines, voltage lines, and the like may be arranged so that light is emitted in an emission area. In the non-display area NDA of the display layer DISL, a scan driving circuit that outputs a scan signal to a scan line, a fan-out line that connects a data line with the driving IC 200, and the like may be arranged.

The encapsulation layer ENC may encapsulate the light emitting element layer EML of the display layer DISL to prevent or reduce the penetration of oxygen or moisture into the light emitting element layer EML of the display layer DISL. The encapsulation layer ENC may be positioned on the display layer DISL. The encapsulation layer ENC may be positioned on the upper and side surfaces of the display layer DISL. The encapsulation layer ENC may be disposed to cover the display layer DISL.

The sensor electrode layer SENL may be positioned on the encapsulation layer ENC. The sensor electrode layer SENL may include a sensor electrode. The sensor electrode layer SENL may sense a touch of a user using the sensor electrode.

Polarizing film PF may be positioned on sensor electrode layer SENL. The polarizing film PF may be positioned on the display panel 100 to reduce reflection of external light. The polarizing film PF may include a first base member, a linear polarizer, a retardation film such as a lambda/4 (quarter wave) plate, and a second base member. The first base member, the retardation film, the linear polarizer, and the second base member of the polarizing film PF may be sequentially stacked on the display panel 100.

The cover window CW may be positioned on the polarizing film PF. The cover window CW may be attached to the polarizing film PF by a transparent adhesive member such as an Optically Clear Adhesive (OCA) film.

The panel bottom cover PB may be positioned on the second surface of the substrate SUB of the display panel 100. The second surface of the substrate SUB may be opposite to the first surface. The panel bottom cover PB may be attached to the second surface of the substrate SUB of the display panel 100 by an adhesive member. The adhesive member may be a Pressure Sensitive Adhesive (PSA).

The panel bottom cover PB may include at least one of: a light blocking member for absorbing light incident from the outside, a buffer member for absorbing external impact, and a heat dissipating member for effectively discharging heat from the display panel 100.

The light blocking member may be positioned under the display panel 100. The light blocking member blocks transmission of light to prevent or reduce a case where an element positioned therebelow, such as the circuit board 300, is seen from above the display panel 100. The light blocking member may include light absorbing materials such as black pigments and black dyes.

The buffer member may be positioned below the light blocking member. The buffer member absorbs external impact to prevent or reduce damage to the display panel 100. The cushioning member may be composed of a single layer or multiple layers. For example, the cushioning member may be formed of a polymer resin such as polyurethane, polycarbonate, polypropylene, and polyethylene, or may be formed of a material having elasticity (such as rubber and sponge obtained by foaming a urethane-based material or an acrylic-based material).

The heat dissipation member may be positioned below the cushioning member. The heat dissipation member may include a first heat dissipation layer including graphite or carbon nanotubes, and a second heat dissipation layer formed of a thin metal film (such as copper, nickel, ferrite, and silver) that can block electromagnetic waves and has high thermal conductivity.

The driving ICs 200 and the circuit board 300 may be bent such that they are positioned under the display panel 100. The circuit board 300 may be attached to the lower surface (or bottom surface) of the panel bottom cover PB by an adhesive member 310. The adhesive member 310 may be a pressure sensitive adhesive.

According to some embodiments, the through holes TH may be formed in the display device 10. The through holes TH may pass light therethrough, and may be physical holes penetrating the panel bottom cover PB and the polarizing film PF and the display panel 100. However, it should be understood that embodiments according to the present disclosure are not limited thereto. The through holes TH may penetrate the panel bottom cover PB, but may not penetrate the display panel 100 or the polarizing film PF. The cover window CW may be arranged to cover the through-holes TH.

The through holes TH may penetrate the substrate SUB, the display layer DISL, the encapsulation layer ENC, and the sensor electrode layer SENL of the display panel 100.

An electronic device comprising a display device 10 according to some embodiments may further comprise an optical device OPD positioned in the through hole TH. The optical device OPD may be spaced apart from the display panel 100, the panel bottom cover PB, and the polarizing film PF. The optical device OPD may be an optical sensor (such as a proximity sensor, an illuminance sensor, and a camera sensor) that senses light incident through the through-hole TH.

Referring to fig. 5, the display panel 100 according to some embodiments of the present disclosure may be an organic light emitting display panel including light emitting elements LEL each including an organic emission layer 172.

The display layer DISL may include a thin film transistor layer TFTL including a plurality of thin film transistors TFTs and a light emitting element layer EML including a plurality of light emitting elements LEL.

The buffer film BF may be positioned on the substrate SUB. The buffer film BF may be formed of an inorganic material such as silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide. Alternatively, the buffer film BF may be constituted of a plurality of layers in which two or more of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are stacked on each other.

An active layer including a channel region TCH, a source region TS, and a drain region TD of the thin film transistor TFT may be positioned on the buffer film BF. The active layer may be made of polycrystalline silicon, single crystal silicon, low temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor. When the active layer includes polysilicon or an oxide semiconductor material, the source and drain regions TS and TD in the active layer may be conductive regions doped with ions or impurities to have conductivity.

The gate insulator 130 may be positioned on an active layer of the thin film transistor TFT. The gate insulator 130 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

A first gate metal layer including the gate electrode TG of the thin film transistor TFT, the first capacitor electrode CAE1 of the capacitor Cst, and the scan line may be positioned on the gate insulator 130. The gate electrode TG of the thin film transistor TFT may overlap the channel region TCH in the third direction (Z-axis direction). The first gate metal layer may be composed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

The first interlayer dielectric film 141 may be positioned on the first gate metal layer. The first interlayer dielectric film 141 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first interlayer dielectric film 141 may include a plurality of inorganic layers.

A second gate metal layer including a second capacitor electrode CAE2 of the capacitor Cst may be positioned on the first interlayer dielectric film 141. The second capacitor electrode CAE2 may overlap the first capacitor electrode CAE1 in a third direction (Z-axis direction). Accordingly, the capacitor Cst may be formed of the first capacitor electrode CAE1, the second capacitor electrode CAE2, and the first interlayer dielectric film 141 positioned therebetween and serving as a dielectric film. The second gate metal layer may be composed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

A second interlayer dielectric film 142 may be positioned on the second gate metal layer. The second interlayer dielectric film 142 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer dielectric film 142 may include a plurality of inorganic layers.

A first data metal layer including the first connection electrode CE1 and the data line may be positioned on the second interlayer dielectric film 142. The first connection electrode CE1 may be connected to the drain region TD through a first contact hole CT1 penetrating the gate insulator 130, the first interlayer dielectric film 141, and the second interlayer dielectric film 142. The first data metal layer may be composed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

The first organic film 160 may be disposed over the first connection electrode CE1 to provide a flat surface over the thin film transistor TFT having the uneven height. The first organic film 160 may be formed to include an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin.

A second data metal layer including a second connection electrode CE2 may be positioned on the first organic film 160. The second data metal layer may be connected to the first connection electrode CE1 through the second contact hole CT2 penetrating the first organic film 160. The second data metal layer may be composed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

The second organic film 180 may be positioned on the second connection electrode CE 2. The second organic film 180 may be formed to include an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin.

It should be noted that the second organic film 180 and the second data metal layer including the second connection electrode CE2 may be removed.

The light emitting element layer EML is positioned on the thin film transistor layer TFTL. The light emitting element layer EML may include light emitting elements LEL and banks 190.

Each of the light emitting elements LEL may include a pixel electrode 171, an emission layer 172, and a common electrode 173. In each of the emission areas EA, the pixel electrode 171, the emission layer 172, and the common electrode 173 are sequentially stacked on one another such that holes from the pixel electrode 171 and electrons from the common electrode 173 are recombined with one another in the emission layer 172 to emit light. In this case, the pixel electrode 171 may be an anode electrode, and the common electrode 173 may be a cathode electrode.

A pixel electrode layer including the pixel electrode 171 may be formed on the second organic film 180. The pixel electrode 171 may be connected to the second connection electrode CE2 through a third contact hole CT3 penetrating the second organic film 180. The pixel electrode layer may be formed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

In the top emission structure in which light is emitted from the emission layer 172 toward the common electrode 173, the pixel electrode 171 may be formed of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may be formed of a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO/APC/ITO) to increase reflectivity. The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

The banks 190 may define the emission areas EA of the pixels. For this, a bank 190 may be formed on the second organic film 180 to expose a portion of the pixel electrode 171. The bank 190 may cover an edge of the pixel electrode 171. The bank 190 may be positioned within the third contact hole CT 3. In other words, the third contact hole CT3 may be filled with the bank 190. The bank 190 may be formed of an organic layer including, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

Spacers 191 may be positioned on the dikes 190. The spacers 191 may support the mask during the process of manufacturing the emission layer 172. The spacer 191 may be formed of an organic layer including, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

An emission layer 172 is formed on the pixel electrode 171. The emission layer 172 may include an organic material to emit light of a certain color. For example, the emission layer 172 may include a hole transport layer, an organic material layer, and an electron transport layer. The organic material layer may include a host and a dopant. The organic material layer may include a material that emits predetermined light, and may be formed using a phosphor or a fluorescent material.

The common electrode 173 is formed on the emission layer 172. The common electrode 173 may be formed to cover the emission layer 172. The common electrode 173 may be a common layer formed across the emission areas EA1, EA2, EA3, and EA4 (see fig. 6). A capping layer may be formed on the common electrode 173.

In the top emission structure, the common electrode 173 may be formed of a transparent conductive material (TCP) such as ITO and IZO or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), and an alloy of magnesium (Mg) and silver (Ag) that may transmit light. When the common electrode 173 is formed of a semi-transmissive metal material, light extraction efficiency may be improved by using microcavities.

The encapsulation layer ENC may be positioned on the light emitting element layer EML. The encapsulation layer ENC may include one or more inorganic encapsulation films TFE1 and TFE3 to prevent or reduce oxygen or moisture penetration into the light emitting element layer EML. In addition, the encapsulation layer ENC may include at least one organic encapsulation film TFE2 to protect the light emitting element layer EML from particles such as dust. For example, the encapsulation layer ENC may include a first inorganic encapsulation film TFE1, an organic encapsulation film TFE2, and a second inorganic encapsulation film TFE3.

The first inorganic encapsulation film TFE1 may be positioned on the common electrode 173, the organic encapsulation film TFE2 may be positioned on the first inorganic encapsulation film TFE1, and the second inorganic encapsulation film TFE3 may be positioned on the organic encapsulation film TFE 2. The first inorganic encapsulation film TFE1 and the second inorganic encapsulation film TFE3 may be constituted by a multilayer in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked on each other. The organic encapsulation film TFE2 may be an organic film including, for example, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

The sensor electrode layer SENL may be positioned on the encapsulation layer ENC. The sensor electrode layer SENL may include sensor electrodes TE and RE.

The second buffer film BF2 may be positioned on the encapsulation layer ENC. The second buffer film BF2 may include at least one inorganic film. For example, the second buffer film BF2 may be composed of a plurality of layers in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked with each other. The second buffer film BF2 may be removed.

The first bridge BE1 may BE positioned on the second buffer film BF 2. The first bridge BE1 may BE composed of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may BE composed of a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO/APC/ITO).

The first sensor insulating film TINS1 may BE positioned on the first bridge BE 1. The first sensor insulating film TINS1 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

The sensor electrodes (i.e., the driving electrode TE and the sensing electrode RE) may be positioned on the first sensor insulating film TINS 1. In addition, the dummy pattern may be positioned on the first sensor insulating film TINS 1. The driving electrode TE, the sensing electrode RE, and the dummy pattern do not overlap the emission area EA. The driving electrode TE, the sensing electrode RE, and the dummy pattern may be composed of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may be composed of a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO/APC/ITO). The driving electrode TE may BE electrically connected to the first bridge BE1 through a first sensor electrode contact hole TCNT1 penetrating the first sensor insulating film TINS 1.

The second sensor insulating film TINS2 may be positioned on the driving electrode TE, the sensing electrode RE, and the dummy pattern. The second sensor insulating film TINS2 may include at least one of an inorganic film and an organic film. The inorganic film may be a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic film may include acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

Fig. 6 is a layout diagram showing an example of the area a of fig. 2 in more detail. Fig. 6 is a layout diagram illustrating the display area DA and the non-display area NDA positioned on the right side of the display panel 100 according to some embodiments.

Referring to fig. 6, the display area DA may include a plurality of emission areas EA1, EA2, EA3, and EA4. The plurality of emission areas EA1, EA2, EA3, and EA4 may include a first emission area EA1 that emits light of a first color, second and fourth emission areas EA2 and EA4 that emit light of a second color, and a third emission area EA3 that emits light of a third color. For example, the light of the first color may be light in a red wavelength range of approximately 600nm to 750nm, the light of the second color may be light in a green wavelength range of approximately 480nm to 560nm, and the light of the third color may be light in a blue wavelength range of approximately 370nm to 460 nm. However, it should be understood that the present disclosure is not limited thereto.

Although the second and fourth emission areas EA2 and EA4 emit the same color of light (i.e., the second color of light) in the example shown in fig. 6, embodiments of the present disclosure are not limited thereto. The second and fourth emission areas EA2 and EA4 may emit light of different colors. For example, the second emission area EA2 may emit light of a second color, and the fourth emission area EA4 may emit light of a fourth color.

In addition, although each of the first, second, third, and fourth emission areas EA1, EA2, EA3, and EA4 may have a rectangular shape when viewed from the top in the example shown in fig. 6, embodiments of the present disclosure are not limited thereto. Each of the first, second, third, and fourth emission areas EA1, EA2, EA3, and EA4 may have other polygonal shapes, circular shapes, or elliptical shapes than the quadrangular shape when viewed from the top.

In addition, as shown in fig. 6, the third emission area EA3 may be the largest, and the second emission area EA2 and the fourth emission area EA4 may be the smallest. The second emission area EA2 and the fourth emission area EA4 may have the same size.

The second emission areas EA2 and the fourth emission areas EA4 may be alternately arranged in the first direction (X-axis direction). The second emission area EA2 may be arranged in a second direction (Y-axis direction). The fourth emission area EA4 may be arranged in the second direction (Y-axis direction). Each of the fourth emission areas EA4 may have a long side in the first diagonal direction DD1 and a short side in the second diagonal direction DD2, and each of the second emission areas EA2 may have a long side in the second diagonal direction DD2 and a short side in the first diagonal direction DD 1. The first diagonal direction DD1 may refer to a diagonal direction between a first direction (X-axis direction) and a second direction (Y-axis direction), and the second diagonal direction DD2 may be perpendicular to the first diagonal direction DD 1.

The first and third emission areas EA1 and EA3 may be alternately arranged in the first direction (X-axis direction). The first emission area EA1 may be arranged in the second direction (Y-axis direction). The third emission area EA3 may be arranged in the second direction (Y-axis direction). Each of the first and third emission areas EA1 and EA3 may have a square shape when viewed from the top, but embodiments of the present disclosure are not limited thereto. In this case, each of the first and third emission areas EA1 and EA3 may include two sides parallel to each other in the first diagonal direction DD1 and two sides parallel to each other in the second diagonal direction DD 2.

The non-display area NDA may include a first non-display area NDA1 and a second non-display area NDA2. In the first non-display area NDA1, a structure for driving pixels of the display area DA may be positioned. The second non-display area NDA2 may be positioned on the outside of the first non-display area NDA 1. The second non-display area NDA2 may be an edge area of the non-display area NDA. In addition, the second non-display area NDA2 may be an edge area of the display panel 100.

The first non-display area NDA1 may include a scan driving circuit SDC, a first power voltage line VSL, a first DAM1, and a second DAM2.

The scan driving circuit SDC may include a plurality of stages STA. The plurality of stages STA may be correspondingly connected to scan lines of the display area DA extending in the first direction (X-axis direction). That is, the plurality of stages STA may be connected to scan lines of the display area DA extending in the first direction (X-axis direction), respectively. The stage STA may sequentially apply a scan signal to the scan lines.

The first power supply voltage line VSL may be positioned on the outside of the scan driving circuit SDC. That is, the first power voltage line VSL may be positioned closer to the edge EG of the display panel 100 than the scan driving circuit SDC. The first power voltage line VSL may extend in the second direction (Y-axis direction) in the non-display area NDA on the right side of the display panel 100.

The first supply voltage line VSL may be electrically connected to the common electrode 173, and thus the common electrode 173 may receive the first supply voltage from the first supply voltage line VSL.

The first DAM1 and the second DAM2 are structures for preventing or reducing the organic encapsulation film TFE2 of the encapsulation layer ENC from overflowing to the edge EG of the display panel 100. The first DAM1 and the second DAM2 may extend in the second direction (Y-axis direction) in the non-display area NDA on the right side of the display panel 100. The second DAM2 may be positioned on the outside of the first DAM 1. The first DAM1 may be positioned closer to the scan driving circuit SDC than the second DAM2, and the second DAM2 may be positioned closer to the edge EG of the display panel 100 than the first DAM 1.

Although the first DAM1 and the second DAM2 are positioned on the first power supply voltage line VSL in the example shown in fig. 6, embodiments of the present disclosure are not limited thereto. For example, one of the first DAM1 and the second DAM2 may not be positioned on the first power supply voltage line VSL. Alternatively, none of the first DAM1 and the second DAM2 may be positioned on the first power supply voltage line VSL. In this case, the first DAM1 and the second DAM2 may be positioned on the outer side of the first power supply voltage line VSL.

In addition, although the display panel 100 according to some embodiments includes two DAMs DAM1 and DAM2 as shown in fig. 6, embodiments of the present disclosure are not limited thereto. For example, the display panel 100 according to some embodiments may include three or more dams.

The second non-display area NDA2 may include a crack dam CRD and an edge area EGA.

The crack dam CRD may be a structure for preventing or reducing the occurrence of cracks during the process of cutting the substrate SUB in the process of manufacturing the display device 10. The crack dam CRD may be an outermost structure positioned at an outermost position on the right side of the display panel 100. The crack dam CRD may extend in the second direction (Y-axis direction) in the non-display area NDA on the right side of the display panel 100.

The edge region EGA may extend along an edge EG of the display panel 100. The edge area EGA may be an area in which a process mark occurs during the process of cutting the substrate SUB.

Fig. 7 is a layout diagram showing an example of the region B of fig. 2 in more detail. Fig. 7 is a layout diagram illustrating a non-display area NDA positioned on the underside of the display panel 100 according to some embodiments.

Referring to fig. 7, the first non-display area NDA1 may include a plurality of display pads PD, a plurality of first driving pads DPD1, a plurality of second driving pads DPD2, a plurality of pad lines PDL, a plurality of fan-out lines FL, a first DAM1, and a second DAM2.

The plurality of display pads PD may be electrically connected to the circuit board 300 through a conductive adhesive member such as an anisotropic conductive film and an anisotropic conductive adhesive. The plurality of display pads PD may be connected to the pad lines PDL, respectively. The pad line PDL may connect the display pad PD with the first driving pad DPD 1.

The plurality of first driving pads DPD1 and the plurality of second driving pads DPD2 may be electrically connected to the driving IC 200 through conductive adhesive members such as an anisotropic conductive film and an anisotropic conductive adhesive. The plurality of first driving pads DPD1 may be input pads for driving the IC 200 to receive signals (e.g., digital video data, data timing control signals, etc.) of the circuit board 300. The plurality of second driving pads DPD2 may be output pads for outputting signals (e.g., data voltages) of the driving IC 200. The plurality of second driving pads DPD2 may be connected to the fanout lines FL, respectively. The fanout line FL may connect the second driving pad DPD2 with the data line of the display area DA.

The plurality of first driving pads DPD1 may be positioned closer to the display area DA in the second direction (Y-axis direction) than the display pad PD connected thereto. That is, among the display pad PD and the first driving pad DPD1 connected to each other, the display pad PD may be positioned closer to the edge EG of the display panel 100 than the first driving pad DPD1 in the second direction (Y-axis direction).

Each of the plurality of second driving pads DPD2 may be positioned closer to the display area DA in the second direction (Y-axis direction) than a corresponding one of the plurality of first driving pads DPD 1. That is, the first driving pad DPD1 may be positioned closer to the edge EG of the display panel 100 than the plurality of second driving pads DPD2 in the second direction (Y-axis direction).

The first DAM1 and the second DAM2 may cross the fan-out line FL. The first DAM1 and the second DAM2 may extend in a first direction (X-axis direction) in the non-display area NDA on the lower side of the display panel 100. The second DAM2 may be positioned on the outside of the first DAM 1. The first DAM1 may be positioned closer to the display area DA than the second DAM2, and the second DAM2 may be positioned closer to the edge EG of the display panel 100 than the first DAM 1.

Fig. 8 is a layout diagram showing an example of the region D of fig. 2 in more detail. Fig. 8 is a layout diagram illustrating a display area DA and a non-display area NDA positioned on an upper side of the display panel 100 according to some embodiments.

Referring to fig. 8, the first non-display area NDA1 may include a first power voltage line VSL, a first DAM1, and a second DAM2. The first non-display area NDA1 may not include the scan driving circuit SDC.

The first power voltage line VSL may extend in a first direction (X-axis direction) in the non-display area NDA on the upper side of the display panel 100. The first supply voltage line VSL may be electrically connected to the common electrode 173, and thus the common electrode 173 may receive the first supply voltage from the first supply voltage line VSL.

The first DAM1 and the second DAM2 may extend in a first direction (X-axis direction) in the non-display area NDA on the upper side of the display panel 100. The second DAM2 may be positioned on the outside of the first DAM 1. The first DAM1 may be positioned closer to the display area DA than the second DAM2, and the second DAM2 may be positioned closer to the edge EG of the display panel 100 than the first DAM 1.

Although the first DAM1 and the second DAM2 are positioned on the first power supply voltage line VSL in the example shown in fig. 8, embodiments of the present disclosure are not limited thereto. For example, one of the first DAM1 and the second DAM2 may not be positioned on the first power supply voltage line VSL. Alternatively, none of the first DAM1 and the second DAM2 may be positioned on the first power supply voltage line VSL. In this case, the first DAM1 and the second DAM2 may be positioned on the outer side of the first power supply voltage line VSL.

The crack dam CRD may be an outermost structure positioned at an outermost position on the upper side of the display panel 100. The crack dam CRD may extend in a first direction (X-axis direction) in the non-display area NDA on the upper side of the display panel 100.

Fig. 9 is a cross-sectional view illustrating an example of a display panel taken along line II-II' of fig. 6. Fig. 10 is a cross-sectional view illustrating an example of a display panel taken along line III-III' of fig. 7. Fig. 11 is a cross-sectional view illustrating an example of a display panel taken along the line IV-IV' of fig. 8.

In the cross-sectional views of fig. 9 to 11, the edge EG of the display panel 100 is shown when the substrate SUB of the display panel 100 is cut by irradiating laser light and then spraying an etchant.

Referring to fig. 9 to 11, when the substrate SUB is cut by irradiating laser light and then spraying an etchant, a process mark may be formed in the edge region EGA on the upper surface US of the substrate SUB by the etchant. The edge region EGA may be within approximately 30 μm.

The edge region EGA may include a first inclined surface ip1_1 formed by irradiating laser light and then spraying an etchant. The angle θ1 between the side surface SS1 and the upper surface US may be approximately 90 degrees. In other words, the side surface SS1 may be substantially perpendicular to the upper surface US. The angle θ2 between the side surface SS1 and the first inclined surface ip1_1 and the angle θ3 between the first inclined surface ip1_1 and the bottom surface BS may be obtuse angles. The process marks formed on the upper surface US of the substrate SUB may overlap the first inclined surface ip1_1 in the third direction (Z-axis direction).

The crack dam CRD may be a structure for preventing or reducing the occurrence of cracks during the process of cutting the substrate SUB in the process of manufacturing the display device 10. The crack dam CRD may be an outermost structure positioned at an outermost position on the right side of the display panel 100. The distance D1 between the crack dam CRD and the edge area EGA may be equal to or less than approximately 70 μm.

The minimum distance from the crack dam CRD to the edge EG of the display panel 100 may be equal to the sum of the width of the edge area EGA and the minimum distance D1 from the crack dam CRD to the edge area EGA. When the substrate SUB is cut by irradiating a laser and then spraying an etchant, the minimum distance between the crack dam CRD and the edge EG of the display panel 100 may vary according to a single-sided tolerance of the laser. For example, when the single-sided tolerance of the laser is 50 μm, the distance D1 between the crack dam CRD and the edge region EGA may be at least 50 μm or at most 150 μm.

The minimum distance from the display pad PD to the edge EG of the display panel 100 may be equal to the sum of the width of the edge area EGA and the minimum distance D2 from the display pad PD to the edge area EGA. When the substrate SUB is cut by irradiating a laser and then spraying an etchant, the minimum distance between the display pad PD and the edge of the substrate SUB may vary according to a single-sided tolerance of the laser. For example, when the one-sided tolerance of the laser is 50 μm, the distance D2 between the display pad PD and the edge region EGA may be at least 50 μm or at most 150 μm.

In addition, when the substrate SUB of the display panel 100 is cut by irradiating laser light and then spraying an etchant during the process of manufacturing the display panel 100, the side surface SS1 and the first inclined surface ip1_1 of the display panel 100 may be etched by the etchant. In this case, the roughness of the side surface SS1 and the first inclined surface ip1_1 of the display panel 100 may be approximately 50 μm or less. The roughness of the side surface SS1 and the first inclined surface ip1_1 of the display panel 100 when the substrate SUB of the display panel 100 is cut by irradiating laser light and then spraying an etchant may be smaller than the roughness of the side surface SS1 and the first inclined surface ip1_1 of the display panel 100 when the substrate SUB is cut by a cutting member and then a polishing process is performed.

When the substrate SUB of the display panel 100 is cut by irradiating laser and then spraying an etchant, the minimum distance from the crack dam CRD to the edge EG of the display panel 100 may be reduced. Therefore, when the substrate SUB of the display panel 100 is cut by irradiating laser light and then spraying an etchant, the width of the second non-display area NDA2 can be greatly reduced. In other words, the width of the non-display area NDA can be reduced.

Referring to fig. 12, the crack dam CRD may include the same material as the first organic film 160. The crack dam CRD may be positioned on the buffer film BF. The crack dam CRD may be formed of an organic layer including, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

Although the crack dam CRD includes one organic film layer in the example shown in fig. 12, embodiments of the present disclosure are not limited thereto. For example, the crack dam CRD may further include another organic film layer including the same material as the second organic film 180. Alternatively, the crack dam CRD may further include another organic film layer including the same material as the bank 190. Optionally, the crack dam CRD may further include a further organic film layer including the same material as the spacer 191 (see fig. 5).

The first power voltage line VSL may include the same material as the first data metal layer including the first connection electrode CE1 and the data line, and may be positioned at the same layer. The first supply voltage line VSL may be positioned on the second interlayer dielectric film 142. The first power voltage line VSL may be composed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

The first DAM1 and the second DAM2 may be positioned on the first power supply voltage line VSL. The first DAM1 may include a first sub-DAM SDAM1 and a second sub-DAM SDAM2, and the second DAM2 may include a first sub-DAM SDAM1, a second sub-DAM SDAM2, and a third sub-DAM SDAM3. The first sub-dam SDAM1 may include the same material as the first organic film 160, and may be positioned at the same layer. The second sub-dam SDAM2 may include the same material as the second organic film 180, and may be positioned at the same layer. The third sub-dam SDAM3 may include the same material as the bank 190 and may be positioned at the same layer.

The height of the first DAM1 may be lower than the height of the second DAM2, but the embodiment of the present disclosure is not limited thereto. The height of the first DAM1 may be substantially equal to or higher than the height of the second DAM 2.

The common electrode 173 may be connected to a portion of the first power voltage line VSL exposed without being covered by the first organic film 160, the second organic film 180, and the first DAM 1. Accordingly, the common electrode 173 may receive the first power supply voltage from the first power supply voltage line VSL.

The first inorganic encapsulation film TFE1 may cover the first DAM1, the second DAM2, and the crack DAM CRD in the non-display area NDA on the right side of the display panel 100. The first inorganic encapsulation film TFE1 may extend to near the edge EG of the display panel 100 in the non-display area NDA on the right side of the display panel 100. The side surface of the first inorganic encapsulation film TFE1 may be aligned with the side surface of the substrate SUB.

The organic encapsulation film TFE2 may be arranged to cover the top surface of the first DAM1, but not the top surface of the second DAM 2. However, it should be understood that the present disclosure is not limited thereto. The organic encapsulation film TFE2 may cover neither the top surface of the first DAM1 nor the top surface of the second DAM 2. By means of the first DAM1 and the second DAM2, it may be possible to prevent or reduce the organic encapsulation film TFE2 from overflowing to the edge EG of the display panel 100.

The second inorganic encapsulation film TFE3 may cover the first DAM1, the second DAM2, and the crack DAM CRD in the non-display area NDA on the right side of the display panel 100. The second inorganic encapsulation film TFE3 may extend to near the edge EG of the display panel 100 in the non-display area NDA on the right side of the display panel 100. The side surface of the second inorganic encapsulation film TFE3 may be aligned with the side surface of the substrate SUB.

An inorganic encapsulation region from the second DAM2 to the edge EG of the display panel 100, in which the first and second inorganic encapsulation films TFE1 and TFE3 contact each other, may be formed. The inorganic encapsulation area may surround the second DAM2.

Incidentally, a scanning thin film transistor STFT (including a scanning channel region STCH, a scanning source region STS, a scanning drain region STD, and a scanning gate electrode STG) of the scanning drive circuit SDC is shown in fig. 12. Since the scanning thin film transistor STFT is substantially the same as the thin film transistor TFT described above with reference to fig. 5; therefore, the scanning thin film transistor STFT will not be described.

Referring to fig. 13, each of the display pad PD, the first driving pad DPD1, and the second driving pad DPD2 may include a first auxiliary pad SPD1, a second auxiliary pad SPD2, and a third auxiliary pad SPD3.

The first auxiliary pad SPD1 may include the same material as the first gate metal layer including the gate electrode TG, the first capacitor electrode CAE1 of the capacitor Cst, and the scan line, and may be positioned at the same layer. The first auxiliary pad SPD1 may be positioned on the gate insulator 130. The first auxiliary pad SPD1 may be composed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

The second auxiliary pad SPD2 may include the same material as the second gate metal layer including the second capacitor electrode CAE2, and may be positioned at the same layer. The second auxiliary pads SPD2 may be positioned on the first interlayer dielectric film 141. The second auxiliary pad SPD2 may be composed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

The third auxiliary pad SPD3 may include the same material as the first data metal layer including the first connection electrode CE1 and the data line, and may be positioned at the same layer. The third auxiliary pads SPD3 may be positioned on the second interlayer dielectric film 142. The third auxiliary pad SPD3 may be composed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

The third auxiliary pads SPD3 of the display pad PD may be electrically connected to the circuit board 300 by conductive adhesive members such as an anisotropic conductive film and an anisotropic conductive adhesive. The third auxiliary pads SPD3 of the first driving pad DPD1 may be electrically connected to the input bumps IBP of the driving IC 200 through conductive adhesive members such as an anisotropic conductive film and an anisotropic conductive adhesive. The third auxiliary pads SPD3 of the second driving pad DPD2 may be electrically connected to the output bumps OBP of the driving IC 200 through conductive adhesive members such as an anisotropic conductive film and an anisotropic conductive adhesive. In fig. 13, for convenience of explanation, the driving IC 200 and the circuit board 300 are schematically shown.

The first and second inorganic encapsulation films TFE1 and TFE3 may be arranged to cover the first DAM1 and partially cover the second DAM2. For example, the first and second inorganic encapsulation films TFE1 and TFE3 may be arranged such that they do not cover a portion of the upper surface of the second DAM2. Alternatively, the first and second inorganic encapsulation films TFE1 and TFE3 may cover the first and second DAM1 and DAM2, but in this case, the first and second inorganic encapsulation films TFE1 and TFE3 may not cover the third auxiliary pad SPD3 of the second drive pad DPD2. That is, the first and second inorganic encapsulation films TFE1 and TFE3 may not extend to the display pad PD, the first and second driving pads DPD1 and DPD2 positioned adjacent to the edge EG of the display panel 100.

Referring to fig. 14, the first and second inorganic encapsulation films TFE1 and TFE3 may be arranged such that they do not cover the crack dam CRD in the non-display area NDA on the upper side of the display panel 100. That is, in the non-display area NDA on the upper side of the display panel 100, the first and second inorganic encapsulation films TFE1 and TFE3 may not extend to the edge EG of the display panel 100.

In addition, the first and second inorganic encapsulation films TFE1 and TFE3 may be arranged such that they cover the crack dam CRD in the non-display area NDA on the left and right sides of the display panel 100 except for the non-display area NDA on the upper side of the display panel 100. That is, the first and second inorganic encapsulation films TFE1 and TFE3 may extend to the edge EG of the display panel 100 in the non-display area NDA on the left and right sides of the display panel 100, except for the non-display area NDA on the upper side of the display panel 100.

Fig. 15 is a layout diagram illustrating an example of a via hole, an inorganic package region, a wiring region, and a display region of the display panel of region I of fig. 2 according to some embodiments. Fig. 16 is a cross-sectional view showing an example of the display panel taken along the line V-V' of fig. 15. Fig. 17 is an enlarged cross-sectional view showing an example of the region K of fig. 16 in more detail. Fig. 18 to 22 are enlarged cross-sectional views showing various examples of the region L of fig. 16.

Referring to fig. 15 to 17, a display panel 100 according to some embodiments of the present disclosure includes an inorganic encapsulation area IEA surrounding a through hole TH and a wiring area WLA surrounding the inorganic encapsulation area IEA.

In the inorganic encapsulation region IEA, the first inorganic encapsulation film TFE1 and the second inorganic encapsulation film TFE3 of the encapsulation layer ENC are in contact with each other to prevent or reduce the penetration of oxygen or moisture into the light emitting element layer EML of the display layer DISL due to the through holes TH.

The inorganic encapsulation area IEA may include at least one dam, at least one tip, and at least one recess. For example, as shown in fig. 17, the inorganic encapsulation area IEA may include a first dam HDAM1, a second dam HDAM2, first to eighth tips T1 to T8, and first to third grooves GR1 to GR3, which will be described later.

The first tip T1 and the second tip T2 may be positioned closer to the routing area WLA than the first dam HDAM 1. The first tip T1 may be positioned closer to the wiring region WLA than the second tip T2. The second tip T2 may be positioned between the first tip T1 and the first dam HDAM 1.

The third tip T3, the fourth tip T4, the fifth tip T5, and the sixth tip T6 may be positioned between the first dam HDAM and the second dam HDAM. At least a portion of the third tip T3 may overlap the first dam HDAM1 in a third direction (Z-axis direction).

The seventh and eighth tips T7 and T8 may be positioned closer to the through hole TH than the second dam HDAM 2. At least a portion of the seventh tip T7 may overlap the second dam HDAM2 in the third direction (Z-axis direction). The distance between the eighth tip T8 and the through hole TH may be approximately 50 μm.

The first groove GR1 may be positioned between the first tip T1 and the second tip T2. The second groove GR2 may be positioned between the third tip T3 and the fourth tip T4. The third groove GR3 may be positioned between the fifth tip T5 and the sixth tip T6.

In the wiring region WLA, a line extends around the through hole TH. Some of the lines may be connected to the data line, and some other of them may be connected to a second power supply voltage line from which a second power supply voltage higher than the first power supply voltage is applied. Still other ones of them may be connected to the scan line. The wiring area WLA may be surrounded by the display area DA.

An edge TEG of the through-hole TH when the substrate SUB of the display panel 100 is cut by irradiating laser light and then spraying an etchant is shown in a cross-sectional view of fig. 16.

Referring to fig. 16, when the substrate SUB is cut by irradiating laser light and then spraying an etchant, a process mark may be formed in the via edge region TEGA on the upper surface US of the substrate SUB by the etchant. The via edge region TEGA may be within approximately 30 μm.

The via edge region TEGA may include a first surface IS1, a second surface IS2, and a third surface IS3 between the first surface IS1 and the second surface IS2, which are formed by spraying an etchant after irradiating laser light. The first surface IS1 and the second surface IS2 may be inclined surfaces. The first surface IS1 and the second surface IS2 may be spaced apart from each other with the third surface IS3 therebetween. In other words, the substrate SUB may include a plurality of inclined surfaces spaced apart from each other.

The angle θ4 between the side surface SS1 and the upper surface US may be approximately 90 degrees. In other words, the side surface SS1 may be substantially perpendicular to the upper surface US. An angle θ5 between the bottom surface BS and the first surface IS1 and an angle θ6 between the third surface IS3 and the second surface IS2 may be obtuse angles. The process marks formed on the upper surface US of the substrate SUB may overlap the second surface IS2 in the third direction (Z-axis direction). However, it should be understood that the present disclosure is not limited thereto. The processing marks formed on the upper surface US of the substrate SUB may overlap the first surface IS1, the second surface IS2, and the third surface IS 3.

When the substrate SUB of the display panel 100 IS cut by irradiating laser light and then spraying an etchant, an angle θ5 between the bottom surface BS and the first surface IS1 and an angle θ6 between the third surface IS3 and the second surface IS2 may vary according to the depth of a laser irradiation area formed by the laser light. The depth of the laser irradiation region formed by the laser for cutting along the edge EG of the display panel 100 may be different from the depth of the laser irradiation region formed by the laser for cutting along the edge TEG of the through hole TH. The first surface IS1, the second surface IS2, and the third surface IS3 will be described in more detail with reference to fig. 18 to 22 to be described later.

Referring to fig. 17, the first dummy pattern DP1 may include the same material as the second gate metal layer including the second capacitor electrode CAE2 of the capacitor Cst, and may be positioned at the same layer. For example, the first dummy pattern DP1 may be positioned on the first interlayer dielectric film 141. The first dummy pattern DP1 may be composed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

The second dummy pattern DP2 may include the same material as the first data metal layer including the first connection electrode CE1 and the data line, and may be positioned at the same layer. For example, the second dummy pattern DP2 may be positioned on the second interlayer dielectric film 142. The second dummy pattern DP2 may be composed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

The second dummy pattern DP2 may overlap the first dummy pattern DP1 in the third direction (Z-axis direction).

The first to eighth tips T1 to T8 may include the same material as the second data metal layer including the second connection electrode CE2, and may be positioned at the same layer. For example, the first to eighth tips T1 to T8 may be positioned on the first organic film 160. The first to eighth tips T1 to T8 may be composed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

Each of the first to eighth tips T1 to T8 may be connected to the second dummy pattern DP2 through a contact hole penetrating the first organic film 160. Each of the first to eighth tips T1 to T8 may include an eave structure having a lower surface (or bottom surface) and an upper surface exposed without being covered by the first and second organic films 160 and 180, the first and second dams HDAM and HDAM. The fourth tip T4 and the fifth tip T5 may be integrally formed. Each of the first to eighth tips T1 to T8 may be a protrusion pattern or a groove pattern for forming a groove (or groove). The eighth tip T8 may be an outermost structure adjacent to the edge TEG of the through-hole TH. Although the eighth tip T8 is depicted in fig. 17 as an outermost structure adjacent to the edge TEG of the through-hole TH, embodiments of the present disclosure are not limited thereto. For example, if the seventh and eighth tips T7 and T8 are removed, the second dam HDAM may be an outermost structure adjacent to the edge TEG of the through-hole TH, which may prevent or reduce the overflow of the organic encapsulation film TFE2 of the encapsulation layer ENC. Alternatively, if the seventh and eighth tips T7 and T8 are removed, the groove separating the emission layer 172 from the common electrode 173 may be an outermost structure adjacent to the edge TEG of the through-hole TH.

The distance from the eighth tip T8 to the edge TEG of the through-hole TH may be approximately 300 μm. The via edge region TEGA may be positioned between the eighth tip T8 and the edge TEG of the via TH.

The first groove GR1 may be formed between the first and second tips T1 and T2, the second groove GR2 may be formed between the third and fourth tips T3 and T4, and the third groove GR3 may be formed between the fifth and sixth tips T5 and T6. The first groove GR1 may have an eave structure formed of the first and second tips T1 and T2, the second groove GR2 may have an eave structure formed of the third and fourth tips T3 and T4, and the third groove GR3 may have an eave structure formed of the fifth and sixth tips T5 and T6.

Since the emission layer 172 is deposited by evaporation and the common electrode 173 is deposited by sputtering, the step coverage is low, and thus it may be broken in each of the first groove GR1, the second groove GR2, and the third groove GR 3. On the other hand, since the first inorganic encapsulation film TFE1 and the second inorganic encapsulation film TFE3 are deposited by chemical vapor deposition, atomic layer deposition, or the like, they have high step coverage, and thus are not broken in each of the first groove GR1, the second groove GR2, and the third groove GR 3. Here, the step coverage means a ratio of the thin film applied on the inclined portion to the thin film applied on the flat portion. In each of the first groove GR1, the second groove GR2, and the third groove GR3, there may be a residue 172_d disconnected from the emission layer 172 and a residue 173_d disconnected from the common electrode 173.

The first dam HDAM may include a first sub-dam HDA1, a second sub-dam HDA2, a third sub-dam HDA3, and a fourth sub-dam HDA4. The first sub-dam HDA1 may be positioned on the first organic film 160 and may include the same material as the second organic film 180. The first sub-dam HDA1 may be positioned on the second tip T2 and the third tip T3. The second sub-dam HDA2 may be positioned on the first sub-dam HDA1 and may include the same material as the bank 190. The third and fourth sub-dams HDA3 and HDA4 may be positioned on the second sub-dam HDA2 and may include the same material as the spacers 191. However, it should be understood that the present disclosure is not limited thereto. The fourth sub-dam HDA4 may be positioned closer to the through holes TH than the third sub-dam HDA 3. The thickness of the fourth sub-dam HDA4 may be greater than the thickness of the third sub-dam HDA 3.

The second dam HDAM may include a fifth sub-dam HDA5, a sixth sub-dam HDA6, and a seventh sub-dam HDA7. The fifth sub-dam HDA5 may be positioned on the first organic film 160 and may include the same material as the second organic film 180. The fifth sub-dam HDA5 may be positioned on the seventh tip T7. The sixth sub-dam HDA6 may be positioned on the fifth sub-dam HDA5 and may include the same material as the bank 190. The seventh sub-dam HDA7 may be positioned on the sixth sub-dam HDA6 and may include the same material as the spacer 191. However, it should be understood that the present disclosure is not limited thereto.

By means of the first dam HDAM and the second dam HDAM, it may be possible to prevent or reduce the organic encapsulation film TFE2 from overflowing into the through holes TH.

The residue 172_d, the residue 173_d, the first inorganic encapsulation film TFE1, and the second inorganic encapsulation film TFE3 may extend to the edge TEG of the through hole TH. The end of the residue 172_d, the end of the residue 173_d, the end of the first inorganic encapsulation film TFE1, and the end of the second inorganic encapsulation film TFE3 may be aligned with the edge TEG of the through hole TH.

As shown in fig. 17, the emission layer 172 and the common electrode 173 are disconnected in each of the first, second, and third grooves GR1, GR2, and GR3 formed by the first to eighth tips T1 to T8, it may be possible to prevent or reduce penetration of oxygen, moisture, and the like through the emission layer 172 and the common electrode 173 exposed through the through holes TH.

According to some embodiments as shown in fig. 18, there may be a step edge between the side surface SS1 and the bottom surface BS in the through hole TH of the substrate SUB. For example, the substrate SUB may include a first surface IS1, a second surface IS2, and a third surface IS3 between the side surface SS1 and the bottom surface BS. The first surface IS1 may intersect the bottom surface BS and may extend from the bottom surface BS at a predetermined angle. The second surface IS2 may intersect the side surface SS1, and may extend from the side surface SS1 at a predetermined angle. The third surface IS3 may be positioned between the first surface IS1 and the second surface IS2, and one end may intersect the first surface IS1 and the other end may intersect the second surface IS 2.

An angle θ5 between the bottom surface BS and the first surface IS1 and an angle θ6 between the second surface IS2 and the third surface IS3 may be obtuse angles. The angle θ7 between the first surface IS1 and the third surface IS3 may be equal to the angle θ5 between the bottom surface BS and the first surface IS 1. The angle θ7 between the first surface IS1 and the third surface IS3 may be an external angle of the substrate SUB.

According to some embodiments of the present disclosure, a first surface IS1, a second surface IS2, and a third surface IS3 between the side surface SS1 and the bottom surface BS may be formed on the substrate SUB. There may be a step edge (i.e., two steps) between the bottom surface BS and the third surface IS3 and between the third surface IS3 and the side surface SS 1. These steps may be formed by laser irradiation regions formed by laser irradiation twice or more, which will be described later. A more detailed description thereof will be given below.

The first surface IS1 and the second surface IS2 may be inclined surfaces. The length of the first surface IS1 in the tilting direction may be equal to the length of the second surface IS2 in the tilting direction. The lengths of the first surface IS1 and the second surface IS2 may be adjusted according to the interval or depth of the laser irradiation area, which will be described later. The third surface IS3 may extend parallel to the bottom surface BS or the upper surface US. The length of the third surface IS3 between the first surface IS1 and the second surface IS2 may be smaller than the length of each of the first surface IS1 and the second surface IS 2. However, it should be understood that the present disclosure is not limited thereto.

In addition, a length TAL formed by the first surface IS1, the second surface IS2, and the third surface IS3 between the side surface SS1 and the bottom surface BS may be approximately 100 μm to 500 μm. For example, the length TAL between the end of the bottom surface BS and the side surface SS1 may be approximately 100 μm to 500 μm when viewed from the top. However, it will be understood that the present disclosure is not limited thereto. As the length TAL formed by the first, second, and third surfaces IS1, IS2, and IS3 increases, the substrate SUB may be easily separated from the mother substrate at the through holes TH. If the substrate SUB is not easily separated from the mother substrate, it is considered that the substrate SUB is separated by physical impact. However, a breakage problem may occur in which the substrate SUB is damaged at the edge of the through hole TH. According to some embodiments, by forming the substrate SUB including the first surface IS1, the second surface IS2, and the third surface IS3, it may be possible to easily separate the substrate SUB at the through holes TH.

According to some embodiments of the present disclosure, the substrate SUB has a step between the bottom surface BS and the third surface IS3 and a step between the third surface IS3 and the side surface SS1, thereby reducing an angle of an edge of the side surface of the substrate SUB. In this way, it may be possible to prevent or reduce the situation in which the substrate SUB is easily damaged by external impact due to a sharp edge on the side surface of the substrate SUB.

Referring to fig. 19 and 20, in the substrate SUB according to some embodiments, the length of the first surface IS1 in the inclined direction may be different from the length of the second surface IS2 in the inclined direction, and the angle θ5 between the bottom surface BS and the first surface IS1 may be different from the angle θ6 between the second surface IS2 and the third surface IS 3.

As shown in fig. 19, the length of the second surface IS2 in the tilting direction may be greater than the length of the first surface IS1 in the tilting direction. The length of the second surface IS2 in the oblique direction may be formed by increasing the depth of a second laser irradiation area, which will be described later, formed by irradiating a second laser. In addition, the length of the second surface IS2 in the oblique direction may be formed by increasing the interval between a third laser irradiation area, which will be described later, and a second laser irradiation area, which IS formed by irradiating a third laser.

In addition, an angle θ5 between the bottom surface BS and the first surface IS1 may be greater than an angle θ6 between the second surface IS2 and the third surface IS 3. Such structural features may be formed by adjusting the spacing or depth of the laser irradiated regions as described above.

In the example shown in fig. 19, the length of the second surface IS2 in the oblique direction IS greater than the length of the first surface IS1 in the oblique direction, and the angle θ5 between the bottom surface BS and the first surface IS1 IS greater than the angle θ6 between the second surface IS2 and the third surface IS 3. However, it should be understood that the present disclosure is not limited thereto. The length of the second surface IS2 in the inclined direction may be greater than the length of the first surface IS1 in the inclined direction, and the angle θ5 between the bottom surface BS and the first surface IS1 may be equal to the angle θ6 between the second surface IS2 and the third surface IS 3. In addition, an angle θ5 between the bottom surface BS and the first surface IS1 may be greater than an angle θ6 between the second surface IS2 and the third surface IS3, and a length of the second surface IS2 in the inclined direction may be equal to a length of the first surface IS1 in the inclined direction.

As shown in fig. 20, the length of the first surface IS1 in the tilting direction may be greater than the length of the second surface IS2 in the tilting direction. The length of the first surface IS1 in the oblique direction may be formed by increasing the depth of a third laser light irradiation region, which will be described later, formed by irradiating a third laser light. In addition, an angle θ6 between the second surface IS2 and the third surface IS3 may be greater than an angle θ5 between the bottom surface BS and the first surface IS 1. Such structural features may be formed by adjusting the depth of the laser irradiated region as described above.

In the example shown in fig. 20, the length of the first surface IS1 in the oblique direction IS greater than the length of the second surface IS2 in the oblique direction, and the angle θ6 between the second surface IS2 and the third surface IS3 IS greater than the angle θ5 between the bottom surface BS and the first surface IS 1. However, it should be understood that the present disclosure is not limited thereto. The length of the first surface IS1 in the inclined direction may be greater than the length of the second surface IS2 in the inclined direction, and the angle θ5 between the bottom surface BS and the first surface IS1 may be equal to the angle θ6 between the second surface IS2 and the third surface IS 3. In addition, an angle θ6 between the second surface IS2 and the third surface IS3 may be greater than an angle θ5 between the bottom surface BS and the first surface IS1, and a length of the first surface IS1 in the inclined direction may be equal to a length of the second surface IS2 in the inclined direction.

Incidentally, the third surface IS3 of the substrate SUB may not be parallel to the bottom surface BS or the upper surface US.

Referring to fig. 21, according to some embodiments, the third surface IS3 may be an inclined surface. For example, an angle θ7 between the third surface IS3 and the first surface IS1 may be different from an angle θ5 between the bottom surface BS and the first surface IS 1. The angle θ7 between the third surface IS3 and the first surface IS1 may be greater than the angle θ5 between the bottom surface BS and the first surface IS 1. In addition, an angle θ7 between the third surface IS3 and the first surface IS1 may be greater than an angle θ6 between the third surface IS3 and the second surface IS 2.

In addition, unlike the flat surfaces according to the above-described embodiments of fig. 18 to 21, the first surface IS1 and the second surface IS2 of the substrate SUB may be curved surfaces.

Referring to fig. 22, according to some embodiments, the first surface IS1 and the second surface IS2 of the substrate SUB may be curved surfaces. For example, the first surface IS1 may be a convex surface between the bottom surface BS and the third surface IS 3. The second surface IS2 may be a convex surface between the side surface SS1 and the third surface IS 3. However, it should be understood that the present disclosure is not limited thereto. One of the first surface IS1 and the second surface IS2 may be a curved surface, and the other may be a flat surface.

Although the first surface IS1 and the second surface IS2 are convex surfaces in fig. 22, the present disclosure IS not limited thereto. At least one of the first surface IS1 and the second surface IS2 may be a concave surface. In addition, although the third surface IS3 IS a flat surface, the present disclosure IS not limited thereto. The third surface IS3 may not be parallel to the bottom surface BS and may be a convex surface.

Hereinafter, a method of manufacturing the above-described display device will be described with reference to other drawings.

Fig. 23 is a flowchart for illustrating a method of manufacturing a display device according to some embodiments of the present disclosure. Fig. 24 to 39 are views for illustrating a method of manufacturing a display device according to some embodiments of the present disclosure. In the description of the method of manufacturing the display device, fig. 27 is a sectional view taken along the line VII-VII 'of fig. 26, except for the rest of the sectional views, taken along the line VI-VI' of the corresponding plan view.

First, as shown in fig. 24 and 25, a plurality of display units DPC are formed on a first surface of a mother substrate MSUB (S110 of fig. 23).

A display layer DISL of each of the plurality of display units DPC is formed on the first surface of the mother substrate MSUB. The display layer DISL includes a thin film transistor layer TFTL, a light emitting element layer EML, an encapsulation layer ENC, and a sensor electrode layer SENL.

Next, as shown in fig. 26 and 27, a plurality of first protective films PRF1 are attached on the plurality of display units DPC, and the plurality of display units DPC are inspected (S120 of fig. 23).

First, a first protective film layer is attached to cover the plurality of display units DPC and the mother substrate MSUB between the plurality of display units DPC. Then, by partially removing the first protective film layer positioned on the mother substrate MSUB, the plurality of first protective films PRF1 may be positioned on the plurality of display units DPC, respectively. That is, the first protective film layer may be partially removed, and the remaining portion may be a plurality of first protective films PRF1. Accordingly, the plurality of first protective films PRF1 may be positioned on the plurality of display units DPC, respectively. In other words, the number of first protective films PRF1 may be equal to the number of the plurality of display units DPC.

Each of the plurality of first protective films PRF1 may be a buffer film for protecting the display unit DPC from external impact. The plurality of first protective films PRF1 may be made of a transparent material.

Third, as shown in fig. 26 and 27, the first laser light LR1 is irradiated onto the second surface of the mother substrate MSUB so that a plurality of first laser irradiation regions CH1 are formed along the edges of the plurality of display units DPC (S130 of fig. 23).

According to some embodiments of the present disclosure, any of various lasers may be used as the first laser LR1. Here, as an example, the first laser light LR1 is an infrared bessel beam having a wavelength of approximately 1030 nm.

The first cutting line CL1 may be defined as a virtual line formed by connecting a plurality of first laser irradiation regions CH 1. The first cutting line CL1 may be formed by irradiating the first laser light LR1 emitted by the first laser module LD1 to form a plurality of first laser irradiation regions CH1 along edges of the plurality of display units DPC.

When the first laser light LR1 is irradiated on the second surface of the mother substrate MSUB, the depth (or approximate length) TCH1 of each of the plurality of first laser irradiation regions CH1 formed by the first laser light LR1 as shown in fig. 28 may be adjusted by adjusting the repetition rate, the processing speed, and the pulse energy. For example, as shown in a in fig. 28, the depth TCH1 of each of the plurality of first laser irradiation regions CH1 may be at least 200 μm from the first surface of the mother substrate MSUB. In addition, since the thickness of the mother substrate MSUB is approximately 500 μm, the depth TCH1 of each of the plurality of first laser irradiation regions CH1 may be as high as 500 μm as shown in b in fig. 28. That is, the depth TCH1 of each of the plurality of first laser irradiation regions CH1 may be approximately 225 μm to 500 μm from the first surface of the mother substrate MSUB. According to some embodiments, the depth TCH1 of the first laser irradiation area CH1 is equal to the thickness of the mother substrate MSUB.

The first laser light LR1 for forming the first laser light irradiation region CH1 may be irradiated at a repetition rate of 10kHz to 250kHz, a processing speed of 10mm/s to 250mm/s, and a pulse energy of 10 μj to 300 μj. In order for the first laser light LR1 to have a depth of approximately 225 μm from the first surface of the mother substrate MSUB, it is desirable to irradiate the first laser light LR1 at a repetition rate of approximately 17.5kHz to 125kHz, a processing speed of 17.5mm/s to 125mm/s, and a pulse energy of 25 μj to 178 μj.

Fourth, as shown in fig. 29 to 32, by irradiating the second laser light LR2 and the third laser light LR3 on the second surface of the mother substrate MSUB, a plurality of second laser irradiation regions CH2 and third laser irradiation regions CH3 for forming through holes in each of the plurality of display units DPC are formed (S140 of fig. 23).

Although step S140 is performed after step S130 is performed in the example shown in fig. 29, embodiments of the present disclosure are not limited thereto. In order to shorten the process time, step S130 and step S140 may be performed simultaneously using a plurality of laser modules (e.g., the second laser module LD2 and the third laser module LD 3).

The second cutting line CL2 may be defined as an imaginary line formed by connecting a plurality of second laser irradiation regions CH 2. The second cutting line CL2 may be formed by irradiating the second laser LR2 to form a plurality of second laser irradiation regions CH2 along the edge of the through hole TH. The second cutting line CL2 may depend on the shape of the through hole. For example, when the through hole TH has a circular shape when viewed from the top, the second cutting line CL2 may be formed in a circular shape.

The third cutting line CL3 may be defined as an imaginary line formed by connecting a plurality of third laser irradiation regions CH 3. The third cutting line CL3 may be formed by irradiating the third laser LR3 to form a plurality of third laser irradiation regions CH3 along the edge of the second cutting line CL 2. The third cutting line CL3 may depend on the shape of the through hole. For example, when the through hole TH has a circular shape when viewed from the top, the third cutting line CL3 may be formed in a circular shape.

According to some embodiments of the present disclosure, any of various lasers may be used as the second laser light LR2 and the third laser light LR3. Here, as an example, each of the second laser light LR2 and the third laser light LR3 is an infrared bessel beam having a wavelength of approximately 1030 nm.

The depth of each of the second laser irradiation regions CH2 formed by the second laser light LR2 may be different from the depth (approximate length) of each of the third laser irradiation regions CH3 formed by the third laser light LR 3. The depth of the second laser irradiation region CH2 may be defined as the depth (or approximate length) of the second laser irradiation region CH2, and the depth of the third laser irradiation region CH3 may be defined as the depth (or approximate length) of the third laser irradiation region CH 3.

Each of the plurality of second laser irradiation regions CH2 may have a depth of about 500 μm from the first surface of the mother substrate MSUB. Since the thickness of the mother substrate MSUB is approximately 500 μm, each of the plurality of second laser irradiation regions CH2 may have a depth of approximately 500 μm from the first surface of the mother substrate MSUB. That is, the depth of each of the plurality of second laser irradiation regions CH2 may be equal to the thickness of the mother substrate MSUB.

Each of the plurality of third laser irradiation regions CH3 may have a depth of approximately 225 μm from the first surface of the mother substrate MSUB. Since the thickness of the mother substrate MSUB is approximately 500 μm, each of the plurality of third laser irradiation regions CH3 may have a depth of approximately 200 μm to 500 μm from the first surface of the mother substrate MSUB. According to some embodiments of the present disclosure, the depth of the second laser irradiation region CH2 from the first surface of the mother substrate MSUB may be greater than the depth of the third laser irradiation region CH3 from the first surface of the mother substrate MSUB.

As shown in fig. 32, the depths (or approximate lengths) of the laser irradiation regions CH2 and CH3 may be adjusted according to the repetition rates, the processing speeds, and the pulse energies of the second laser light LR2 and the third laser light LR 3. If the depth (or approximate length) of the second laser irradiation region CH2 formed by the second laser LR2 is different from the depth (or approximate length) of the third laser irradiation region CH3 formed by the third laser LR3, the second laser LR2 and the third laser LR3 have different repetition rates, processing speeds, pulse energies, and the like.

For example, the second laser light LR2 may be irradiated at a repetition rate of 1kHz to 50kHz, a processing speed of 1mm/s to 50mm/s, and a pulse energy of 10 μj to 300 μj. In order to make the second laser light LR2 have a depth of approximately 400 μm to 500 μm from the first surface of the mother substrate MSUB, the second laser light LR2 may be irradiated at a repetition rate of approximately 10kHz, a processing speed of 10mm/s, and a pulse energy of 60 μj to 178 μj.

For example, the third laser light LR3 may be irradiated at a repetition rate of 10kHz to 250kHz, a processing speed of 10mm/s to 250mm/s, and a pulse energy of 10 μj to 300 μj. In order for the third laser light LR3 to have a depth of approximately 225 μm or more from the first surface of the mother substrate MSUB, it is desirable to irradiate the third laser light LR3 at a repetition rate of approximately 17.5kHz to 125kHz, a processing speed of 17.5mm/s to 125mm/s, and a pulse energy of 25 μj to 178 μj.

The single-sided tolerance of each of the second laser light LR2 and the third laser light LR3 may be within approximately 50 μm and the double-sided tolerance may be within approximately 100 μm. Here, the single-sided tolerance may refer to a cutting error in one direction (for example, the X-axis direction) when forming a laser irradiation region with laser light.

In addition, the interval SDL between the second laser light irradiation region CH2 formed by the second laser light LR2 and the third laser light irradiation region CH3 formed by the third laser light LR3 may be approximately 50 μm. The interval SDL between the second laser irradiation region CH2 and the third laser irradiation region CH3 may determine the lengths of the first surface IS1 and the second surface IS2 of the substrate SUB. For example, as the interval SDL between the second laser irradiation region CH2 and the third laser irradiation region CH3 increases, the length of the second surface IS2 in the oblique direction may become greater than the length of the first surface IS1 in the oblique direction.

Fifth, as shown in fig. 33, the second protective films PRF2 are attached on the plurality of first protective films PRF1 (S150 of fig. 23).

The second protective film PRF2 may be attached on the first protective film PRF1 and the exposed portion of the mother substrate MSUB that is not covered with the plurality of first protective films PRF 1. The second protective film PRF2 may cover the plurality of first laser irradiation regions CH1, the plurality of second laser irradiation regions CH2, and the plurality of third laser irradiation regions CH3. The second protective film PRF2 may be an acid-resistant film for protecting the plurality of display units DPC from the etchant in a subsequent process of etching the mother substrate MSUB.

Sixth, as shown in fig. 34 to 37, the etchant is sprayed on the second surface of the mother substrate MSUB without an additional mask so that the thickness of the mother substrate MSUB is reduced. In addition, the mother substrate MSUB is cut along the plurality of first and second laser irradiation regions CH1 and CH2, and the second protective film PRF2 is separated (S160 of fig. 23).

When the etchant is sprayed on the second surface of the mother substrate MSUB, the mother substrate MSUB may be reduced from the first thickness T1 '(see fig. 24) to the second thickness T2'. Since the mother substrate MSUB is etched without an additional mask, the mother substrate MSUB may be uniformly etched throughout the entire area of the second surface.

Each of the first laser irradiation regions CH1 may include a physical hole formed by the first laser LR1 and a region in which physical properties are changed by laser light as a periphery of the physical hole. Alternatively, each of the plurality of first laser irradiation regions CH1 may be a region in which physical properties are changed by the first laser LR1 without physical holes. Accordingly, the etching rate of the etchant in each of the plurality of first laser irradiation regions CH1 may be higher than that in other regions of the mother substrate MSUB where the laser is not irradiated.

Each of the second laser irradiation regions CH2 may include a physical hole formed by the second laser LR2 and a region in which physical properties are changed by laser light as a periphery of the physical hole. Alternatively, each of the plurality of second laser irradiation regions CH2 may be a region in which physical properties are changed by the second laser LR2 without physical holes. Accordingly, the etching rate of the etchant in each of the plurality of second laser irradiation regions CH2 may be higher than that in other regions of the mother substrate MSUB where the laser is not irradiated.

Each of the third laser irradiation regions CH3 may include a physical hole formed by the third laser LR3 and a region in which physical properties are changed by laser light as a periphery of the physical hole. Alternatively, each of the plurality of third laser irradiation regions CH3 may be a region in which physical properties are changed by the third laser LR3 without physical holes. Accordingly, the etching rate of the etchant in each of the plurality of third laser irradiation regions CH3 may be higher than that in other regions of the mother substrate MSUB where the laser is not irradiated. The third laser irradiation area CH3 may surround the second laser irradiation area CH2.

As shown in fig. 35, thinning is performed with an etchant to reduce the thickness of the mother substrate MSUB. At the same time, the etchant permeates into the plurality of second laser irradiation regions CH2 formed by the second laser light LR 2. Since the depth of each of the plurality of second laser irradiation regions CH2 is greater than the depth of each of the plurality of third laser irradiation regions CH3, the etchant may first infiltrate into the plurality of second laser irradiation regions CH 2. When the etchant penetrates into the second laser irradiation region CH2, there may be a difference in etching rate between the second laser irradiation region CH2 and a region where the second laser irradiation region CH2 is not formed. As a result, thinning can be performed at an inclination in the vicinity of the second laser irradiation area CH 2.

As shown in fig. 36, when the etchant penetrates into the third laser irradiation region CH3, there may be a difference in etching rate between the third laser irradiation region CH3 and a region where the third laser irradiation region CH3 is not formed. Specifically, there may be a difference in etching rate between the third laser irradiation area CH3 and the second laser irradiation area CH 2. Therefore, thinning is performed at an inclination in the vicinity of the second laser irradiation area CH2 and the third laser irradiation area CH 3. Thinning may be performed when the inclination may be reduced at some regions between the third laser irradiation region CH3 and the second laser irradiation region CH 2.

As shown in fig. 37, since etching is first performed in the second laser irradiation region CH2, the substrate SUB may be cut at the second cutting line CL2 formed through the second laser irradiation region CH2 so that the substrate SUB may be separated from the mother substrate MSUB. Accordingly, the substrate SUB may form the through hole TH, and a step may exist between the side surface SS1 and the bottom surface BS in the through hole TH, so that the first surface IS1, the second surface IS2, and the third surface IS3 between the first surface IS1 and the second surface IS2 may be formed.

In addition, as the etchant penetrates into the plurality of first laser irradiation regions CH1 formed by the first laser LR1, the mother substrate MSUB may be separated along the first cutting line CL 1. In other words, each of the plurality of display units DPC may be separated from the mother substrate MSUB.

The etchant does not permeate into the first surface of the substrate SUB separated from the mother substrate MSUB due to the second protective film PRF2, and the second surface of the substrate SUB is etched by the etchant. Accordingly, the first and second surfaces of the substrate SUB may have differences in roughness, hardness, light transmittance, light reflectance, local density, surface chemical structure, and the like.

After the etching process is completed, the second protective film PRF2 may be separated.

Seventh, as shown in fig. 38 and 39, the driving IC 200 and the circuit board 300 are attached to each of the plurality of display units DPC, and the first protective film PRF1 is separated from each of the plurality of display units DPC (S170 of fig. 23).

As described above, by using the etching process, the thickness of the mother substrate MSUB may be reduced, the substrate SUB of each of the plurality of display units DPC may be separated from the mother substrate MSUB, and the through holes TH may be formed. In this way, it may be possible to increase the efficiency of the manufacturing process.

Referring to fig. 40 to 42, according to some embodiments, after the above-described second laser light LR2 and third laser light LR3 are irradiated, a fourth laser light irradiation region CH4 may be further formed by irradiating fourth laser light LR 4.

The fourth laser light LR4 may be irradiated between the third laser irradiation regions CH3 adjacent to the second laser irradiation regions CH 2. When the through hole TH has a circular shape when viewed from the top, the fourth laser irradiation area CH4 formed by the fourth laser light LR4 may have a circular shape when viewed from the top. The fourth laser light LR4 may be an infrared bessel beam having a wavelength of approximately 1030nm similarly to the third laser light LR3, and may be irradiated under the same conditions as the third laser light LR 3.

The depth of the fourth laser irradiation region CH4 formed by the fourth laser LR4 may be smaller than the depth of the third laser irradiation region CH 3. This is because if the depth of the fourth laser irradiation area CH4 is relatively large, the substrate SUB may be cut at the fourth laser irradiation area CH 4.

As shown in fig. 41, when the etchant penetrates into the fourth laser irradiation region CH4, there may be a difference in etching rate between the fourth laser irradiation region CH4 and a region where the fourth laser irradiation region CH4 is not formed. Specifically, there may be a difference in etching rate between the fourth laser irradiation area CH4 and the second laser irradiation area CH 2. Therefore, thinning is performed at an inclination in the vicinity of the fourth laser irradiation area CH 4. When there is substantially no inclination between the fourth laser irradiation area CH4 and the second laser irradiation area CH2, thinning may be performed.

As shown in fig. 42, since etching is first performed in the second laser irradiation region CH2, the substrate SUB may be cut at the second cutting line CL2 formed through the second laser irradiation region CH2 so that the substrate SUB may be separated from the mother substrate MSUB. The side surface of the mother substrate MSUB, in which the through holes TH are formed, forms a stepped edge similar to the substrate SUB. The step edge of the side surface of the mother substrate MSUB may decrease an angle of the edge of the mother substrate MSUB, and may increase a width of the step edge. Therefore, when the mother substrate MSUB is separated from the substrate SUB, the through holes TH have a larger width, so that they can be more easily separated.

Fig. 43 is an image showing a through hole of the display device according to the comparative example. Fig. 44 is an image illustrating a through hole of a display device according to some embodiments of the present disclosure.

Fig. 43 shows a via formed via a laser ablation process. Fig. 44 shows a via hole formed by the laser irradiation and the etchant described above.

As can be seen from fig. 43, the display device according to the comparative example is damaged due to the high heat in the vicinity of the through hole TH. In contrast, as shown in fig. 44, in the display device according to some embodiments, damage hardly occurs in the vicinity of the through holes TH.

In view of the above, by forming the through-hole using laser irradiation and an etchant, it may be possible to prevent or reduce the display device according to some embodiments from being damaged in the vicinity of the through-hole.

In summarizing the detailed description, those skilled in the art will understand that many variations and modifications may be made to the example embodiments without substantially departing from the principles of the present utility model. Accordingly, the example embodiments of the disclosed utility model are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. A display device, characterized in that the display device comprises:

A substrate including an upper surface carrying a light emitting element, a bottom surface facing the upper surface, and a through hole penetrating the upper surface and the bottom surface,

Wherein the substrate comprises: a side surface intersecting the upper surface in the through hole; a first surface intersecting the bottom surface; a second surface intersecting the side surface; and a third surface between the first surface and the second surface, and

Wherein the first and second surfaces are spaced apart from each other with the third surface between the first and second surfaces, and the first and second surfaces are sloped surfaces.

2. The display device of claim 1, wherein the display device comprises a display device,

One end of the third surface intersects the first surface; and

The opposite end of the third surface intersects the second surface.

3. The display device according to claim 1, wherein an angle between the bottom surface and the first surface and an angle between the third surface and the second surface are obtuse angles.

4. The display device of claim 1, wherein an angle between the bottom surface and the first surface is equal to, greater than, or less than an angle between the third surface and the second surface.

5. The display device according to claim 1, wherein a length of the first surface in an oblique direction is equal to, greater than, or less than a length of the second surface in the oblique direction.

6. The display device according to claim 1, wherein the third surface extends parallel to the bottom surface or the upper surface; or alternatively

The third surface is an inclined surface.

7. The display device of claim 1, wherein at least one of the first surface and the second surface is a flat surface or a curved surface.

8. The display device according to claim 1, wherein a length between the bottom surface and the side surface on a plane formed by the first surface, the second surface, and the third surface is 100 μm to 500 μm.

9. A display device, characterized in that the display device comprises:

Wherein the substrate comprises: a side surface intersecting the upper surface in the through hole; a first surface intersecting the bottom surface; a second surface intersecting the side surface; and a third surface, between the first surface and the second surface,

Wherein the angle between the bottom surface and the first surface and the angle between the third surface and the second surface are obtuse angles, and

Wherein the bottom surface and the third surface form a stepped edge.

10. The display device according to claim 9, wherein the display device further comprises: an optical device is at least partially embedded in the through hole.