CN220603807U

CN220603807U - Display device

Info

Publication number: CN220603807U
Application number: CN202322272543.6U
Authority: CN
Inventors: 金完政; 金东朝; 金仙花; 金荣志; 金昌植; 南炅我; 文孝英; 朴镛昇; 严理璱; 尹大相; 李宽熙; 李昭玲; 李荣勳; 崔永瑞; 金善永; 孙智媛; 李度咏; 李承勳
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2022-08-31
Filing date: 2023-08-22
Publication date: 2024-03-15
Anticipated expiration: 2033-08-22
Also published as: CN117631348A

Abstract

A display device is disclosed. The display device includes: a substrate including a first surface, a second surface opposite the first surface, and a side surface between the first surface and the second surface; an outermost structure on the first surface of the substrate and positioned adjacent to an edge of one side of the substrate; and a display region including a plurality of light emitting regions on the first surface of the substrate. The minimum distance from the side surface of the substrate to the outermost structure is 130 μm or less. Accordingly, the width of the non-display region may be reduced or minimized, the mechanical strength of the display device may be improved, and it may be possible to cut the substrate while reducing the thickness of the substrate.

Description

Display device

Technical Field

One or more embodiments of the present disclosure relate to a display device, a method for manufacturing the display device, and an electronic device including the display device.

Background

With the development of information society, demands for display devices for displaying images are increasing in various forms. The display device may be a flat panel display such as a liquid crystal display, a field emission display, or a light emitting display panel.

The display device includes a display area for displaying an image and a non-display area arranged to surround a periphery of the display area (e.g., the display area). Recently, the width of the non-display area is gradually decreasing in order to increase the immersion of the display area and to increase the aesthetic appearance of the display device.

The display device may be formed by cutting the mother substrate along lines defining a plurality of display units formed on the mother substrate including the plurality of display units in a manufacturing process of the display device.

The non-display region may include a first non-display region in which lines and circuits for driving the display region are disposed, and a second non-display region corresponding to a margin for a cutting process in the manufacturing process. Because there are limitations in reducing lines and circuits in the first non-display area, methods for reducing the width of the second non-display area are being studied.

Disclosure of Invention

An object of the present utility model is to provide a display device capable of reducing or minimizing a width of a non-display area, a method of manufacturing the display device, and an electronic device including the display device.

Another object of the present utility model is to provide a display device capable of improving mechanical strength of the display device, a method of manufacturing the display device, and an electronic device including the display device.

It is still another object of the present utility model to provide a display device capable of cutting a substrate while reducing the thickness of the substrate, a method of manufacturing the display device, and an electronic device including the display device.

However, embodiments of the present disclosure are not limited to the embodiments set forth herein. The above and other embodiments of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

According to one or more embodiments of the present disclosure, there is provided a display device, which may include: a substrate including a first surface, a second surface opposite the first surface, and a side surface between the first surface and the second surface; an outermost structure on the first surface of the substrate and positioned adjacent to an edge of one side of the substrate; and a display region including a plurality of light emitting regions on the first surface of the substrate, wherein a minimum distance from a side surface of the substrate to the outermost structure may be equal to 130 μm or less.

In an embodiment, the plurality of light emitting regions may be positioned farther from an edge of a side of the substrate than the outermost structure, and the first surface of the substrate may include a treatment trace positioned closer to the edge of the side of the substrate than the outermost structure, wherein a width of the treatment trace may be 50 μm or less.

In an embodiment, the minimum distance between the outermost structure and the processing trace may be 30 μm or less.

In an embodiment, the substrate may further include a first inclined surface between the side surface and the second surface, wherein an angle between the side surface and the first inclined surface and an angle between the first inclined surface and the second surface may be an obtuse angle.

In an embodiment, the outermost structure may include a crack dam extending between one side and the other side of the display area and along an edge of the substrate.

In an embodiment, the outermost structure may include a display pad electrically connected to the circuit board by a conductive adhesive member.

In an embodiment, the display device may further include an electrostatic protection line between the display pad and one edge of the substrate.

In an embodiment, the electrostatic protection line may include: a main path region extending from the display pad to one edge of the substrate; and a secondary path region protruding from the primary path region.

According to one or more embodiments of the present disclosure, there is provided a display device, which may include: a substrate including a first surface, a second surface opposite to the first surface, a side surface between the first surface and the second surface, a through hole penetrating the first surface and the second surface, and a side surface of the through hole between the first surface and the second surface at an edge of the through hole; a first outermost structure on the first surface of the substrate and positioned adjacent to one edge of the substrate; and a second outermost structure on the first surface of the substrate and positioned adjacent to the edge of the through hole, wherein a distance from the first outermost structure to one edge of the substrate may be smaller than a distance from the second outermost structure to the edge of the through hole.

According to one or more embodiments of the present disclosure, there is provided a display device, which may include: a first substrate including a first surface, a second surface opposite the first surface, and a first side surface between the first surface and the second surface; a second substrate on the first substrate; and a light emitting element layer including a plurality of light emitting regions on the second substrate, wherein the first substrate may further include a side surface of the curved region between the first surface and the second surface at an edge of the curved region where the second substrate is curved, wherein a cross-sectional shape of the first side surface and a cross-sectional shape of the side surface of the curved region may be different from each other.

According to one or more embodiments of the present disclosure, there is provided a display device including: a glass substrate including a first surface, a second surface opposite to the first surface, and a side surface between the first surface and the second surface; an outermost structure on the first surface of the glass substrate and positioned adjacent to an edge of one side of the glass substrate, and a display region including a plurality of light emitting regions on the first surface of the glass substrate and positioned farther from the edge of one side of the glass substrate than the outermost structure. The minimum distance from the side surface of the glass substrate to the outermost structure is 130 μm or less.

According to one or more embodiments of the present disclosure, there is provided a display device including: a glass substrate including a first surface, a second surface opposite to the first surface, a side surface connected to the first surface, and a first inclined surface between the side surface and the second surface; and a display region including a plurality of light emitting regions on the first surface of the glass substrate. The side surface and the first inclined surface are formed by irradiating laser light to form a first laser irradiated region, and then separating the first laser irradiated region from the mother substrate by an etching process.

According to one or more embodiments of the present disclosure, there is provided a display device including: a glass substrate including a first surface, a second surface opposite to the first surface, a side surface disposed between the first surface and the second surface, a through hole penetrating the first surface and the second surface, and a side surface of the through hole between the first surface and the second surface at an edge of the through hole; a first outermost structure on the first surface of the glass substrate and positioned adjacent to one edge of the glass substrate; and a second outermost structure on the first surface of the glass substrate and positioned adjacent to an edge of the through hole. The distance from the first outermost structure to one edge of the glass substrate is smaller than the distance from the second outermost structure to the edge of the through hole.

According to one or more embodiments of the present disclosure, there is provided a display device including: a first substrate comprising glass and including a first surface, a second surface opposite the first surface, and a first side surface between the first surface and the second surface; a second substrate on the first substrate and comprising a flexible material; and a light emitting element layer including a plurality of light emitting regions on the second substrate. The first substrate further includes a side surface of the curved region between the first surface and the second surface at an edge of the curved region where the second substrate is curved. The cross-sectional shape of the first side surface and the cross-sectional shape of the side surface of the curved region are different from each other.

According to one or more embodiments of the present disclosure, there is provided a display device including: a first substrate including glass and including a first surface, a second surface opposite to the first surface, a first side surface between the first surface and the second surface, a through hole penetrating the first surface and the second surface, and a side surface of the through hole between the first surface and the second surface at an edge of the through hole; a second substrate on the first substrate and comprising a flexible material; and a light emitting element layer including a plurality of light emitting regions on the second substrate. The first substrate further includes a side surface of the curved surface between the first surface and the second surface at an edge of the curved region where the second substrate is curved. The cross-sectional shape of the side surface of the through hole and the cross-sectional shape of the side surface of the curved region are different from each other.

According to one or more embodiments of the present disclosure, there is provided a method for manufacturing a display device, the method including the steps of: forming a plurality of display units on a first surface of a mother substrate; forming a plurality of first laser irradiation regions along edges of the plurality of display units by irradiating first laser light on a second surface of the mother substrate opposite to the first surface; and cutting the mother substrate along the plurality of first laser irradiation regions while reducing the thickness of the mother substrate by spraying an etchant on the second surface of the mother substrate without a mask.

According to one or more embodiments of the present disclosure, there is provided an electronic device including: a display panel including a glass substrate having a through hole; and an optical device in the through hole. The display panel includes: a first outermost structure on the first surface of the glass substrate and positioned adjacent to one edge of the glass substrate; and a second outermost structure on the first surface of the glass substrate and positioned adjacent to an edge of the through hole. The distance from the first outermost structure to one edge of the glass substrate is smaller than the distance from the second outermost structure to the edge of the through hole.

According to one or more embodiments of the present disclosure, there is provided an electronic device including: a plastic substrate comprising a curved region; and a first glass layer laminated on the first surface of the plastic substrate and including a first contact surface contacting the first surface of the plastic substrate and a first opposing surface parallel to the first contact surface; a second glass layer laminated on the first surface of the plastic substrate, facing the first glass layer, and including a second contact surface in contact with the first surface of the plastic substrate and a second opposite surface parallel to the second contact surface and narrower than the second contact surface; a light emitting layer on a second surface of the plastic substrate, the second surface being parallel to and opposite to the first surface of the plastic substrate, and the light emitting layer being overlapped with the first glass layer in a thickness direction of the plastic substrate; and a passivation layer entirely covering the light emitting layer.

According to one or more embodiments of the present disclosure, there is provided an electronic device including: a first glass substrate: a second glass substrate facing the first glass substrate; and an organic layer on the first glass substrate and the second glass substrate, connecting the first glass substrate and the second glass substrate, and including a bending region. The first glass substrate includes a first contact surface contacting the organic layer and a first opposing surface parallel to the first contact surface. The second glass substrate includes a second contact surface contacting the organic layer and a second opposing surface parallel to the second contact surface. The electronic device further includes a light emitting layer positioned on the organic layer on the first glass substrate and a protective film entirely covering the light emitting layer.

According to one or more embodiments of the present disclosure, there is provided an electronic device including: a glass substrate having a through hole penetrating the glass substrate; a light emitting layer on a first surface of the glass substrate; an organic layer covering the light emitting layer; and a protective film covering the light emitting layer. The glass substrate includes a contact surface contacting the organic layer and an opposite surface. The angle between the side surface of the glass substrate and the contact surface at the edge of the glass substrate is the same as the angle between the side surface of the glass substrate and the contact surface at the edge of the through hole. The edges of the glass substrate and the through holes are treated by laser.

In accordance with the foregoing and other embodiments of the present disclosure, the width of the non-display area may be reduced or minimized.

According to the foregoing and other embodiments of the present disclosure, the mechanical strength of the display device may be improved.

In accordance with the foregoing and other embodiments of the present disclosure, it may be possible to cut a substrate while reducing the thickness of the substrate.

Drawings

The above and other embodiments and features of the present disclosure will become more apparent by describing embodiments thereof with reference to the accompanying drawings in which:

FIG. 1 is a perspective view illustrating a display device in accordance with one or more embodiments;

Fig. 2 is a plan view illustrating a display panel and a driving IC according to one or more embodiments;

FIG. 3A is a block diagram illustrating a display device in accordance with one or more embodiments;

fig. 3B is a circuit diagram illustrating a pixel of a display device in accordance with one or more embodiments;

fig. 3C is a circuit diagram illustrating a pixel of a display device in accordance with one or more embodiments;

FIG. 3D is a circuit diagram illustrating a pixel of a display device in accordance with one or more embodiments;

fig. 4 is a cross-sectional view showing an example of the display device taken along the line I-I' of fig. 1;

fig. 5 is a cross-sectional view showing an example of a display device in which the circuit board of fig. 4 is bent;

fig. 6 is a cross-sectional view illustrating an example of a display area of a display panel in accordance with one or more embodiments;

fig. 7 is a cross-sectional view illustrating an example of a display area of a display panel in accordance with one or more embodiments;

fig. 8 is a detailed cross-sectional view illustrating the light emitting diode element of fig. 7;

fig. 9 is a cross-sectional view illustrating an example of a display area of a display panel in accordance with one or more embodiments;

fig. 10 is a cross-sectional view illustrating an example of a display area of a display panel in accordance with one or more embodiments;

Fig. 11 is a layout diagram showing an example of the area a of fig. 2 in more detail;

fig. 12 is a layout diagram showing an example of the region B of fig. 2 in more detail;

fig. 13 is a layout diagram showing an example of the region D of fig. 2 in more detail;

fig. 14 is a cross-sectional view showing an example of a display panel taken along line II-II' of fig. 11;

fig. 15 is a cross-sectional view showing an example of the display panel taken along line III-III' of fig. 12;

fig. 16 is an image showing the width of the first sub-edge area;

FIG. 17 is an image showing debris from the second sub-edge area;

fig. 18 is an image showing roughness of a first side surface, a first inclined surface, and a second inclined surface of a display panel according to one or more embodiments;

fig. 19 is a cross-sectional view showing an example of the display panel taken along the line II-II' of fig. 11;

fig. 20 is a cross-sectional view showing an example of the display panel taken along line III-III' of fig. 12;

fig. 21 is a cross-sectional view showing an example of the display panel taken along the line IV-IV' of fig. 13;

FIG. 22 is an image showing a width of a processing trace of a display panel in accordance with one or more embodiments;

fig. 23 is an image illustrating roughness of a first side surface and a first inclined surface of a display panel according to one or more embodiments;

Fig. 24 is an enlarged cross-sectional view showing an example of the region E of fig. 19 in more detail;

fig. 25 is an enlarged cross-sectional view showing an example of the region F of fig. 20 in more detail;

fig. 26 is an enlarged cross-sectional view showing an example of the region G of fig. 21 in more detail;

FIG. 27 is a graph illustrating torsion test results of a display panel in accordance with one or more embodiments;

FIG. 28 is a graph illustrating 4PB test results of a display panel in accordance with one or more embodiments;

fig. 29 is a layout diagram illustrating cut areas of a display panel in accordance with one or more embodiments;

fig. 30 is a cross-sectional view showing an example of a display panel taken along line II-II' of fig. 11;

fig. 31 is a cross-sectional view showing an example of a display panel taken along line II-II' of fig. 11;

fig. 32 is an example diagram showing a laser irradiation region formed by laser to form the circular side surface of fig. 31;

fig. 33 is a cross-sectional view showing an example of the display panel taken along the line II-II' of fig. 11;

fig. 34 is a cross-sectional view showing an example of the region H of fig. 33 in more detail;

fig. 35 is a cross-sectional view showing an example of the region H of fig. 33 in more detail;

fig. 36 is a cross-sectional view showing an example of the region H of fig. 33 in more detail;

Fig. 37 is a cross-sectional view showing an example of the display panel taken along the line II-II' of fig. 11;

FIGS. 38A and 38B are layout diagrams illustrating display pads and electrostatic protection lines in accordance with one or more embodiments;

fig. 39 is a cross-sectional view showing an example of the display panel taken along the line V-V' of fig. 38B;

fig. 40A and 40B are layout diagrams illustrating display pads and electrostatic protection lines in accordance with one or more embodiments;

fig. 41A and 41B are layout diagrams illustrating display pads and electrostatic protection lines in accordance with one or more embodiments;

fig. 42A and 42B are layout diagrams illustrating display pads and electrostatic protection lines in accordance with one or more embodiments;

fig. 43 is a cross-sectional view showing an example of the display panel taken along line VI-VI' of fig. 42B;

FIG. 44 is a flow diagram illustrating a method of manufacturing a display device in accordance with one or more embodiments;

fig. 45-49 are perspective views illustrating a method of manufacturing a display device according to one or more embodiments;

fig. 50 to 55 are cross-sectional views illustrating a method of manufacturing a display device according to one or more embodiments;

FIG. 56 is a flow diagram illustrating a method of manufacturing a display device in accordance with one or more embodiments;

Fig. 57-61 are perspective views illustrating a method of manufacturing a display device according to one or more embodiments;

fig. 62-66 are cross-sectional views illustrating a method of manufacturing a display device according to one or more embodiments;

FIG. 67 is an example diagram illustrating the depth of a laser irradiated region formed by a laser in accordance with one or more embodiments;

FIG. 68 is an image showing a bottom surface of a display device in accordance with one or more embodiments;

FIG. 69 is a perspective view illustrating a display device in accordance with one or more embodiments;

fig. 70 is a plan view illustrating a display panel and a drive IC according to one or more embodiments;

fig. 71 is a cross-sectional view showing an example of the display device taken along line IX-IX' of fig. 69;

fig. 72 is a cross-sectional view showing an example of a display device in which the circuit board of fig. 71 is bent;

fig. 73 is a layout diagram illustrating an example of a via hole, an inorganic package region, a line region, and a display region of a display panel in accordance with one or more embodiments;

fig. 74 is a cross-sectional view showing an example of the display panel taken along the line X-X' of fig. 73;

fig. 75 is an enlarged cross-sectional view showing an example of region K of fig. 74 in more detail;

Fig. 76 is a cross-sectional view showing an example of the display panel taken along the line X-X' of fig. 73;

fig. 77 is an enlarged cross-sectional view showing an example of the region L of fig. 76 in more detail;

fig. 78 is a cross-sectional view showing an example of the display panel taken along the line X-X' of fig. 73;

fig. 79 is an enlarged cross-sectional view showing an example of the region M of fig. 78 in more detail;

fig. 80 is a cross-sectional view showing an example of the display panel taken along the line X-X' of fig. 73;

fig. 81 is an enlarged cross-sectional view showing an example of the region N of fig. 80 in more detail;

fig. 82 is an enlarged cross-sectional view showing an example of the region N of fig. 80 in more detail;

fig. 83 is an enlarged cross-sectional view showing an example of the region N of fig. 80 in more detail;

fig. 84 is a cross-sectional view showing an example of the display panel taken along the line X-X' of fig. 73;

fig. 85 is an exemplary view showing a minimum distance between an optical device and a black matrix when no through hole is formed in a display panel;

fig. 86 is an exemplary view showing a minimum distance between an optical device and a black matrix when a through hole is formed in a display panel;

fig. 87 is a cross-sectional view illustrating an example of an electronic device including a display panel and an optical device disposed in a through hole in accordance with one or more embodiments;

Fig. 88 and 89 are cross-sectional views illustrating examples of an electronic device including a display panel and an optical device disposed in a through hole in accordance with one or more embodiments;

FIG. 90 is a flow diagram illustrating a method of manufacturing a display device in accordance with one or more embodiments;

fig. 91-96 are perspective views illustrating a method of manufacturing a display device according to one or more embodiments;

fig. 97-101 are cross-sectional views illustrating a method of manufacturing a display device according to one or more embodiments;

FIG. 102 is a flow diagram illustrating a method of manufacturing a display device in accordance with one or more embodiments;

FIG. 103 is a cross-sectional view illustrating a method of manufacturing a display device in accordance with one or more embodiments;

FIG. 104 is a flow diagram illustrating a method of manufacturing a display device in accordance with one or more embodiments;

FIG. 105 is a cross-sectional view illustrating a method of manufacturing a display device in accordance with one or more embodiments;

FIG. 106 is a perspective view illustrating a display device in accordance with one or more embodiments;

fig. 107 is a plan view illustrating a display panel and a drive IC in accordance with one or more embodiments;

fig. 108 is a cross-sectional view showing an example of the display device taken along the line XA-XA 'and the line XB-XB' of fig. 106;

Fig. 109 is a cross-sectional view showing an example of a display device in which the bending region of fig. 108 is bent;

fig. 110 is a cross-sectional view showing an example of the display device taken along the line XA-XA 'and the line XB-XB' of fig. 106;

fig. 111 is a cross-sectional view showing an example of a display device in which a bending region of fig. 110 is bent;

fig. 112 is a cross-sectional view showing an example of the display device taken along the line XA-XA 'and the line XB-XB' of fig. 106;

fig. 113 is a cross-sectional view showing an example of a display device in which the bending region of fig. 112 is bent;

FIG. 114 is a cross-sectional view showing an example of the display device taken along lines XA-XA 'and XB-XB' of FIG. 106;

fig. 115 is a cross-sectional view showing an example of a display device in which the bending region of fig. 114 is bent;

FIG. 116 is a cross-sectional view showing an example of the display device taken along lines XA-XA 'and XB-XB' of FIG. 106;

fig. 117 is a cross-sectional view showing an example of a display device in which the bending region of fig. 116 is bent;

FIG. 118 is a cross-sectional view showing an example of the display device taken along lines XA-XA 'and XB-XB' of FIG. 106;

fig. 119 is a cross-sectional view showing an example of a display device in which the bending region in fig. 118 is bent;

FIG. 120 is a cross-sectional view showing an example of a display device taken along lines XA-XA 'and XB-XB' of FIG. 106;

Fig. 121 is a cross-sectional view showing an example of a display device in which a bending region of fig. 120 is bent;

fig. 122A is a cross-sectional view showing an example of the display device taken along the line XA-XA 'and the line XB-XB' of fig. 106;

fig. 122B is a cross-sectional view showing an example of a display device in which the bending region of fig. 122A is bent;

fig. 123A is a cross-sectional view showing an example of the display device taken along the line XA-XA 'and the line XB-XB' of fig. 106;

fig. 123B is a cross-sectional view showing an example of a display device in which the bending region of fig. 123A is bent;

fig. 123C is a cross-sectional view showing an example of the display device taken along the line XA-XA 'and the line XB-XB' of fig. 106;

fig. 123D is a cross-sectional view showing an example of a display device in which the bending region of fig. 123C is bent;

fig. 123E is a cross-sectional view showing an example of the display device taken along the line XA-XA 'and the line XB-XB' of fig. 106;

fig. 123F is a cross-sectional view showing an example of a display device in which the bending region of fig. 123E is bent;

fig. 123G is a cross-sectional view showing an example of the display device taken along the line XA-XA 'and the line XB-XB' of fig. 106;

fig. 123H is a cross-sectional view showing an example of a display device in which the bending region of fig. 123G is bent;

Fig. 123I is a cross-sectional view showing an example of the display device taken along the line XA-XA 'and the line XB-XB' of fig. 106;

fig. 123J is a cross-sectional view showing an example of a display device in which the bending region of fig. 123I is bent;

FIG. 124 is a flow diagram illustrating a method of manufacturing a display device in accordance with one or more embodiments;

fig. 125-131 are perspective views illustrating a method of manufacturing a display device according to one or more embodiments;

fig. 132-136 are cross-sectional views illustrating a method of manufacturing a display device according to one or more embodiments;

FIG. 137 is a flow diagram illustrating a method of manufacturing a display device in accordance with one or more embodiments;

fig. 138-143 are perspective views illustrating a method of manufacturing a display device according to one or more embodiments;

FIG. 144 is a flow diagram illustrating a method of manufacturing a display device in accordance with one or more embodiments;

fig. 145-150 are perspective views illustrating a method of manufacturing a display device according to one or more embodiments;

FIG. 151 is an example diagram illustrating an electronic device including a display device in accordance with one or more embodiments;

FIG. 152 is an example diagram illustrating an electronic device including a display device in accordance with one or more embodiments;

FIG. 153 is an example diagram illustrating an electronic device including a display device in accordance with one or more embodiments;

FIG. 154 is an example diagram illustrating an electronic device including a display device in accordance with one or more embodiments;

FIG. 155 is an example diagram illustrating an electronic device including a display device in accordance with one or more embodiments;

FIG. 156 is an example diagram illustrating an electronic device including a display device in accordance with one or more embodiments;

FIG. 157 is an example diagram illustrating a vehicle dashboard and center dashboard to which an electronic device including a display device has been applied, in accordance with one or more embodiments; and

FIG. 158 is an exemplary diagram illustrating an electronic device including a display device in accordance with one or more embodiments.

Detailed Description

Aspects and features of embodiments of the present disclosure, as well as methods of accomplishing the same, may be understood more readily by reference to the detailed description of the embodiments and the accompanying drawings. Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. The described embodiments may, however, be embodied in various different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of the disclosure to those skilled in the art. Thus, processes, elements and techniques not necessary for a person of ordinary skill in the art to fully understand aspects and features of the present disclosure may not be described.

Like reference numerals, characters, or combinations thereof denote like elements throughout the drawings and written description unless otherwise indicated, and thus, the description thereof will not be repeated. Moreover, portions that are not relevant to the description of one or more embodiments may not be shown in order to clarify the description.

In the drawings, the relative sizes of elements, layers and regions may be exaggerated for clarity. In addition, the use of cross-hatching and/or shading in the drawings is typically provided to clarify the boundaries between adjacent elements. As such, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, dimension, proportion, commonality between illustrated elements, and/or any other characteristic, attribute, property, or the like, unless otherwise indicated.

Various embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments and/or intermediate structures. As such, variations in the shape of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Furthermore, the specific structural or functional descriptions disclosed herein are merely illustrative of the embodiments that are consistent with the principles of the present disclosure. Accordingly, the embodiments disclosed herein should not be construed as limited to the particular illustrated shapes of regions, but are to include deviations (or variations) in shapes that result, for example, from manufacturing.

For example, an implanted region shown as a rectangle may have rounded (rounded) or curved features and/or gradients of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which implantation occurs. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to be limiting. In addition, as will be recognized by those skilled in the art, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

In the description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments. It may be evident, however, that the various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various embodiments.

Spatially relative terms, such as "under … …," "under … …," "lower," "under … …," "over … …," and "upper" may be used herein for ease of explanation, to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the example terms "below … …" and "below … …" may encompass both an orientation of above and below. The device may additionally be positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Similarly, when a first portion is described as being disposed "on" a second portion, this means that the first portion is disposed at an upper or lower side of the second portion (and not limited to the upper side of the second portion) based on the direction of gravity.

Further, in the present disclosure, the phrase "on a plane" or "in a plan view" means that the target portion is viewed from the top, and the phrase "on a section" means that the section formed by vertically cutting the target portion from the side is viewed.

It will be understood that when an element, layer, region or component is referred to as being "formed on," "connected to" or "coupled to" another element, layer, region or component, it can be directly on, connected to or coupled to the other element, layer, region or component, or be indirectly on, connected to or coupled to the other element, layer, region or component, such that one or more intervening elements, layers, regions or components may be present. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it can be directly electrically connected or directly electrically coupled to the other layer, region, and/or component, or intervening layers, regions, or components may be present. However, "directly connected/directly coupled" means that one component is directly connected or directly coupled to another component without intervening components. Meanwhile, other expressions describing the relationship between components, such as "between … …", "directly between … …" or "adjacent to … …" and "directly adjacent to … …" may be similarly interpreted. In addition, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

For purposes of this disclosure, expressions such as "at least one of … …", "… …" and "selected from … …" modify an entire column of elements before or after a column of elements, rather than modifying individual elements of the column. For example, "at least one (seed/person)" of X, Y and Z, "at least one (seed/person) selected from X, Y and Z," and "at least one (seed/person) selected from the group consisting of X, Y and Z," can be interpreted as any combination of two or more of X only, Y only, Z, X, Y only, and Z (such as exemplified by XYZ, XYY, YZ and ZZ or any variant thereof). Similarly, expressions such as "at least one (seed) of a and B" may include A, B or a and B. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. For example, expressions such as "a and/or B" may include A, B or a and B. Furthermore, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Accordingly, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the spirit and scope of the present disclosure.

In an example, the X-axis, Y-axis, and/or Z-axis are not limited to three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. This applies to the first direction, the second direction and/or the third direction.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "has," "including" and/or variations thereof, when used in this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

As used herein, the terms "substantially," "about," "approximately," and similar terms are used as approximation terms and not as degree terms, and are intended to explain the inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art. In view of the measurements in question and the errors associated with a particular amount of measurement (i.e., limitations of the measurement system), as used herein, "about" or "approximately" includes the stated values and refers to within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure.

While one or more embodiments may be implemented differently, the particular process sequence may be performed differently than as described. For example, two consecutively described processes may be performed substantially simultaneously or in reverse order from that described.

Furthermore, any numerical range disclosed and/or recited herein is intended to include all sub-ranges subsumed with the same numerical precision within the recited range. For example, a range of "1.0 to 10.0" is intended to include all subranges between (and including) the recited minimum value of 1.0 and the recited maximum value of 10.0, e.g., having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as for example 2.4 to 7.6. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein, and any minimum numerical limitation recited in this disclosure is intended to include all higher numerical limitations subsumed therein. Accordingly, applicants reserve the right to modify the present disclosure (including the claims) to expressly state any sub-ranges subsumed within the range explicitly recited herein. All such ranges are intended to be inherently described in this disclosure so that modifications that explicitly recite any such sub-ranges will be satisfactory.

An electronic or electrical device and/or any other related device or component according to embodiments of the disclosure described herein may be implemented using any suitable hardware, firmware (e.g., application specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, the various components of these devices may be formed on one Integrated Circuit (IC) chip or on separate IC chips. In addition, the various components of these devices may be implemented on a flexible printed circuit film, tape Carrier Package (TCP), printed Circuit Board (PCB), or formed on one substrate.

Further, the various components of these devices may be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions, and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in a memory that may be implemented in a computing device using standard memory means, such as Random Access Memory (RAM) for example. The computer program instructions may also be stored in other non-transitory computer readable media such as a CD-ROM or flash memory drive, for example. Moreover, those skilled in the art will recognize that the functionality of various computing devices may be combined or integrated into a single computing device, or that the functionality of a particular computing device may be distributed across one or more other computing devices, without departing from the spirit and scope of embodiments of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 is a perspective view illustrating a display device in accordance with one or more embodiments. Fig. 2 is a plan view illustrating a display panel and a driving IC according to one or more embodiments.

Referring to fig. 1 and 2, a display device 10 is a device for displaying a moving image and/or a still image. The display device 10 may be used as a display screen for various products such as televisions, laptop computers, monitors, billboards, or internet of things (IOT) devices, as well as portable electronic devices such as mobile phones, smart phones, tablet personal computers (tablet PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable Multimedia Players (PMPs), navigation systems, or Ultra Mobile PCs (UMPCs).

The display device 10 according to one or more embodiments may be a light emitting display device such as an organic light emitting display device using an organic light emitting diode, a quantum dot light emitting display including a quantum dot light emitting layer, an inorganic light emitting display device including an inorganic semiconductor, or a micro light emitting display device using a micro or nano light emitting diode (micro LED or nano LED). Hereinafter, the display device 10 will be mainly described as an organic light emitting display device, but the present disclosure is not limited thereto.

The display device 10 according to one or more embodiments includes a display panel 100, a driving Integrated Circuit (IC) 200, and a circuit board 300.

The display panel 100 may be formed in a rectangular plane having a long side in a first direction (X-axis direction) and a short side in a second direction (Y-axis direction) intersecting the first direction (X-axis direction). The corner where the long side in the first direction (X-axis direction) and the short side in the second direction (Y-axis direction) meet may be formed in a right angle or in a circular shape (rounded) to have curvature. The flat shape of the display panel 100 is not limited to a quadrangle, and the display panel 100 may be formed in other polygonal shapes, circular shapes, or elliptical shapes.

The display panel 100 may be formed flat, but is not limited thereto. For example, the display panel 100 may include a curved portion (or bent portion) having a constant curvature or a varying curvature at left and right ends thereof. In addition, the display panel 100 may be flexibly formed to be bent, folded, or curled.

The display panel 100 may include a display area DA for displaying an image and a non-display area NDA disposed around the display area DA.

The display area DA may occupy a large area of the display panel 100. The display area DA may be disposed at the center of the display panel 100. Pixels each including a plurality of light emitting regions may be disposed in the display region DA to display an image.

The non-display area NDA may be disposed adjacent to the display area DA. The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be disposed to surround the display area DA. The non-display area NDA may be an edge area of the display panel 100.

A display pad (or "pad") PD may be disposed in the non-display area NDA to be connected to the circuit board 300. The display pad PD may be disposed on one edge of the display panel 100. For example, the display pad PD may be disposed on the lower edge of the display panel 100.

The display pad PD may be an outermost structure disposed at the outermost side of the lower side (or bottom side) of the display panel 100. The outermost structure may be a structure disposed closest to an edge of the display panel 100. The outermost structure may be a structure for driving the display panel 100 or a structure for improving the function of the display panel 100.

The display panel 100 may include a first DAM1, a second DAM2, and a crack DAM CRD.

The first DAM1 and the second DAM2 may be structures for preventing the overflow of the encapsulation organic layer (TFE 2 of fig. 6) of the encapsulation layer (ENC of fig. 4). The first DAM1 may be disposed around the display area DA, and the second DAM2 may be disposed around the first DAM1.

The crack dam CRD may be a structure for preventing propagation of cracks in the inorganic layer of the encapsulation layer ENC in the process of cutting the substrate SUB during the manufacturing process of the display device 10. The crack dam CRD may be disposed along the left, upper and right edges of the display panel 100. The crack dam CRD may not be provided at the lower edge of the display panel 100. The crack dam CRD may be an outermost structure disposed at the outermost sides of the left, upper and right sides of the display panel 100.

The driving Integrated Circuit (IC) 200 may generate a data voltage, a power supply voltage, and/or a scan timing signal, etc. The driving ICs 200 may output data voltages, power supply voltages, and/or scan timing signals, etc.

The driving Integrated Circuit (IC) 200 may be disposed between the display pad PD and the display area DA in the non-display area NDA. Each of the driving ICs 200 may be attached to the non-display area NDA of the display panel 100 using a Chip On Glass (COG) method. Alternatively, each of the driving ICs 200 may be attached to the circuit board 300 using a Chip On Plastic (COP) method.

The circuit board 300 may be disposed on the display pad PD disposed at one edge of the display panel 100. The circuit board 300 may be attached to the display pad PD using a conductive adhesive member CAD (see fig. 25) such as an anisotropic conductive film and an anisotropic conductive adhesive. Accordingly, the circuit board 300 may be electrically connected to the signal lines of the display panel 100. The circuit board 300 may be a flexible printed circuit board or a flexible film such as a chip on film.

Fig. 3A is a block diagram illustrating a display device in accordance with one or more embodiments.

Referring to fig. 3A, the display apparatus 10 according to one or more embodiments includes a display panel 100, a scan driving circuit unit SDC, a driving IC 200, and a power supply unit PSU.

The display panel 100 includes data lines DL, scan lines SL, and pixels PX. The scan lines SL may extend in a first direction (X-axis direction) and may be spaced apart from each other along a second direction (Y-axis direction). The data lines DL may extend in a second direction (Y-axis direction) and may be spaced apart from each other along the first direction (X-axis direction).

Each of the pixels PX may be connected to at least one of the data lines DL and at least one of the scan lines SL. As shown in fig. 3B to 3D, each of the pixels PX may include a light emitting element LE and a pixel circuit unit PXC including a plurality of transistors for supplying a driving current to the light emitting element LE. A detailed description of the pixel PX will be described later with reference to fig. 3B to 3D.

The scan driving circuit unit SDC and the driving IC 200 may be referred to as a display panel driving unit. The driving IC 200 may include a timing control circuit unit (timing controller) TIC and a data driving circuit unit DIC.

The scan driving circuit unit SDC is connected to the scan lines SL to apply a scan signal. The scan driving circuit unit SDC may generate a scan signal according to the scan timing control signal SCS input from the timing control circuit unit TIC, and output the scan signal to the scan line SL.

The scan driving circuit unit SDC may include a plurality of transistors. In this case, the scan driving circuit unit SDC may be disposed in the non-display area NDA disposed at the left and right sides of the display panel 100.

The data driving circuit unit DIC is connected to the data line DL to supply the data voltage. The DATA driving circuit unit DIC receives the digital video DATA and the DATA timing control signal DCS from the timing control circuit unit TIC. The DATA driving circuit unit DIC converts the digital video DATA into a DATA voltage according to the DATA timing control signal DCS and outputs the DATA voltage to the DATA line DL.

The timing control circuit unit TIC receives the digital video DATA and the timing signal TS. The timing signal TS may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and/or a clock signal (such as a dot clock).

The timing control circuit unit TIC generates control signals for controlling operation timings of the data driving circuit unit DIC and the scan driving circuit unit SDC. The control signals may include a data timing control signal DCS for controlling the operation timing of the data driving circuit unit DIC and a scan timing control signal SCS for controlling the operation timing of the scan driving circuit unit SDC.

The timing control circuit unit TIC outputs the digital video DATA and the DATA timing control signal DCS to the DATA driving circuit unit DIC, and outputs the scan timing control signal SCS to the scan driving circuit unit SDC.

The power supply unit PSU may generate a first power supply voltage VSS corresponding to a low potential voltage and a second power supply voltage VDD corresponding to a high potential voltage according to main power applied from the outside. Further, the power supply unit PSU may supply various driving voltages to the data driving circuit unit DIC, the scan driving circuit unit SDC, and the timing control circuit unit TIC.

Fig. 3B is a circuit diagram illustrating a pixel of a display device in accordance with one or more embodiments.

Referring to fig. 3B, a pixel PX according to one or more embodiments may include a pixel circuit unit PXC and a light emitting element LE.

The light emitting element LE emits light according to the driving current Ids. The amount of light emitted from the light emitting element LE may be proportional to the driving current Ids.

The light emitting element LE may be an organic light emitting element including an anode electrode, a cathode electrode, and an organic light emitting layer disposed between the anode electrode and the cathode electrode. Alternatively, the light emitting element LE may be an inorganic light emitting element including an anode electrode, a cathode electrode, and an inorganic semiconductor disposed between the anode electrode and the cathode electrode.

The anode electrode of the light emitting element LE may be connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, and the cathode electrode may be connected to the first power line VSL. The parasitic capacitance Cel may be formed between the anode electrode and the cathode electrode of the light emitting element LE.

The pixel circuit unit PXC includes a driving transistor DT, a switching element, and a capacitor C1. The switching element includes first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6.

The driving transistor DT includes a gate electrode, a first electrode, and a second electrode. The driving transistor DT controls a drain-source current (Ids, hereinafter, referred to as "driving current") flowing between the first electrode and the second electrode according to a data voltage applied to the gate electrode.

The capacitor C1 is formed between the gate electrode of the driving transistor DT and the second power line VDL. One electrode of the capacitor C1 may be connected to the gate electrode of the driving transistor DT, and the other electrode may be connected to the second power line VDL.

When the first electrode of each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6 and the driving transistor DT is a source electrode, the second electrode may be a drain electrode. Alternatively, when the first electrode of each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6 and the driving transistor DT is a drain electrode, the second electrode may be a source electrode.

The active layer of each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5, ST6 and the driving transistor DT may be formed of any one of polysilicon, amorphous silicon and an oxide semiconductor. When the semiconductor layers of the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6 and the driving transistor DT are all formed of polysilicon, a process for forming them may be a Low Temperature Polysilicon (LTPS) process.

In addition, in fig. 3B, the first to sixth transistors ST1, ST2, ST3, ST4, ST5, ST6 and the driving transistor DT are mainly described as P-type MOSFETs (metal oxide semiconductor field effect transistors). However, the present disclosure is not limited thereto, and one or more of the first to sixth transistors ST1, ST2, ST3, ST4, ST5, ST6 and the driving transistor DT may be formed of an N-type MOSFET.

Further, the first power supply voltage VSS of the first power supply line VSL, the second power supply voltage VDD of the second power supply line VDL, and the third power supply voltage (or initialization voltage) of the third power supply line VIL may be set in consideration of characteristics of the driving transistor DT and characteristics of the light emitting element LE. In fig. 3B, a first transistor ST1 (including transistors ST1-1 and ST 1-2) is connected between the capacitor C1 and the driving transistor DT, and has a gate (gates of transistors ST1-1 and ST 1-2) connected to the write scan line GWL. The second transistor ST2 is connected between the data line DL and the driving transistor DT, and has a gate connected to the write scan line GWL. The third transistor ST3 (including the transistors ST3-1 and ST 3-2) is connected between the capacitor C1 or the gate electrode of the driving transistor DT and the third power line VIL, and has a gate (the gates of the transistors ST3-1 and ST 3-2) connected to the initialization scan line GIL. The fourth transistor ST4 is connected between the third power supply line VIL and the light emitting element LE, and has a gate connected to the control scan line GCL. The fifth transistor ST5 is connected between the second power supply line VDL and the driving transistor DT, and the sixth transistor ST6 is connected between the driving transistor DT and the light emitting element LE. The gates of the fifth transistor ST5 and the sixth transistor ST6 are connected to the light emitting line EL.

Fig. 3C is a circuit diagram illustrating a pixel of a display device in accordance with one or more embodiments.

The embodiment of fig. 3C differs from the embodiment of fig. 3B in that: the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed of P-type MOSFETs, and the first transistor ST1 and the third transistor ST3 are formed of N-type MOSFETs.

Referring to fig. 3C, the respective active layers of the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 formed of P-type MOSFETs may be formed of polysilicon, and the respective active layers of the first transistor ST1 and the third transistor ST3 formed of N-type MOSFETs may be formed of oxide semiconductors.

The embodiment of fig. 3C differs from the embodiment of fig. 3B in that: the gate electrode of the second transistor ST2 and the gate electrode of the fourth transistor ST4 are connected to the write scan line GWL, and the gate electrode of the first transistor ST1 is connected to the control scan line GCL. Further, in fig. 3C, since the first transistor ST1 and the third transistor ST3 are formed of N-type MOSFETs, a scan signal of a gate high voltage may be applied to the control scan line GCL and the initialization scan line GIL. In contrast, since the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed of P-type MOSFETs, a scan signal of a gate low voltage may be applied to the write scan line GWL and the light emitting line EL.

Fig. 3D is a circuit diagram illustrating a pixel of a display device in accordance with one or more embodiments.

Referring to fig. 3D, the light emitting element LE emits light according to the driving current Ids. The amount of light emitted from the light emitting element LE may be proportional to the driving current Ids. The anode electrode of the light emitting element LE is connected to the source electrode of the driving transistor DT, and the cathode electrode may be connected to a first power line VSL supplied with a first power voltage VSS lower than the second power voltage VDD.

The driving transistor DT adjusts a current flowing from the second power line VDL supplied with the second power voltage VDD to the light emitting element LE according to a voltage difference between the gate electrode and the source electrode. A gate electrode of the driving transistor DT may be connected to a first electrode of the first transistor ST1, a source electrode may be connected to an anode electrode of the light emitting element LE, and a drain electrode may be connected to the second power line VDL.

The first transistor ST1 is turned on by a scan signal of the scan line SL to connect the data line DL to the gate electrode of the driving transistor DT. A gate electrode of the first transistor ST1 may be connected to the scan line SL, a first electrode may be connected to a gate electrode of the driving transistor DT, and a second electrode may be connected to the data line DL.

The second transistor ST2 is turned on by a sensing signal of the sensing signal line SSL to connect the initialization voltage line VIL to the source electrode of the driving transistor DT. The gate electrode of the second transistor ST2 may be connected to the sensing signal line SSL, the first electrode may be connected to the initialization voltage line VIL, and the second electrode may be connected to the source electrode of the driving transistor DT.

The first electrode of each of the first and second transistors ST1 and ST2 may be a source electrode and the second electrode may be a drain electrode, but it should be noted that the present disclosure is not limited thereto. That is, the first electrode of each of the first and second transistors ST1 and ST2 may be a drain electrode, and the second electrode may be a source electrode.

The capacitor Cst is formed between the gate electrode and the source electrode of the driving transistor DT. The capacitor Cst stores a voltage difference between the gate voltage and the source voltage of the driving transistor DT.

In fig. 3D, the driving transistor DT and the first and second transistors ST1 and ST2 have been mainly described as being formed of an N-type MOSFET (metal oxide semiconductor field effect transistor), but it should be noted that the present disclosure is not limited thereto. The driving transistor DT and the first and second transistors ST1 and ST2 may be formed of P-type MOSFETs.

It should be noted that the pixels PX according to one or more embodiments of the present disclosure are not limited to the pixels PX shown in fig. 3B to 3D. In addition to the embodiments shown in fig. 3B to 3D, the pixels PX according to one or more embodiments of the present disclosure may be formed in other known circuit structures that may be employed by those skilled in the art.

Fig. 4 is a cross-sectional view showing an example of the display device taken along the line I-I' of fig. 1. Fig. 5 is a cross-sectional view showing an example of a display device in which the circuit board in fig. 4 is bent.

Referring to fig. 4 and 5, a display device 10 according to one or more embodiments may include a display panel 100, a polarizing film PF, a cover window CW, and a panel bottom cover PB. The display panel 100 may include a substrate SUB, a display layer dis, an encapsulation layer ENC, and a sensor electrode layer SENL.

The substrate SUB may comprise (or be made of) a rigid material. For example, the substrate SUB may be made of glass, but is not limited thereto. For example, the substrate SUB may be made of ultra-thin glass (UTG) having a thickness of about 200 μm or less.

The display layer dis may be disposed on the first surface of the substrate SUB. The display layer dis may be a layer displaying an image. The display layer dis may include a thin film transistor layer TFTL (see fig. 6) in which a thin film transistor is formed and a light emitting element layer EML (see fig. 6) in which a light emitting element LEL (see fig. 6) for emitting light is disposed in a light emitting area EA (see fig. 6).

In the display area DA of the display layer dis, scan lines SL, data lines DL, power supply lines, and the like for light emitting areas that emit light may be provided. In the non-display area NDA of the display layer dis, a scan driving circuit unit SDC for outputting a scan signal to the scan lines SL and a fanout line connecting the data lines DL and the driving IC 200 may be provided.

The encapsulation layer ENC may be a layer for encapsulating the light emitting element layer EML of the display layer dis to prevent oxygen or moisture from penetrating into the light emitting element layer EML of the display layer dis. The encapsulation layer ENC may be disposed on the display layer dis. The encapsulation layer ENC may be disposed on the top and side surfaces of the display layer dis. The encapsulation layer ENC may be disposed to cover the display layer dis.

The sensor electrode layer SENL may be disposed on the display layer dis. The sensor electrode layer SENL may include a sensor electrode. The sensor electrode layer SENL may sense a touch of a user using the sensor electrode.

The polarizing film PF may be disposed on the display panel 100 to reduce reflection of external light. The polarizing film PF may include a first base member, a linear polarizing plate, a phase retardation film such as a λ/4 plate (quarter wave plate), and a second base member. The first base member, the phase retardation film, the linear polarizing plate, and the second base member of the polarizing film PF may be sequentially stacked on the display panel 100.

The cover window CW may be provided on the polarizing film PF. The cover window CW may be attached to the polarizing film PF by a transparent adhesive member such as an Optically Clear Adhesive (OCA) film.

The panel bottom cover PB may be disposed on the second surface of the substrate SUB of the display panel 100. The second surface of the substrate SUB may be opposite to the first surface. The panel bottom cover PB may be attached to the second surface of the substrate SUB of the display panel 100 by an adhesive member. The adhesive member may be a Pressure Sensitive Adhesive (PSA).

The panel bottom cover PB may include at least one selected from among a light blocking member for absorbing light incident from the outside, a buffer member for absorbing impact from the outside, and a heat dissipating member for effectively dissipating heat of the display panel 100.

The light blocking member may be disposed under the display panel 100. The light blocking member blocks light transmission to prevent components (e.g., the circuit board 300) disposed below the light blocking member from being viewed from above the display panel 100. The light blocking member may include a light absorbing material such as a black pigment or a black dye.

The buffer member may be disposed under the light blocking member. The buffer member may absorb external impact to prevent or protect the display panel 100 from being damaged. The cushioning member may be formed of a single layer or multiple layers. For example, the cushioning member may be formed of a polymer resin such as polyurethane, polycarbonate, polypropylene, or polyethylene, or may include a material having elasticity such as rubber, urethane-based material, or sponge formed by foam molding an acrylic material.

The heat dissipation member may be disposed under the buffer member. The heat dissipation member may include a first heat dissipation layer including graphite or carbon nanotubes, and a second heat dissipation layer formed of a thin metal film such as copper, nickel, ferrite, or silver, which can shield electromagnetic waves and has excellent thermal conductivity.

As shown in fig. 5, the circuit board 300 may be bent downward from the display panel 100. The circuit board 300 may be attached to the bottom surface of the panel bottom cover PB by an adhesive member 310. The adhesive member 310 may be a Pressure Sensitive Adhesive (PSA).

Fig. 6 is a cross-sectional view illustrating an example of a display area of a display panel in accordance with one or more embodiments.

Referring to fig. 6, the display panel 100 according to one or more embodiments may be an organic light emitting display panel including a light emitting element LEL including an organic light emitting layer 172.

The display layer dis may include a thin film transistor layer TFTL including a plurality of thin film transistors TFTs and a light emitting element layer EML including a plurality of light emitting elements LEL.

The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may be formed of an inorganic material such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. Alternatively, the first buffer layer BF1 may be formed as a multilayer in which one or more of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked.

An active layer of the thin film transistor TFT including a channel region TCH, a source region TS, and a drain region TD may be disposed on the first buffer layer BF 1. The active layer may be formed of polysilicon, monocrystalline silicon, low temperature polysilicon, amorphous silicon, or an oxide semiconductor material. When the active layer includes polysilicon or an oxide semiconductor material, the source and drain regions TS and TD in the active layer may be conductive regions doped with ions or impurities to have conductivity.

The gate insulating layer 130 may be disposed on the active layer of the thin film transistor TFT. The gate insulating layer 130 may be formed of an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer).

A first gate metal layer including the gate electrode TG of the thin film transistor TFT, the first capacitor electrode CAE1 of the capacitor Cst, and the scan line SL may be disposed on the gate insulating layer 130. The gate electrode TG of the thin film transistor TFT may overlap the channel region TCH in the third direction (Z-axis direction). The first gate metal layer may be formed of a single layer or multiple layers made of any one or more selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

The first interlayer insulating layer 141 may be disposed on the first gate metal layer. The first interlayer insulating layer 141 may be formed of an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer). The first interlayer insulating layer 141 may include a plurality of inorganic layers.

A second gate metal layer including the second capacitor electrode CAE2 of the capacitor Cst may be disposed on the first interlayer insulating layer 141. The second capacitor electrode CAE2 may overlap the first capacitor electrode CAE1 in a third direction (Z-axis direction). Accordingly, the capacitor Cst may be formed of the first capacitor electrode CAE1, the second capacitor electrode CAE2, and an inorganic insulating dielectric layer disposed therebetween and serving as a dielectric layer. The second gate metal layer may be formed of a single layer or multiple layers made of any one or more selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

The second interlayer insulating layer 142 may be disposed on the second gate metal layer. The second interlayer insulating layer 142 may be formed of an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer). The second interlayer insulating layer 142 may include a plurality of inorganic layers.

A first data metal layer including the first connection electrode CE1 and the data line DL may be disposed on the second interlayer insulating layer 142. The first connection electrode CE1 may be connected to the drain region TD through a first contact hole CT1 penetrating the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142. The first data metal layer may be formed of a single layer or multiple layers made of any one or more selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

A first organic layer 160 for planarizing a step difference due to the thin film transistor TFT may be disposed on the first connection electrode CE1. The first organic layer 160 may be formed of an organic layer such as acryl resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

A second data metal layer including a second connection electrode CE2 may be disposed on the first organic layer 160. The second data metal layer may be connected to the first connection electrode CE1 through a second contact hole CT2 penetrating the first organic layer 160. The second data metal layer may be formed of a single layer or multiple layers made of any one or more selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

The second organic layer 180 may be disposed on the second connection electrode CE2. The second organic layer 180 may be formed of an organic layer such as acryl resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

In one or more embodiments, the second data metal layer including the second connection electrode CE2 and the second organic layer 180 may be omitted.

The light emitting element layer EML is disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include light emitting elements LEL and banks 190.

Each of the light emitting elements LEL may include a pixel electrode 171, a light emitting layer 172, and a common electrode 173. Each of the light emitting regions EA represents a light emitting region in which holes from the pixel electrode 171 and electrons from the common electrode 173 are recombined with each other in the light emitting layer 172 to emit light by sequentially stacking the pixel electrode 171, the light emitting layer 172, and the common electrode 173. In one or more embodiments, the pixel electrode 171 may be an anode electrode, and the common electrode 173 may be a cathode electrode.

A pixel electrode layer including the pixel electrode 171 may be formed on the second organic layer 180. The pixel electrode 171 may be connected to the second connection electrode CE2 through a third contact hole CT3 penetrating the second organic layer 180. The pixel electrode layer may be formed of a single layer or a plurality of layers made of any one or more selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

In the top (or upper) emission structure based on the emission layer 172 emitting light in the direction of the common electrode 173, the pixel electrode 171 may be formed of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), an APC alloy, or a stacked structure of APC alloy and ITO (ITO/APC/ITO) to increase reflectivity. The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

The banks 190 serve to define the light emitting areas EA of the pixels. For this, the bank 190 may be formed on the second organic layer 180 to expose a partial region of the pixel electrode 171. The bank 190 may cover an edge of the pixel electrode 171. The bank 190 may be disposed in the third contact hole CT 3. That is, the third contact hole CT3 may be filled with the bank 190. The bank 190 may be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

Spacers 191 may be disposed on the banks 190. The spacers 191 may be used to support a mask during a process of manufacturing the light emitting layer 172. The spacer 191 may be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

The light emitting layer 172 is formed on the pixel electrode 171. The light emitting layer 172 may include an organic material to emit light of a desired color (e.g., a predetermined color). For example, the light emitting layer 172 may include a hole transport layer, an organic material layer, and an electron transport layer. The organic material layer may include a host and a dopant. The organic material layer may include a material for emitting desired light (e.g., predetermined light), and may be formed using a phosphorescent material or a fluorescent material.

The common electrode 173 is formed on the light emitting layer 172. The common electrode 173 may be formed to cover the light emitting layer 172. The common electrode 173 may be a common layer commonly formed in the light emitting areas EA1, EA2, EA3, and EA4 (see fig. 11). A capping layer may be formed on the common electrode 173.

In the upper emission structure, the common electrode 173 may be formed of a transparent conductive material (TCO) such as ITO or IZO or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag) that may transmit light. When the common electrode 173 is formed of a transflective metal material, light output efficiency may be improved by the microcavity.

The encapsulation layer ENC may be formed on the light emitting element layer EML. The encapsulation layer ENC may include at least one inorganic layer (e.g., first encapsulation inorganic layer TFE 1) to prevent oxygen or moisture from penetrating into the light emitting element layer EML. Further, the encapsulation layer ENC may include at least one organic layer TFE2 to protect the light emitting element layer EML from foreign matter such as dust. For example, the encapsulation layer ENC may include a first encapsulation inorganic layer TFE1, an encapsulation organic layer TFE2, and a second encapsulation inorganic layer TFE3.

The first encapsulation inorganic layer TFE1 may be disposed on the common electrode 173, the encapsulation organic layer TFE2 may be disposed on the first encapsulation inorganic layer TFE1, and the second encapsulation inorganic layer TFE3 may be disposed on the encapsulation organic layer TFE 2. The first and second encapsulation inorganic layers TFE1 and TFE3 may be formed into a multilayer in which one or more inorganic layers selected from among a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. The encapsulation organic layer TFE2 may be an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

The sensor electrode layer SENL is disposed on the encapsulation layer ENC. The sensor electrode layer SENL may include a second buffer layer BF2, a first connection portion BE1, sensor electrodes (or referred to as touch electrodes) TE and RE, a first sensor insulating layer TINS1, and a second sensor insulating layer TINS2 (or referred to as touch insulating layer).

The second buffer layer BF2 may be disposed on the encapsulation layer ENC. The second buffer layer BF2 may include at least one inorganic layer. For example, the second buffer layer BF2 may be formed as a multilayer in which one or more inorganic layers selected from among a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. The second buffer layer BF2 may be omitted.

The first connection portion BE1 may BE disposed on the second buffer layer BF 2. The first connection part BE1 may BE formed of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), an APC alloy, or a stacked structure of APC alloy and ITO (ITO/APC/ITO).

The first sensor insulating layer TINS1 may BE disposed on the first connection portion BE 1. The first sensor insulating layer TINS1 may be formed of an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer).

The sensor electrodes (i.e., the driving electrode TE and the sensing electrode RE) may be disposed on the first sensor insulating layer TINS 1. In addition, a dummy pattern may be disposed on the first sensor insulating layer TINS 1. The driving electrode TE, the sensing electrode RE, and the dummy pattern do not overlap the light emitting area EA. The driving electrode TE, the sensing electrode RE, and the dummy pattern may be formed of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), an APC alloy, or a stacked structure of APC alloy and ITO (ITO/APC/ITO).

The second sensor insulating layer TINS2 may be disposed on the driving electrode TE, the sensing electrode RE, and the dummy pattern. The second sensor insulating layer TINS2 may include at least one selected from among an inorganic layer and an organic layer. The inorganic layer may be a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer may be an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

Fig. 7 is a cross-sectional view illustrating an example of a display area of a display panel in accordance with one or more embodiments. Fig. 8 is a detailed cross-sectional view illustrating the light emitting diode element of fig. 7.

Referring to fig. 7, the display panel 100 according to one or more embodiments may be a light emitting diode display panel including a light emitting element lel_1, the light emitting element lel_1 including a light emitting diode element 172_1 extending in a third direction (Z-axis direction). The light emitting diode element 172_1 has a length or a size in micrometers, and may be a micro light emitting diode made of an inorganic material. In this case, the display panel 100 according to one or more embodiments may be a micro light emitting diode display panel.

Since the display panel 100 according to one or more embodiments includes the light emitting diode element 172_1 made of an inorganic material, an encapsulation structure may not be required. Accordingly, the display panel 100 according to one or more embodiments may not include the encapsulation layer ENC.

In addition, when the light emitting diode elements 172_1 of the display panel 100 according to one or more embodiments emit the same light, a color control layer CCL may be included. When the light emitting diode element 172_1 of the display panel 100 according to one or more embodiments is classified as an element for emitting light having a plurality of colors, the color control layer CCL may be omitted.

In addition, in fig. 7, the polarizing film PF and the cover window CW are omitted for convenience of description. The polarizing film PF may be disposed on the color control layer CCL, and the cover window CW may be disposed on the polarizing film PF.

The display layer dis of the display panel 100 according to one or more embodiments includes a thin film transistor layer TFTL, a light emitting element layer EML, and a color control layer CCL. Since the thin film transistor layer TFTL illustrated in fig. 7 is substantially the same as the thin film transistor layer TFTL described with reference to fig. 6, a description of the thin film transistor layer TFTL is omitted in fig. 7.

The light emitting element layer EML may include a light emitting element lel_1, a bank 190, a third organic layer 191, and a fourth organic layer 192.

Each of the light emitting elements lel_1 may include a pixel electrode 171_1, a light emitting diode element 172_1, and a common electrode 173_1. Since the pixel electrode 171_1 is substantially the same as the pixel electrode 171 described with reference to fig. 6, a description of the pixel electrode 171_1 is omitted with reference to fig. 7.

The bank 190 may be disposed to cover an edge of the pixel electrode 171_1. The bank 190 may be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The bank 190 may include a light blocking material to prevent light from the light emitting diode element 172_1 of one subpixel from propagating to a subpixel adjacent to the one subpixel. For example, the bank 190 may include an inorganic black pigment (such as carbon black or an organic black pigment).

A plurality of light emitting diode elements 172_1 may be disposed on the exposed pixel electrode 171_1 without being covered by the bank 190. According to one or more example embodiments, each of the plurality of light emitting diode elements 172_1 is a vertical micro LED extending in the third direction DR 3. In this case, each of the plurality of light emitting diode elements 172_1 may have a rectangular or inverted cone cross-sectional shape. However, each of the plurality of light emitting diode elements 172_1 is not limited to the vertical type micro LED, and may be a flip type micro LED.

Each of the plurality of light emitting diode elements 172_1 may be formed of an inorganic material such as GaN. Each of the plurality of light emitting diode elements 172_1 may have a length in the first direction (X-axis direction), a length in the second direction (Y-axis direction), and a length in the third direction (Z-axis direction) of several micrometers to several hundred micrometers, respectively. For example, each of the plurality of light emitting diode elements 172_1 may have a length in the first direction (X-axis direction), a length in the second direction (Y-axis direction), and a length in the third direction (Z-axis direction) of about 100 μm or less, respectively.

Each of the plurality of light emitting diode elements 172_1 may be formed by growth on a semiconductor substrate (such as a silicon wafer). Each of the plurality of light emitting diode elements 172_1 may be directly transferred from the silicon wafer onto the pixel electrode 171_1 on the substrate SUB. Alternatively, each of the plurality of light emitting diode elements 172_1 may be transferred on the pixel electrode 171_1 on the substrate SUB by an electrostatic method using an electrostatic head or an imprint method using an elastic polymer material (such as PDMS or silicone) as a transfer substrate.

The light emitting diode element 172_1 may have a length or a size of micrometers, and may be an inorganic light emitting diode made of an inorganic material. The light emitting diode element 172_1 may have a shape extending in one direction. Each of the plurality of light emitting diode elements 172_1 may have a shape such as a cylinder, a rod, a wire, or a tube. However, the shape of the light emitting diode element 172_1 is not limited thereto, and may have a polygonal prism shape such as a cube, a cuboid, or a hexagonal prism, or may have a shape extending in one direction and having an outer surface partially inclined.

As shown in fig. 8, each of the plurality of light emitting diode elements 172_1 may include a contact electrode CTE, a first semiconductor layer SEM1, an electron blocking layer EBL, an active layer MQW, a superlattice layer SLT, and a second semiconductor layer SEM2. A description of the contact electrode CTE, the first semiconductor layer SEM1, the electron blocking layer EBL, the active layer MQW, the superlattice layer SLT, and the second semiconductor layer SEM2 of each of the plurality of light emitting diode elements 172_1 will be provided below with reference to fig. 8.

The contact electrode CTE may be disposed on the pixel electrode 171_1. The contact electrode CTE and the pixel electrode 171_1 may be fusion bonded by heat and pressure. Alternatively, the contact electrode CTE and the pixel electrode 171_1 may be bonded to each other by a conductive adhesive member such as an anisotropic conductive film or an anisotropic conductive adhesive. Alternatively, the contact electrode CTE and the pixel electrode 171_1 may be bonded to each other by a soldering process. For example, the contact electrode CTE may include at least one selected from among gold (Au), copper (Cu), aluminum (Al), and tin (Sn).

The first semiconductor layer SEM1 may be disposed on the contact electrode CTE. The first semiconductor layer SEM1 may be formed of GaN doped with a p-type dopant (such as Mg, zn, ca, sr or Ba).

An electron blocking layer EBL may be disposed on the first semiconductor layer SEM 1. The electron blocking layer EBL may be a layer for inhibiting or preventing too many electrons from flowing into the active layer MQW. For example, the electron blocking layer EBL may be p-AlGaN doped with p-type Mg. In one or more embodiments, the electron blocking layer EBL may be omitted.

The active layer MQW may be disposed on the electron blocking layer EBL. The active layer MQW may emit light by recombining electron-hole pairs according to an electrical signal applied through the first and second semiconductor layers SEM1 and SEM 2.

The active layer MQW may include a material having a single quantum well structure or a multiple quantum well structure. When the active layer MQW includes a material having a multi-quantum well structure, a plurality of well layers and barrier layers may be alternately stacked. In this case, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but is not limited thereto. Alternatively, the active layer MQW may have a structure in which a type of semiconductor material having a large energy band gap and a semiconductor material having a small energy band gap are alternately stacked with each other. In addition, the active layer MQW may include other group III to group V semiconductor materials according to the wavelength band of the emitted light.

When the active layer MQW includes InGaN, the color of the emitted light may vary according to the content of indium (In). For example, as the content of indium (In) increases, the band of light emitted by the active layer MQW may shift to the red band, and as the content of indium (In) decreases, the band of light emitted by the active layer MQW may shift to the blue band. For example, the content of indium (In) In the active layer MQW of the light-emitting diode element 172_1 emitting light of the blue wavelength band may be approximately 10wt% to 20wt%.

The superlattice layer SLT may be disposed on the active layer MQW. The superlattice layer SLT may be a layer that relieves stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the superlattice layer SLT may be formed of InGaN or GaN. In one or more embodiments, the superlattice layer SLT may be omitted.

The second semiconductor layer SEM2 may be disposed on the superlattice layer SLT. The second semiconductor layer SEM2 may be doped with a second conductive type dopant such as Si, ge, se, or Sn. For example, the second semiconductor layer SEM2 may be n-GaN doped with n-type Si.

Referring back to fig. 7, the third organic layer 191 may be disposed on the pixel electrode 171_1 not covered by the bank 190 and the plurality of light emitting diode elements 172_1. The third organic layer 191 may be disposed to cover a portion of the top surface and side surfaces of the bank 190. The height of the third organic layer 191 may be greater than the height of the bank 190. The third organic layer 191 may be disposed on a portion of a side surface of each of the plurality of light emitting diode elements 172_1. The height of the third organic layer 191 may be less than the height of each of the plurality of light emitting diode elements 172_1. The third organic layer 191 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

The fourth organic layer 192 may be disposed on the third organic layer 191. The fourth organic layer 192 may be disposed on a portion of a side surface of each of the plurality of light emitting diode elements 172_1. The sum of the height of the third organic layer 191 and the height of the fourth organic layer 192 may be smaller than the height of each of the plurality of light emitting diode elements 172_1. The fourth organic layer 192 may be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

The third organic layer 191 and the fourth organic layer 192 are layers for planarizing steps caused by the plurality of light emitting diode elements 172_1. When the height of each of the plurality of light emitting diode elements 172_1 is similar to that of the third organic layer 191, the fourth organic layer 192 may be omitted.

The common electrode 173_1 may be disposed on a top surface of each of the plurality of light emitting diode elements 172_1 and a top surface of the fourth organic layer 192. The common electrode 173_1 may be disposed on the bank 190 exposed without being covered with the third and fourth organic layers 191 and 192. The common electrode 173_1 may be a common layer commonly formed in the first, second, and third sub-pixels. The common electrode 173_1 may be formed of a transparent metal material (TCO, transparent conductive material) such as ITO (indium tin oxide) and Indium Zinc Oxide (IZO) that may transmit light.

The color control layer CCL may include a first CAP layer CAP1, a light blocking layer BM, a first light conversion layer QDL1, a second light conversion layer QDL2, a light transmission layer TPL, a second CAP layer CAP2, a fifth organic layer 193, a plurality of color filters CF1, CF2, and CF3, and a sixth organic layer 194.

The first CAP layer CAP1 may be disposed on the common electrode 173_1. The first CAP layer CAP1 may be formed of an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer).

The light blocking layer BM, the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL may be disposed on the first CAP layer CAP 1. The first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL may be formed by dividing the light blocking layer BM. Accordingly, the first light conversion layer QDL1 is disposed on the first CAP layer CAP1 in the first subpixel outputting the first light, the second light conversion layer QDL2 is disposed on the first CAP layer CAP1 in the second subpixel outputting the second light, and the light transmission layer TPL may be disposed on the first CAP layer CAP1 in the third subpixel outputting the third light. The light blocking layer BM may overlap the bank 190 in the third direction DR3 and may not overlap the plurality of light emitting diode elements 172_1.

The first light conversion layer QDL1 may convert a part of light of the blue wavelength band incident from the light emitting diode element 172_1 into light of the red wavelength band. The first light conversion layer QDL1 may include a first matrix resin BRS1 and first wavelength converting particles WCP1. The first matrix resin BRS1 may include a light transmissive organic material. For example, the first base resin BRS1 may include an epoxy-based resin, an acrylic-based resin, a cardy-based resin, or an imide-based resin. The first wavelength converting particles WCP1 may convert a portion of light of a blue wavelength band incident from the light emitting diode element 172_1 into light of a red wavelength band. The first wavelength converting particles WCP1 may be Quantum Dots (QDs), quantum bars, fluorescent materials, or phosphorescent materials.

The second light conversion layer QDL2 may convert a part of light of the blue wavelength band incident from the light emitting diode element 172_1 into light of the green wavelength band. The second light conversion layer QDL2 may include a second matrix resin BRS2 and second wavelength converting particles WCP2. The second matrix resin BRS2 may include a light transmissive organic material. For example, the second base resin BRS2 may include an epoxy-based resin, an acrylic-based resin, a cardo-based resin, or an imide-based resin. The second wavelength converting particles WCP2 may convert a portion of light of the blue wavelength band incident from the light emitting diode element 172_1 into light of the green wavelength band. The second wavelength converting particles WCP2 may be Quantum Dots (QDs), quantum strips, fluorescent materials, or phosphorescent materials.

The light transmissive layer TPL may include a light transmissive organic material. For example, the light transmissive layer TPL may include an epoxy-based resin, an acrylic-based resin, a card-based resin, or an imide-based resin.

The light blocking layer BM may include a first light blocking layer BM1 and a second light blocking layer BM2 sequentially stacked. The length of the first light blocking layer BM1 in the first direction (X-axis direction) or the length of the second light blocking layer BM2 in the second direction (Y-axis direction) may be greater than the length of the first light blocking layer BM1 in the first direction (X-axis direction) or the length of the second light blocking layer BM in the second direction (Y-axis direction). The first light blocking layer BM1 and the second light blocking layer BM2 may be formed as organic layers such as acryl resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like. The first and second light blocking layers BM1 and BM2 may include a light blocking material to prevent light from the light emitting diode element 172_1 of one subpixel from propagating to a subpixel adjacent to the one subpixel. For example, the first light blocking layer BM1 and the second light blocking layer BM2 may include an inorganic black pigment such as carbon black or an organic black pigment.

The second CAP layer CAP2 may be disposed on the light blocking layer BM, the first light-converting layer QDL1, the second light-converting layer QDL2, and the light-transmitting layer TPL. The second CAP layer CAP2 may be formed of an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer). The light blocking layer BM, the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL may be encapsulated by the first CAP layer CAP1 and the second CAP layer CAP 2.

A fifth organic layer 193 may be disposed on the second CAP layer CAP 2. The fifth organic layer 193 may be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

A plurality of color filters CF1, CF2, and CF3 may be disposed on the fifth organic layer 193. The plurality of color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3.

Each of the first color filters CF1 disposed in the first sub-pixel may transmit light of a red wavelength band and may absorb or block light of a blue wavelength band. Accordingly, each of the first color filters CF1 transmits light of the red wavelength band converted by the first light conversion layer QDL1 among light of the blue wavelength band emitted from the light emitting diode element 172_1, and may absorb or block light of the blue wavelength band not converted by the first light conversion layer QDL 1. Thus, the first subpixel may emit light in the red wavelength band.

Each of the second color filters CF2 disposed in the second sub-pixels may transmit light of a green wavelength band and may absorb or block light of a blue wavelength band. Accordingly, each of the second color filters CF2 transmits light of a green wavelength band converted by the second light conversion layer QDL2 among light of a blue wavelength band emitted from the light emitting diode element 172_1, and may absorb or block light of a blue wavelength band not converted by the second light conversion layer QDL 2. Thus, the second sub-pixel may emit light in the green band.

Each of the third color filters CF3 provided in the third sub-pixel may transmit light of a blue band. Accordingly, each of the third color filters CF3 may transmit light of a blue wavelength band emitted from the light emitting diode element 172_1 through the light transmitting layer TPL. Thus, the third sub-pixel may emit light in the blue band.

The sixth organic layer 194 for planarization may be disposed on the plurality of color filters CF1, CF2, and CF 3. The sixth organic layer 194 may be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

Fig. 9 is a cross-sectional view illustrating an example of a display area of a display panel in accordance with one or more embodiments.

Referring to fig. 9, the display panel 100 according to one or more embodiments may be a light emitting diode display panel including a light emitting element lel_1, the light emitting element lel_1 including a light emitting diode element 172_1 extending in a horizontal direction such as a first direction (X-axis direction) and/or a second direction (Y-axis direction). The light emitting diode element 172_1 has a length or a size of nanometers, and may be a nano light emitting diode made of an inorganic material. In this case, the display panel 100 according to one or more embodiments may be a nano light emitting diode display panel.

In addition, when the light emitting diode elements 172_1 of the display panel 100 according to one or more embodiments emit the same light, a color control layer CCL may be included. In fig. 9, the color control layer CCL is omitted for convenience of description. In addition, when the light emitting diode element 172_1 of the display panel 100 according to one or more embodiments is classified as an element for emitting light of a plurality of colors, the color control layer CCL may be omitted.

In addition, in fig. 9, the polarizing film PF and the cover window CW are omitted for convenience of description. The polarizing film PF may be disposed on the color control layer CCL disposed on the light emitting element layer EML, and the cover window CW may be disposed on the polarizing film PF.

The display layer dis of the display panel 100 according to one or more embodiments includes a thin film transistor layer TFTL and a light emitting element layer EML.

The thin film transistor layer TFTL illustrated in fig. 9 will be described mainly with respect to differences from the thin film transistor layer TFTL illustrated in fig. 6, and duplicate description may be omitted.

In fig. 9, the second gate metal layer, the second interlayer insulating layer 142, the second data metal layer, and the second organic layer 180 are omitted. In addition, in fig. 9, the capacitor Cst is omitted for convenience of description.

As shown in fig. 9, a first data metal layer including a first connection electrode CE1, a second connection electrode CE2_1, and a third connection electrode CE3 may be disposed on the first interlayer insulating layer 141. The first connection electrode CE1 may be connected to the drain region TD through a first contact hole CT1 penetrating the first interlayer insulating layer 141. The second connection electrode CE2_1 may be connected to the source region TS through a second contact hole CT1_1 penetrating the first interlayer insulating layer 141.

The light emitting element layer EML may include first to third bank patterns BP1, BP2 and BP3, an alignment electrode RME, a connection electrode CNE and a light emitting diode element 172_1.

The first bank pattern BP1 may be disposed between the second bank pattern BP2 and the third bank pattern BP 3. That is, the second bank pattern BP2 may be disposed at one side of the first bank pattern BP1, and the third bank pattern BP3 may be disposed at the other side of the first bank pattern BP 1.

The plurality of light emitting diode elements 172_1 may be disposed between the first and second bank patterns BP1 and BP2 and between the first and third bank patterns BP1 and BP 3. The first to third bank patterns BP1, BP2 and BP3 may be arranged in an island pattern.

The first to third bank patterns BP1, BP2 and BP3 may be disposed on the first organic layer 160. Each of the first to third bank patterns BP1, BP2 and BP3 may protrude in a third direction (Z-axis direction) on the first organic layer 160. Each of the first to third bank patterns BP1, BP2 and BP3 may have an inclined side surface (or a plurality of inclined side surfaces).

The first alignment electrode RME1 may be disposed between the second alignment electrode RME2 and the third alignment electrode RME 3. The first alignment electrode RME1 may cover an upper surface and an inclined side surface of the first bank pattern BP 1. Accordingly, the first alignment electrode RME1 may reflect light emitted from the plurality of light emitting diode elements 172_1 in the third direction (Z-axis direction).

The second alignment electrode RME2 may be disposed at one side of the first alignment electrode RME 1. The second alignment electrode RME2 may cover an upper surface and an inclined side surface of the second bank pattern BP 2. Accordingly, the second alignment electrode RME2 may reflect light emitted from the plurality of light emitting diode elements 172_1 disposed between the first bank pattern BP1 and the second bank pattern BP2 in an upward direction (Z-axis direction).

The third alignment electrode RME3 may be disposed at the other side of the first alignment electrode RME 1. The third align electrode RME3 may cover an upper surface and an inclined side surface of the third bank pattern BP 3. Accordingly, the third alignment electrode RME3 may reflect light emitted from the plurality of light emitting diode elements 172_1 disposed between the first bank pattern BP1 and the third bank pattern BP3 in an upward direction (Z-axis direction).

The first to third alignment electrodes RME1, RME2 and RME3 may be disposed on the first organic layer 160 and the first to third bank patterns BP1, BP2 and BP 3.

The first alignment electrode RME1 may be connected to the first connection electrode CE1 through the third contact hole CT3, and thus may be electrically connected to the thin film transistor TFT.

The third align electrode RME3 may be connected to the third connection electrode CE3 through the fourth contact hole CT 4. Since the third connection electrode CE3 is electrically connected to the first power line VSL, the first power voltage VSS of the first power line VSL may be applied to the third connection electrode CE3.

The first to third alignment electrodes RME1, RME2 and RME3 are electrically connected to the light emitting diode element 172_1, and light emitted from the plurality of light emitting diode elements 172_1 may be reflected in an upward direction of the substrate SUB. To this end, the first to third alignment electrodes RME1, RME2 and RME3 may include a conductive material having a high reflectivity. For example, the first to third alignment electrodes RME1, RME2 and RME3 may include a metal such as silver (Ag), copper (Cu) or aluminum (Al), or may have an alloy including aluminum (Al), nickel (Ni) and/or lanthanum (La) or the like or a structure in which a metal layer such as titanium (Ti), molybdenum (Mo) and/or niobium (Nb) and an alloy are laminated. In some embodiments, the first to third alignment electrodes RME1, RME2 and RME3 may be formed of a double layer or a multi-layer in which an alloy including aluminum (Al) and at least one metal layer made of titanium (Ti), molybdenum (Mo) and/or niobium (Nb) are stacked.

Optionally, the first to third alignment electrodes RME1, RME2 and RME3 may further include transparent conductive material. For example, the first to third alignment electrodes RME1, RME2 and RME3 may include a material such as ITO, IZO or ITZO. In some embodiments, each of the alignment electrodes RME may have a structure in which a transparent conductive material and a metal layer having high reflectivity are stacked in one or more layers, or may be formed to include one layer of these. For example, the first to third alignment electrodes RME1, RME2 and RME3 may have a stacked structure such as ITO/Ag/ITO, ITO/Ag/IZO or ITO/Ag/ITZO/IZO.

As shown in fig. 8, each of the plurality of light emitting diode elements 172_1 may include a contact electrode CTE, a first semiconductor layer SEM1, an electron blocking layer EBL, an active layer MQW, a superlattice layer SLT, and a second semiconductor layer SEM2.

The plurality of light emitting diode elements 172_1 may be aligned between the first and second alignment electrodes RME1 and RME2 or between the first and third alignment electrodes RME1 and RME3. The first insulating layer PAS1 may cover the first to third alignment electrodes RME1, RME2 and RME3. The plurality of light emitting diode elements 172_1 may be insulated from the first to third alignment electrodes RME1, RME2 and RME3 by a first insulating layer PAS 1. Each of the first to third alignment electrodes RME1, RME2 and RME3 may receive an alignment signal before the first to third alignment electrodes RME1, RME2 and RME3 are separated by the separating unit. Thus, an electric field may be formed between the first to third alignment electrodes RME1, RME2 and RME3. For example, the plurality of light emitting diode elements 172_1 may be ejected onto the first to third alignment electrodes RME1, RME2 and RME3 by an inkjet printing process, and the plurality of light emitting diode elements 172_1 dispersed in ink may be aligned by receiving dielectrophoretic forces via an electric field formed between the first to third alignment electrodes RME1, RME2 and RME3. Accordingly, the plurality of light emitting diode elements 172_1 may be arranged between the first and second alignment electrodes RME1 and RME2 and between the first and third alignment electrodes RME1 and RME3 in the second direction (Y-axis direction).

The first insulating layer PAS1 may be disposed on the first organic layer 160 and the first to third alignment electrodes RME1, RME2 and RME3. The first insulating layer PAS1 may include an insulating material to protect the first to third alignment electrodes RME1, RME2 and RME3. Since the first insulating layer PAS1 is disposed to cover the first to third alignment electrodes RME1, RME2 and RME3 before the formation of the bank layer BNL, damage to the first to third alignment electrodes RME1, RME2 and RME3 can be prevented in the process of forming the bank layer BNL. In addition, the first insulating layer PAS1 may prevent or protect the plurality of light emitting diode elements 172_1 from being damaged due to direct contact with other members.

The first to third connection electrodes CNE1, CNE2 and CNE3 may be disposed on the first to third alignment electrodes RME1, RME2 and RME3. The second insulating layer PAS2 may be disposed on the bank layer BNL, the first insulating layer PAS1, and a central portion of each of the plurality of light emitting diode elements 172_1. The third insulating layer PAS3 may cover the second insulating layer PAS2 and the first to third connection electrodes CNE1, CNE2 and CNE3. The second and third insulating layers PAS2 and PAS3 may insulate each of the first to third connection electrodes CNE1, CNE2 and CNE3.

The first connection electrode CNE1 may be disposed on the first alignment electrode RME1, and may be connected to the first alignment electrode RME1 through a contact hole penetrating the first insulating layer PAS 1. The first connection electrode CNE1 may connect one end of the light emitting diode element 172_1 disposed between the first and second bank patterns BP1 and BP2 to the first alignment electrode RME1.

The second connection electrode CNE2 may be disposed on the first and second alignment electrodes RME1 and RME2, and may be insulated from the first and second alignment electrodes RME1 and RME 2. The first portion of the second connection electrode CNE2 may be disposed on the second alignment electrode RME2, and may extend in the second direction (Y-axis direction). The second portion of the second connection electrode CNE2 may be bent from the bottom side of the first portion to extend in the first direction (X-axis direction). The third portion of the second connection electrode CNE2 may be bent from the right side of the second portion to extend in the second direction (Y-axis direction), and may be disposed on the first alignment electrode RME1. The second connection electrode CNE2 may connect the other end of the light emitting diode element 172_1 disposed between the first and second bank patterns BP1 and BP2 to one end of the light emitting diode element 172_1 disposed between the second and third bank patterns BP2 and BP 3.

The third connection electrode CNE3 may be disposed on the third alignment electrode RME3, and may be connected to the third alignment electrode RME3 through a contact hole penetrating the first insulating layer PAS 1. The third connection electrode CNE3 may connect the other end of the light emitting diode element 172_1 disposed between the second bank pattern BP2 and the third bank pattern BP3 to the third alignment electrode RME3.

Fig. 10 is a cross-sectional view illustrating an example of a display area of a display panel in accordance with one or more embodiments.

Referring to fig. 10, a display panel 100 according to one or more embodiments may be a liquid crystal display panel including a liquid crystal layer LCL including a liquid crystal LC.

A gate metal layer including the scan line, the first capacitor electrode CAE1, and the gate electrode GE may be disposed on the substrate SUB. The gate metal layer may include one or more selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu), or an alloy thereof. Alternatively, the gate metal layer may have a dual layer structure of molybdenum/aluminum-neodymium, molybdenum/aluminum, or copper/titanium.

The gate insulating layer 130 may be disposed on the gate metal layer. The gate insulating layer 130 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or a combination thereof.

The active layer ACT may be disposed on the gate insulating layer 130. The active layer ACT may include a channel region CH disposed between the source electrode SE and the drain electrode DE in a first direction (X-axis direction). The channel region CH may overlap the gate electrode GE.

The active layer ACT may include a silicon-based semiconductor material such as amorphous silicon, polycrystalline silicon, or single crystal silicon. Alternatively, the active layer ACT may include an oxide semiconductor.

An ohmic contact layer may be disposed on the active layer ACT. For example, ohmic contact layers may be disposed between the source electrode SE and the active layer ACT and between the drain electrode DE and the active layer ACT. The ohmic contact layer may reduce contact resistance by lowering the schottky barrier (i.e., work function) between the metal and silicon. The ohmic contact layer may be formed of amorphous silicon doped with a high concentration of n-type impurities.

A data metal layer including a data line, a source electrode SE, a drain electrode DE, and a first connection electrode CE1 may be disposed on the gate insulating layer 130. The source electrode SE and the drain electrode DE may be disposed on the active layer ACT. The source electrode SE and the first connection electrode CE1 may be integrally formed. The data metal layer may include one or more selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu), or an alloy thereof. Alternatively, the data metal layer may have a two-layer structure of molybdenum/aluminum-neodymium, molybdenum/aluminum, or copper/titanium, or a three-layer structure of molybdenum/titanium/molybdenum or molybdenum/aluminum/molybdenum.

The first organic layer 160 may be disposed on the data metal layer. The first organic layer 160 may include an organic insulating material or an inorganic insulating material. For example, the first organic layer 160 may be an overcoat layer made of an organic insulating material.

A pixel electrode layer including the pixel electrode 171_2 may be disposed on the first organic layer 160. The pixel electrode 171_2 may be connected to the first connection electrode CE1 through a contact hole CT penetrating the first organic layer 160. The pixel electrode layer may be formed of a transparent material through which light may pass. For example, the pixel electrode layer may be made of Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), or Indium Tin Zinc Oxide (ITZO), but is not limited thereto. Any transparent and electrically conductive material may be used.

The color filter substrate CSUB facing the substrate SUB may be a transparent insulating substrate similar to the substrate SUB. For example, the color filter substrate CSUB may be made of glass.

The light blocking member BM may be disposed between the color filters CF on one surface of the color filter substrate CSUB facing the substrate SUB. The light blocking member BM may overlap the thin film transistor tft_1 and the contact hole CT. The light blocking member BM may include a light blocking pigment such as carbon black or an opaque metallic material such as chromium (Cr). Alternatively, the light blocking member BM may include a photosensitive organic material. The light blocking member BM may be disposed on the substrate SUB.

The common electrode 173_2 may be disposed on one surface of the light blocking member BM facing the substrate SUB. The common electrode 173_2 may be made of a transparent conductive material such as Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), or Indium Tin Zinc Oxide (ITZO). The common electrode 173_2 may be integrally formed throughout the entire surface of the color filter substrate CSUB.

The liquid crystal layer LCL may be disposed between the substrate SUB and the color filter substrate CSUB. The liquid crystal layer LCL may include a liquid crystal LC having dielectric anisotropy. When a data voltage is applied to the pixel electrode 171_2 and a common voltage is applied to the common electrode 173_2, an electric field may be formed between the pixel electrode 171_2 and the common electrode 173_2. The arrangement of the liquid crystal LC of the liquid crystal layer LCL may be changed according to the electric field between the pixel electrode 171_2 and the common electrode 173_2, so that the transmittance of light passing through the liquid crystal layer LCL may be controlled.

For example, when an electric field is formed between the pixel electrode 171_2 and the common electrode 173_2, the liquid crystal LC may be rotated in a specific direction to adjust a phase retardation value of light passing through the liquid crystal layer LCL. The amount of light passing through the lower polarizing film disposed on the bottom surface of the substrate SUB may be different from the amount of light passing through the upper polarizing film disposed on the upper surface of the color filter substrate CSUB. Therefore, the transmittance of light passing through the liquid crystal layer LCL can be controlled.

As shown in fig. 6 to 10, the display panel 100 according to one or more embodiments may be an organic light emitting diode display panel, a micro light emitting diode display panel, a nano light emitting diode display panel, or a liquid crystal display panel. Alternatively, the display panel 100 according to one or more embodiments may be an electroluminescent display panel using an electroluminescent element or an electrochromic display panel using an electrochromic element. Hereinafter, for convenience of description, the display panel 100 according to one or more embodiments will be mainly described as an organic light emitting display panel.

Fig. 11 is a layout diagram showing an example of the area a of fig. 2 in more detail. Fig. 11 is a layout diagram illustrating a display area DA and a non-display area NDA disposed on the right side of the display panel 100 according to one or more embodiments.

Referring to fig. 11, the display area DA may include a plurality of light emitting areas EA1, EA2, EA3, and EA4. The plurality of light emitting areas EA1, EA2, EA3 and EA4 include a first light emitting area EA1 for emitting light of a first color, second and fourth light emitting areas EA2 and EA4 for emitting light of a second color, and a third light emitting area EA3 for emitting light of a third color. For example, the light of the first color is light in a red wavelength band of approximately 600nm to 750nm, the light of the second color is light in a green wavelength band of approximately 480nm to 560nm, and the light of the third color is light in a blue wavelength band of approximately 370nm to 460nm, but the embodiment of the present specification is not limited thereto.

Fig. 11 shows that the second light emitting area EA2 and the fourth light emitting area EA4 emit light of the same color (i.e., light of the second color), but the embodiment of the present disclosure is not limited thereto. The second and fourth light emitting areas EA2 and EA4 may emit light of different colors. For example, the second light emitting area EA2 may emit light of the second color, and the fourth light emitting area EA4 may emit light of the fourth color.

In addition, although fig. 11 shows that each of the first, second, third, and fourth light emitting areas EA1, EA2, EA3, and EA4 has a rectangular planar shape, embodiments of the present disclosure are not limited thereto. Each of the first, second, third, and fourth light emitting areas EA1, EA2, EA3, and EA4 may have a polygonal shape other than a quadrangular shape, a circular shape, an elliptical shape, or any other suitable shape.

In addition, as shown in fig. 11, the area of the third light emitting area EA3 may be the largest, and the area of the second light emitting area EA2 and the area of the fourth light emitting area EA4 may be the smallest. The area of the second light emitting area EA2 and the area of the fourth light emitting area EA4 may be the same.

The second light emitting areas EA2 and the fourth light emitting areas EA4 may be alternately arranged in the first direction (X-axis direction). The second light emitting area EA2 may be arranged (e.g., aligned) along the second direction (Y-axis direction). The fourth light emitting area EA4 may be arranged (e.g., aligned) along the second direction (Y-axis direction). Each of the fourth light emitting areas EA4 has a long side in the first diagonal direction DD1 and a short side in the second diagonal direction DD2, and each of the second light emitting areas EA2 may have a long side in the second diagonal direction DD2 and a short side in the first diagonal direction DD 1. The first diagonal direction DD1 indicates a diagonal direction between the first direction (X-axis direction) and the second direction (Y-axis direction), and the second diagonal direction DD2 may be orthogonal to the first diagonal direction DD 1.

The first and third light emitting areas EA1 and EA3 may be alternately arranged along the first direction (X-axis direction). The first light emitting areas EA1 may be arranged (e.g., aligned) along the second direction (Y-axis direction). The third light emitting area EA3 may be arranged (e.g., aligned) along the second direction (Y-axis direction). Each of the first and third light emitting areas EA1 and EA3 may have a square planar shape, but embodiments of the present disclosure are not limited thereto. In this case, each of the first and third light emitting areas EA1 and EA3 may include two sides parallel to each other in the first diagonal direction DD1 and two sides parallel to each other in the second diagonal direction DD 2.

The non-display area NDA includes a first non-display area NDA1 and a second non-display area NDA2. The first non-display area NDA1 may be an area in which a structure for driving the pixels SP of the display area DA is disposed. The second non-display area NDA2 may be disposed outside the first non-display area NDA 1. The second non-display area NDA2 may be an edge area of the non-display area NDA. In addition, the second non-display area NDA2 may be an edge area of the display panel 100.

The first non-display area NDA1 may include a scan driving circuit unit SDC, a first power line VSL, a first DAM1, and a second DAM2.

The scan driving circuit unit SDC may include a plurality of stages STA. The plurality of stages STA may be connected to scan lines SL of the display area DA extending in a first direction (X-axis direction), respectively. That is, the plurality of stages STA may be connected one-to-one to the scan lines SL of the display area DA extending in the first direction (X-axis direction). The plurality of stages STA may sequentially apply the scan signals to the plurality of scan lines SL.

The first power line VSL may be disposed outside the scan driving circuit unit SDC. That is, the first power line VSL may be disposed closer to the edge EG of the display panel 100 than the scan driving circuit unit SDC. In one or more embodiments, the first power line VSL may extend in the second direction (Y-axis direction) in the first non-display area NDA 1.

The first power line VSL may be electrically connected to the common electrode 173 (e.g., see fig. 6) such that the common electrode 173 may receive the first power voltage VSS from the first power line VSL.

The first DAM1 and the second DAM2 are structures for preventing the encapsulation organic layer TFE2 of the encapsulation layer ENC from overflowing to the edge EG of the display panel 100. The first DAM1 and the second DAM2 may extend in the second direction (Y-axis direction) in the first non-display area NDA 1. The second DAM2 may be disposed outside the first DAM 1. The first DAM1 may be disposed closer to the scan driving circuit unit SDC than the second DAM2, and the second DAM2 may be disposed closer to the edge EG of the display panel 100 than the first DAM 1.

Fig. 11 illustrates that the first DAM1 and the second DAM2 are disposed on the first power line VSL, but the embodiment of the present disclosure is not limited thereto. For example, either the first DAM1 or the second DAM2 may not be provided on the first power line VSL. Alternatively, neither the first DAM1 nor the second DAM2 may be provided on the first power line VSL. In this case, the first DAM1 and the second DAM2 may be disposed outside the first power line VSL.

Although fig. 11 illustrates that the display panel 100 according to one or more embodiments includes two DAMs DAM1 and DAM2, embodiments of the present disclosure are not limited thereto. That is, the display panel 100 according to one or more embodiments may include three or more dams.

The second non-display area NDA2 may include a crack dam CRD and an edge area EGA.

The crack dam CRD may extend in the second direction (Y-axis direction) in the second non-display area NDA 2. The width of the crack dam CRD may be about 30 μm or less.

The edge region EGA may be disposed along an edge EG of the display panel 100. The edge area EGA may be an area in which a processing trace generated in the process of cutting the substrate SUB is generated.

Since the region C of fig. 2 is substantially symmetrical with the region a shown in fig. 11, a description of the region C of fig. 2 will be omitted.

Fig. 12 is a layout diagram showing an example of the region B of fig. 2 in more detail. Fig. 12 is a layout diagram illustrating a non-display area NDA disposed on the underside of the display panel 100 in accordance with one or more embodiments.

Referring to fig. 12, the first non-display area NDA1 may include a plurality of display pads PD, a plurality of first driving pads DPD1, a plurality of second driving pads DPD2, and a plurality of pad lines, a plurality of fan-out lines, a first DAM1, and a second DAM2.

The plurality of display pads PD may be electrically connected to the circuit board 300 through a conductive adhesive member CAD (see fig. 25) such as an anisotropic conductive film or an anisotropic conductive adhesive. Each of the plurality of display pads PD may be connected to a pad line PDL. The pad line PDL may connect the display pad PD and the first driving pad DPD 1.

The plurality of first driving pads DPD1 and the plurality of second driving pads DPD2 may be electrically connected to the driving IC 200 through a conductive adhesive member CAD such as an anisotropic conductive film or an anisotropic conductive adhesive. The plurality of first driving pads DPD1 may be input pads for the driving IC 200 to receive signals (e.g., digital video DATA, DATA timing control signals DCS, etc.) of the circuit board 300. The plurality of second driving pads DPD2 may be output pads for outputting signals (e.g., data voltages) of the driving IC 200. Each of the plurality of second driving pads DPD2 may be connected to a fanout line FL. The fanout line FL may connect the second driving pad DPD2 with the data line DL of the display area DA.

Each of the plurality of first driving pads DPD1 may be disposed closer to the display area DA in the second direction (Y-axis direction) than the display pad PD connected thereto. That is, among the display pad PD and the first driving pad DPD1 connected to each other, the display pad PD may be disposed closer to the edge EG of the display panel 100 in the second direction (Y-axis direction) than the first driving pad DPD 1.

Each of the plurality of second driving pads DPD2 may be disposed closer to the display area DA than any one of the plurality of first driving pads DPD1 in the second direction (Y-axis direction). That is, the first driving pad DPD1 may be disposed closer to the edge EG of the display panel 100 than any one of the plurality of second driving pads DPD2 in the second direction (Y-axis direction).

The first DAM1 and the second DAM2 may cross the fan-out line FL. The first DAM1 and the second DAM2 may extend in a first direction (X-axis direction) in the non-display area NDA of the lower side of the display panel 100. The second DAM2 may be disposed outside the first DAM 1. The first DAM1 may be disposed closer to the display area DA than the second DAM2, and the second DAM2 may be disposed closer to the edge EG of the display panel 100 than the first DAM 1.

Fig. 13 is a layout diagram showing an example of the region D of fig. 2 in more detail. Fig. 13 is a layout diagram illustrating a display area DA and a non-display area NDA disposed on an upper side of the display panel 100 according to one or more embodiments.

Referring to fig. 13, the first non-display area NDA1 may include a first power line VSL, a first DAM1, and a second DAM2. The first non-display area NDA1 may not include the scan driving circuit unit SDC.

The first power line VSL may extend in a first direction (X-axis direction) in the first non-display area NDA1 of the upper side of the display panel 100. The first power line VSL may be electrically connected to the common electrode 173 (e.g., see fig. 6) such that the common electrode 173 may receive the first power voltage VSS from the first power line VSL.

The first DAM1 and the second DAM2 may extend in a first direction (X-axis direction) in a first non-display area NDA1 of an upper side of the display panel 100. The second DAM2 may be disposed outside the first DAM 1. The first DAM1 may be disposed closer to the display area DA than the second DAM2, and the second DAM2 may be disposed closer to the edge EG of the display panel 100 than the first DAM 1.

Fig. 13 illustrates that the first DAM1 and the second DAM2 are disposed on the first power line VSL, but the embodiment of the present disclosure is not limited thereto. For example, any one of the first DAM1 and the second DAM2 may not be provided on the first power line VSL. Alternatively, neither the first DAM1 nor the second DAM2 may be provided on the first power line VSL. In this case, the first DAM1 and the second DAM2 may be disposed outside the first power line VSL.

The crack dam CRD may be an outermost structure disposed at the outermost side of the display panel 100. The crack dam CRD may extend in a first direction (X-axis direction) in the non-display area NDA of the upper side of the display panel 100.

Fig. 14 is a cross-sectional view showing an example of the display panel taken along the line II-II' of fig. 11. Fig. 15 is a cross-sectional view showing an example of the display panel taken along line III-III' of fig. 12. Fig. 16 is an image showing the width of the first sub-edge area. Fig. 17 is an image showing debris of the second sub-edge area. Fig. 18 is an image illustrating roughness of a first side surface, a first inclined surface, and a second inclined surface of a display panel according to one or more embodiments.

In fig. 14 and 15, a cross section of an edge EG of the display panel 100 when the substrate SUB is cut with a cutting member such as a cutting wheel and then a polishing process is performed during a manufacturing process of the display panel 100 is shown.

Referring to fig. 14 and 15, the edge region EGA may include a first sub-edge region SEGA1 and a second sub-edge region SEGA2.

The first SUB-edge area SEGA1 may be an area in which a processing trace is formed on the substrate SUB by a polishing process performed after the substrate SUB is cut with the cutting member. That is, the first sub-edge area SEGA1 may include a first inclined surface IP1 and a second inclined surface IP2 formed through a polishing process.

The angle θ1 between the side surface SS and the first inclined surface IP1 and the angle θ3 between the first inclined surface IP1 and the upper surface US may be obtuse angles. An angle θ2 between the side surface SS and the second inclined surface IP2 and an angle θ4 between the second inclined surface IP2 and the bottom surface BS may be obtuse angles.

Fig. 14 shows that the length of the first inclined surface IP1 in the inclined direction is longer than the length of the second inclined surface IP2 in the inclined direction. In this case, an angle θ1 between the side surface SS and the first inclined surface IP1 may be greater than an angle θ2 between the side surface SS and the second inclined surface IP2. Further, an angle θ4 between the second inclined surface IP2 and the bottom surface BS may be greater than an angle θ3 between the first inclined surface IP1 and the upper surface US.

The width of the first sub-edge area SEGA1 may be within about 150 μm. For example, as shown in fig. 16, the width of the first sub-edge area SEGA1 may be greater than about 80 μm.

The second SUB-edge area SEGA2 may be an area in which a processing trace such as chipping (chipping) is formed on the upper surface of the substrate SUB by a polishing process (as shown in fig. 17). The width of the second sub-edge area SEGA2 may be within about 50 μm.

The crack dam CRD may be a structure for preventing cracks from occurring in the process of cutting the substrate SUB during the manufacturing process of the display device 10. The crack dam CRD may be an outermost structure disposed at the outermost side of the right side of the display panel 100.

The distance D1 between the crack dam CRD and the edge area EGA may be set in consideration of manufacturing tolerances of the crack dam CRD. For example, the distance D1 between the crack dam CRD and the edge region EGA may be about 30 μm or less. The distance D1 between the crack dam CRD and the edge area EGA may be 0 μm.

The minimum distance from the crack dam CRD, which is the outermost structure, to the edge EG of the display panel 100 may be the sum of the width of the first sub-edge area SEGA1, the width of the second sub-edge area SEGA2, and the minimum distance D1 from the crack dam CRD to the edge area EGA. For example, the minimum distance from the crack dam CRD as the outermost structure to the edge EG of the display panel 100 may be about 230 μm or less.

However, when the substrate SUB is cut with the cutting member, the minimum distance from the crack dam CRD to the edge EG of the display panel 100 may vary according to a tolerance of one side of the cutting member. In this case, the minimum distance from the crack dam CRD to the edge EG of the display panel 100 may be the sum of the width of the first sub-edge region SEGA1, the width of the second sub-edge region SEGA2, the minimum distance D1 from the crack dam CRD to the edge region EGA, and the one-side tolerance of the cutting member. For example, the minimum distance from the crack dam CRD as the outermost structure to the edge EG of the display panel 100 may be approximately 130 μm to 330 μm. That is, the minimum distance from the crack dam CRD, which is the outermost structure, to the edge EG of the display panel 100 may be greater than about 130 μm. A description will be given later of a distance between the crack dam CRD and the edge EG of the display panel 100 according to a tolerance of one side of the cutting member with reference to fig. 53.

The display pad PD may be an outermost structure disposed at the outermost side of the lower side of the display panel 100. The distance D2 between the display pad PD and the edge area EGA may be set in consideration of manufacturing tolerances of the display pad PD. For example, the distance D2 between the display pad PD and the edge region EGA may be about 30 μm or less. The distance D2 between the display pad PD and the edge area EGA may be 0 μm.

The minimum distance from the display pad PD to the edge EG of the display panel 100 may be a sum of the width of the first sub-edge area SEGA1, the width of the second sub-edge area SEGA2, and the minimum distance D2 from the display pad PD to the edge area EGA. For example, the minimum distance from the display pad PD, which is the outermost structure, to the edge EG of the display panel 100 may be approximately 230 μm.

However, when the substrate SUB is cut with the cutting member, the minimum distance from the display pad PD to the edge EG of the display panel 100 may vary according to a tolerance of one side of the cutting member. In this case, the minimum distance from the display pad PD to the edge EG of the display panel 100 may be the sum of the width of the first sub-edge area SEGA1, the width of the second sub-edge area SEGA2, the minimum distance D2 from the display pad PD to the edge area EGA, and a side tolerance of the cutting member. For example, when the tolerance of one side of the cutting member is about 100 μm, the minimum distance from the display pad PD to the edge EG of the display panel 100 may be 130 μm to 330 μm or less. That is, when the substrate SUB is cut with the cutting member, the minimum distance from the display pad PD to the edge EG of the display panel 100 may be greater than 130 μm.

In addition, when the substrate SUB is cut with the cutting member and then the polishing process is performed during the manufacturing process of the display panel 100, the side surface SS, the first inclined surface IP1, and the second inclined surface IP2 of the display panel 100 may be polished by the polishing apparatus. In this case, as shown in fig. 18, the roughness of the side surface SS, the first inclined surface IP1, and the second inclined surface IP2 of the display panel 100 may be about 1 μm.

Fig. 19 is a cross-sectional view showing an example of the display panel taken along the line II-II' of fig. 11. Fig. 20 is a cross-sectional view showing an example of the display panel taken along line III-III' of fig. 12. Fig. 21 is a cross-sectional view showing an example of the display panel taken along the line IV-IV' of fig. 13. Fig. 22 is an image showing a width of a processing trace of a display panel in accordance with one or more embodiments. Fig. 23 is an image illustrating roughness of a first side surface and a first inclined surface of a display panel according to one or more embodiments.

Fig. 19 to 21 show cross sections of the edge EG of the display panel 100 when the substrate SUB of the display panel 100 is cut by irradiating laser light and then spraying an etchant. The side surface of the substrate SUB shown in fig. 19 disposed at the right side of the display panel 100 may be a first side surface or a right side surface of the substrate SUB. The side surface of the substrate SUB shown in fig. 20 disposed at the lower side of the display panel 100 may be a second side surface or a bottom side surface of the substrate SUB. The side surface of the substrate SUB shown in fig. 21 disposed at the upper side of the display panel 100 may be a third side surface or an upper side surface of the substrate SUB. The side surface of the substrate SUB disposed at the left side of the display panel 100 may be a fourth side surface or a left side surface of the substrate SUB.

Referring to fig. 19 to 21, the edge region EGA may be a region in which a processing trace is formed on the upper surface US of the substrate SUB by an etchant when the substrate SUB is cut by spraying the etchant after irradiating a laser. As shown in fig. 22, the edge region EGA may be within about 30 μm.

The edge region EGA may include a first inclined surface ip1_1 formed by spraying an etchant after irradiating laser light. The angle θ5 between the side surface SS-1 and the upper surface US may be about 90 degrees. That is, the angle between the side surface ss_1 and the upper surface US may be substantially nearly perpendicular. An angle θ6 between the side surface ss_1 and the first inclined surface ip1_1 and an angle θ7 between the first inclined surface ip1_1 and the bottom surface BS may be obtuse angles. The processing trace formed on the upper surface US of the substrate SUB may overlap the first inclined surface ip1_1 in the third direction (Z-axis direction).

Although the processing trace is a trace formed by penetration of the etchant between the acid-resistant film and the upper surface US of the substrate SUB in the manufacturing process, the first inclined surface ip1_1 is an inclined surface directly formed by the etchant. Therefore, the width of the edge area EGA in which the processing trace is formed may be smaller than the width of the first inclined surface ip1_1. The width of the edge area EGA means the length of the edge area EGA in the first direction (X-axis direction) or in the second direction (Y-axis direction). The width of the first inclined surface IP1_1 represents the length of the first inclined surface IP1_1 in the first direction (X-axis direction) or in the second direction (Y-axis direction).

The crack dam CRD may be a structure for preventing cracks from occurring in the process of cutting the substrate SUB during the manufacturing process of the display device 10. The crack dam CRD may be an outermost structure disposed at the outermost side of the right side of the display panel 100. The distance D1 between the crack dam CRD and the edge area EGA may be about 30 μm or less. In one or more embodiments, the distance D1 between the crack dam CRD and the edge region EGA may be 0 μm.

The minimum distance from the crack dam CRD to the edge EG of the display panel 100 may be a sum of the width of the edge area EGA and the minimum distance D1 from the crack dam CRD to the edge area EGA. For example, the minimum distance D1 from the crack dam CRD as the outermost structure to the edge region EGA may be about 30 μm or less.

At this time, when the substrate SUB is cut by spraying an etchant after laser irradiation, the minimum distance between the crack dam CRD and the edge EG of the display panel 100 may vary according to one-side tolerance of the laser. In this case, the minimum distance from the crack dam CRD, which is the outermost structure, to the edge EG of the display panel 100 may be the sum of the width of the edge area EGA, the minimum distance D1 from the crack dam CRD to the edge area EGA, and one-side tolerance of the laser. For example, when the one-side tolerance of the laser is 50 μm, the minimum distance D1 from the crack dam CRD as the outermost structure to the edge region EGA may be about 80 μm or less. In addition, when the laser side tolerance is 50 μm, the minimum distance from the crack dam CRD as the outermost structure to the edge EG of the display panel 100 may be about 130 μm or less. A description will be given later of the distance between the crack dam CRD and the edge area EGA due to one-side tolerance of the laser light with reference to fig. 64.

The minimum distance from the display pad PD to the edge EG of the display panel 100 may be a sum of the width of the edge area EGA and the minimum distance D2 from the display pad PD to the edge area EGA. For example, the minimum distance from the display pad PD, which is the outermost structure, to the edge EG of the display panel 100 may be about 80 μm or less.

When the substrate SUB is cut by spraying an etchant after laser irradiation, the minimum distance from the display pad PD to the edge EG of the display panel 100 may vary according to a tolerance of one side of the laser. The minimum distance from the display pad PD, which is the outermost structure, to the edge EG of the display panel 100 may be the sum of the width of the edge area EGA, the minimum distance D2 from the display pad PD to the edge area EGA, and one-side tolerance of the laser. For example, when the one-side tolerance of the laser is 50 μm, the minimum distance from the display pad PD to the edge EG of the display panel 100 may be about 130 μm or less.

In addition, when the substrate SUB of the display panel 100 is cut by irradiating laser light and then spraying an etchant during the manufacturing process of the display panel 100, the side surface ss_1 and the first inclined surface IP1_1 of the display panel 100 may be etched by the etchant. In this case, as shown in fig. 23, the roughness of the side surface ss_1 and the first inclined surface ip1_1 of the display panel 100 may be about 0.5 μm or less.

When the substrate SUB of the display panel 100 is cut by spraying an etchant after the laser light is irradiated, the roughness of the side surface ss_1 and the first inclined surface IP1_1 of the display panel 100 may be smaller than the roughness of the side surface SS, the first inclined surface IP1 and the second inclined surface IP2 of the display panel 100 when the polishing process is performed after the substrate SUB is cut with the cutting member.

In addition, the side surface ss_1 of the display panel 100 is formed of a laser and an etchant, and the first inclined surface ip1_1 is formed of an etchant. Accordingly, the roughness of the side surface ss_1 of the display panel 100 may be different from that of the first inclined surface ip1_1. For example, the difference between the roughness of the side surface ss_1 of the display panel 100 and the roughness of the first inclined surface ip1_1 may be approximately 1% to 20%.

The first power line VSL may be a first external structure disposed in the first non-display area NDA 1. The first external structure may be disposed farther from the edge EG of the display panel 100 than the outermost structure. That is, the distance from the first power line VSL, which is the first external structure, to the edge EG of the display panel 100 may be greater than the distance from the crack dam CRD, which is the outermost structure, to the edge EG of the display panel 100.

The distance from the first power line VSL to the crack dam CRD at the right side of the display panel 100 may be smaller than the distance from the first power line VSL to the crack dam CRD at the upper side of the display panel 100. Accordingly, a distance from the first power line VSL to the edge EG of the display panel 100 at the right side of the display panel 100 may be smaller than a distance from the first power line VSL to the edge EG of the display panel 100 at the upper side of the display panel 100. For example, a distance from the first power line VSL to the edge EG of the display panel 100 at the right side of the display panel 100 may be about 160 μm or less. Further, a distance from the first power line VSL to the edge EG of the display panel 100 at the upper side of the display panel 100 may be about 445 μm or less.

The second DAM2 may be a second external structure disposed in the first non-display area NDA 1. The second external structure may be disposed farther from the edge EG of the display panel 100 than the first external structure. That is, the distance from the second DAM2 as the second external structure to the edge EG of the display panel 100 may be greater than the distance from the first power line VSL as the first external structure to the edge EG of the display panel 100.

The distance from the second DAM2 to the crack DAM CRD at the right side of the display panel 100 may be smaller than the distance from the second DAM2 to the crack DAM CRD at the upper side of the display panel 100. Accordingly, a distance from the second DAM2 to the edge EG of the display panel 100 at the right side of the display panel 100 may be smaller than a distance from the second DAM2 to the edge EG of the display panel 100 at the upper side of the display panel 100. For example, a distance from the second DAM2 to the edge EG of the display panel 100 at the right side of the display panel 100 may be about 220 μm or less. Further, a distance from the second DAM2 to the edge EG of the display panel 100 at the upper side of the display panel 100 may be about 445 μm or less.

As described above, the minimum distance from the crack dam CRD to the edge EG of the display panel 100 when the substrate SUB of the display panel 100 is cut by spraying the etchant after the laser is irradiated may be at least about 170 μm smaller than the minimum distance from the crack dam CRD to the edge EG of the display panel 100 when the polishing process is performed after the substrate SUB is cut with the cutting member. Therefore, when the substrate SUB of the display panel 100 is cut by spraying the etchant after the laser is irradiated, the width of the second non-display area NDA2 may be greatly reduced as compared with the case where the polishing process is performed after the substrate SUB is cut by the cutting member. That is, the width of the non-display area NDA may be reduced or minimized.

In fig. 19 to 21, the crack dam CRD is provided as an example of an outermost structure at the left, upper and right sides of the display panel 100, and the display pad PD is provided as an example of an outermost structure at the bottom side of the display panel 100, but the embodiment of the present disclosure is not limited thereto. The outermost structure is a structure disposed closest to the edge EG of the display panel 100, and may be a structure for driving the display panel 100 or a structure for improving the function of the display panel 100. When the crack dam CRD is omitted or deleted, the outermost structure may be a power line (e.g., a first power line VSL) for driving the display panel 100. Alternatively, when the crack dam CRD is omitted or deleted, the outermost structure may be a signal line. The signal line may be a signal line for driving the scan driving circuit unit SDC. Alternatively, the outermost structure may be a line or an organic layer structure (e.g., a first DAM1 and a second DAM 2) for improving the function of the display panel 100.

In addition, the outermost structure may not be a structure disposed at or near the edge EG of the display panel 100, but may be a structure disposed to be spaced apart (or spaced apart) from the edge EG of the display panel 100. Further, the outermost structure may be a structure that does not overlap with the processing trace of the display panel 100. That is, the structure overlapped with the processing trace of the display panel 100 or provided at the edge EG of the display panel 100 corresponds to a structure for improving the manufacturing process of the display panel 100 but not removed to remain in the display panel 100, not to a structure for driving the display panel 100 or a structure for improving the function of the display panel 100. Therefore, the heat dissipation layer IRL and the plurality of electrostatic protection lines ESL1 and ESL2, which will be described later, are not the outermost structures defined in the present disclosure.

Fig. 24 is an enlarged cross-sectional view showing an example of the region E of fig. 19 in more detail.

Referring to fig. 24, the crack dam CRD may include the same material as the first organic layer 160, and may be disposed at the same layer (or at the same layer) as the first organic layer 160. In fig. 24, the crack dam CRD is shown as being disposed on the first buffer layer BF 1. In one or more embodiments, the crack dam CRD may be disposed on the second interlayer insulating layer 142 or any other suitable layer. The crack dam CRD may be formed of an organic film such as an acryl resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

Fig. 24 illustrates that the crack dam CRD includes one organic layer, but embodiments of the present disclosure are not limited thereto. For example, the crack dam CRD may further include another organic layer including the same material as the second organic layer 180. Alternatively, the crack dam CRD may further include another organic layer including the same material as the bank 190. Alternatively, the crack dam CRD may further include another organic layer including the same material as the spacer 191.

The first power line VSL may include the same material as the first data metal layer including the first connection electrode CE1 and the data line DL, and may be disposed at the same layer (or at the same layer) as the first data metal layer. The first power line VSL may be disposed on the second interlayer insulating layer 142. The first power line VSL may be formed of a single layer or multiple layers made of any one or more selected from among molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

The first DAM1 and the second DAM2 may be disposed on the first power line VSL. The first DAM1 may include a first sub-DAM SDAM1 and a second sub-DAM SDAM2, and the second DAM2 may include a first sub-DAM SDAM1, a second sub-DAM SDAM2, and a third sub-DAM SDAM3. The first sub-dam SDAM1 may include the same material as the first organic layer 160, and may be disposed at the same layer (or at the same layer) as the first organic layer 160. The second sub-dam SDAM2 may include the same material as the second organic layer 180, and may be disposed at the same layer (or at the same layer) as the second organic layer 180. The third sub-dam SDAM3 may include the same material as the bank 190, and may be disposed at the same layer (or at the same layer) as the bank 190.

The height of the first DAM1 may be lower than the height of the second DAM2, but the embodiment of the present disclosure is not limited thereto. The height of the first DAM1 may be substantially the same as the height of the second DAM2, or may be higher than the height of the second DAM 2.

The common electrode 173 may be connected to the first organic layer 160, the second organic layer 180, and the first power line VSL exposed without being covered by the first DAM 1. Accordingly, the common electrode 173 may receive the first power supply voltage VSS of the first power supply line VSL.

In one or more embodiments, the first encapsulation inorganic layer TFE1 may cover the first DAM1, the second DAM2, and the crack DAM CRD in the non-display area NDA of the right side of the display panel 100. The first encapsulation inorganic layer TFE1 may extend to an edge EG of the display panel 100 in a non-display area NDA on the right side of the display panel 100.

The encapsulation organic layer TFE2 may be disposed to cover the upper surface of the first DAM1 without covering the upper surface of the second DAM 2. However, embodiments of the present disclosure are not limited thereto. The encapsulation organic layer TFE2 may not cover both the upper surface of the first DAM1 and the upper surface of the second DAM 2. The encapsulation organic layer TFE2 may not overflow to the edge EG of the display panel 100 due to the first DAM1 and the second DAM 2.

The second encapsulation inorganic layer TFE3 may cover the first DAM1, the second DAM2, and the crack DAM CRD in the non-display area NDA on the right side of the display panel 100. The second encapsulation inorganic layer TFE3 may extend to an edge EG of the display panel 100 in a non-display area NDA on the right side of the display panel 100.

An inorganic encapsulation region in which the first encapsulation inorganic layer TFE1 and the second encapsulation inorganic layer TFE3 contact each other may be formed from the second DAM2 to the edge EG of the display panel 100. The inorganic encapsulation region may be disposed to surround the second DAM2.

In addition, fig. 24 shows a scanning thin film transistor STFT of the scanning driving circuit unit SDC as an example. Since the scanning thin film transistor STFT is substantially the same as the thin film transistor TFT described with reference to fig. 7, a description of the scanning thin film transistor STFT will be omitted.

Fig. 25 is an enlarged cross-sectional view showing an example of the region F of fig. 20 in more detail.

Referring to fig. 25, each of the display pad PD (e.g., see fig. 20), the first driving pad DPD1, and the second driving pad DPD2 may include a first sub-pad SPD1, a second sub-pad SPD2, and a third sub-pad SPD3.

The first sub-pad SPD1 may include the same material as the first gate metal layer including the gate electrode TG, the first capacitor electrode CAE1 of the capacitor Cst, and the scan line SL, and may be disposed at the same layer (or at the same layer) as the first gate metal layer. The first sub-pad SPD1 may be disposed on the gate insulating layer 130. The first sub-pad SPD1 may be formed of a single layer or a plurality of layers made of any one or more selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

The second sub-pad SPD2 may include the same material as the second gate metal layer including the second capacitor electrode CAE2, and may be disposed at the same layer (or at the same layer) as the second gate metal layer. The second sub-pad SPD2 may be disposed on the first interlayer insulating layer 141. The second sub-pad SPD2 may be formed of a single layer or a plurality of layers made of any one or more selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

The third sub-pad SPD3 may include the same material as the first data metal layer including the first connection electrode CE1 and the data line DL, and may be disposed at the same layer (or at the same layer) as the first data metal layer. The third sub-pad SPD3 may be disposed on the second interlayer insulating layer 142. The third sub-pad SPD3 may be formed of a single layer or a plurality of layers made of any one or more selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

The third sub-pad SPD3 of the display pad PD may be electrically connected to the lead line LEAL of the circuit board 300 by a conductive adhesive member CAD such as an anisotropic conductive film or an anisotropic conductive adhesive. The third sub-pad SPD3 of the first driving pad DPD1 may be electrically connected to the input bump IBP of the driving IC 200 through a conductive adhesive member CAD such as an anisotropic conductive film or an anisotropic conductive adhesive. The third sub-pad SPD3 of the second driving pad DPD2 may be electrically connected to the output bump OBP of the driving IC 200 through a conductive adhesive member CAD such as an anisotropic conductive film or an anisotropic conductive adhesive.

The first and second encapsulation inorganic layers TFE1 and TFE3 may be disposed to cover the first DAM1 and partially cover the second DAM2. For example, the first and second encapsulation inorganic layers TFE1 and TFE3 may be disposed so as not to cover a portion of the upper surface of the second DAM2. Alternatively, the first and second encapsulation inorganic layers TFE1 and TFE3 may entirely cover the second DAM2, but in this case, the third sub-pad SPD3 of the second drive pad DPD2 may not be covered. That is, the first and second encapsulation inorganic layers TFE1 and TFE3 may not extend to the display pad PD, the first and second driving pads DPD1 and DPD2 adjacent to the edge EG of the display panel 100.

Fig. 26 is an enlarged cross-sectional view showing an example of the region G of fig. 21 in more detail.

Referring to fig. 26, the first and second encapsulation inorganic layers TFE1 and TFE3 may be disposed so as not to cover the crack dam CRD in the non-display area NDA of the upper side of the display panel 100. That is, in the non-display area NDA of the upper side of the display panel 100, the first and second encapsulation inorganic layers TFE1 and TFE3 may not extend to the edge EG of the display panel 100.

In addition, in one or more embodiments, the first and second encapsulation inorganic layers TFE1 and TFE3 may be disposed not to cover the crack dam CRD in the non-display area NDA of the upper side of the display panel 100 and the non-display areas NDA of the left and right sides of the display panel 100. That is, in the non-display area NDA of the upper side of the display panel 100 and the non-display areas NDA of the left and right sides of the display panel 100, the first and second encapsulation inorganic layers TFE1 and TFE3 may not extend to the edge EG of the display panel 100.

Fig. 27 is a graph illustrating torsion test results of a display panel in accordance with one or more embodiments.

Fig. 27 shows the torsion angle obtained after the torsion test in the following cases: the polishing process is not performed after the substrate SUB of the display panel 100 is cut with the cutting member (case 1), the polishing process is performed after the substrate SUB of the display panel 100 is cut with the cutting member (case 2), the polishing process is not performed after the substrate SUB of the display panel 100 is cut with the laser (case 3), the substrate SUB of the display panel 100 is cut with the laser and then the polishing process is performed (case 4), and the substrate SUB of the display panel 100 is cut by spraying an etchant after the laser is irradiated (case 5). The twist angle refers to an angle generated when the display panel 100 is twisted after fixing any one side, any one corner, or any one corner of the display panel 100, and may be measured by a known method.

Referring to fig. 27, according to the result of the torsion experiment of the display panel 100, when the substrate SUB of the display panel 100 is cut by irradiating laser and then spraying an etchant (case 5), deformation of the display panel 100 may be desired. Because the measured torsion angle is higher than the other cases (case 1, case 2, case 3, case 4).

Fig. 28 is a graph illustrating 4PB test results of a display panel in accordance with one or more embodiments.

Fig. 28 shows stress intensity (unit: MPa) in the following cases: the polishing process is performed after cutting the substrate SUB of the display panel 100 with the cutting wheel (case 2), the polishing process is performed after cutting the substrate SUB of the display panel 100 with the laser (case 3), and the substrate SUB of the display panel 100 is cut by irradiating the laser and then spraying the etchant (case 1).

Referring to fig. 28, the 4PB test result may be measured by applying stress to the bottom surface BS of the display panel 100 using four support members SAM in a state in which the upper surface US of the display panel 100 faces upward (faces upward) and a state in which the upper surface US of the display panel 100 faces downward (faces downward). For example, when two support members SAM provided on the display panel 100 press the display panel 100, stress of the display panel 100 is measured in a state where the display panel 100 is supported by the two support members SAM provided under the display panel 100. As a result of the 4PB experiment, since the measured stress-bearing strength is high compared to other cases (case 2, case 3) when the substrate SUB of the display panel 100 is cut by irradiating laser and then spraying etchant in both the state where the upper surface US of the display panel 100 faces upward (faces upward) and the state where the upper surface US of the display panel 100 faces downward (faces downward), it may be desirable when considering the stress of the display panel 100.

Fig. 29 is a layout diagram illustrating cut areas of a display panel in accordance with one or more embodiments. Table 1 shows distances between display regions and edges of display panels in accordance with one or more embodiments.

Fig. 29 shows a first edge EG1, a second edge EG2, and a display area DA, the first edge EG1 corresponding to an edge of the display panel 100 when the polishing process is performed after the substrate SUB is cut with the cutting member, and the second edge EG2 corresponding to the edge EG2 of the display panel 100 when the substrate SUB is cut by spraying an etchant after the laser is irradiated. Fig. 29 shows distances LD1, RD1, and UD1 between the display area DA and the first edge EG1 and distances LD2, RD2, and UD2 between the display area DA and the second edge EG2 on the left, right, and upper sides of the display panel 100 when the size of the display panel 100 is 15.6 inches. Further, fig. 29 shows a distance BD1 between the display pad PD and the first edge EG1 and a distance BD2 between the display pad PD and the second edge EG2 on the lower side of the display panel 100 when the size of the display panel 100 is 15.6 inches.

TABLE 1

	Upper side of	Left side	Right side
				Case 1	1.6mm	2.36mm	2.36mm
Case 2	1.48mm	2.24mm	2.24mm

Referring to fig. 29 and table 1, a distance LD1 (case 1, left) between the left display area DA and the first edge EG1 of the display panel 100 and a distance RD1 (case 1, right) between the right display area DA and the first edge EG1 of the display panel 100 may be approximately 2.36mm. The distance LD2 (case 2, left) between the left display area DA and the second edge EG2 of the display panel 100 and the distance RD2 (case 2, right) between the right display area DA and the second edge EG2 of the display panel 100 may be approximately 2.24mm. That is, at each of the left and right sides of the display panel 100, distances LD2 and RD2 between the display area DA and the second edge EG2 may be smaller than distances LD1 and RD1 between the display area DA and the first edge EG 1.

In addition, on the upper side of the display panel 100, a distance UD1 (case 1, upper side) between the display area DA and the first edge EG1 may be approximately 1.6mm. On the upper side of the display panel 100, a distance UD2 (case 2, upper side) between the display area DA and the second edge EG2 may be about 1.48mm. That is, on the upper side of the display panel 100, a distance UD2 between the display area DA and the second edge EG2 may be smaller than a distance UD1 between the display area DA and the first edge EG 1.

In addition, at the bottom side of the display panel 100, the distance BD1 between the display pad PD and the first edge EG1 may be approximately 270 μm. At the bottom side of the display panel 100, a distance BD2 between the display pad PD and the second edge EG2 may be approximately 100 μm. That is, at the bottom side of the display panel 100, the distance BD2 between the display pad PD and the second edge EG2 may be smaller than the distance BD1 between the display pad PD and the first edge EG 1.

As described above, when the substrate SUB of the display panel 100 is cut by spraying the etchant after the laser light is irradiated, the distance between the display area DA and the edge EG2 of the display panel 100 may be smaller than the distance between the display area DA and the edge EG1 of the display panel 100 when the polishing process is performed after the substrate SUB is cut with the cutting member. That is, when the substrate SUB of the display panel 100 is cut by spraying an etchant after irradiating laser light, the width of the non-display area NDA may be significantly reduced as compared with a case in which a polishing process is performed after cutting the substrate SUB with a cutting member.

Table 2 shows distances between display areas and edges of display panels in accordance with one or more embodiments.

TABLE 2

	Upper side of	Left side	Right side
				Case 1	1.6mm	1.95mm	1.95mm
Case 2	1.48mm	1.8mm	1.8mm

Table 2 shows distances LD1 (case 1, left side), RD1 (case 1, right side) and UD1 (case 1, upper side) between the left, right and upper display areas DA and the first edge EG1 of the display panel 100 and distances LD2 (case 2, left side), RD2 (case 2, right side) and UD2 (case 2, upper side) between the display areas DA and the second edge EG2 when the size of the display panel 100 is 16 inches.

Referring to fig. 29 and table 2, a distance LD1 (case 1, left) between the left display area DA and the first edge EG1 of the display panel 100 and a distance RD1 (case 1, right) between the right display area DA and the first edge EG1 of the display panel 100 may be approximately 1.95mm. The distance LD2 (case 2, left) between the left display area DA and the second edge EG2 of the display panel 100 and the distance RD2 (case 2, right) between the right display area DA and the second edge EG2 of the display panel 100 may be approximately 1.8mm. That is, at each of the left and right sides of the display panel 100, distances LD2 and RD2 between the display area DA and the second edge EG2 may be smaller than distances LD1 and RD1 between the display area DA and the first edge EG 1.

In addition, on the upper side of the display panel 100, a distance UD1 (case 1, upper side) between the display area DA and the first edge EG1 may be about 1.6mm. On the upper side of the display panel 100, a distance UD2 (case 2, upper side) between the display area DA and the second edge EG2 may be about 1.48mm. That is, on the upper side of the display panel 100, a distance UD2 between the display area DA and the second edge EG2 may be smaller than a distance UD1 between the display area DA and the first edge EG 1.

As described above, when the substrate SUB of the display panel 100 is cut by spraying the etchant after the laser light is irradiated (case 1), the distance between the display area DA and the edge EG2 of the display panel 100 may be smaller than the distance between the display area DA and the edge EG1 of the display panel 100 when the polishing process is performed after the substrate SUB is cut with the cutting member (case 2). That is, when the substrate SUB of the display panel 100 is cut by spraying an etchant after the laser is irradiated, the width of the non-display area NDA may be significantly reduced as compared with a case in which a polishing process is performed after the substrate SUB is cut with a cutting member.

Fig. 30 is a cross-sectional view illustrating an example of a display panel taken along line II-II' of fig. 11.

Referring to fig. 30, the edge region EGA may include a first sub-edge region SEGA1 and a second sub-edge region SEGA2.

The first SUB-edge area SEGA1 may be an area in which a processing trace is formed on the substrate SUB by a polishing process performed after irradiating laser light and then spraying an etchant on the substrate SUB. The width of the first sub-edge area SEGA1 may be within about 30 μm.

The second SUB-edge area SEGA2 may be an area in which a processing trace such as debris (as shown in fig. 17) is formed on the upper surface US of the substrate SUB by a polishing process. The width of the second sub-edge area SEGA2 may be within about 50 μm.

The first sub-edge area SEGA1 may include a first inclined surface ip1_2 formed by spraying an etchant after irradiating laser light and a second inclined surface ip2_2 formed by a polishing process. The first inclined surface ip1_2 and the second inclined surface ip2_2 may overlap each other in a third direction (Z-axis direction).

The roughness of the side surface ss_2 and the roughness of the first inclined surface ip1_2 may be different from those of the second inclined surface ip2_2 because the side surface ss_2 and the first inclined surface ip1_2 are formed by an etchant after laser irradiation and the second inclined surface ip2_2 is formed by a polishing process. As shown in fig. 23, the roughness of the side surface ss_2 and the roughness of the first inclined surface ip1_2 may be 0.5 μm or less, and as shown in fig. 18, the roughness of the second inclined surface ip2_2 may be about 1 μm.

The angle θ6 between the side surface ss_2 and the first inclined surface ip1_2 and the angle θ7 between the first inclined surface ip1_2 and the bottom surface BS may be obtuse angles. The angle θ8 between the side surface ss_2 and the second inclined surface ip2_2 and the angle θ9 between the second inclined surface ip2_2 and the upper surface US may be obtuse angles. The angle θ6 between the side surface ss_2 and the first inclined surface ip1_2 may be greater than the angle θ8 between the side surface ss_2 and the second inclined surface ip2_2. Further, an angle θ9 between the second inclined surface ip2_2 and the upper surface US may be greater than an angle θ7 between the first inclined surface ip1_2 and the bottom surface BS.

In addition, the length of the first inclined surface IP1_2 in the inclined direction may be longer than the length of the second inclined surface IP2_2 in the inclined direction. The length of the first inclined surface IP1_2 in the inclined direction may be defined as a minimum distance from an edge of the first inclined surface IP1_2 contacting the side surface SS _2 to an edge of the first inclined surface IP1_2 contacting the bottom surface BS. Further, the length of the second inclined surface IP2_2 in the inclined direction may be defined as a minimum distance from an edge of the second inclined surface IP2_2 contacting the side surface ss_2 to an edge of the second inclined surface IP2_2 contacting the upper surface US.

In addition, the thickness of the first inclined surface ip1_2 may be greater than the thickness of the second inclined surface ip2_2. The thickness of the first inclined surface IP1_2 may be defined as a maximum length of the first inclined surface IP1_2 in the third direction (Z-axis direction), and the thickness of the second inclined surface IP2_2 may be defined as a maximum length of the second inclined surface IP2_2 in the third direction (Z-axis direction).

Fig. 31 is a cross-sectional view showing an example of the display panel taken along the line II-II' of fig. 11. Fig. 32 is an exemplary view showing a laser irradiation area formed by laser to form the circular side surface of fig. 31.

Referring to fig. 31, a side surface ss1_1 of the substrate SUB may have a circular cross section. The side surface ss1_1 of the substrate SUB may be provided to have a curvature.

Referring to fig. 32, when the substrate SUB is cut by irradiating laser and then spraying an etchant so that the side surface ss1_1 of the substrate SUB has a circular cross section, the laser irradiation position and the irradiation depth may be adjusted. In this case, a plurality of laser irradiation regions CH may be formed according to the laser irradiation position and irradiation depth. The interval in the first direction (X-axis direction) or the interval in the second direction (Y-axis direction) of the laser irradiation regions CH adjacent to each other among the plurality of laser irradiation regions CH may be approximately 0.1 μm to 10 μm. The depth of the plurality of laser irradiation regions CH may be 30 μm or less.

Fig. 33 is a cross-sectional view showing an example of the display panel taken along the line II-II' of fig. 11.

Referring to fig. 33, the display panel 100 according to one or more embodiments may include a heat dissipation layer IRL disposed in the edge region EGA. The heat dissipation layer IRL may include a metal material having high thermal conductivity to dissipate heat generated when a laser-irradiated region is formed with a laser in a dicing process. In addition, the heat radiation layer IRL may include a material having a high infrared absorption rate to reduce or minimize an influence of the laser light on the display panel 100 in the cutting process by increasing the infrared absorption rate. For example, the heat radiation layer IRL may be formed of a single layer or of multiple layers made of any one or more selected from among molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

The length of the heat radiation layer IRL in the first direction (X-axis direction) may be longer than the length of the edge region EGA in the first direction (X-axis direction). For example, the length of the heat radiation layer IRL in the X-axis direction may be 50 μm or more and 300 μm or less.

As shown in fig. 33, the heat dissipation layer IRL may not contact the crack dam CRD. For example, the length of the heat dissipation layer IRL in the first direction (X-axis direction) may be smaller than the distance between the crack dam CRD and the edge EG of the display panel 100. However, embodiments of the present disclosure are not limited thereto. The heat dissipation layer IRL may entirely cover the crack dam CRD or cover at least a portion of the crack dam CRD. For example, the length of the heat dissipation layer IRL in the first direction (X-axis direction) may be greater than the distance between the crack dam CRD and the edge EG of the display panel 100.

Fig. 34 is a cross-sectional view showing an example of the region H of fig. 33 in more detail.

Referring to fig. 34, the heat dissipation layer IRL may include the same material as the crack dam CRD and the first organic layer 160, and may be disposed at the same layer (or at the same layer) as the crack dam CRD and/or the first organic layer 160. In one or more embodiments, the heat dissipation layer IRL may be disposed on the first buffer layer BF 1. In one or more other embodiments, a heat dissipation layer IRL may be disposed on the second interlayer insulating layer 142. The heat dissipation layer IRL may be formed of an organic film such as an acryl resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

Since the heat dissipation layer IRL and the crack dam CRD are formed of the same organic material, the cross-sectional shape of the heat dissipation layer IRL and the cross-sectional shape of the crack dam CRD may be substantially the same. For example, the heat dissipation layer IRL and the crack dam CRD may have a trapezoidal cross section.

Fig. 35 is a cross-sectional view showing an example of the region H of fig. 33 in more detail.

Referring to fig. 35, the heat dissipation layer IRL may include a first heat dissipation layer IRL1 and a second heat dissipation layer IRL2.

The first heat dissipation layer IRL1 may be disposed on the second interlayer insulating layer 142. The first heat dissipation layer IRL1 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

The first heat dissipation layer IRL1 may include a material different from that of the crack dam CRD. Therefore, although both the first heat dissipation layer IRL1 and the crack dam CRD are formed of an organic layer, the cross-sectional shape of the first heat dissipation layer IRL1 may be different from the cross-sectional shape of the crack dam CRD. For example, the crack dam CRD may have a trapezoidal cross section, but the first heat radiation layer IRL1 may have a fan-shaped cross section.

The second heat dissipation layer IRL2 may include the same material as the first data metal layer including the first connection electrode CE1 and the data line DL, and may be disposed at the same layer (or at the same layer) as the first data metal layer. The second heat dissipation layer IRL2 may be disposed on the second interlayer insulating layer 142. The second heat radiation layer IRL2 may be formed of a single layer or a plurality of layers made of any one or more selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

Since the second heat radiation layer IRL2 covers the first heat radiation layer IRL1, the length of the second heat radiation layer IRL2 in the first direction (X-axis direction) may be longer than the length of the first heat radiation layer IRL1 in the first direction (X-axis direction).

The first heat radiation layer IRL1 and the second heat radiation layer IRL2 may overlap with the processing trace provided on the upper surface of the substrate SUB in the edge area EGA.

Fig. 36 is a cross-sectional view showing an example of the region H of fig. 33 in more detail.

Referring to fig. 36, the heat dissipation layer IRL may include a plurality of first heat dissipation layers IRL1 and second heat dissipation layers IRL2.

The plurality of first heat dissipation layers IRL1 may be disposed to be spaced apart from each other in the first direction (X-axis direction). A width of each of the plurality of first heat dissipation layers IRL1 in the first direction (X-axis direction) may be smaller than a width of the crack dam CRD in the first direction (X-axis direction).

The plurality of first heat dissipation layers IRL1 may include the same material as the crack dam CRD and the first organic layer 160, and may be disposed at the same layer (or at the same layer) as the crack dam CRD and/or the first organic layer 160. In one or more embodiments, a plurality of first heat dissipation layers IRL1 may be disposed on the first buffer layer BF 1. In one or more other embodiments, a plurality of first heat dissipation layers IRL1 may be disposed on the second interlayer insulating layer 142. The plurality of first heat dissipation layers IRL1 may be formed of an organic film such as acryl resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

Since the plurality of first heat dissipation layers IRL1 and the crack dam CRD are formed of the same organic material, the cross-sectional shape of each of the plurality of first heat dissipation layers IRL1 and the cross-sectional shape of the crack dam CRD may be substantially the same. For example, the plurality of first heat dissipation layers IRL1 and the crack dams CRD may have a trapezoidal cross section.

However, a portion of the first heat dissipation layer IRL1 closest to the edge EG of the display panel 100 may be cut by a laser process in the cutting process of the substrate SUB. Accordingly, the first heat dissipation layer IRL1 closest to the edge EG of the display panel 100 may have a cross section in which a portion of the trapezoid is cut away.

The second heat dissipation layer IRL2 may cover a plurality of first heat dissipation layers IRL1. Therefore, the length of the second heat dissipation layer IRL2 in the first direction (X-axis direction) may be longer than the lengths of the plurality of first heat dissipation layers IRL1 in the first direction (X-axis direction). The second heat dissipation layer IRL2 may also be disposed on an upper surface of the first buffer layer BF1 exposed between the plurality of first heat dissipation layers IRL1. The area of the second heat radiation layer IRL2 may be increased due to the plurality of first heat radiation layers IRL1, and thus the heat radiation effect may be increased.

Fig. 37 is a cross-sectional view showing an example of the display panel taken along the line II-II' of fig. 11.

Referring to fig. 37, the heat dissipation layer irl_1 may be disposed to be spaced apart (or spaced apart) from the edge EG of the display panel 100 in the first direction (X-axis direction). That is, the heat radiation layer irl_1 may be provided while avoiding a region where laser light is directly irradiated. For this, the heat dissipation layer IRL may be disposed to be spaced apart (or spaced apart) from the edge EG of the display panel 100 by approximately 1 μm to 50 μm.

The heat radiation layer irl_1 shown in fig. 37 may be implemented in substantially the same manner as described with reference to fig. 33 to 36, and thus an enlarged cross-sectional view of the region I of fig. 37 will be omitted.

Fig. 38A and 38B are layout diagrams illustrating display pads and electrostatic protection lines in accordance with one or more embodiments.

Referring to fig. 38A and 38B, the electrostatic protection line ESL may be disposed from one side of the display pad PD to an edge EG of the display panel 100.

The electrostatic protection line ESL may be connected to the display pad PD. The plurality of electrostatic protection lines ESL may be connected to the plurality of display pads PD one-to-one.

Referring to fig. 38A, the electrostatic protection line ESL may include a first main path region MP1, at least one first auxiliary path region AP1, at least one second auxiliary path region AP2, at least one third auxiliary path region AP3, and at least one fourth auxiliary path region AP4.

The first main path region MP1 may have a saw tooth shape or a serpentine shape. For example, the first main path region MP1 may have a shape in which a shape extending in the second direction (Y-axis direction), a shape extending in the first direction (X-axis direction), a shape extending in the second direction (Y-axis direction), and a shape extending in a direction opposite to the first direction (X-axis direction) are repeated.

The first auxiliary path area AP1 may be an area protruding from the first main path area MP1 in the first direction (X-axis direction). The second auxiliary path area AP2 may be an area protruding in the second direction (Y-axis direction) from an end of the first auxiliary path area AP 1.

The third auxiliary path area AP3 may be an area protruding from the first main path area MP1 in a direction opposite to the first direction (X-axis direction). The fourth auxiliary path region AP4 may be a region protruding in the second direction (Y-axis direction) from an end of the third auxiliary path region AP 3.

Referring to fig. 38B, the electrostatic protection line ESL includes a second main path region MP2, at least one fifth auxiliary path region AP5, at least one sixth auxiliary path region AP6, at least one seventh auxiliary path region AP7, and at least one eighth auxiliary path region AP8.

The second main path area MP2 may have a saw tooth shape or a serpentine shape. The planar shape of the second main path area MP2 may be substantially the same as the planar shape of the first main path area MP 1.

The fifth auxiliary path area AP5 may be an area protruding from the second main path area MP2 in the first direction (X-axis direction). The sixth auxiliary path area AP6 may be an area protruding from an end of the fifth auxiliary path area AP5 in a direction opposite to the second direction (Y-axis direction).

The seventh auxiliary path area AP7 may be an area protruding from the second main path area MP2 in a direction opposite to the first direction (X-axis direction). The eighth auxiliary path region AP8 may be a region protruding from an end of the seventh auxiliary path region AP7 in a direction opposite to the second direction (Y-axis direction).

When the electrostatic protection line ESL is disposed from one side of each of the plurality of display pads PD to the edge EG of the display panel 100, the electrostatic protection line ESL may be exposed to the outside at the edge EG of the display panel 100. Therefore, when the substrate SUB of the display panel 100 is cut by spraying the etchant after the laser is irradiated, the etchant may penetrate into the display pad PD through the electrostatic protection line ESL.

As shown in fig. 38A and 38B, the plurality of electrostatic protection lines ESL may include a plurality of auxiliary path regions AP1, AP2, AP3, AP4, AP5, AP6, AP7, and AP8 protruding from the main path regions MP1/MP2 and for dispersing an etchant permeated through the main path regions MP1/MP2, in addition to the main path regions MP1/MP2 extending from one side of the plurality of display pads PD to the edge EG of the display panel 100. Accordingly, the etchant can be prevented from penetrating into the plurality of display pads PD through the plurality of electrostatic protection lines ESL1 and ESL 2.

Fig. 39 is a cross-sectional view showing an example of the display panel taken along the line V-V' of fig. 38B.

Referring to fig. 39, the electrostatic protection line ESL includes the same material as an active layer of the thin film transistor TFT including the channel region TCH, the source region TS, and the drain region TD, and may be disposed at the same layer (or at the same layer) as the active layer. For example, the electrostatic protection line ESL may be disposed on the first buffer layer BF 1. The electrostatic protection line ESL may be formed of polysilicon, monocrystalline silicon, low temperature polysilicon, amorphous silicon, or an oxide semiconductor material.

Fig. 40A and 40B are layout diagrams illustrating display pads and electrostatic protection lines in accordance with one or more embodiments.

Referring to fig. 40A, the electrostatic protection line esl1_1 (shown as ESL) includes a first main path region mp1_1, at least one first auxiliary path region ap1_1, and at least one second auxiliary path region ap2_1.

The first main path region mp1_1 may have a saw tooth shape or a serpentine shape. The first auxiliary path area AP1_1 may be an area protruding from the first main path area mp1_1 in the first direction (X-axis direction). The second auxiliary path area AP2_1 may be an area protruding from the first main path area mp1_1 in a direction opposite to the first direction (X-axis direction).

Referring to fig. 40B, the electrostatic protection line esl2_1 (shown as ESL) includes a second main path region mp2_1, at least one third auxiliary path region ap3_1, at least one fourth auxiliary path region ap4_1, at least one fifth auxiliary path region ap5_1, and at least one sixth auxiliary path region ap6_1.

The second main path region mp2_1 may have a saw tooth shape or a serpentine shape. The planar shape of the second main path region mp2_1 may be substantially the same as the planar shape of the first main path region mp1_1.

The third auxiliary path region ap3_1 may be a region protruding from the second main path region mp2_1 in the first direction (X-axis direction). The fourth auxiliary path area AP4_1 may extend in the second direction (Y-axis direction), and a center area of the fourth auxiliary path area AP4_1 may be connected to an end of the third auxiliary path area AP 3_1.

The fifth auxiliary path region AP5_1 may be a region protruding from the second main path region mp2_1 in a direction opposite to the first direction (X-axis direction). The sixth auxiliary path area a6_1 may extend in the second direction (Y-axis direction), and a center area of the sixth auxiliary path area a6_1 may be connected to an end of the fifth auxiliary path area a5_1.

Fig. 41A and 41B are layout diagrams illustrating display pads and electrostatic protection lines in accordance with one or more embodiments.

Referring to fig. 41A, the electrostatic protection line esl1_2 (shown as ES 1) includes a first main path region mp1_2, at least one first auxiliary path region ap1_2, and at least one second auxiliary path region ap2_2.

The first main path region mp1_2 may have a saw tooth shape or a serpentine shape. The first auxiliary path area AP1_2 may be an area protruding from the first main path area mp1_2 in the first diagonal direction DD 1. The second auxiliary path region ap2_2 may be a region protruding from the first main path region mp1_2 in the second diagonal direction DD 2. The first diagonal direction DD1 indicates a diagonal direction between the first direction (X-axis direction) and the second direction (Y-axis direction). The second diagonal direction DD2 may be a direction perpendicular to the first diagonal direction DD 1.

Referring to fig. 41B, the electrostatic protection line esl2_2 (shown as ESL) includes a second main path region mp2_2, at least one third auxiliary path region ap3_2, at least one fourth auxiliary path region ap4_2, at least one fifth auxiliary path region ap5_2, and at least one sixth auxiliary path region ap6_2.

The second main path region mp2_2 may extend in the second direction (Y-axis direction). The planar shape of the second main path area mp2_2 may be substantially the same as the planar shape of the first main path area mp1_2.

The third auxiliary path region ap3_2 may be a region protruding from the second main path region mp2_2 in the first diagonal direction DD 1. The fourth auxiliary path area AP4_2 may extend in the second direction (Y-axis direction), and a center area of the fourth auxiliary path area AP4_2 may be connected to an end of the third auxiliary path area AP 3_2.

The fifth auxiliary path region AP5_2 may be a region protruding from the second main path region mp2_2 in the second diagonal direction DD 2. The sixth auxiliary path area a6_2 may extend in the second direction (Y-axis direction), and a center area of the sixth auxiliary path area a6_2 may be connected to an end of the fifth auxiliary path area a5_2.

Fig. 42A and 42B are layout diagrams illustrating display pads and electrostatic protection lines in accordance with one or more embodiments. Fig. 43 is a cross-sectional view showing an example of the display panel taken along line VI-VI' of fig. 42B.

Referring to fig. 42A, 42B, and 43, the display panel 100 according to one or more embodiments may include at least one third DAM3 extending in a first direction (X-axis direction).

At least one or more third DAM3 may be disposed on the first buffer layer BF 1. The at least one or more third DAM3 may include the same material as the first buffer layer BF 1. Alternatively, when the first buffer layer BF1 has a structure in which different inorganic layers are alternately stacked, at least one or more third DAM3 may include the same material as the uppermost layer of the first buffer layer BF 1. The at least one or more third DAM3 may be formed of an inorganic material such as one or more selected from among a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

The electrostatic protection line ESL may intersect at least one or more third DAMs DAM3. For example, the main path area MP1/MP2 of the electrostatic protection line ESL may intersect at least one or more third DAM3. The electrostatic protection line ESL may be disposed on the at least one third DAM3. Because the at least one third DAM3 serves as a threshold, the etchant penetrating through the electrostatic protection line ESL does not exceed the at least one third DAM3. Accordingly, it may be possible to prevent the etchant from penetrating into the display pad PD through the electrostatic protection line ESL.

Fig. 44 is a flowchart illustrating a method of manufacturing a display device in accordance with one or more embodiments. Fig. 45-49 are perspective views illustrating a method of manufacturing a display device according to one or more embodiments. Fig. 50 to 55 are cross-sectional views illustrating a method of manufacturing a display device according to one or more embodiments.

Fig. 45 to 49 are perspective views of the mother substrate MSUB and the plurality of display units DPC disposed on the mother substrate MSUB. Fig. 50 to 55 show cross-sections of the mother substrate MSUB (or the formed substrate SUB) and the plurality of display units DPC taken along the line VII-VII' in fig. 45 to 49.

First, as shown in fig. 45 and 50, a plurality of display units DPC are formed on a first surface of a mother substrate MSUB. (S110 in FIG. 44)

A display layer dis of each of the plurality of display units DPC is formed on a first surface of the mother substrate MSUB. The display layer dis includes a thin film transistor layer TFTL, a light emitting element layer EML, an encapsulation layer ENC, and a sensor electrode layer SENL.

Second, as shown in fig. 51, a plurality of first protective films PRF1 and second protective films PRF2 are attached on a plurality of display units DPC. (S120 in FIG. 44)

First, a first protective film layer is attached to cover the plurality of display units DPC and a mother substrate MSUB disposed between the plurality of display units DPC. Then, by removing a part of the first protective film layer provided on the mother substrate MSUB, a plurality of first protective films PRF1 may be provided on the plurality of display units DPC, respectively. That is, a portion of the first protective film layer may be removed, and the remaining portion may be a plurality of first protective films PRF1. Accordingly, a plurality of first protective films PRF1 may be disposed on the plurality of display units DPC, respectively. That is, the plurality of first protective films PRF1 may be disposed to correspond to the plurality of display units DPC on a one-to-one basis.

Each of the plurality of first protective films PRF1 may be a buffer film for protecting the plurality of display units DPC from external impact. The plurality of first protective films PRF1 may be made of a transparent material.

The second protective film PRF2 may be attached on the mother substrate MSUB exposed without being covered with the plurality of first protective films PRF 1. The second protective film PRF2 may be an acid-resistant film for protecting the plurality of display units DPC from an etchant in an etching process of the mother substrate MSUB to be performed in the next step.

Third, as shown in fig. 46 and 52, the thinning process for reducing the thickness of the mother substrate MSUB is performed by spraying the etchant ECH on the second surface of the mother substrate MSUB opposite to the first surface without a separate mask. Then, the second protective film PRF2 is peeled off. (S130 in FIG. 44)

The thickness of the mother substrate MSUB may be reduced by spraying the etchant ECH on the second surface of the mother substrate MSUB. For example, the thickness of the mother substrate MSUB may be reduced from the first thickness T1 to the second thickness T2. For example, the second thickness T2 may differ from the first thickness T1 by about 50 μm or more.

After the thickness of the mother substrate MSUB is reduced, the second protective film PRF2 may be peeled off.

Fourth, as shown in fig. 47 and 53, the mother substrate MSUB is cut along the edges of the plurality of display units DPC using a cutting member CWD such as a cutting wheel. (S140 in FIG. 44)

The cutting member CWD cuts the mother substrate MSUB along edges of the plurality of display units DPC. Accordingly, the plurality of display units DPC may be separated from the mother substrate MSUB.

The side tolerance SE1 of one side of the cutting member CWD may be about 100 μm or less. One side tolerance SE1 of the cutting member CWD may be a cutting error in one direction (e.g., X-axis direction) when cutting with the cutting member CWD.

The distance from the crack dam CRD to the edge EG of the display panel 100 may be affected by one side tolerance SE1 of the cutting member CWD. When the cutting member CWD is properly cut at a position where it should cut, a distance from the crack dam CRD to the cutting surface CSS is defined as "DCS".

When the cutting member CWD is cut from the left side with a maximum value of a side tolerance of one side of the cutting member CWD, the distance from the crack dam CRD to the cutting surface CSS may be "DCS-SE1". When the cutting member CWD is cut from the right side with a maximum value of a side tolerance of one side of the cutting member CWD, the distance from the crack dam CRD to the cutting surface CSS may be "dcs+se1".

Since the cutting surface CSS corresponds to the edge EG of the display panel 100 after the substrate SUB of the display unit DPC is separated from the mother substrate MSUB, the distance from the crack dam CRD to the cutting surface CSS may be substantially the same as the minimum distance from the crack dam CRD to the edge EG of the display panel 100 in the display panel 100 shown in fig. 14. Accordingly, the minimum distance from the crack dam CRD in the display panel 100 to the edge EG of the display panel 100 may differ by 200 μm, which in some cases is a distance corresponding to "one-sided tolerance x 2" (or "double-sided tolerance") of the cutting member CWD.

That is, in the display panel 100 shown in fig. 14, the minimum distance from the crack dam CRD to the edge EG of the display panel 100 may be "DCS-SE1" to "dcs+se1". When the distance DCS1 from the crack dam CRD to the cutting surface CSS is 230 μm and the one-side tolerance of the cutting member CWD is 100 μm, in the display panel 100 shown in fig. 14, the minimum distance from the crack dam CRD to the edge EG of the display panel 100 may be 330 μm or less.

Fifth, as shown in fig. 48 and 54, the side face of each of the plurality of display units DPC is polished using a Computer Numerical Control (CNC) polishing apparatus. (S150 in FIG. 44)

The cutting member CWD, such as a cutting wheel, may cut the mother substrate MSUB in a straight line when viewed from a plane. Therefore, when the corner portion of each of the plurality of display units DPC has a circular shape to have a curvature, each of the corners of the plurality of display units DPC may be processed to have a curvature using a polishing apparatus.

As shown in fig. 54, the first sub-edge area SEGA1 including the inclined surface and the second sub-edge area SEGA2 including the processing trace such as the chips may be formed by a polishing process using a polishing apparatus. The width of the first sub-edge area SEGA1 may be within approximately 150 μm and the width of the second sub-edge area SEGA2 may be within approximately 50 μm.

Sixth, the plurality of display units DPC are inspected using an inspection apparatus. (S160 in FIG. 44)

After the probes are connected to the plurality of inspection pads provided in each of the plurality of display units DPC, lighting inspection of each of the plurality of display units DPC may be performed. After the inspection is completed, a plurality of inspection pads may be cut from each of the plurality of display units DPC.

Seventh, as shown in fig. 49 and 55, the drive IC 200 and the circuit board 300 are attached to each of the plurality of display units DPC, and the first protective film PRF1 is peeled from each of the plurality of display units DPC. (S170 in FIG. 44)

The driving IC 200 is attached to a non-display area NDA provided at a lower edge of each of the plurality of display units DPC. The driving IC 200 may be attached on the first and second driving pads DPD1 and DPD2 of each of the plurality of display units DPC using a conductive adhesive member CAD such as an anisotropic conductive film or an anisotropic conductive adhesive.

In addition, the circuit board 300 is attached to the non-display area NDA of the lower edge of each of the plurality of display units DPC. The circuit board 300 may be attached on the display pad PD of each of the plurality of display units DPC using a conductive adhesive member CAD such as an anisotropic conductive film or an anisotropic conductive adhesive.

Then, the first protective film PRF1 is peeled from the display unit DPC. Then, the polarizing film PF is attached to the display unit DPC using a transparent adhesive member. Then, the display panel 100 may be completed by attaching the cover window CW to the polarizing film PF using a transparent adhesive member.

Fig. 56 is a flowchart illustrating a method of manufacturing a display device in accordance with one or more embodiments. Fig. 57 to 61 are perspective views illustrating a method of manufacturing a display device according to one or more embodiments. Fig. 62 to 66 are cross-sectional views illustrating a method of manufacturing a display device according to one or more embodiments.

Fig. 57 to 61 are perspective views of the mother substrate MSUB and the plurality of display units DPC disposed on the mother substrate MSUB. Fig. 62 to 66 show cross sections of the mother substrate MSUB (or substrate SUB) and the plurality of display units DPC taken along the line VIII-VIII' in fig. 57 to 61. Fig. 67 is an example diagram illustrating the depth of a laser irradiated region formed by a laser in accordance with one or more embodiments. Fig. 68 is an image illustrating a bottom surface of a display device in accordance with one or more embodiments.

First, as shown in fig. 57 and 62, a plurality of display units DPC are formed on a first surface of a mother substrate MSUB. (S210 in FIG. 56)

Second, as shown in fig. 62, a plurality of first protective films PRF1 are attached on the plurality of display units DPC, and the plurality of display units DPC are inspected. (S220 in FIG. 56)

First, a first protective film layer is attached to cover the plurality of display units DPC and a mother substrate MSUB disposed between the plurality of display units DPC. Then, the plurality of first protective films PRF1 may be respectively disposed on the plurality of display units DPC by removing a portion of the first protective film layer disposed on the mother substrate MSUB. That is, a portion of the first protective film layer may be removed, and the remaining portion may be a plurality of first protective films PRF1. Accordingly, a plurality of first protective films PRF1 may be disposed on the plurality of display units DPC, respectively. That is, the plurality of first protective films PRF1 may be disposed to correspond to the plurality of display units DPC on a one-to-one basis.

Then, the plurality of display units DPC are inspected using an inspection apparatus. After the probes are connected to the plurality of inspection pads provided in each of the plurality of display units DPC, lighting inspection of each of the plurality of display units DPC may be performed.

When the lighting inspection is performed after the plurality of display units DPC are separated from the mother substrate MSUB by the dicing process, an additional process for removing the plurality of inspection pads is required after the lighting inspection is completed. On the other hand, when the lighting inspection is performed on the mother substrate MSUB, the plurality of inspection pads are removed when the plurality of display units DPC are separated from the mother substrate MSUB by laser irradiation and etching. Accordingly, when performing the lighting inspection on the mother substrate MSUB, a separate additional process for removing the plurality of inspection pads may not be required.

Third, as shown in fig. 58 and 63, a plurality of first laser irradiation regions CH1 are formed along the edges of the plurality of display units DPC by irradiating the laser light LR from the laser device LD onto a second surface of the mother substrate MSUB opposite to the first surface. (S230 in FIG. 56)

Various lasers may be used as the laser device LD according to one or more embodiments, but in the present disclosure, the laser LR may be an infrared bessel beam having a wavelength of approximately 1030 nm.

As shown in fig. 63, the laser LR may be irradiated on the second surface of the mother substrate MSUB. However, embodiments of the present disclosure are not limited thereto. The laser LR may be irradiated on the first surface of the mother substrate MSUB.

The cutting line CL may be defined as a virtual line connecting the plurality of first laser irradiation regions CH1. The cutting line CL may be formed by irradiating the laser light LR to form a plurality of first laser irradiation regions CH1 along edges of the plurality of display units DPC.

One-sided tolerance SE2 of one side of the laser LR may be within about 50 μm, and two-sided tolerance of the laser LR may be within about 100 μm. When forming the plurality of first laser irradiation regions CH1 with the laser light LR, one side tolerance SE2 of the laser light LR may be a cutting error in one direction (for example, X-axis direction).

The distance from the crack dam CRD to the edge EG of the display panel 100 may vary according to a side tolerance SE2 of one side of the laser LR. When the laser light LR is properly irradiated to the position to be irradiated, the distance from the crack dam CRD to the first laser irradiation area CH1 is defined as "DCH".

When the laser light LR is irradiated to the left with the maximum value of the one-side tolerance SE2 of the laser light LR, the distance from the crack dam CRD to the first laser irradiation area CH1 may be "DCH-SE2". On the other hand, when the laser light LR is irradiated to the right side with the maximum value of the one-side tolerance SE2 of the laser light LR, the distance from the crack dam CRD to the first laser irradiation area CH1 may be "dch+se2".

Since the substrate SUB of the display unit DPC is separated from the mother substrate MSUB based on the first laser irradiation area CH1 in the etching process as the next step, the distance from the crack dam CRD to the first laser irradiation area CH1 may be substantially the same as the minimum distance from the crack dam CRD to the edge EG of the display panel 100 in the display panel 100 as shown in fig. 19. Accordingly, in the display panel 100, the minimum distance from the crack dam CRD to the edge EG of the display panel 100 may differ by 100 μm, which is a distance corresponding to "one-side tolerance SE2×2" (or "double-side tolerance") of the laser LR.

That is, in the display panel 100 shown in fig. 19, the minimum distance from the crack dam CRD to the edge EG of the display panel 100 may be "DCH-SE2" to "dch+se2". For example, when the distance from the crack dam CRD to the first laser irradiation area CH1 is 80 μm and the one-side tolerance SE2 of the laser LR is 50 μm, in the display panel 100 shown in fig. 19, the minimum distance from the crack dam CRD to the edge EG of the display panel 100 may be 130 μm or less.

As described above, the side tolerance SE2 of the laser LR is 50 μm, but the side tolerance SE1 of the cutting member CWD such as a cutting wheel is 100 μm. That is, because the one-side tolerance SE2 of the laser LR is smaller than the one-side tolerance SE1 of the cutting member CWD such as the cutting wheel, when cutting using the laser LR, the distance from the crack dam CRD to the edge EG of the display panel 100 can be reduced as compared to the case of cutting using the cutting member CWD such as the cutting wheel.

When the laser light LR is irradiated on the second surface of the mother substrate MSUB, the depth (or sketch length) TCH1 of each of the plurality of first laser irradiation regions CH1 may be adjusted according to the repetition rate, the process speed, and/or the pulse energy, as shown in fig. 67. For example, the depth TCH1 of each of the plurality of first laser irradiation regions CH1 may be approximately 50 μm from the first surface of the mother substrate MSUB, as shown in (a) of fig. 67. In addition, since the thickness of the mother substrate MSUB is about 500 μm, the depth TCH1 of each of the plurality of first laser irradiation regions CH1 may be as high as 500 μm as shown in (b) of fig. 67. That is, the depth TCH1 of each of the plurality of first laser irradiation regions CH1 may be about 50 μm to 500 μm from the first surface of the mother substrate MSUB.

The laser light LR for forming the first laser irradiation region CH1 may be irradiated at a repetition rate of 10kHz to 250kHz, a processing speed of 10mm/s to 250mm/s, and/or a pulse energy of 10 μj to 300 μj. However, in order for each of the plurality of first laser irradiation regions CH1 to have a depth of approximately 225 μm from the first surface of the mother substrate MSUB, it is desirable to irradiate at a repetition rate of approximately 17.5kHz to 125kHz, a processing speed of 17.5mm/s to 125mm/s, and a pulse energy of 25 μj to 178 μj.

Fourth, as shown in fig. 64, the second protective films PRF2 are attached on the plurality of first protective films PRF 1. (S240 in FIG. 56)

The second protective film PRF2 may be attached on the mother substrate MSUB and the plurality of first protective films PRF1 that are exposed without being covered with the plurality of first protective films PRF 1. The second protective film PRF2 may cover the first laser irradiation area CH1. The second protective film PRF2 may be an acid-resistant film for protecting the plurality of display units DPC from the etchant ECH in the etching process of the mother substrate MSUB to be performed in the next step.

Fifth, as shown in fig. 59, 60, 64, and 65, the thickness of the mother substrate MSUB is reduced by spraying the etchant ECH on the second surface of the mother substrate MSUB without a separate mask while cutting the mother substrate MSUB along the plurality of first laser irradiation regions CH1 and peeling the second protective film PRF2. (S250 in FIG. 56)

When the etchant ECH is sprayed on the second surface of the mother substrate MSUB, the mother substrate MSUB may be reduced from the first thickness T1 'to the second thickness T2'. Since the mother substrate MSUB is etched without a separate mask, isotropic etching in which all regions of the second surface of the mother substrate MSUB are uniformly etched up to the region in which the first laser irradiation region CH1 is formed may be performed.

Each of the plurality of first laser irradiation regions CH1 may include a physical hole formed by the laser LR and a region in which physical characteristics are changed by the laser LR as a periphery of the physical hole. Alternatively, each of the plurality of first laser irradiation regions CH1 may be a region in which physical properties are changed by the laser LR without physical holes. Accordingly, the etching rate of the etchant ECH in each of the plurality of first laser irradiation regions CH1 may be higher than that in other regions of the mother substrate MSUB where the laser is not irradiated.

When the thickness of the mother substrate MSUB is reduced by the etchant ECH and the etchant ECH permeates into the plurality of first laser irradiation regions CH1 formed by the laser light LR, a difference in etching rate occurs due to the plurality of first laser irradiation regions CH1 in the region in which the first laser irradiation regions CH1 are formed and in the region in which the first laser irradiation regions CH1 are not formed. That is, the mother substrate MSUB may be anisotropically etched in which the etching rate in the region in which the first laser irradiation region CH1 is formed is faster than the etching rate in the region in which the first laser irradiation region CH1 is not formed. Accordingly, as shown in fig. 65, the substrate SUB separated from the mother substrate MSUB may include a first inclined surface ip1_1 disposed between the side surface ss_1 and the bottom surface BS.

In addition, when the etchant ECH permeates into the plurality of first laser irradiation regions CH1 formed by the laser light LR, the mother substrates MUSB may be separated along the cutting lines CL. That is, each of the plurality of display units DPC may be separated from the mother substrate MSUB.

Since the etchant ECH does not penetrate the first surface of the substrate SUB separated from the mother substrate MSUB due to the second protective film PRF2, the second surface of the substrate SUB is etched by the etchant ECH. Therefore, differences in roughness, hardness, light transmittance, light reflectance, local density, surface chemical structure, and the like may occur between the first surface and the second surface of the substrate SUB. For example, as shown in fig. 68, pits due to the etchant ECH may occur on the second surface of the mother substrate MSUB. Pits indicate that minute defects (such as scratches) present on the second surface of the substrate SUB are enlarged by reacting with the etchant ECH.

In fig. 64 and 65, the one-side tolerance of the laser light LR is approximately 50 μm, and the width of the first laser irradiation area CH1 formed by the laser light LR can be enlarged by approximately 40 μm by the etchant ECH. Therefore, the separation distance SD between adjacent display units DPC may be about 280 μm in consideration of the double-sided tolerance of the laser light of each of the display units DPC and the width of the first laser irradiation area CH1 expanded by the etchant ECH.

After the etching process is completed, the second protective film PRF2 may be peeled off.

Sixth, as shown in fig. 61 and 66, the drive IC 200 and the circuit board 300 are attached to each of the plurality of display units DPC, and the polarizing film PF and the cover window CW are attached after the first protective film PRF1 is peeled off from each of the plurality of display units DPC. (S260 in FIG. 56)

As described above, the thickness of the mother substrate MSUB may be reduced by using an etching process, and the substrate SUB of each of the plurality of display units DPC may be separated from the mother substrate MSUB. Therefore, the efficiency of the manufacturing process can be improved.

In addition, when viewed on a plane, the laser light LR can be applied by adjusting the repetition rate, the processing speed, and the pulse energy so that the plurality of first laser irradiation regions CH1 are arranged along a curve. Therefore, by spraying the etchant ECH along the plurality of first laser irradiation regions CH1 and etching after forming the plurality of first laser irradiation regions CH1 in a curve, the corner of each of the plurality of display units DPC can be formed in a circular shape having a curvature. That is, since the corner of each of the plurality of display units DPC may be formed in a circular shape without a separate polishing process, the efficiency of the manufacturing process may be improved.

Fig. 69 is a perspective view illustrating a display device in accordance with one or more embodiments. Fig. 70 is a plan view illustrating a display panel and a driving IC according to one or more embodiments. Fig. 71 is a cross-sectional view showing an example of the display device along the line IX-IX' of fig. 69. Fig. 72 is a cross-sectional view showing an example of a display device in which the circuit board of fig. 71 is bent.

Referring to fig. 69 to 72, the through holes TH may be formed in the display device 10 according to one or more embodiments. The through holes TH are holes allowing light to pass therethrough, and may be physical holes penetrating the panel bottom cover PB and the polarizing film PF, and the display panel 100. However, embodiments of the present disclosure are not limited thereto. The through holes TH may pass through the panel bottom cover PB, but may not pass through the display panel 100 and the polarizing film PF. The cover window CW may be provided to cover the through holes TH.

The through holes TH may pass through the substrate SUB, the display layer dis, the encapsulation layer ENC, and the sensor electrode layer SENL of the display panel 100.

The electronic device including the display device 10 according to one or more embodiments may further include an optical device OPD disposed in the through hole TH. Electronic devices in accordance with one or more embodiments may be devices such as televisions, laptop computers, monitors, billboards, and/or internet of things (IOT) devices, as well as portable electronic devices such as mobile phones, smart phones, tablet personal computers (tablet PCs), smartwatches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable Multimedia Players (PMPs), navigation systems, and/or Ultra Mobile PCs (UMPCs).

The optical device OPD may be spaced apart from the display panel 100, the panel bottom cover PB, and the polarizing film PF. The optical device OPD may be an optical sensor, such as a proximity sensor, an illuminance sensor, and/or a camera sensor, that detects light incident through the through-hole TH.

Fig. 73 is a layout diagram illustrating an example of a via hole, an inorganic package region, a line region, and a display region of a display panel according to one or more embodiments. Fig. 73 is an enlarged view of region I in fig. 70.

Referring to fig. 73, the display panel 100 according to one or more embodiments includes an inorganic encapsulation area IEA surrounding a through hole TH and a line area WLA surrounding the inorganic encapsulation area IEA.

In the inorganic encapsulation region IEA, the first encapsulation inorganic layer TFE1 and the second encapsulation inorganic layer TFE3 of the encapsulation layer ENC are in contact with each other (see, for example, fig. 74 and 75), and thus the inorganic encapsulation region IEA may be a layer for preventing oxygen or moisture from penetrating into the light emitting element layer EML of the display layer dis due to the through holes TH.

The inorganic encapsulation area IEA may include at least one dam, at least one tip, and at least one recess. For example, as shown in fig. 75, the inorganic encapsulation region IEA may include a first dam HDAM1, a second dam HDAM2, first to eighth tips T1 to T8, and first to third grooves GR1 to GR3.

The first and second tips T1 and T2 may be disposed closer to the line area WLA than the first dam HDAM 1. The first tip T1 may be disposed closer to the line region WLA than the second tip T2. The second tip T2 may be disposed between the first tip T1 and the first dam HDAM 1.

The third, fourth, fifth and sixth tips T3, T4, T5 and T6 may be disposed between the first and second dams HDAM1 and HDAM 2. At least a portion of the third tip T3 may overlap the first dam HDAM1 in the third direction (Z-axis direction).

The seventh and eighth tips T7 and T8 may be disposed closer to the through holes TH than the second dam HDAM 2. At least a portion of the seventh tip T7 may overlap the second dam HDAM2 in the third direction (Z-axis direction). The distance between the eighth tip T8 and the through hole TH may be approximately 300 μm.

The first groove GR1 may be disposed between the first tip T1 and the second tip T2. The second groove GR2 may be disposed between the third tip T3 and the fourth tip T4. The third groove GR3 may be disposed between the fifth tip T5 and the sixth tip T6.

The line region WLA may be a region in which a bypass line is provided due to the through hole TH. Some of the bypass lines may be connected to the data line DL, and another portion of the bypass lines may be connected to a second power line VDL to which a second power voltage VDD higher than the first power voltage VSS is applied. Also some of the bypass lines may be connected to the scan lines SL. The line area WLA may be surrounded by the display area DA.

Fig. 74 is a cross-sectional view showing an example of the display panel taken along the line X-X' of fig. 73.

Fig. 74 shows a section of the edge TEG of the through-hole TH when the substrate SUB of the display panel 100 is cut by jetting an etchant after laser irradiation.

Referring to fig. 74, the via edge region TEGA is a region in which a processing trace is formed on the upper surface US of the substrate SUB by an etchant when the substrate SUB is cut by jetting the etchant after irradiation of laser light. The via edge face area TEGA may be within about 30 μm as shown in fig. 22.

The via edge region TEGA may include a first inclined surface ip1_4 formed by spraying an etchant after irradiating laser light. The angle θ10 between the side surface ss_4 and the upper surface US of the edge TEG of the through-hole TH may be about 90 degrees. That is, the angle between the side surface ss_4 and the upper surface US of the edge TEG of the through-hole TH may be substantially close to a vertical angle (e.g., vertical angle). An angle θ11 formed between the side surface ss_4 of the edge TEG of the through-hole TH and the first inclined surface ip1_4 and an angle θ12 formed between the first inclined surface ip1_4 and the bottom surface BS may be obtuse angles. The processing trace formed on the upper surface US of the substrate SUB may overlap the first inclined surface ip1_4 in the third direction (Z-axis direction).

When the substrate SUB of the display panel 100 is cut by spraying the etchant after the laser light is irradiated, an angle θ11 between the side surface ss_4 of the edge TEG of the through hole TH and the first inclined surface ip1_4 and an angle θ12 between the first inclined surface ip1_4 and the bottom surface BS may vary according to the depth of the laser light irradiation region formed by the laser light. The depth of the laser irradiation region formed by cutting the laser along the edge EG of the display panel 100 may be different from the depth of the laser irradiation region formed by cutting the laser along the edge TEG of the through-hole TH.

Accordingly, an angle θ11 between the side surface ss_4 of the edge TEG of the through hole TH and the first inclined surface ip1_4 shown in fig. 74 may be smaller than an angle θ6 between the side surface ss_1 and the first inclined surface ip1_1 shown in fig. 19 to 21. The angle θ12 between the first inclined surface ip1_4 and the bottom surface BS shown in fig. 74 may be smaller than the angle θ7 between the first inclined surface ip1_1 and the bottom surface BS shown in fig. 19 to 21.

The depth of the laser irradiation area formed by laser cutting along the edge EG of the display panel 100 and the depth of the laser irradiation area formed by laser cutting along the edge TEG of the through-hole TH will be described later with reference to fig. 98 and 99.

Fig. 75 is an enlarged cross-sectional view showing an example of the region K of fig. 74 in more detail.

Referring to fig. 75, the first dummy pattern DP1 may include the same material as the second gate metal layer including the second capacitor electrode CAE2 of the capacitor Cst, and may be disposed at the same layer (or at the same layer) as the second gate metal layer. For example, the first dummy pattern DP1 may be disposed on the first interlayer insulating layer 141. The first dummy pattern DP1 may be formed of a single layer or multiple layers made of any one or more selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

The second dummy pattern DP2 may include the same material as the first data metal layer including the first connection electrode CE1 and the data line DL, and may be disposed at the same layer (or at the same layer) as the first data metal layer. For example, the second dummy pattern DP2 may be disposed on the second interlayer insulating layer 142. The second dummy pattern DP2 may be formed of a single layer or multiple layers made of any one or more selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

The second dummy pattern DP2 may overlap the first dummy pattern DP1 in the third direction (Z-axis direction).

The first to eighth tips T1 to T8 may include the same material as the second data metal layer including the second connection electrode CE2, and may be disposed at the same layer (or at the same layer) as the second data metal layer. For example, the first to eighth tips T1 to T8 may be disposed on the first organic layer 160. The first to eighth tips T1 to T8 may be formed of a single layer or a plurality of layers made of any one or more selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

Each of the first to eighth tips T1 to T8 may be connected to the second dummy pattern DP2 through a contact hole penetrating the first organic layer 160. Each of the first to eighth tips T1 to T8 may include an eave structure in which upper and bottom surfaces are exposed without being covered by the first organic layer 160, the second organic layer 180, the first dam HDAM1, and the second dam HDAM2. The fourth tip T4 and the fifth tip T5 may be integrally formed. Each of the first to eighth tips T1 to T8 may be a protrusion pattern or a groove pattern for forming a groove (or groove). The eighth tip T8 is adjacent to the edge TEG of the through-hole TH. In fig. 75, the eighth tip T8 is shown as an outermost structure adjacent to the edge TEG of the through-hole TH, for example, but the embodiment of the present disclosure is not limited thereto. For example, when the seventh and eighth tips T7 and T8 are omitted, the outermost structure adjacent to the edge TEG of the through-hole TH may be the second dam HDAM2 for preventing the encapsulation organic layer TFE2 of the encapsulation layer ENC from overflowing. Alternatively, when the seventh and eighth tips T7 and T8 are omitted, the outermost structure adjacent to the edge TEG of the through-hole TH may be a groove for separating the light emitting layer 172 from the common electrode 173.

The distance from the eighth tip T8 to the edge TEG of the through-hole TH may be approximately 300 μm or less. The via edge region TEGA may be disposed between the eighth tip T8 and the edge TEG of the via TH.

The first groove GR1 may be formed between the first tip T1 and the second tip T2, the second groove GR2 may be formed between the third tip T3 and the fourth tip T4, and the third groove GR3 may be formed between the fifth tip T5 and the sixth tip T6. The first groove GR1 may have an eave structure formed of the first and second tips T1 and T2, the second groove GR2 may have an eave structure formed of the third and fourth tips T3 and T4, and the third groove GR3 may have an eave structure formed of the fifth and sixth tips T5 and T6.

According to one or more embodiments, the light emitting layer 172 is deposited by evaporation, and the common electrode 173 is deposited by sputtering. As a result, the step coverage may be low, and thus the first to third grooves GR1, GR2, and GR3 may be disposed to be spaced apart (or spaced apart) from each other. In contrast, the first encapsulation inorganic layer TFE1 and the second encapsulation inorganic layer TFE3 are deposited by chemical vapor deposition and atomic layer deposition. As a result, the step coverage can be high, and thus the first to third grooves GR1, GR2, and GR3 can be continuously connected without being cut off. The step coverage may refer to a ratio of the degree of coating the thin film on the inclined portion to the degree of coating the thin film on the flat portion. In each of the first to third grooves GR1, GR2, and GR3, a light emitting layer 172, a light emitting layer residue 172_d, a common electrode 173, and a disconnected common electrode residue 173_d may be provided.

The first dam HDAM1 may include first to fourth sub-dams HDA1, HDA2, HDA3, and HDA4. The first sub-dam HDA1 may be disposed on the first organic layer 160 and may include the same material as the second organic layer 180. The first sub-dam HDA1 may be disposed on the second and third tips T2 and T3. The second sub-dam HDA2 may be disposed on the first sub-dam HDA1 and may include the same material as the bank 190. The third and fourth sub-dams HDA3 and HDA4 may be disposed on the second sub-dam HDA2 and may include the same material as the spacer 191, but is not limited thereto. The fourth sub-dam HDA4 may be disposed closer to the through holes TH than the third sub-dam HDA 3. The thickness of the fourth sub-dam HDA4 may be greater than the thickness of the third sub-dam HDA 3.

The second dam HDAM2 may include fifth to seventh sub-dams HDA5, HDA6 and HDA7. The fifth sub-dam HDA5 may be disposed on the first organic layer 160 and may include the same material as the second organic layer 180. The fifth sub-dam HDA5 may be disposed on the seventh nib T7. The sixth sub-dam HDA6 may be disposed on the fifth sub-dam HDA5 and may include the same material as the bank 190. The seventh sub-dam HDA7 may be disposed on the sixth sub-dam HDA6 and may include the same material as the spacer 191, but is not limited thereto.

The first dam HDAM1 and the second dam HDAM2 can prevent the encapsulation organic layer TFE2 from overflowing into the through holes TH.

The light emitting layer residue 172_d, the common electrode residue 173_d, the first encapsulation inorganic layer TFE1, and the second encapsulation inorganic layer TFE3 may extend to an edge TEG of the through hole TH. The end of the light emitting layer residue 172_d, the end of the common electrode residue 173_d, the end of the first encapsulation inorganic layer TFE1, and the end of the second encapsulation inorganic layer TFE3 may coincide with the edge TEG of the through hole TH.

As shown in fig. 75, since the light emitting layer 172 and the common electrode 173 are cut off in each of the first to third grooves GR1, GR2, and GR3 formed by the first to eighth tips T1 to T8, the light emitting layer 172 and the common electrode 173 exposed to the through holes TH can be prevented from being paths of penetration of oxygen, moisture, and the like.

Fig. 76 is a cross-sectional view showing an example of the display panel taken along the line X-X' of fig. 73. Fig. 79 is an enlarged cross-sectional view showing an example of the region L of fig. 78 in more detail.

Referring to fig. 76 and 77, an organic planarization layer ORL may be disposed on the encapsulation layer ENC. The polarizing film PF can be easily attached to the organic planarization layer ORL due to the organic planarization layer ORL.

The organic planarization layer ORL may be disposed to be spaced apart (or spaced apart) from the edge TEG of the through-hole TH. For example, the substrate SUB (e.g., MSUB in fig. 76) may protrude beyond the organic planarization layer ORL in the through holes TH. The organic planarization layer ORL may be disposed on at least a portion of the via edge region TEGA. The organic planarization layer ORL may cover at least a portion of the processing trace of the via edge region TEGA. The distance between the end of the organic planarization layer ORL and the eighth tip T8 may be about 100 μm or more. The distance between the end of the organic planarization layer ORL and the edge TEG of the through-hole TH may be within about 200 μm.

The organic planarization layer ORL may be formed of an organic film such as acryl resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like. For example, the organic planarization layer ORL may include the same material as the second sensor insulation layer TINS2 shown in fig. 6. The organic planarization layer ORL may be formed concurrently (e.g., simultaneously) with the second sensor insulating layer TINS2 shown in fig. 6.

The light emitting layer residue 172_d, the common electrode residue 173_d, the first encapsulation inorganic layer TFE1, and the second encapsulation inorganic layer TFE3 may be disposed to be spaced apart (or spaced apart) from the edge TEG of the through hole TH. For example, the substrate SUB may protrude from the light emitting layer residue 172_d, the common electrode residue 173_d, the first encapsulation inorganic layer TFE1, and the second encapsulation inorganic layer TFE3 in the through holes TH. The light emitting layer residue 172_d, the common electrode residue 173_d, the first encapsulation inorganic layer TFE1, and the second encapsulation inorganic layer TFE3 may cover at least a portion of the processing trace of the via edge region TEGA.

The end of the light emitting layer residue 172_d, the end of the common electrode residue 173_d, the end of the first encapsulation inorganic layer TFE1, or the end of the second encapsulation inorganic layer TFE3 may coincide with the end of the organic planarization layer ORL. The distance between the end of the light emitting layer residue 172_d, the end of the common electrode residue 173_d, the end of the first encapsulation inorganic layer TFE1, or the end of the second encapsulation inorganic layer TFE3 and the eighth tip T8 may be approximately 100 μm or more. The distance between the light emitting layer residue 172_d, the common electrode residue 173_d, the first encapsulation inorganic layer TFE1 or the second encapsulation inorganic layer TFE3 and the edge TEG of the through-hole TH may be approximately 200 μm or less.

Although fig. 77 illustrates that the first buffer layer BF1 may extend to the edge TEG of the through-hole TH, embodiments of the present disclosure are not limited thereto. The first buffer layer BF1 may be disposed to be spaced apart (or spaced apart) from the edge TEG of the through-hole TH. For example, the substrate SUB may protrude beyond the first buffer layer BF1 in the through holes TH. The end of the first buffer layer BF1 may coincide with the end of the organic planarization layer ORL.

Fig. 78 is a cross-sectional view showing an example of the display panel taken along the line X-X' of fig. 73. Fig. 81 is an enlarged cross-sectional view showing an example of the region M of fig. 78 in more detail.

Referring to fig. 78 and 79, the organic planarization layer ORL may be disposed to be spaced apart (or spaced apart) from the edge TEG of the through-hole TH. For example, the organic planarization layer ORL may be formed to protrude from the substrate SUB in the through holes TH. The organic planarization layer ORL may be disposed in the via edge region TEGA. The organic planarization layer ORL may cover the processing trace of the via edge region TEGA.

In addition, the first buffer layer BF1, the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142 may be disposed to be spaced apart (or spaced apart) from the edge TEG of the through-hole TH. For example, the first buffer layer BF1, the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142 may protrude from the substrate SUB in the through holes TH. The first buffer layer BF1, the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142 may be disposed in the via edge region TEGA. The first buffer layer BF1, the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142 may cover the processing trace of the via edge region TEGA.

Whether the organic planarization layer ORL protrudes as compared with the substrate SUB (e.g., the mother substrate MSUB) shown in fig. 76 and 78 may vary according to a difference in the order of removal of the organic planarization layer ORL and laser treatment of the substrate SUB, and will be described later with reference to fig. 103 and 105.

Fig. 80 is a cross-sectional view showing an example of the display panel taken along the line X-X' of fig. 73.

Referring to fig. 80, the display panel 100 according to one or more embodiments may include a heat dissipation layer IRL disposed in the via edge region TEGA. The heat dissipation layer IRL may include a metal material having high thermal conductivity to dissipate heat generated when a laser-irradiated region is formed with a laser in a dicing process. In addition, the heat radiation layer IRL may include a material having a high infrared absorption rate to reduce or minimize an influence of laser light on the display panel 100 during the cutting process by increasing the infrared absorption rate. For example, the heat radiation layer IRL may be formed of a single layer or a plurality of layers made of any one or more selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

The length of the heat radiation layer IRL in the first direction (X-axis direction) may be longer than the length of the via-edge region TEGA in the first direction (X-axis direction). For example, the length of the heat radiation layer IRL in the first direction (X-axis direction) may be approximately 50 μm to 300 μm.

Fig. 81 is an enlarged cross-sectional view showing an example of the region N of fig. 80 in more detail.

Referring to fig. 81, the heat sink layer IRL may include the same material as the first data metal layer including the first connection electrode CE1 and the data line DL, and may be disposed at the same layer (or at the same layer) as the first data metal layer. The heat dissipation layer IRL may be disposed on the second interlayer insulating layer 142. In one or more embodiments, the heat dissipation layer IRL may be disposed on the first buffer layer BF 1. The heat radiation layer IRL may be formed of a single layer or a plurality of layers made of any one or more selected from among molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

Alternatively, the heat sink layer IRL may include the same material as the second gate metal layer including the second capacitor electrode CAE2 of the capacitor Cst, and be disposed at the same layer (or at the same layer) as the second gate metal layer. The heat dissipation layer IRL may be disposed on the first interlayer insulating layer 141.

Alternatively, the heat dissipation layer IRL may include the same material as the first gate metal layer including the gate electrode TG of the thin film transistor TFT, the first capacitor electrode CAE1 of the capacitor Cst, and the scan line SL, and may be disposed at the same layer (or at the same layer) as the first gate metal layer including the gate electrode TG of the thin film transistor TFT, the first capacitor electrode CAE1 of the capacitor Cst, and/or the scan line SL. The heat dissipation layer IRL may be disposed on the gate insulating layer 130.

Fig. 82 is an enlarged cross-sectional view showing an example of the region N of fig. 80 in more detail.

Referring to fig. 82, the first heat dissipation layer IRL1 may include the same material as the first organic layer 160, and may be disposed at the same layer (or at the same layer) as the first organic layer 160. The first heat dissipation layer IRL1 may be disposed on the second interlayer insulating layer 142. In one or more embodiments, the first heat dissipation layer IRL1 may be disposed on the first buffer layer BF 1. The first heat dissipation layer IRL1 may be formed of an organic film such as acryl resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like. The first heat dissipation layer IRL1 may have a trapezoidal cross section.

The second heat dissipation layer IRL2 may cover the first heat dissipation layer IRL1. The second heat radiation layer IRL2 may be formed of a single layer or a plurality of layers made of any one or more selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

Fig. 83 is an enlarged cross-sectional view showing an example of the region N of fig. 80 in more detail.

Referring to fig. 83, the heat dissipation layer IRL may include a plurality of first heat dissipation layers IRL1 and second heat dissipation layers IRL2. The plurality of first heat dissipation layers IRL1 may be disposed to be spaced apart from each other in one direction.

The plurality of first heat dissipation layers IRL1 may include the same material as the first organic layer 160, and may be disposed at the same layer (or at the same layer) as the first organic layer 160. A plurality of first heat dissipation layers IRL1 may be disposed on the second interlayer insulating layer 142. In one or more embodiments, a plurality of first heat dissipation layers IRL1 may be disposed on the first buffer layer BF 1. The plurality of first heat dissipation layers IRL1 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The plurality of first heat dissipation layers IRL1 may have a trapezoidal cross section.

However, a portion of the edge TEG of the first heat dissipation layer IRL1 closest to the through holes TH may be cut by a laser process in the cutting process of the substrate SUB. Accordingly, the first heat dissipation layer IRL1 closest to the edge TEG of the through-hole TH may have a cross section in which a portion of the trapezoid is cut away.

The second heat dissipation layer IRL2 may cover a plurality of first heat dissipation layers IRL1. Therefore, the length of the second heat dissipation layer IRL2 in one direction may be longer than the lengths of the plurality of first heat dissipation layers IRL1 in one direction. The second heat dissipation layer IRL2 may also be disposed on an upper surface of the substrate SUB exposed between the plurality of first heat dissipation layers IRL1. The area of the second heat dissipation layer IRL2 may be increased due to the plurality of first heat dissipation layers IRL1, so that the heat dissipation effect may be increased.

Fig. 84 is a cross-sectional view showing an example of the display panel taken along the line X-X' of fig. 73.

Referring to fig. 84, the heat dissipation layer IRL may be disposed to be spaced apart (or spaced apart) from the edge TEG of the through-hole TH in one direction. That is, the heat radiation layer IRL may be provided while avoiding the region where the laser light is directly irradiated. For this, the heat dissipation layer IRL may be disposed to be spaced apart (or spaced apart) from the edge TEG of the through-hole TH by approximately 1 μm to 50 μm.

Fig. 85 is an exemplary diagram showing a minimum distance between an optical device and a black matrix when no through hole is formed in a display panel.

Referring to fig. 85, when the through holes TH are not formed in the display panel 100, the optical device OPD may be disposed under the substrate SUB. In this case, the thin film transistor TFT, the light emitting element LEL, and the sensor electrodes TE and RE of the display panel 100 may not be disposed in a region overlapping the optical device OPD in the path of light incident on the optical device OPD to block the light incident on the optical device OPD. That is, a material transmitting light, such as an inorganic layer and/or an organic layer of the display panel 100, may be disposed in a path of light incident on the optical device OPD.

Light incident on the optical device OPD may be refracted by a difference in refractive index in each of the upper surface of the substrate SUB, the upper surface of the display layer dis, the upper surface of the encapsulation layer ENC, the upper surface of the sensor electrode layer SENL, the upper surface of the polarizing film PF, and the air layer on the upper surface of the cover window CW. Accordingly, when the through holes TH are not formed in the display panel 100, the distance DOB1 between the optical device OPD and the black matrix BM of the cover window CW may increase in a horizontal direction (e.g., a first direction (X-axis direction) or a second direction (Y-axis direction)) parallel to the substrate SUB.

Fig. 86 is an exemplary view showing a minimum distance between an optical device and a black matrix when a through hole is formed in a display panel.

Referring to fig. 86, when the through holes TH are formed in the display panel 100, light incident on the optical device OPD may be refracted by a difference in refractive index between the cover window CW and the air layer on the upper surface of the cover window CW. That is, the number of times light incident on the optical device OPD is refracted can be reduced (e.g., greatly reduced).

Accordingly, when the through holes TH are formed in the display panel 100, a distance DOB2 between the optical device OPD and the black matrix BM of the cover window CW in a horizontal direction (e.g., a first direction (X-axis direction) or a second direction (Y-axis direction)) parallel to the substrate SUB may be smaller (e.g., significantly smaller) than a distance DOB1 between the optical device OPD and the black matrix BM of the cover window CW in a horizontal direction parallel to the substrate SUB when the through holes TH are not formed in the display panel 100, e.g., the distance DOB2 may be about 50 μm. Accordingly, when the through holes TH are formed in the display panel 100, the size of the through holes TH may be reduced (e.g., greatly reduced) as compared to the size of the through holes TH when the through holes TH are not formed in the display panel 100.

Fig. 87 is a cross-sectional view illustrating an example of an electronic device including a display panel and an optical device disposed in a through hole in accordance with one or more embodiments. Fig. 87 is a cross-sectional view illustrating an example of region J of fig. 71 in greater detail in accordance with one or more embodiments.

Referring to fig. 87, an electronic device in accordance with one or more embodiments may further include an upper optical cover OCV disposed on the optical device OPD. The upper optical cover OCV may have a funnel or cone shape. The width of the upper optical cover OCV may gradually increase from the optical device OPD to the cover window CW. The upper optical cover OCV may be integrally formed with the optical device OPD, or may be separately configured (or positioned) from the optical device OPD. Because the optical device OPD detects light passing through the upper optical cover OCV, noise light incident on the optical device OPD can be reduced or minimized.

The width W1 of the upper optical cover OCV is greater than the minimum width W2 of the through holes TH, but the upper width W3 of the through holes TH may be smaller than the lower width W4 of the through holes TH. The minimum width W2 of the through holes TH may be the width of the through holes TH in the substrate SUB. The upper width W3 of the through hole TH may be the width of the through hole TH in the polarizing film PF. The lower width W4 of the through holes TH may be the width of the through holes TH in the panel bottom cover PB. Accordingly, the upper optical cover OCV may be inserted into the through hole TH through an upper portion of the through hole TH.

Fig. 88 and 89 are cross-sectional views illustrating examples of an electronic device including a display panel and an optical device disposed in a through hole in accordance with one or more embodiments. Fig. 88 and 89 are cross-sectional views illustrating an example of region J of fig. 71 in greater detail in accordance with one or more embodiments. Fig. 88 shows the variable optical cover VOCV in a reduced state, and fig. 89 shows the variable optical cover VOCV in an expanded state.

Referring to fig. 88 and 89, an electronic device in accordance with one or more embodiments may include a variable optical cover VOCV disposed over an optical device OPD. The width and height of the variable optical cover VOCV can be adjusted. For example, as shown in fig. 88, the minimum width MIW of the variable optical cover VOCV may be smaller than the minimum width W2 of the through hole TH. As shown in fig. 89, the maximum width MXW of the variable optical cover VOCV is greater than the minimum width W2 of the through hole TH, but the upper width W3 of the through hole TH may be smaller than the lower width W4 of the through hole TH. Because of this, the variable optical cover VOCV can be inserted into the through hole TH in a reduced state through any one of the upper and lower portions of the through hole TH, and can be expanded in a state disposed in the through hole TH.

The variable optical cover VOCV may include first to third optical covers OCV1, OCV2, and OCV3.

In a state in which the variable optical cover VOCV is reduced, at least a portion of the second optical cover OCV2 is retracted into the first optical cover OCV1, and at least a portion of the third optical cover OCV3 may be retracted into the second optical cover OCV 2. The first optical cover OCV1 has a thickness MIT, which may be the thickness of the variable optical cover VOCV when the second and third optical covers OCV2 and OCV3 are completely retracted into the first optical cover OCV1, but the present disclosure is not limited thereto. In a state in which the variable optical cover VOCV expands, the second optical cover OCV2 may be withdrawn from the first optical cover OCV1, and the third optical cover OCV3 may be withdrawn from the second optical cover OCV 2. In a state in which the variable optical cover VOCV expands, the width of the second optical cover OCV2 is greater than the width of the first optical cover OCV1, and the width of the third optical cover OCV3 may be greater than the width of the second optical cover OCV 2. In a state in which the variable optical cover VOCV is sufficiently expanded, the variable optical cover VOCV may have a thickness MXT greater than a thickness MIT.

Fig. 90 is a flowchart illustrating a method of manufacturing a display device in accordance with one or more embodiments. Fig. 91-96 are perspective views illustrating a method of manufacturing a display device according to one or more embodiments. Fig. 97 to 101 are cross-sectional views illustrating a method of manufacturing a display device according to one or more embodiments. Fig. 97 to 101 show cross sections of the mother substrate MSUB (or the formed substrate SUB) and the plurality of display units DPC taken along the line X-X' in fig. 91 to 96.

First, as shown in fig. 91 and 97, a plurality of display units DPC are formed on a first surface of a mother substrate MSUB. (S310 in FIG. 90)

Second, as shown in fig. 97, a plurality of first protective films PRF1 are attached on the plurality of display units DPC, and the plurality of display units DPC are inspected. (S320 in FIG. 90)

Third, as shown in fig. 92 and 98, a plurality of first laser irradiation regions CH1 provided along the edges of the plurality of display units DPC are formed by irradiating the first laser light LR1 from the first laser device LD1 on the second surface of the mother substrate MSUB opposite to the first surface. (S330 in FIG. 90)

Various laser devices may be used as the laser device LD according to one or more embodiments, but as an example, the first laser device LD1 may generate an infrared bessel beam having a wavelength of approximately 1030nm as the first laser light LR1 according to one or more embodiments of the present disclosure.

The first cutting line CL1 may be defined as a virtual line connecting the plurality of first laser irradiation regions CH1. The first cutting line CL1 may be formed by irradiating the first laser light LR1 to form a plurality of first laser irradiation regions CH1 along edges of the plurality of display units DPC.

When the first laser light LR1 is irradiated on the second surface of the mother substrate MSUB, the depth (or sketch length) TCH1 of each of the plurality of first laser light irradiation regions CH1 formed by the first laser light LR1 may be adjusted as shown in fig. 67 by adjusting the repetition rate, the processing speed, and the pulse energy. For example, as shown in (a) of fig. 67, the depth TCH1 of each of the plurality of first laser irradiation regions CH1 may be about 50 μm or more from the first surface of the mother substrate MSUB. In addition, since the thickness of the mother substrate MSUB is approximately 500 μm, the depth TCH1 of each of the plurality of first laser irradiation regions CH1 may be as high as 500 μm as shown in (b) of fig. 67. That is, the depth TCH1 of each of the plurality of first laser irradiation regions CH1 may be approximately 50 μm to 500 μm from the first surface of the mother substrate MSUB.

The first laser light LR1 for forming the first laser light irradiation region CH1 may be irradiated at a repetition rate of 10kHz to 250kHz, a processing speed of 10mm/s to 250mm/s, and a pulse energy of 10 μj to 300 μj. However, in order for each of the plurality of first laser irradiation regions CH1 to have a depth of approximately 225 μm from the first surface of the mother substrate MSUB, irradiation is preferably performed at a repetition rate of approximately 17.5kHz to 125kHz, a processing speed of 17.5mm/s to 125mm/s, and a pulse energy of 25 μj to 178 μj.

Fourth, as shown in fig. 93 and 99, a plurality of second laser irradiation regions CH2 for forming through holes TH in each of the plurality of display units DPC are formed by irradiating the second laser LR2 from the second laser device LD2 on the second surface of the mother substrate MSUB. (S340 of FIG. 90)

Fig. 90 illustrates that step S340 is performed after step S330 is performed, but embodiments of the present disclosure are not limited thereto. Steps S330 and S340 may be performed concurrently (e.g., simultaneously) by a plurality of laser devices LD to shorten the processing time.

The second cutting line CL2 may be defined as a virtual line connecting the plurality of second laser irradiation regions CH2. The second cutting line CL2 may be formed by irradiating the second laser LR2 to form a plurality of second laser irradiation regions CH2 along the edge TEG of the through-hole TH. The second cutting line CL2 may depend on the shape of the through holes TH. For example, when the through holes TH have a circular planar shape, the second cutting lines CL2 may be formed in a circular shape.

According to one or more embodiments, various laser devices may be used to generate the first laser light LR1 and the second laser light LR2, but as an example, according to one or more embodiments of the present disclosure, the first laser device LD1 and the second laser device LD2 may generate infrared bessel beams having a wavelength of approximately 1030nm as the first laser light LR1 and the second laser light LR2, respectively.

The depth of each of the plurality of first laser irradiation regions CH1 formed by the first laser LR1 and the depth (or sketch length) of each of the plurality of second laser irradiation regions CH2 formed by the second laser LR2 may be different. The depth of the first laser irradiation region CH1 may be defined as the depth (or sketch length) of the first laser irradiation region CH1, and the depth of the second laser irradiation region CH2 may be defined as the depth (or sketch length) of the second laser irradiation region CH 2.

Each of the plurality of first laser irradiation regions CH1 may have a depth of about 50 μm or more from the first surface of the mother substrate MSUB. Since the thickness of the mother substrate MSUB may be approximately 500 μm, the depth (or sketch length) TCH1 of each of the plurality of first laser irradiation regions CH1 may be approximately 50 μm to 500 μm from the first surface of the mother substrate MSUB. Further, the depth (or sketch length) of each of the plurality of second laser irradiation regions CH2 may be approximately 50 μm to 500 μm from the first surface of the mother substrate MSUB.

The depth (or sketch length) of each of the plurality of second laser irradiation regions CH2 may be longer than the depth (or sketch length) of each of the plurality of first laser irradiation regions CH 1. As shown in fig. 67, the depth (or sketch length) of the laser light irradiation region may be adjusted according to the repetition rate, the processing speed, and the pulse energy of the first laser light LR1 and the second laser light LR 2. Since the depth (or sketch length) of the first laser light irradiation region CH1 formed by the first laser light LR1 is different from the depth (or sketch length) of the second laser light irradiation region CH2 formed by the second laser light LR2, the first laser light LR1 and the second laser light LR2 have differences in repetition rate, processing speed, pulse energy, and the like.

For example, the first laser light LR1 may be irradiated at a repetition rate of 10kHz to 250kHz, a processing speed of 10mm/s to 250mm/s, and a pulse energy of 10 μj to 300 μj. However, in order to make the first laser irradiation area CH1 have a depth of about 225 μm or more from the first surface of the mother substrate MSUB, it is preferable to irradiate at a repetition rate of approximately 17.5kHz to 125kHz, a treatment speed of 17.5mm/s to 125mm/s, and a pulse energy of 25 μj to 178 μj.

In addition, the second laser light LR2 may be irradiated at a repetition rate of 1kHz to 50kHz, a processing speed of 1mm/s to 50mm/s, and a pulse energy of 10 μj to 300 μj. However, in order to make the second laser irradiation region CH2 have a depth of about 400 μm to 500 μm from the first surface of the mother substrate MSUB, irradiation may be performed at a repetition rate of about 10kHz, a treatment speed of 10mm/s, and a pulse energy of 60 μj to 178 μj. For example, when the second laser LR2 forms the circular second cutting line CL2, the processing speed of the second laser LR2 may be lower than that of the first laser LR1. Since the first laser light LR1 forms the first cutting line CL1 along the edge of each of the plurality of display units DPC.

One-sided tolerance SE3 of second laser light LR2 can be within approximately 50 μm and two-sided tolerance of second laser light LR2 can be within approximately 100 μm. When the plurality of second laser irradiation regions CH2 are formed with the second laser light LR2, one side tolerance SE2 of the second laser light LR2 may be a cutting error in one direction (for example, the X-axis direction).

The distance from the second dam HDAM2 to the edge TEG of the through-hole TH may vary according to a side tolerance SE3 of the second laser light LR 2. When the second laser light LR2 is properly irradiated to the position to be irradiated, the distance from the second dam HDAM2 to the second laser irradiation area CH2 is defined as "HDCH".

When the second laser light LR2 is irradiated to the left with the maximum value of the one-side tolerance SE3 of the second laser light LR2, the distance from the second dam HDAM2 to the second laser irradiation area CH2 may be "HDCH-SE3". In contrast, when the second laser light LR2 is irradiated to the right with the maximum value of the one-side tolerance SE3 of the second laser light LR2, the distance from the second dam HDAM2 to the second laser irradiation area CH2 may be "hdch+se3".

Since the substrate SUB of the display unit DPC is separated from the mother substrate MSUB based on the second laser irradiation area CH2 in the etching process, a distance from the second dam HDAM2 to the second laser irradiation area CH2 may be substantially the same as a minimum distance from the second dam HDAM2 to the edge TEG of the through hole TH in the display panel 100 shown in fig. 74. Therefore, in some cases, the minimum distance from the second dam HDAM2 to the edge TEG of the through hole TH in the display panel 100 may have a difference of 100 μm, which is a distance corresponding to "one-side tolerance SE3×2" (or "double-side tolerance") of the second laser LR 2.

That is, in the display panel 100 shown in fig. 74, the minimum distance from the second dam HDAM2 to the edge TEG of the through hole TH may be "HDCH-SE3" to "hdch+se3". For example, when the distance from the second dam HDAM2 to the second laser irradiation area CH2 is 100 μm and the side tolerance SE3 of the second laser light LR2 is 50 μm, in the display panel 100 shown in fig. 74, the minimum distance from the second dam HDAM2 to the edge TEG of the through hole TH may be at least 50 μm or at most 150 μm.

As described above, the side tolerance SE3 of the second laser LR2 is 50 μm, but the side tolerance SE1 of the cutting member CWD such as a cutting wheel is 100 μm. That is, since the one-side tolerance SE3 of the second laser LR2 is smaller than the one-side tolerance SE1 of the cutting member CWD such as the cutting wheel, when cutting is performed using the second laser LR2, the minimum distance from the second dam HDAM2 to the edge TEG of the through hole TH can be reduced as compared with the case when cutting is performed using the cutting member CWD such as the cutting wheel when cutting is performed using the second laser LR 2.

Fifth, as shown in fig. 99, the second protective films PRF2 are attached on the plurality of first protective films PRF 1. (S350 in FIG. 90)

The second protective film PRF2 may be attached on the mother substrate MSUB exposed without being covered with the plurality of first protective films PRF1 and on the plurality of first protective films PRF 1. The second protective film PRF2 may cover the plurality of first laser irradiation regions CH1 and the plurality of second laser irradiation regions CH2. The second protective film PRF2 may be an acid-resistant film for protecting the plurality of display units DPC from the etchant ECH in the etching process of the mother substrate MSUB to be performed in the next step.

Sixth, as shown in fig. 94, 95, 99 and 100, by spraying the etchant ECH on the second surface of the mother substrate MSUB without a separate mask, the mother substrate MSUB is cut along the plurality of first and second laser irradiation regions CH1 and CH2 while reducing the thickness of the mother substrate MSUB, and the second protective film PRF2 is peeled off. (S360 in FIG. 90)

When the etchant ECH is sprayed on the second surface of the mother substrate MSUB, the mother substrate MSUB may be reduced from the first thickness T1 'to the second thickness T2'. Since the mother substrate MSUB is etched without a separate mask, the mother substrate MSUB can be uniformly etched throughout the entire area of the second surface.

Each of the plurality of first laser irradiation regions CH1 is a physical hole formed by the first laser LR1 and a periphery of the physical hole, and may include a region whose physical property is changed by the first laser LR 1. Alternatively, each of the plurality of first laser irradiation regions CH1 may be a region whose physical properties are changed by the first laser LR1 without physical holes. For this reason, the etching rate of the etchant ECH in each of the plurality of first laser irradiation regions CH1 may be higher than that in other regions of the mother substrate MSUB where the laser is not irradiated.

Each of the plurality of second laser irradiation regions CH2 is formed as a physical hole formed by the second laser LR2 and a periphery of the physical hole, and may include a region whose physical property is changed by the second laser LR 2. Alternatively, each of the plurality of second laser irradiation regions CH2 may be a region whose physical properties are changed by the second laser LR2 without physical holes. For this reason, the etching rate of the etchant ECH in each of the plurality of second laser irradiation regions CH2 may be higher than that in other regions of the mother substrate MSUB where the laser is not irradiated.

At this time, as shown in fig. 63 and 98, since the depth of each of the plurality of second laser irradiation regions CH2 is greater than the depth of each of the plurality of first laser irradiation regions CH1, the etchant ECH may first penetrate the plurality of second laser irradiation regions CH2 instead of the plurality of first laser irradiation regions CH1. That is, since the plurality of second laser irradiation regions CH2 are etched with a thinning process in which the thickness of the mother substrate MSUB is reduced by the etchant ECH, the substrate SUB forms a tapered profile in the through hole TH formed by the second laser irradiation regions CH2 by isotropic etching. In contrast, when thinning is performed, etching is not performed on the plurality of first laser irradiation regions CH1. Accordingly, the length and angle of the inclined direction of the first inclined surface IP1_1 at the edge EG of the substrate SUB formed by the plurality of first laser irradiation regions CH1 may be different from those of the first inclined surface IP1_4 in the through hole TH formed by the plurality of second laser irradiation regions CH 2.

For example, as shown in fig. 19 and 101, the length of the first inclined surface IP1_1 in the inclined direction at the edge EG of the display panel 100 may be shorter than the length of the first inclined surface IP1_4 in the inclined direction at the edge TEG of the through-hole TH. The angle θ6 of the first inclined surface ip1_1 with respect to the edge EG of the display panel 100 may be smaller than the angle θ11 of the first inclined surface ip1_4 with respect to the edge TEG of the through hole TH. The angle θ6 of the first inclined surface ip1_1 with respect to the edge EG of the display panel 100 may be an angle between the side surface ss_1 and the first inclined surface ip1_1. The angle θ11 of the first inclined surface IP1_4 with respect to the edge TEG of the through-hole TH may be an angle between the side surface ss_4 of the edge TEG of the through-hole TH and the first inclined surface IP 1_4.

Seventh, as shown in fig. 96 and 101, the driving IC 200 and the circuit board 300 are attached to each of the plurality of display units DPC, and the first protective film is peeled off from each of the plurality of display units DPC. (S370 of FIG. 90)

As described above, the thickness of the mother substrate MSUB may be reduced by using a laser and an etching process, and the substrate SUB of each of the plurality of display units DPC may be separated from the mother substrate MSUB. Further, since the through holes TH can be formed, the efficiency of the manufacturing process can be improved.

FIG. 102 is a flow diagram illustrating a method of manufacturing a display device in accordance with one or more embodiments. Fig. 103 is a cross-sectional view illustrating a method of manufacturing a display device according to one or more embodiments.

Since the embodiment of fig. 102 is different from the embodiment of fig. 90 in that a step S380 of removing the organic planarization layer ORL provided in the region where the through holes TH will be formed is added, the step S380 will be described in more detail hereinafter.

As shown in fig. 103, before the first laser light LR1 and the second laser light LR2 are irradiated on the second surface of the mother substrate MSUB, the organic planarization layer ORL disposed in the region where the through holes TH are to be formed may be removed by laser ablation. In this case, the inorganic layers of the first and second encapsulation inorganic layers TFE1 and TFE3 and the thin film transistor layer TFTL may also be removed.

When the organic planarization layer ORL is not removed before the first laser light LR1 and the second laser light LR2 are irradiated, cracks may be generated in the organic planarization layer ORL or foreign matters peeled from the organic planarization layer ORL may be generated due to the organic planarization layer ORL being physically divided. In this case, as shown in fig. 76 and 77, the substrate SUB may protrude from the organic planarization layer ORL in the through holes TH.

Fig. 104 is a flowchart illustrating a method of manufacturing a display device in accordance with one or more embodiments. Fig. 105 is a cross-sectional view illustrating a method of manufacturing a display device according to one or more embodiments.

Since the embodiment of fig. 104 is different from the embodiment of fig. 90 in that a step S390 of removing the organic planarization layer ORL disposed in the region where the through holes TH will be formed is added, the step S390 will be described in more detail hereinafter.

As shown in fig. 105, a plurality of first and second laser irradiation regions CH1 and CH2 are formed by irradiating the first and second laser light LR1 and LR2 on the second surface of the mother substrate MSUB, and the organic planarization layer ORL disposed in the through hole TH may be removed after the plurality of display units DPC having the through hole TH are divided by spraying the etchant ECH on the mother substrate MSUB. For example, the organic planarization layer ORL disposed in the through hole TH may be removed by a laser cutting process. The inorganic layers of the first and second encapsulation inorganic layers TFE1 and TFE3 and the thin film transistor layer TFTL disposed in the through holes TH may be removed together with the organic planarization layer ORL. In this case, as shown in fig. 78 and 79, the organic planarization layer ORL may protrude from the substrate SUB in the through holes TH.

Fig. 106 is a perspective view illustrating a display device in accordance with one or more embodiments. Fig. 107 is a plan view illustrating a display panel and a drive IC according to one or more embodiments.

Referring to fig. 106 and 107, the display device 10 according to one or more embodiments may include a curved area BA and a pad area PDA disposed in a non-display area NDA.

The curved area BA may be disposed between the display area DA and the pad area PDA in the second direction (Y-axis direction). The bending area BA may extend in the first direction (X-axis direction). The bending area BA refers to an area of the display panel 100 bent downward. When the bending area BA is bent under the display panel 100, a plurality of driving ICs 200 and circuit boards 300 may be disposed under the display panel 100.

The pad area PDA may be a lower edge area of the display panel 100. The pad area PDA may be an area in which the display pad PD connected to the circuit board 300 and the first and second driving pads DPD1 and DPD2 connected to the driving IC 200 are disposed.

Fig. 108 is a cross-sectional view showing an example of the display device taken along the line XA-XA 'and the line XB-XB' of fig. 106. Fig. 109 is a cross-sectional view showing an example of a display device in which the bending region of fig. 108 is bent.

Referring to fig. 108 and 109, the display panel 100 may include a first substrate SUB1 having a rigid material and a second substrate SUB2 made of a polymeric resin having a flexible material.

The first substrate SUB1 may be made of ultra-thin glass (UTG) having a thickness of about 500 μm or less, but embodiments of the present disclosure are not limited thereto. The first substrate SUB1 may include a first SUB substrate SSUB1 disposed in the display area DA and a second SUB substrate SSUB2 disposed in the pad area PDA.

The second substrate SUB2 may be made of a polymeric resin having a thickness smaller than that of the first substrate SUB 1. For example, the second substrate SUB2 may be formed of an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. Since the second substrate SUB2 is made of a polymer resin, it may be referred to as a plastic substrate. Alternatively, since the second substrate SUB2 is formed of an organic material, it may be referred to as an organic layer.

The first substrate SUB1 may not be disposed in the bending area BA. That is, since the second substrate SUB2 having a flexible material is included in the bending area BA, it can be easily bent.

The thin film transistor layer TFTL may be disposed in the display area DA, the bending area BA, and the pad area PDA.

The passivation layer PRTL may be disposed on the thin film transistor layer TFTL in the bending region BA. The passivation layer PRTL may be a layer for protecting the thin film transistor layer TFTL exposed to the outside in the bending region BA. The passivation layer PRTL may be formed of an organic material such as acryl resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

The cross-sectional shape of the substrate SUB at the edge BEG of the bending area BA may be different from the cross-sectional shape of the substrate SUB at the edge EG of the display panel 100. The cross-sectional shape of the substrate SUB at the edge BEG of the bending area BA may be different from the cross-sectional shape of the substrate SUB at the edge TEG of the through-hole TH. The cross-sectional shape of the substrate SUB at the edge EG of the display panel 100 may be different from the cross-sectional shape of the substrate SUB at the edge TEG of the through-hole TH.

As in step S330 of fig. 90, when the edge EG of the display panel 100 is formed by spraying the etchant ECH after the first laser light LR1 is irradiated, the first substrate SUB1 may include a side surface ss_1 and a first inclined surface ip1_1 at the edge EG of the display panel 100. An angle θ6 between the side surface ss_1 and the first inclined surface ip1_1 and an angle θ7 between the first inclined surface ip1_1 and the bottom surface BS at the edge EG of the display panel 100 may be obtuse angles.

As in step S340 of fig. 90, when the edge TEG of the through-hole TH is formed by spraying the etchant ECH after the second laser light LR2 is irradiated, the first substrate SUB1 may include the side surface ss_4 and the first inclined surface ip1_4 at the edge TEG of the through-hole TH. The angle θ10 between the side surface ss_4 and the upper surface US of the edge TEG of the through-hole TH may be about 90 degrees. An angle θ11 between the side surface ss_4 and the first inclined surface ip1_4 and an angle θ12 between the first inclined surface ip1_4 and the bottom surface BS at the edge TEG of the through hole TH may be obtuse angles.

As described in steps S330 and S340 of fig. 90, since the depth (or sketch length) of each of the first laser irradiation regions CH1 formed by the first laser LR1 is different from the depth (or sketch length) of each of the second laser irradiation regions CH2 formed by the second laser LR2, the cross-sectional shapes of the side surface ss_1 and the first inclined surface IP1_1 of the edge EG of the display panel 100 may be different from the cross-sectional shapes of the side surface ss_4 and the first inclined surface IP1_4 of the edge TEG of the through hole TH.

For example, the side surface ss_1 of the edge EG of the display panel 100 may have a length in the third direction (Z-axis direction) longer than the side surface ss_4 of the edge TEG of the through hole TH. The length of the first inclined surface ip1_1 of the edge EG of the display panel 100 in the inclined direction may be smaller than the length of the first inclined surface ip1_4 of the edge TEG of the through hole TH in the inclined direction.

In addition, an angle θ6 between the side surface ss_1 and the first inclined surface ip1_1 at the edge EG of the display panel 100 may be greater than an angle θ11 between the side surface ss_4 and the first inclined surface ip1_4 at the edge TEG of the through hole TH. Further, an angle θ7 between the first inclined surface ip1_1 at the edge EG of the display panel 100 and the bottom surface BS may be smaller than an angle θ12 between the first inclined surface ip1_4 at the edge TEG of the through hole TH and the bottom surface BS.

At the edge BEG of the bending area BA, the side surface ss_5 of the first substrate SUB1 may form an angle of substantially 90 degrees with the upper surface US and the bottom surface BS of the first substrate SUB 1.

Fig. 110 is a cross-sectional view showing an example of the display device taken along the line XA-XA 'and the line XB-XB' of fig. 106. Fig. 111 is a cross-sectional view showing an example of a display device in which the bending region of fig. 110 is bent.

Referring to fig. 110 and 111, when the edge BEG of the bending area BA is formed by spraying the etchant ECH, the side surface ss_6 of the first substrate SUB1 at the edge BEG of the bending area BA may be an inclined surface formed obliquely. The angle θ13 formed between the side surface ss_6 of the first substrate SUB1 and the upper surface US at the edge BEG of the curved region BA may be an acute angle, and the angle θ14 between the side surface ss_6 of the first substrate SUB1 and the bottom surface BS may be an obtuse angle.

The length of the side surface ss_6 of the edge BEG of the bending area BA of the first substrate SUB1 in the third direction (Z-axis direction) may be longer than the length of the side surface ss_1 of the edge EG of the display panel 100 in the third direction (Z-axis direction) and the length of the first inclined surface IP1_1 in the inclined direction and the length of the side surface ss_4 of the edge TEG of the through hole TH in the third direction (Z-axis direction) and the length of the first inclined surface IP1_4 in the inclined direction. An angle θ13 between the side surface ss_6 and the upper surface US of the first substrate SUB1 at the edge BEG of the bending area BA may be smaller than an angle θ5 between the side surface ss_1 and the upper surface US of the first substrate SUB1 at the edge EG of the display panel 100, an angle θ6 between the side surface ss_1 and the first inclined surface ip1_1 of the first substrate SUB1, and an angle θ7 formed between the first inclined surface ip1_1 and the bottom surface BS of the first substrate SUB 1.

A method of forming the side surface ss_6 of the first substrate SUB1 as a surface inclined obliquely at the edge BEG of the bending area BA will be described later with reference to fig. 124.

Fig. 112 is a cross-sectional view showing an example of the display device taken along the line XA-XA 'and the line XB-XB' of fig. 106. Fig. 113 is a cross-sectional view showing an example of a display device in which the bending region of fig. 112 is bent.

Referring to fig. 112 and 113, a cross-sectional shape of the substrate SUB at an edge BEG of the bending area BA may be substantially the same as a cross-sectional shape of the substrate SUB at an edge EG of the display panel 100. The cross-sectional shape of the substrate SUB at the edge BEG of the bending area BA may be different from the cross-sectional shape of the substrate SUB at the edge TEG of the through-hole TH.

The edge BEG of the bending area BA may be formed through the same manufacturing process as the edge EG of the display panel 100. That is, when the edge BEG of the bending area BA is formed by spraying the etchant ECH after the first laser light LR1 is irradiated, the first substrate SUB1 at the edge BEG of the bending area BA may include the side surface ss_7 and the first inclined surface ip1_7. The angle θ15 between the side surface ss_7 and the upper surface US at the edge BEG of the curved region BA may be about 90 degrees. The angle θ16 between the side surface ss_7 and the first inclined surface ip1_7 and the angle θ17 between the first inclined surface ip1_7 and the bottom surface BS at the edge BEG of the curved region BA may be obtuse angles.

In this case, the length of the side surface ss_7 of the edge BEG of the bending area BA in the third direction (Z-axis direction) may be substantially the same as the length of the side surface ss_1 of the edge EG of the display panel 100 in the third direction (Z-axis direction). The length of the first inclined surface ip1_7 of the edge BEG of the bending area BA in the inclined direction may be substantially the same as the length of the first inclined surface ip1_1 of the edge EG of the display panel 100 in the inclined direction.

In addition, the length of the side surface ss_7 of the edge BEG of the bending area BA in the third direction (Z-axis direction) may be longer than the length of the side surface ss_4 of the edge TEG of the through hole TH in the third direction (Z-axis direction). The length of the first inclined surface ip1_7 of the edge BEG of the bending area BA in the inclined direction may be smaller than the length of the first inclined surface ip1_4 of the edge TEG of the through hole TH in the inclined direction.

In addition, an angle θ16 between the side surface ss_7 and the first inclined surface ip1_7 at the edge BEG of the bending area BA may be substantially the same as an angle θ6 between the side surface ss_1 and the first inclined surface ip1_1 at the edge EG of the display panel 100. Further, an angle θ17 between the first inclined surface ip1_7 and the bottom surface BS at the edge BEG of the bending area BA may be substantially the same as an angle θ7 between the first inclined surface ip1_1 and the bottom surface BS at the edge EG of the display panel 100.

In addition, an angle θ16 between the side surface ss_7 and the first inclined surface ip1_7 at the edge BEG of the bending area BA may be greater than an angle θ11 between the side surface ss_4 and the first inclined surface ip1_4 at the edge TEG of the through hole TH. Further, an angle θ17 between the first inclined surface ip1_7 and the bottom surface BS at the edge BEG of the bending area BA may be smaller than an angle θ12 between the first inclined surface ip1_4 and the bottom surface BS at the edge TEG of the through hole TH.

Fig. 114 is a cross-sectional view showing an example of the display device taken along the line XA-XA 'and the line XB-XB' of fig. 106. Fig. 115 is a cross-sectional view showing an example of a display device in which the bending region of fig. 114 is bent.

Referring to fig. 114 and 115, a cross-sectional shape of the substrate SUB at an edge BEG of the bending area BA may be different from a cross-sectional shape of the substrate SUB at an edge EG of the display panel 100. The cross-sectional shape of the substrate SUB at the edge BEG of the bending area BA may be substantially the same as the cross-sectional shape of the substrate SUB at the edge TEG of the through-hole TH.

The edge BEG of the bending area BA may be formed through the same manufacturing process as the edge TEG of the through-hole TH. That is, when the edge BEG of the bending area BA is formed by spraying the etchant ECH after the second laser light LR2 is irradiated, the first substrate SUB1 may include the side surface ss_8 and the first inclined surface ip1_8 at the edge BEG of the bending area BA. The angle θ18 between the side surface ss_8 and the upper surface US at the edge BEG of the curved region BA may be about 90 degrees. The angle θ19 between the side surface ss_8 and the first inclined surface ip1_8 and the angle θ20 between the first inclined surface ip1_8 and the bottom surface BS at the edge BEG of the curved region BA may be obtuse angles.

In this case, the length of the side surface ss_8 of the edge BEG of the bending area BA in the third direction (Z-axis direction) may be smaller than the length of the side surface ss_1 of the edge EG of the display panel 100 in the third direction (Z-axis direction). The length of the first inclined surface ip1_8 of the edge BEG of the bending area BA in the inclined direction may be longer than the length of the first inclined surface ip1_8 of the edge EG of the display panel 100 in the inclined direction.

In addition, the length of the side surface ss_8 of the edge BEG of the bending area BA in the third direction (Z-axis direction) may be substantially the same as the length of the side surface ss_4 of the edge TEG of the through hole TH in the third direction (Z-axis direction). The length of the first inclined surface ip1_8 of the edge BEG of the bending area BA in the inclined direction may be substantially the same as the length of the first inclined surface ip1_4 of the edge TEG of the through hole TH in the inclined direction.

In addition, an angle θ19 between the side surface ss_8 and the first inclined surface ip1_8 at the edge BEG of the bending area BA may be smaller than an angle θ6 between the side surface ss_1 and the first inclined surface ip1_1 at the edge EG of the display panel 100. Further, an angle θ20 between the first inclined surface ip1_8 and the bottom surface BS at the edge BEG of the bending area BA may be greater than an angle θ7 between the first inclined surface ip1_1 and the bottom surface BS at the edge EG of the display panel 100.

In addition, an angle θ19 between the side surface ss_8 and the first inclined surface ip1_8 at the edge BEG of the bending area BA may be substantially the same as an angle θ11 between the side surface ss_4 and the first inclined surface ip1_4 at the edge TEG of the through hole TH. Further, an angle θ20 between the first inclined surface ip1_8 and the bottom surface BS at the edge BEG of the bending area BA may be substantially the same as an angle θ12 between the first inclined surface ip1_4 and the bottom surface BS at the edge TEG of the through-hole TH.

Fig. 116 is a cross-sectional view showing an example of the display device taken along the line XA-XA 'and the line XB-XB' of fig. 106. Fig. 117 is a cross-sectional view showing an example of a display device in which the bending region of fig. 116 is bent.

Referring to fig. 116 and 117, the first substrate SUB1 disposed in the pad area PDA may be removed. In this case, the second substrate SUB2 may be fixed to the bottom surface of the panel bottom cover PB by the adhesive member 310. The thickness of the display panel 100 may be reduced by removing the first substrate SUB1 from the pad area PDA.

Fig. 118 is a cross-sectional view showing an example of the display device taken along the line XA-XA 'and the line XB-XB' of fig. 106. Fig. 119 is a cross-sectional view showing an example of a display device in which the bending region in fig. 118 is bent.

Referring to fig. 118 and 119, instead of removing the first substrate SUB1 disposed in the pad area PDA, a support substrate SSUB having a thickness smaller than that of the first substrate SUB1 may be included. The support substrate SSUB may be formed of a rigid material. For example, the support substrate SSUB may be a plastic film such as Polycarbonate (PC) or polyethylene terephthalate (PET).

In this case, the support base SSUB may be fixed to the bottom surface of the panel bottom cover PB by the adhesive member 310. The thickness of the display panel 100 may be reduced by replacing the first substrate SUB1 in the pad area PDA with the support substrate SSUB having a thickness smaller than that of the first substrate SUB1.

Fig. 120 is a cross-sectional view showing an example of the display device taken along the line XA-XA 'and the line XB-XB' of fig. 106. Fig. 121 is a cross-sectional view showing an example of a display device in which the bending region of fig. 120 is bent.

Referring to fig. 120 and 121, the second substrate SUB2 may be disposed in the bending area BA and may be deleted from the display area DA and the pad area PDA. In this case, the thin film transistor layer TFTL may be directly disposed on the first substrate SUB1 in the display area DA and the pad area PDA.

Fig. 122A is a cross-sectional view showing an example of the display device taken along the line XA-XA 'and the line XB-XB' of fig. 106. Fig. 122B is a cross-sectional view showing an example of a display device in which the bending region of fig. 122A is bent.

Referring to fig. 122A and 122B, the second substrate SUB2 may be omitted from the display panel 100. In this case, an organic layer of the thin film transistor layer TFTL may be used as the second substrate SUB2. The passivation layer PRTL may be disposed on the thin film transistor layer TFTL.

Fig. 123A is a cross-sectional view showing an example of the display device taken along the line XA-XA 'and the line XB-XB' of fig. 106. Fig. 123B is a cross-sectional view showing an example of a display device in which the bending region of fig. 123A is bent.

Referring to fig. 123A and 123B, a cross-sectional shape of the substrate SUB at an edge BEG of the bending area BA may be substantially the same as a cross-sectional shape of the substrate SUB at an edge EG of the display panel 100. The cross-sectional shape of the substrate SUB at the edge BEG of the bending area BA may be substantially the same as the cross-sectional shape of the substrate SUB at the edge TEG of the through-hole TH.

The edge BEG of the bending area BA and the edge TEG of the through-hole TH may be formed through the same manufacturing process as the edge EG of the display panel 100.

Since the edge BEG of the bending area BA is substantially the same as the edge BEG of the bending area BA described with reference to fig. 112 and 113, a description of the edge BEG of the bending area BA will be omitted.

When the edge TEG of the through-hole TH is formed by spraying the etchant ECH after the first laser light LR1 is irradiated, the first substrate SUB1 may include a side surface ss_9 and a first inclined surface ip1_9 at the edge TEG of the through-hole TH. The angle θ21 between the side surface ss_9 and the upper surface US at the edge TEG of the through-hole TH may be about 90 degrees. An angle θ22 between the side surface ss_9 and the first inclined surface ip1_9 and an angle θ23 between the first inclined surface ip1_9 and the bottom surface BS at the edge TEG of the through hole TH may be obtuse angles.

In this case, the length of the side surface ss_9 of the edge TEG of the through-hole TH in the third direction (Z-axis direction) may be substantially the same as the length of the side surface ss_1 of the edge EG of the display panel 100 in the third direction (Z-axis direction). The length of the first inclined surface ip1_9 of the edge TEG of the through-hole TH in the inclined direction may be substantially the same as the length of the first inclined surface ip1_1 of the edge EG of the display panel 100 in the inclined direction.

In addition, an angle θ22 between the side surface ss_9 and the first inclined surface ip1_9 at the edge TEG of the through-hole TH may be substantially the same as an angle θ6 between the side surface ss_1 and the first inclined surface ip1_1 at the edge EG of the display panel 100. Further, an angle θ23 between the first inclined surface ip1_9 and the bottom surface BS at the edge TEG of the through-hole TH may be substantially the same as an angle θ7 between the first inclined surface ip1_1 and the bottom surface BS at the edge EG of the display panel 100.

Fig. 123C is a cross-sectional view showing an example of the display device taken along the line XA-XA 'and the line XB-XB' of fig. 106. Fig. 123D is a cross-sectional view showing an example of a display device in which the bending region of fig. 123C is bent.

Referring to fig. 123C and 123D, a cross-sectional shape of the substrate SUB at an edge BEG of the bending area BA may be substantially different from a cross-sectional shape of the substrate SUB at an edge EG of the display panel 100. The cross-sectional shape of the substrate SUB at the edge BEG of the bending area BA may be substantially different from the cross-sectional shape of the substrate SUB at the edge TEG of the through-hole TH. The cross-sectional shape of the substrate SUB at the edge EG of the display panel 100 may be substantially the same as the cross-sectional shape of the substrate SUB at the edge TEG of the through-hole TH.

The edge TEG of the through-hole TH may be formed through the same manufacturing process as the edge EG of the display panel 100. The edge BEG of the bending area BA may be formed through a different manufacturing process from the edge TEG of the through hole TH and the edge EG of the display panel 100.

Since the edge BEG of the bending area BA is substantially the same as the edge BEG of the bending area BA described with reference to fig. 114 and 115, a description of the edge BEG of the bending area BA will be omitted.

Since the edge TEG of the through-hole TH is substantially the same as that described with reference to fig. 123A and 123B, a description of the edge TEG of the through-hole TH will be omitted.

Fig. 123E is a cross-sectional view showing an example of the display device taken along the line XA-XA 'and the line XB-XB' of fig. 106. Fig. 123F is a cross-sectional view showing an example of a display device in which the bending region of fig. 123E is bent.

Referring to fig. 123E and 123F, a cross-sectional shape of the substrate SUB at an edge BEG of the bending area BA may be substantially different from a cross-sectional shape of the substrate SUB at an edge EG of the display panel 100. The cross-sectional shape of the substrate SUB at the edge BEG of the bending area BA may be substantially different from the cross-sectional shape of the substrate SUB at the edge TEG of the through-hole TH. The cross-sectional shape of the substrate SUB at the edge EG of the display panel 100 may be substantially the same as the cross-sectional shape of the substrate SUB at the edge TEG of the through-hole TH.

Since the edge BEG of the bending area BA is substantially the same as the edge BEG of the bending area BA described with reference to fig. 116 and 117, a description of the edge BEG of the bending area BA will be omitted.

Fig. 123G is a cross-sectional view showing an example of the display device taken along the line XA-XA 'and the line XB-XB' of fig. 106. Fig. 123H is a cross-sectional view showing an example of a display device in which the bending region of fig. 123G is bent.

Referring to fig. 123G and 123H, a cross-sectional shape of the substrate SUB at an edge BEG of the bending area BA is substantially different from a cross-sectional shape of the substrate SUB at an edge EG of the display panel 100. The cross-sectional shape of the substrate SUB at the edge BEG of the bending area BA may be substantially the same as the cross-sectional shape of the substrate SUB at the edge TEG of the through-hole TH. The cross-sectional shape of the substrate SUB at the edge EG of the display panel 100 may be substantially different from the cross-sectional shape of the substrate SUB at the edge TEG of the through-hole TH.

Since the edge TEG of the through-hole TH is formed by spraying the etchant ECH, the side surface ss_10 of the first substrate SUB1 at the edge TEG of the through-hole TH may be an inclined surface formed obliquely. The angle θ24 formed between the side surface ss_10 of the first substrate SUB1 and the upper surface US at the edge TEG of the through hole TH may be an acute angle, and the angle θ25 formed between the side surface ss_10 of the first substrate SUB1 and the bottom surface BS at the edge TEG of the through hole TH may be an obtuse angle.

The length of the side surface ss_10 of the first substrate SUB1 of the edge TEG of the through hole TH in the third direction (Z-axis direction) may be longer than the length of the side surface ss_1 of the edge EG of the display panel 100 in the third direction (Z-axis direction) and the length of the first inclined surface IP1_1 of the edge EG of the display panel 100 in the third direction (Z-axis direction). An angle θ24 formed between the upper surface US and the side surface ss_10 of the first substrate SUB1 at the edge TEG of the through hole TH is smaller than an angle θ5 between the side surface ss_1 and the upper surface US of the first substrate SUB1, an angle θ6 between the side surface ss_1 and the first inclined surface ip1_1 of the first substrate SUB1, and an angle θ7 formed between the first inclined surface ip1_1 and the bottom surface BS of the first substrate SUB1 at the edge EG of the display panel 100.

The edge TEG of the through-hole TH may be formed in the same manufacturing process as the edge BEG of the bending area BA. The edge EG of the display panel 100 may be formed in a different manufacturing process from the edge TEG of the through hole TH and the edge BEG of the bending area BA.

Since the edge BEG of the bending area BA is substantially the same as the edge BEG of the bending area BA described with reference to fig. 110 and 111, a description of the edge BEG of the bending area BA will be omitted.

Fig. 123I is a cross-sectional view showing an example of the display device taken along the line XA-XA 'and the line XB-XB' of fig. 106. Fig. 123J is a cross-sectional view showing an example of a display device in which the bending region of fig. 123I is bent.

Referring to fig. 123I and 123J, a cross-sectional shape of the substrate SUB at an edge BEG of the bending area BA, a cross-sectional shape of the substrate SUB at an edge EG of the display panel 100, and a cross-sectional shape of the substrate SUB at an edge TEG of the through-hole TH may be substantially the same.

Since the edge EG of the display panel 100 is formed by spraying the etchant ECH, the side surface ss_11 of the first substrate SUB1 at the edge EG of the display panel 100 may be an inclined surface formed obliquely. The angle θ26 formed between the side surface ss_11 and the upper surface US at the edge EG of the first substrate SUB1 is an acute angle, and the angle θ27 formed between the side surface ss_11 and the bottom surface BS of the first substrate SUB1 is an obtuse angle.

The angle θ26 formed between the upper surface US and the side surface ss_11 of the first substrate SUB1 at the edge EG of the display panel 100 may be substantially the same as the angle θ24 formed between the upper surface US and the side surface ss_10 of the first substrate SUB1 at the edge TEG of the through hole TH, and the angle θ13 formed between the upper surface US and the side surface ss_6 of the first substrate SUB1 at the edge TEG of the bending region BA. In addition, an angle θ27 between the side surface ss_11 and the bottom surface BS of the first substrate SUB1 at the edge EG of the display panel 100 may be substantially the same as an angle θ25 formed between the side surface ss_10 and the bottom surface BS of the first substrate SUB1 at the edge TEG of the through hole TH and an angle θ14 formed between the bottom surface BS and the side surface ss_6 of the first substrate SUB1 at the edge TEG of the bending region BA.

The edge EG of the display panel 100, the edge TEG of the through holes TH, and the edge BEG of the bending area BA may be formed by the same manufacturing process.

Since the edge BEG of the bending area BA is substantially the same as the edge BEG of the bending area BA described with reference to fig. 110 and 111, a description of the edge BEG of the bending area BA will be omitted. Further, since the edge TEG of the through-hole TH is substantially the same as that of the through-hole TH described with reference to fig. 123G and 123H, a description of the edge TEG of the through-hole TH will be omitted.

FIG. 124 is a flow diagram illustrating a method of manufacturing a display device in accordance with one or more embodiments. Fig. 125 through 131 are perspective views illustrating a method of manufacturing a display device according to one or more embodiments. Fig. 132 to 136 are cross-sectional views illustrating a method of manufacturing a display device according to one or more embodiments.

First, as shown in fig. 125, a plurality of display units DPC are formed on a first surface of a mother substrate MSUB. (S410 in FIG. 124)

Second, a plurality of first protective films PRF1 are attached on the plurality of display units DPC, and the plurality of display units DPC are inspected. (S420 in FIG. 124)

Third, as shown in fig. 126 and 132 to 135, the second protective film PRF2 is attached on the first surface of the mother substrate MSUB, the third protective film PRF3 is attached on the second surface of the mother substrate MSUB, and a portion of the third protective film PRF3 disposed in the bending area BA is removed. Then, an etchant ECH is sprayed on a second surface of the mother substrate MSUB opposite to the first surface to remove a portion of the mother substrate MSUB disposed in the bending region BA, and the third protective film PRF3 is removed. (S430 in FIG. 124)

First, as shown in fig. 132, the second protective film PRF2 is attached on the first surface of the mother substrate MSUB, and the third protective film PRF3 is attached on the second surface of the mother substrate MSUB. The second protective film PRF2 may be attached on the mother substrate MSUB and the plurality of first protective films PRF1 that are exposed without being covered with the plurality of first protective films PRF 1. The second and third protective films PRF2 and PRF3 may be acid-resistant films for protecting the plurality of display units DPC from the etchant ECH in the etching process of the mother substrate MSUB to be performed in the next step.

Then, as shown in fig. 133, a portion of the third protective film PRF3 corresponding to the bending region BA is removed.

Then, as shown in fig. 134, the mother substrate MSUB exposed without being covered with the third protective film PRF3 is etched by spraying the etchant ECH on the second surface of the mother substrate MSUB. Thus, a portion of the mother substrate MSUB disposed in the bending area BA may be removed. Accordingly, the thickness Tba of the mother substrate MSUB in the bending region BA may be smaller than the thickness T1 of the mother substrate MSUB in the remaining region other than the bending region BA.

Then, as shown in fig. 135, the third protective film PRF3 is peeled from the second surface of the mother substrate MSUB.

Fourth, as shown in fig. 127, by irradiating the first laser light LR1 on the second surface of the mother substrate MSUB, a plurality of first laser irradiation regions CH1 are formed along the edges EG of the plurality of display units DPC and the edges BEG of the bending regions BA. (S440 in FIG. 124)

Fifth, as shown in fig. 128, a plurality of second laser irradiation regions CH2 for forming through holes TH in each of the plurality of display units DPC are formed by irradiating the second laser LR2 on the second surface of the mother substrate MSUB. (S450 in FIG. 124)

Sixth, as shown in fig. 129, 130 and 136, the etchant ECH is sprayed on the second surface of the mother substrate MSUB without a separate mask to reduce the thickness of the mother substrate MSUB while cutting the mother substrate MSUB along the plurality of first and second laser irradiation regions CH1 and CH2, removing the mother substrate MSUB of the bending region BA, and peeling the second protective film PRF2.

(S460 in FIG. 124)

Seventh, as shown in fig. 131, the driving IC 200 and the circuit board 300 are attached to each of the plurality of display units DPC, and the first protective film PRF1 is peeled from each of the plurality of display units DPC.

(S470 in FIG. 124)

Fig. 137 is a flowchart illustrating a method of manufacturing a display device in accordance with one or more embodiments. Fig. 138-143 are perspective views illustrating a method of manufacturing a display device according to one or more embodiments.

First, as shown in fig. 138, a plurality of display units DPC are formed on a first surface of a mother substrate MSUB. (S510 in FIG. 137)

Second, a plurality of first protective films PRF1 are attached on the plurality of display units DPC, and the plurality of display units DPC are inspected. (S520 of FIG. 137)

Third, as shown in fig. 139, by irradiating the first laser light LR1 on the second surface of the mother substrate MSUB, a plurality of first laser irradiation regions CH1 are formed along the edges EG of the plurality of display units DPC and the edges BEG of the bending regions BA. (S530 in FIG. 137)

The first cutting line CL1 may be defined as a virtual line connecting the plurality of first laser irradiation regions CH1. The first cutting line CL1 may be formed by irradiating the first laser LR1 to form a plurality of first laser irradiation regions CH1 along the edges EG of the plurality of display units DPC and the edges BEG of the bending regions BA. The depth TCH1 of each of the plurality of first laser irradiation regions CH1 may be approximately 50 μm to 500 μm from the first surface of the mother substrate MSUB.

Fourth, as shown in fig. 140, a plurality of second laser irradiation regions CH2 for forming through holes TH in each of the plurality of display units DPC are formed by irradiating the second laser LR2 on the second surface of the mother substrate MSUB. (S540 of FIG. 137)

Fig. 137 illustrates that step S540 is performed after step S530 is performed, but embodiments of the present disclosure are not limited thereto. Step S530 and step S540 may be performed concurrently (e.g., simultaneously) by a plurality of laser devices.

Fifth, the second protective films PRF2 are attached to the plurality of first protective films PRF1 to shorten the process time. (S550 in FIG. 137)

Sixth, as shown in fig. 141 and 142, the thickness of the mother substrate MSUB is reduced by spraying the etchant ECH on the second surface of the mother substrate MSUB without a separate mask while cutting the mother substrate MSUB along the plurality of first and second laser irradiation regions CH1 and CH2 and peeling the second protective film PRF2. (S560 of FIG. 137)

Each of the plurality of display units DPC is separated from the mother substrate MSUB, and a through hole TH is formed in each of the plurality of display units DPC, and the mother substrate MSUB of the bending area BA may be removed by an etching process.

Seventh, as shown in fig. 143, the drive IC 200 and the circuit board 300 are attached to each of the plurality of display units DPC, and the first protective film PRF1 is peeled from each of the plurality of display units DPC. (S570 in FIG. 137)

As described above, the thickness of the mother substrate MSUB may be reduced by using a laser and an etching process, and the substrate SUB of each of the plurality of display units DPC may be separated from the mother substrate MSUB. In addition, since the through holes TH can be formed and the substrate SUB of the bending area BA can be removed, the efficiency of the manufacturing process can be improved.

Fig. 144 is a flowchart illustrating a method of manufacturing a display device in accordance with one or more embodiments. Fig. 145-150 are perspective views illustrating a method of manufacturing a display device according to one or more embodiments.

First, as shown in fig. 145, a plurality of display units DPC are formed on a first surface of a mother substrate MSUB. (S610 of FIG. 144)

Second, a plurality of first protective films PRF1 are attached on the plurality of display units DPC, and the plurality of display units DPC are inspected. (S620 of FIG. 144)

Third, as shown in fig. 146, by irradiating the first laser light LR1 on the second surface of the mother substrate MSUB, a plurality of first laser irradiation regions CH1 are formed along the edges EG of the plurality of display units DPC. (S630 of FIG. 144)

Fourth, as shown in fig. 147, by irradiating the second laser light LR2 on the second surface of the mother substrate MSUB, a plurality of second laser irradiation regions CH2 are formed along the edge TEG of the through hole TH and the edge BEG of the bending region BA in each of the plurality of display units DPC. (S640 of FIG. 144)

Fig. 144 illustrates that step S640 is performed after step S630 is performed, but embodiments of the present disclosure are not limited thereto. Step S630 and step S640 may be performed concurrently (e.g., simultaneously) by a plurality of laser devices LD to shorten the processing time.

The second cutting line CL2 may be defined as a virtual line connecting the plurality of second laser irradiation regions CH2. The second cutting line CL2 may be formed by irradiating the second laser LR2 to form a plurality of second laser irradiation regions CH2 along the edge TEG of the through hole TH and the edge BEG of the bending region BA. The depth (or sketch length) of each of the plurality of second laser irradiation regions CH2 may be approximately 50 μm to 500 μm from the first surface of the mother substrate MSUB. The depth (or sketch length) of each of the plurality of second laser irradiation regions CH2 may be longer than the depth (or sketch length) TCH1 of each of the plurality of first laser irradiation regions CH 1.

Fifth, the second protective films PRF2 are attached to the plurality of first protective films PRF 1. (S650 in FIG. 144)

Sixth, as shown in fig. 148 and 149, the etchant ECH is sprayed on the second surface of the mother substrate MSUB without a separate mask to reduce the thickness of the mother substrate MSUB while cutting the mother substrate along the plurality of first and second laser irradiation regions CH1 and CH2 and peeling the second protective film PRF2. (S660 in FIG. 144)

Each of the plurality of display units DPC is separated from the mother substrate MSUB, a through hole TH is formed in each of the plurality of display units DPC, and the mother substrate MSUB of the bending area BA may be removed by an etching process.

Seventh, as shown in fig. 150, the driving IC 200 and the circuit board 300 are attached to each of the plurality of display units DPC, and the first protective film PRF1 formed in each of the plurality of display units DPC is removed. (S670 in FIG. 144)

Fig. 151 is an example diagram illustrating an electronic device including a display device in accordance with one or more embodiments. Fig. 151 illustrates an example of a tablet computer as an electronic device to which the display device 10 according to one or more embodiments is applied.

FIG. 152 is an exemplary diagram illustrating an electronic device including a display device in accordance with one or more embodiments. Fig. 152 illustrates an example of a smart phone as an electronic device to which the display device 10 according to one or more embodiments is applied.

Fig. 153 is an example diagram illustrating an electronic device including a display device in accordance with one or more embodiments. Fig. 153 illustrates an example of a TV as an electronic device to which a display device according to one or more embodiments is applied.

FIG. 154 is an exemplary diagram illustrating an electronic device including a display device in accordance with one or more embodiments. Fig. 154 illustrates an example of an electronic device to which a monitor of a display device according to one or more embodiments is applied.

Fig. 155 is an exemplary diagram illustrating an electronic device including a display device in accordance with one or more embodiments.

Referring to fig. 155, the display device 10_1 according to one or more embodiments may be applied to a smart watch 1 as one of smart devices. The flat shape of the watch display unit of the smart watch 1 may follow the flat shape of the display device 10_1. For example, when the display device 10_1 according to one or more embodiments has a rectangular flat shape, the watch display unit of the smart watch 1 may have a rectangular flat shape. Alternatively, when the display device 10_1 according to one or more embodiments has a circular or oval flat shape, the watch display unit of the smart watch 1 may have a circular or oval flat shape. However, the embodiments of the present disclosure are not limited thereto, and the watch display unit of the smart watch 1 may not follow the flat shape of the display device 10_1.

FIG. 156 is an example diagram illustrating an electronic device including a display device in accordance with one or more embodiments. Fig. 156 shows an example of a virtual reality device 1 to which a display device 10_2 according to one or more embodiments is applied.

Referring to fig. 156, the virtual reality device 1 according to one or more embodiments may be a device in the form of glasses. The virtual reality device 1 according to one or more embodiments may include a display device 10_2, a left eye lens 10a, a right eye lens 10b, a support frame 20, glasses frame legs 30a and 30b, and a display device accommodating unit 50.

Fig. 156 illustrates a virtual reality device 1 including eyeglass frame legs 30a and 30b, the virtual reality device 1 according to one or more embodiments may be applied to a head mounted display including a head mounted strap that may be mounted on the head without eyeglass frame legs 30a and 30 b.

The display device accommodating unit 50 may include the display device 10_2 and the reflection member 40. The image displayed on the display device 10_2 may be reflected by the reflection member 40 and provided to the right eye of the user through the right eye lens 10 b. Accordingly, the user can view the virtual reality image displayed on the display device 10_2 through the right eye.

Fig. 156 shows that the display device accommodating unit 50 is disposed at the right end of the support frame 20, but embodiments of the present disclosure are not limited thereto. For example, the display device accommodating unit 50 may be disposed at the left end of the support frame 20. In this case, the image displayed on the display device 10_2 may be reflected by the reflection member 40 and provided to the left eye of the user through the left eye lens 10 a. Accordingly, the user can view the virtual reality image displayed on the display device 10_2 through the left eye. Alternatively, the display device accommodating unit 50 may be provided at both left and right ends of the support frame 20. In this case, the user can view the virtual reality image displayed on the display device 10_2 through the left and right eyes.

FIG. 157 is an exemplary diagram illustrating a vehicle dashboard and center dashboard to which electronic devices including display devices are applied, in accordance with one or more embodiments. Fig. 157 illustrates a vehicle to which display devices 10_a, 10_b, 10_c, 10_d, and 10_e are applied according to one or more embodiments.

Referring to fig. 157, the display devices 10_a, 10_b, and 10_c according to one or more embodiments may be applied to a dashboard of a vehicle, a center dashboard of a vehicle, or a Center Information Display (CID) provided on the dashboard of a vehicle. Further, the display devices 10_d and 10_e according to one or more embodiments may be applied to an indoor mirror display of a vehicle instead of a side view mirror.

Referring to fig. 158, the display device 10_3 according to one or more embodiments may be applied to a transparent display device. The transparent display device may transmit light while displaying the image IM. Accordingly, the user located in front of the transparent display device can view not only the image IM displayed on the display device 10_3 but also the object RS or the background positioned on the rear side of the transparent display device 10_3. When the display device 10_3 is applied to a transparent display device, the substrate SUB of the display device 10_3 may include a light transmitting portion capable of transmitting light, or may be formed of a material capable of transmitting light.

However, it should be understood that aspects and features of embodiments of the present disclosure are not limited to the aspects and features set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referencing the claims, and the functional equivalents of the claims are intended to be included therein.

Claims

1. A display device, characterized in that the display device comprises:

a substrate comprising a first surface, a second surface opposite the first surface, and a side surface between the first surface and the second surface;

An outermost structure on the first surface of the substrate and positioned adjacent to an edge of one side of the substrate; and

a display region including a plurality of light emitting regions on the first surface of the substrate,

wherein a minimum distance from the side surface of the substrate to the outermost structure is equal to 130 μm or less.

2. The display device of claim 1, wherein the display device comprises a display device,

the plurality of light emitting areas are positioned farther from the edge of the side of the substrate than the outermost structure, and

the first surface of the substrate includes treatment marks positioned closer to the edge of the one side of the substrate than the outermost structure,

wherein the processing trace is disposed within 30 μm or less from the edge of the one side of the substrate.

3. The display device according to claim 2, wherein a minimum distance between the outermost structure and the processing trace is 30 μm or less.

4. The display device of claim 1, wherein the substrate further comprises a first sloped surface between the side surface and the second surface,

Wherein an angle between the side surface and the first inclined surface and an angle between the first inclined surface and the second surface are obtuse angles.

5. The display device of claim 1, wherein the outermost structure comprises a crack dam extending between one side and the other side of the display area and along an edge of the substrate.

6. The display device of claim 1, wherein the outermost structure comprises a display pad electrically connected to a circuit board by a conductive adhesive member.

7. The display device of claim 6, further comprising an electrostatic protection line between the display pad and one edge of the substrate.

8. The display device according to claim 7, wherein the electrostatic protection line includes:

a main path region extending from the display pad to one edge of the substrate; and

and a secondary path region protruding from the primary path region.

9. A display device, characterized in that the display device comprises:

a substrate including a first surface, a second surface opposite to the first surface, a side surface between the first surface and the second surface, a through hole penetrating the first surface and the second surface, and a side surface of the through hole between the first surface and the second surface at an edge of the through hole;

A first outermost structure on the first surface of the substrate and positioned adjacent to one edge of the substrate; and

a second outermost structure on said first surface of said substrate and positioned adjacent to said edge of said through hole,

wherein a distance from the first outermost structure to the one edge of the substrate is smaller than a distance from the second outermost structure to the edge of the via.

10. A display device, characterized in that the display device comprises:

a first substrate comprising a first surface, a second surface opposite the first surface, and a first side surface between the first surface and the second surface;

a second substrate on the first substrate; and

a light emitting element layer including a plurality of light emitting regions on the second substrate,

wherein the first substrate further comprises a side surface of the curved region between the first surface and the second surface at an edge of the curved region where the second substrate is curved,

wherein a cross-sectional shape of the first side surface and a cross-sectional shape of the side surface of the curved region are different from each other.