KR102374299B1 - Flexible circuit board for all in one chip on film and chip pakage comprising the same, and electronic device comprising the same - Google Patents

Abstract

A flexible circuit board for an all-in-one chip on film according to an embodiment includes a substrate, a wiring pattern layer disposed on the substrate, a plating layer disposed on the wiring pattern layer, and a protective layer partially disposed on the wiring pattern layer and the content of tin (Sn) in the plating layer in the first open region of the passivation layer may include a greater content of tin (Sn) in the plating layer in the second open region of the passivation layer.
A chip package including a flexible circuit board for an all-in-one chip-on-film according to an embodiment includes a substrate, a conductive pattern part disposed on the substrate, and a protection part partially disposed in an area on the conductive pattern part, and the conductive pattern The portion includes a wiring pattern layer, a plating layer disposed on the wiring pattern layer, and a protective layer partially disposed on the wiring pattern layer, wherein the tin (Sn) of the plating layer is formed in the first open region of the protective layer. The content is greater than the content of tin (Sn) in the plating layer in the second open region of the passivation layer, and includes a first chip disposed in the first open region and a second chip disposed in the second open region can
An electronic device according to an embodiment includes a substrate; a conductive pattern portion disposed on the substrate; a protection part partially disposed in one region on the conductive pattern part, wherein the conductive pattern part includes a wiring pattern layer, a first plating layer disposed on the wiring pattern layer, and a second plating layer disposed on the first plating layer , and a passivation layer partially disposed on the wiring pattern layer, wherein the content of tin (Sn) of the second plating layer in the first open area of the passivation layer is determined in the second open area of the passivation layer. an all-in-one chip-on-film flexible circuit board containing more than the content of tin (Sn) in the second plating layer; a display panel connected to one end of the all-in-one flexible circuit board; and a main board connected to the other end opposite to the one end of the all-in-one flexible circuit board.

Description

Flexible circuit board for all-in-one chip-on film, chip package including same, and electronic device including same

The embodiment relates to a flexible circuit board for an all-in-one chip on film, a chip package including the same, and an electronic device including the same.

In detail, the flexible circuit board for the all-in-one chip on film may be a flexible circuit board capable of mounting different types of chips on one substrate, a chip package thereof, and an electronic device including the same there is.

Recently, various electronic products are becoming thinner, smaller, and lighter. Accordingly, various studies are being conducted to mount a semiconductor chip at a high density in a narrow area of an electronic device.

Among them, since the COF (Chip On Film) method uses a flexible substrate, it can be applied to both a flat panel display and a flexible display. That is, the COF method is receiving attention in that it can be applied to various wearable electronic devices. In addition, since the COF method can implement a fine pitch, it can be used to implement a high-resolution (QHD) display according to an increase in the number of pixels.

COF (Chip On Film) is a method of mounting a semiconductor chip on a flexible circuit board in the form of a thin film. For example, the semiconductor chip may be an integrated circuit (IC) chip or a large scale integrated circuit (LSI) chip.

However, the COF flexible circuit board cannot be directly connected between the display panel and the main board.

That is, at least two printed circuit boards are required between the display panel and the main board.

An electronic device having a display has a problem in that a plurality of printed circuit boards are required, resulting in an increase in thickness. In addition, the size of the plurality of printed circuit boards may be a constraint on miniaturization of the electronic device. In addition, poor bonding of the plurality of printed circuit boards may deteriorate the reliability of the electronic device.

Therefore, a new flexible circuit board capable of solving such a problem is required.

Embodiments are to provide an all-in-one chip-on-film flexible circuit board capable of mounting a plurality of chips on one substrate, a chip package including the same, and an electronic device including the same.

A flexible circuit board for an all-in-one chip-on-film according to an embodiment includes a substrate, a wiring pattern layer disposed on the substrate, a plating layer disposed on the wiring pattern layer, and a protective layer partially disposed on the wiring pattern layer and the content of tin (Sn) of the plating layer in the first open region of the passivation layer may include more than the content of tin (Sn) of the plating layer in the second open region of the passivation layer.

A chip package including a flexible circuit board for an all-in-one chip-on-film according to an embodiment includes: a substrate; a conductive pattern portion disposed on the substrate; a protection part partially disposed on one region on the conductive pattern part, wherein the conductive pattern part includes a wiring pattern layer, a plating layer disposed on the wiring pattern layer, and a protective layer partially disposed on the wiring pattern layer , wherein the content of tin (Sn) of the plating layer in the first open region of the passivation layer is greater than the content of tin (Sn) of the plating layer in the second open region of the passivation layer, and the first open region It may include a first chip disposed in the , and a second chip disposed in the second open area.

An electronic device according to an embodiment includes a substrate; a conductive pattern portion disposed on the substrate; a protection part partially disposed on one region on the conductive pattern part, wherein the conductive pattern part includes a wiring pattern layer, a first plating layer disposed on the wiring pattern layer, and a second plating layer disposed on the first plating layer , and a passivation layer partially disposed on the wiring pattern layer, wherein the content of tin (Sn) of the second plating layer in the first open area of the passivation layer is determined in the second open area of the passivation layer. A flexible circuit board for an all-in-one chip-on-film, comprising more than the content of tin (Sn) in the second plating layer; a display panel connected to one end of the all-in-one flexible circuit board; and a main board connected to the other end opposite to the one end of the all-in-one flexible circuit board.

The flexible circuit board for an all-in-one chip-on-film according to the embodiment may include a substrate and a conductive pattern portion disposed on the substrate.

The conductive pattern part may include a wiring pattern layer, a first plating layer, and a second plating layer.

A protective layer may be disposed on one region of the conductive pattern part to form a protective part, and a protective part may not be disposed on a region different from the one region. The plurality of areas in which the protection part is not disposed may be a first open area and a second open area.

A content of tin (Sn) in the second plating layer in the first open region may be different from a content of tin (Sn) in the second plating layer in the second open region.

A first connection part may be disposed on the first open area, and a first chip may be disposed on the first connection part. The first connection part may electrically connect the conductive pattern part and the first chip.

A second connection part may be disposed on the second open area, and a second chip may be disposed on the second connection part. The second connection part may electrically connect the conductive pattern part and the second chip.

Accordingly, in the embodiment, different types of first and second chips can be mounted on a single flexible circuit board, thereby providing an all-in-one chip-on-film flexible circuit board chip package having improved reliability.

In addition, one flexible circuit board for an all-in-one chip-on-film according to the embodiment may directly connect the display panel and the main board. Accordingly, the size and thickness of the flexible circuit board for transmitting the signal generated from the display panel to the main board may be reduced.

Accordingly, the flexible circuit board for the all-in-one chip-on-film according to the embodiment, the chip package including the same, and the electronic device including the same may expand the space of other components and/or the space of the battery.

In addition, since the connection of a plurality of printed circuit boards is not required, the convenience of the process and the reliability of the electrical connection may be improved.

Accordingly, the flexible circuit board for an all-in-one chip-on-film according to the embodiment, a chip package including the same, and an electronic device including the same may be suitable for an electronic device having a high-resolution display.

1A is a cross-sectional view of an electronic device having a display unit including a conventional printed circuit board.
1B is a cross-sectional view of the printed circuit board according to FIG. 1A in a bent form.
FIG. 1C is a plan view in which the printed circuit board of FIG. 1A is bent.
2A is a cross-sectional view of an electronic device having a display unit including a flexible circuit board for an all-in-one chip-on-film according to an embodiment.
FIG. 2B is a cross-sectional view of the flexible circuit board for an all-in-one chip-on-film according to FIG. 2A in a bent form.
FIG. 2C is a plan view of the flexible circuit board for an all-in-one chip-on-film according to FIG. 2A in a bent form.
3A is a cross-sectional view of a single-sided all-in-one chip-on-film flexible circuit board according to an embodiment.
3B is a cross-sectional view of a chip package including a flexible circuit board for a single-sided all-in-one chip-on-film according to an embodiment.
4 to 6 are cross-sectional views illustrating a manufacturing process of a chip package including a flexible circuit board for an all-in-one chip-on-film according to an embodiment;
7 is a cross-sectional view of a chip package including a flexible circuit board for a double-sided all-in-one chip-on-film according to an embodiment.
8A is another cross-sectional view of a flexible circuit board for a double-sided all-in-one chip-on-film according to an embodiment.
8B is a cross-sectional view of a chip package including a flexible circuit board for a double-sided all-in-one chip-on-film according to FIG. 8A.
9 is another cross-sectional view of a chip package including a flexible circuit board for a double-sided all-in-one chip-on-film according to an embodiment.
10 is an enlarged cross-sectional view of a region of the flexible circuit board for double-sided all-in-one chip-on-film according to the embodiment.
11 is a plan view of the flexible circuit board for a double-sided all-in-one chip-on-film according to FIG. 8A.
12 is a bottom view of the flexible circuit board for a double-sided all-in-one chip-on-film according to FIG. 8A.
13 is a schematic plan view of a chip package including a flexible circuit board for a double-sided all-in-one chip-on-film according to FIG. 8B.
14 to 16 are views illustrating a process of manufacturing the double-sided all-in-one chip-on-film flexible circuit board according to FIG. 8A into a chip package including the double-sided all-in-one chip-on-film flexible circuit board according to FIG. 8B.
17 is a cross-sectional view of a chip package including a flexible circuit board for a double-sided all-in-one chip-on-film according to FIG. 16 .
18 to 22 are diagrams of various electronic devices including a flexible circuit board for an all-in-one chip-on-film.

In the description of embodiments, each layer (film), region, pattern or structure is “on” or “under” the substrate, each layer (film), region, pad or patterns. The description of being formed in " includes all those formed directly or through another layer. The standards for the upper/above or lower/lower layers of each layer will be described with reference to the drawings.

In addition, when a certain part is said to be "connected" with another part, it includes not only the case where it is "directly connected" but also the case where it is "indirectly connected" with another member interposed therebetween. In addition, when a part "includes" a certain component, this means that other components may be further provided without excluding other components unless otherwise stated.

In the drawings, the thickness or size of each layer (film), region, pattern, or structure may be changed for clarity and convenience of description, and thus does not fully reflect the actual size.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

A printed circuit board according to a comparative example will be described with reference to FIGS. 1A to 1C .

An electronic device having a display unit requires at least two printed circuit boards to transmit a signal of the display panel to the main board.

The number of printed circuit boards included in the electronic device including the display unit according to the comparative example may be at least two.

The electronic device including the display unit according to the comparative example may include a first printed circuit board 10 and a second printed circuit board 20 .

The first printed circuit board 10 may be a flexible printed circuit board. In detail, the first printed circuit board 10 may be a flexible printed circuit board for a chip on film (COF). The first printed circuit board 10 may be a flexible printed circuit board for COF on which the first chip C1 is mounted. In more detail, the first printed circuit board 10 may be a COF flexible printed circuit board for arranging a drive IC chip.

The second printed circuit board 20 may be a flexible printed circuit board. In detail, the second printed circuit board 20 may be a flexible printed circuit board (FPCB) for arranging a different type of second chip C2 from the first chip C1. Here, the second chip C2 is other than a drive IC chip, and is electrically connected on a flexible printed circuit board such as a chip, a semiconductor device, a socket, etc. other than a drive IC chip. It may mean various chips disposed for The second printed circuit board 20 may be a flexible printed circuit board (FPCB) for arranging the plurality of second chips C2. For example, the second printed circuit board 20 may be a flexible printed circuit board for arranging a plurality of second chips C2a and C2b of different types.

The first printed circuit board 10 and the second printed circuit board 20 may have different thicknesses. The thickness of the second printed circuit board 20 may be smaller than the thickness of the first printed circuit board 10 . For example, the first printed circuit board 10 may have a thickness of about 20 μm to 100 μm. The second printed circuit board 20 may have a thickness of about 100 μm to 200 μm. For example, the total thickness t1 of the first printed circuit board 10 and the second printed circuit board may be 200 μm to 250 μm.

Since the electronic device having the display unit according to the comparative example requires the first and second printed circuit boards between the display panel and the main board, the overall thickness of the electronic device may increase. In detail, since the electronic device having the display unit according to the comparative example requires first and second printed circuit boards stacked up and down, the overall thickness of the electronic device may be increased.

The first printed circuit board 10 and the second printed circuit board 20 may be formed by different processes. For example, the first printed circuit board 10 may be manufactured by a roll to roll process. The second printed circuit board 20 may be manufactured in a sheet method.

Different types of chips are respectively disposed on the first printed circuit board 10 and the second printed circuit board 20 , and a pitch of conductive pattern portions to be connected to each chip may be different from each other. For example, a pitch of the conductive pattern portions disposed on the second printed circuit board 20 may be greater than a pitch of the conductive pattern portions disposed on the first printed circuit board 10 . For example, the pitch of the conductive pattern portions disposed on the second printed circuit board 20 is 100 μm or more, and the pitch of the conductive pattern portions disposed on the first printed circuit board 10 is may be less than 100 μm.

In detail, manufacturing the first printed circuit board 10 having conductive pattern portions arranged at fine pitches through a roll-to-roll process is process-efficient and can reduce process costs. On the other hand, since it is difficult to handle the second printed circuit board 20 having conductive pattern portions disposed at intervals of 100 μm or more by a roll-to-roll process, it was common to use a sheet process.

Since the first and second printed circuit boards according to the comparative example are formed by different processes, respectively, process efficiency may be reduced.

In addition, since the chip package including the flexible circuit board according to the comparative example has difficulty in the process of disposing different types of chips on one substrate, separate first and second printed circuit boards are required.

In addition, the chip package including the flexible circuit board according to the comparative example has a problem in that it is difficult to connect different types of chips on one substrate.

That is, the first and second printed circuit boards may be disposed between the existing display panel and the main board.

In order to control, process or transmit R, G, and B signals generated from the display panel 30 , the first printed circuit board 10 is connected to the display panel 30 , and the first printed circuit board 10 is again The second printed circuit board 20 may be connected, and the second printed circuit board 20 may be connected to the main board 40 .

One end of the first printed circuit board 10 may be connected to the display panel 30 . The display panel 30 may be connected to the first printed circuit board 10 by an adhesive layer 50 .

The other end opposite to the one end of the first printed circuit board 10 may be connected to the second printed circuit board 20 . The first printed circuit board 10 may be connected to the second printed circuit board 20 by the adhesive layer 50 .

One end of the second printed circuit board 20 may be connected to the first printed circuit board 10 , and the other end opposite to the one end of the second printed circuit board 20 may be connected to the main board 40 . there is. The second printed circuit board 20 may be connected to the main board 40 by the adhesive layer 50 .

In the electronic device having a display unit according to a comparative example, between the display panel 30 and the first printed circuit board 10 , the first printed circuit board 10 and the second printed circuit board 20 . In between, a separate adhesive layer 50 may be required between the second printed circuit board 20 and the main board 40 . That is, since the electronic device having the display unit according to the comparative example requires a plurality of adhesive layers, the reliability of the electronic device may be deteriorated due to poor connection of the adhesive layers. In addition, the adhesive layer disposed between the first printed circuit board 10 and the second printed circuit board 20 connected up and down may increase the thickness of the electronic device.

1B and 1C , a first printed circuit board 10 , a second printed circuit board 20 , a display panel 30 , and a main board 40 housed in an electronic device according to a comparative example are illustrated. Explain.

FIG. 1B is a cross-sectional view of the printed circuit board according to FIG. 1A in a bent form, and FIG. 1C is a plan view from the lower surface of FIG. 1B .

The display panel 30 and the main board 40 may be disposed to face each other. A first printed circuit board 10 including a bending area may be disposed between the display panel 30 and the main board 40 disposed to face each other.

One area of the first printed circuit board 10 may be bent, and the first chip C1 may be disposed on a non-bent area.

In addition, the second printed circuit board 20 may be disposed to face the display panel 30 . The second chip C2 may be disposed in a non-bending area of the second printed circuit board 20 .

Referring to FIG. 1C , since the comparative example requires a plurality of substrates, the length L1 in one direction is the sum of the lengths of each of the first printed circuit board 10 and the second printed circuit board 20 . can The length L1 in one direction of the first printed circuit board 10 and the second printed circuit board 20 is the length of the short side of the first printed circuit board 10 and the second printed circuit board ( 20) may be the sum of the lengths of the short sides. For example, the length L1 in one direction of the first printed circuit board 10 and the second printed circuit board 20 may be 30 mm to 40 mm. However, the length L1 of the first printed circuit board 10 and the second printed circuit board 20 in one direction may have various sizes according to the type of the chip for mounting and the type of the electronic device.

As the electronic device according to the comparative example requires a plurality of printed circuit boards, a space for mounting other components or a space for arranging the battery 60 may be reduced.

Recently, in an electronic device such as a smart phone, parts having various functions are added to enhance user convenience or security. For example, electronic devices such as smart phones and smart watches are equipped with multiple camera modules (dual camera modules) or parts having various functions such as iris recognition and virtual reality (VR, Virtual Reality). are being added Accordingly, it is important to secure a space for mounting additional parts.

In addition, various electronic devices, including wearable devices, require an expansion of a battery space in order to improve user convenience.

Accordingly, as a plurality of printed circuit boards used in existing electronic devices are replaced with a single printed circuit board, the importance of securing a space for mounting new components or securing a space for increasing the size of a battery rises.

In the electronic device according to the comparative example, different types of first and second chips may be respectively disposed on separate first and second printed circuit boards 10 and 30 . Accordingly, the thickness of the adhesive layer 50 between the first printed circuit board 10 and the second printed circuit board 30 and the thickness of the second printed circuit board 30 increase the thickness of the electronic device. there was

In addition, there is a problem in that the space for mounting the battery or other components is reduced by the size of the second printed circuit board 30 .

In addition, there is a problem in that the poor bonding of the first and second printed circuit boards lowers the reliability of the electronic device.

In order to solve this problem, the embodiment provides a flexible circuit board for an all-in-one chip-on-film of a new structure capable of mounting a plurality of chips on one substrate, a chip package including the same, and an electronic device including the same there is. The same reference numerals in Examples and Comparative Examples denote the same components, and descriptions overlapping those of the Comparative Examples described above are excluded.

An electronic device including a flexible circuit board for an all-in-one chip-on-film according to an embodiment will be described with reference to FIGS. 2A to 2C .

The electronic device according to the embodiment may use one printed circuit board to transmit the signal of the display panel to the main board. The printed circuit board included in the electronic device including the display unit according to the embodiment may be a single flexible printed circuit board. Accordingly, the flexible circuit board 100 for an all-in-one chip on film according to the embodiment is bent between the display unit and the main board facing each other to connect the display unit and the main board. there is.

In detail, the flexible circuit board 100 for an all-in-one chip on film according to the embodiment may be one substrate for arranging a plurality of chips of different types.

The flexible circuit board 100 for an all-in-one chip on film according to the embodiment may be a substrate on which different types of first and second chips c1 and c2 are disposed.

The thickness t2 of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment may be 20 μm to 100 μm. For example, the thickness t2 of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment may be 30 μm to 80 μm. For example, the thickness t2 of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment may be 50 μm to 75 μm. However, the thickness of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment may be designed to have various sizes depending on the type of chip to be mounted and the type of electronic device. .

The thickness t2 of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment is 1 of the thickness t1 of the plurality of first and second printed circuit boards according to the comparative example. It may have a thickness of /5 to 1/2 level. That is, the thickness t2 of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment is the thickness t1 of the plurality of first and second printed circuit boards according to the comparative example. It may have a thickness of 20% to 50% of the For example, the thickness t2 of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment is the thickness of the plurality of first and second printed circuit boards according to the comparative example ( It may have a thickness of 25% to 40% of t1). For example, the thickness t2 of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment is the thickness of the plurality of first and second printed circuit boards according to the comparative example ( It may have a thickness of a level of 25% to 35% of t1).

Since the electronic device having the display unit according to the embodiment requires only one flexible circuit board 100 for an all-in-one chip on film between the display panel and the main board, the overall thickness of the electronic device can reduce In detail, since the electronic device having the display unit according to the embodiment requires a single-layer printed circuit board, the overall thickness of the electronic device may be reduced.

In addition, the embodiment may omit the adhesive layer 50 between the first printed circuit board and the second printed circuit board included in the comparative example. It is possible to reduce the overall thickness of the electronic device.

In addition, the embodiment can omit the adhesive layer 50 between the first printed circuit board and the second printed circuit board, so that the problem caused by poor adhesion can be solved, and thus the reliability of the electronic device can be improved.

In addition, since the bonding process of a plurality of printed circuit boards can be omitted, process efficiency can be increased and process costs can be reduced.

In addition, as the substrate managed as a separate process is replaced with a single process, process efficiency and product yield can be improved.

The flexible circuit board 100 for an all-in-one chip on film according to the embodiment may include a bent region and a non-bent region. The flexible circuit board 100 for an all-in-one chip on film according to the embodiment includes a bent region, so that the display panel 30 and the main board 40 that are disposed to face each other are formed. can be connected to each other.

Non-bending regions of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment may be disposed to face the display panel 30 . The first chip C1 and the second chip C2 may be disposed on the non-bending area of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment. Accordingly, in the flexible circuit board 100 for an all-in-one chip on film according to the embodiment, the first chip c1 and the second chip c2 may be stably mounted.

Fig. 2c is a plan view from the lower surface of Fig. 2b;

Referring to FIG. 2C , since one substrate is required in the embodiment, the length L2 in one direction may be the length of one substrate. The length L2 in one direction of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment is for an all-in-one chip on film according to the embodiment. It may be the length of the short side of the flexible circuit board 100 . For example, the length L2 in one direction of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment may be 10 mm to 50 mm. For example, the length L2 in one direction of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment may be 10 mm to 30 mm. For example, the length L2 in one direction of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment may be 15 mm to 25 mm. However, the embodiment is not limited thereto, and it goes without saying that various sizes may be designed according to the type and/or number of chips to be disposed and the type of electronic device.

The length L2 in one direction of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment is one direction of the plurality of first and second printed circuit boards according to the comparative example. It may have a length of 50% to 70% of the length L1 in . For example, the length L2 in one direction of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment is a plurality of first and second printed circuits according to the comparative example. It may have a length of 55% to 70% of the length L1 in one direction of the substrate. The length L2 in one direction of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment is one direction of the plurality of first and second printed circuit boards according to the comparative example. It may have a length of 60% to 70% of the length L1 in .

Accordingly, in the embodiment, the size of the chip package including the flexible circuit board 100 for an all-in-one chip on film in the electronic device can be reduced, so that the space for arranging the battery 60 . This can be enlarged. In addition, the chip package including the flexible circuit board 100 for an all-in-one chip on film according to the embodiment may have a reduced planar area, so it may be possible to secure a space for mounting other components. .

3A, 3B, 7, 8A, 8B, 9 and 10, a flexible circuit board 100 for an all-in-one chip on film according to an embodiment and a chip thereof Describe the package.

3A and 3B, the flexible circuit board 100 for an all-in-one chip on film according to the embodiment is a single-sided flexible circuit board for an all-in-one chip on film having an electrode pattern part on one surface. can

The flexible circuit board 100 for an all-in-one chip on film according to the embodiment includes a substrate 110 , a wiring pattern layer 120 disposed on the substrate 110 , a plating layer 130 , and A protective layer 140 may be included.

The substrate 110 may be a support substrate supporting the wiring pattern layer 120 , the plating layer 130 , and the protective layer 140 .

The substrate 110 may include a bent region and a region other than the bent region. That is, the substrate 110 may include a bent region in which bending is made and a non-bending region other than the bent region.

The substrate 110 may be a flexible substrate. Accordingly, the substrate 110 may be partially bent. That is, the substrate 110 may include a flexible plastic. For example, the substrate 110 may be a polyimide (PI) substrate. However, embodiments are not limited thereto, and the substrate may be made of a polymer material such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN). Accordingly, the flexible circuit board including the substrate 110 may be used in various electronic devices provided with curved display devices. For example, since the flexible circuit board including the substrate 110 has excellent flexibility, it may be suitable for mounting a semiconductor chip of a wearable electronic device. Specifically, embodiments may be suitable for electronic devices including curved displays.

The substrate 110 may be an insulating substrate. That is, the substrate 110 may be an insulating substrate supporting various wiring patterns.

The substrate 110 may have a thickness of 20 μm to 100 μm. For example, the substrate 110 may have a thickness of 25 μm to 50 μm. For example, the substrate 100 may have a thickness of 30 μm to 40 μm. When the thickness of the substrate 100 is greater than 100 μm, the overall thickness of the flexible circuit board may increase. When the thickness of the substrate 100 is less than 20 μm, it may be difficult to simultaneously dispose the first chip C1 and the second chip C2. When the thickness of the substrate 110 is less than 20 μm, the substrate 110 may be vulnerable to heat/pressure, etc. in the process of mounting a plurality of chips, and thus it may be difficult to place a plurality of chips at the same time. A wiring may be disposed on the 110). The wiring may be a plurality of patterned wirings. For example, the plurality of wires may be disposed to be spaced apart from each other on the substrate 110 . That is, the wiring pattern layer 120 may be disposed on one surface of the substrate 110 .

An area of the substrate 110 may be larger than an area of the wiring pattern layer 120 . In detail, a planar area of the substrate 110 may be larger than a planar area of the wiring pattern layer 120 . That is, the wiring pattern layer 120 may be partially disposed on the substrate 110 . For example, a lower surface of the wiring pattern layer 120 may be in contact with the substrate 110 , and the substrate 110 may be exposed between the plurality of wirings. The wiring pattern layer 120 may include a conductive material.

For example, the wiring pattern layer 120 may include a metal material having excellent electrical conductivity. In more detail, the wiring pattern layer 120 may include copper (Cu). However, embodiments are not limited thereto, and copper (Cu), aluminum (Al), chromium (Cr), nickel (Ni), silver (Ag), and molybdenum (Mo). Of course, it may include at least one metal among gold (Au), titanium (Ti), and alloys thereof.

The wiring pattern layer 120 may be disposed to a thickness of 1 μm to 15 μm. For example, the wiring pattern layer 120 may be disposed to have a thickness of 1 μm to 10 μm. For example, the wiring pattern layer 120 may be disposed to have a thickness of 2 μm to 10 μm.

When the thickness of the wiring pattern layer 120 is less than 1 μm, the resistance of the wiring pattern layer may increase. When the thickness of the wiring pattern layer 120 is greater than 10 μm, it may be difficult to implement a fine pattern.

A plating layer 130 may be disposed on the wiring pattern layer 120 . The plating layer 130 may include a first plating layer 131 and a second plating layer 132 .

A first plating layer 131 may be disposed on the wiring pattern layer 120 , and the second plating layer 132 may be disposed on the first plating layer 131 . The first plating layer 131 and the second plating layer 132 may be formed in two layers on the wiring pattern layer 120 to prevent the whisker from forming. Accordingly, a short circuit between the patterns of the wiring pattern layer 120 may be prevented. In addition, as the two plating layers are disposed on the wiring pattern layer 120 , bonding characteristics with the chip may be improved. When the wiring pattern layer includes copper (Cu), the wiring pattern layer cannot be directly bonded to the first chip C1 , and a separate bonding process may be required. On the other hand, when the plating layer disposed on the wiring pattern layer includes tin (Sn), the surface of the plating layer may be a pure tin layer, so that bonding to the first chip C1 may be easy. In this case, the wire connected to the first chip C1 can be easily connected only with the pure tin layer and heat and pressure, thereby improving the accuracy of chip wire bonding and the convenience of the manufacturing process.

The region in which the first plating layer 131 is disposed may correspond to the region in which the second plating layer 132 is disposed. That is, an area in which the first plating layer 131 is disposed may correspond to an area in which the second plating layer 132 is disposed.

The plating layer 130 may include tin (Sn). For example, the first plating layer 131 and the second plating layer 132 may include tin (Sn).

For example, the wiring pattern layer 120 may be formed of copper (Cu), and the first plating layer 131 and the second plating layer 132 may be formed of tin (Sn). When the plating layer 130 includes tin, since the corrosion resistance of tin (Sn) is excellent, oxidation of the wiring pattern layer 120 can be prevented.

Meanwhile, the material of the plating layer 130 may have lower electrical conductivity than the material of the wiring electrode layer 120 . The plating layer 130 may be electrically connected to the wiring electrode layer 120 .

The first plating layer 131 and the second plating layer 132 are formed of the same tin (Sn), but may be formed by a separate process.

When a heat treatment process such as thermosetting is included in the manufacturing process of the flexible circuit board according to the embodiment, the diffusion action of copper (Cu) in the wiring pattern layer 120 or tin (Sn) in the plating layer 130 is reduced. can happen In detail, through the curing of the protective layer 140 , a diffusion action of copper (Cu) in the wiring pattern layer 120 or tin (Sn) in the plating layer 130 may occur.

Accordingly, as the diffusion concentration of copper (Cu) decreases from the first plating layer 131 to the surface of the second plating layer 132 , the copper (Cu) content may continuously decrease. Meanwhile, the content of tin (Sn) may increase continuously from the first plating layer 131 toward the surface of the second plating layer 132 . Accordingly, the uppermost portion of the plating layer 130 may include pure tin.

That is, the wiring pattern layer 120 and the plating layer 130 may be formed of an alloy of tin and copper due to a chemical action at the stacking interface. The thickness of the alloy of tin and copper after curing the protective layer 140 on the plating layer 130 rather than the thickness of the alloy of tin and copper after the formation of the plating layer 130 on the wiring pattern layer 120 is The thickness may be increased.

The alloy of tin and copper included in at least a portion of the plating layer 130 may have a chemical formula of Cu _x Sn _y , and may be 0<x+y<12. For example, in the above formula, the sum of x and y may be 4≤x+y≤11. For example, the alloy of tin and copper included in the plating layer 130 is Cu ₃ Sn and Cu ₆ Sn ₅ may include at least one of In detail, the first plating layer 131 may be an alloy layer of tin and copper.

In addition, the first plating layer 131 and the second plating layer 132 may have different contents of tin and copper. The copper content of the first plating layer 131 in direct contact with the copper wiring pattern layer may be greater than that of the second plating layer 132 .

The second plating layer 132 may have a greater content of tin than the first plating layer 131 . The second plating layer 132 may include pure tin. Here, pure tin may mean that the content of tin (Sn) is 50 atomic% or more, 70 atomic% or more, and 90 atomic% or more. In this case, the element other than tin may be copper. For example, the content of tin (Sn) in the second plating layer 132 may be 50 atomic% or more. For example, the content of tin (Sn) in the second plating layer 132 may be 70 atomic% or more. For example, the content of tin (Sn) in the second plating layer 132 may be 90 atomic% or more. For example, the content of tin (Sn) in the second plating layer 132 may be 95 atomic% or more. For example, the content of tin (Sn) in the second plating layer 132 may be 98 atomic% or more.

The plating layer according to the embodiment may prevent electrochemical migration resistance due to Cu/Sn diffusion, thereby preventing short circuit defects due to metal growth.

However, the embodiment is not limited thereto, and the plating layer 130 may be formed of a Ni/Au alloy, gold (Au), electroless nickel immersion gold (ENIG), Ni/Pd alloy, or organic compound plating (Organic). Of course, any one of Solderability Preservative (OSP) may be included.

The first plating layer 131 may correspond to the second plating layer 132 or may have different thicknesses. The total thickness of the first plating layer 131 and the second plating layer 132 may be 0.3 μm to 1 μm. The total thickness of the first plating layer 131 and the second plating layer 132 may be 0.3 μm to 0.7 μm. The total thickness of the first plating layer 131 and the second plating layer 132 may be 0.3 μm to 0.5 μm. Any one of the first plating layer 131 and the second plating layer 132 may have a thickness of 0.05 μm to 0.15 μm or less. For example, any one of the first plating layer 131 and the second plating layer 132 may have a thickness of 0.07 μm to 0.13 μm or less.

The protective layer 140 may be partially disposed on the wiring pattern layer 120 . For example, the protective layer 140 may be disposed on the plating layer 130 on the wiring pattern layer 120 . The protective layer 140 may cover the plating layer 130 , thereby preventing damage or film removal due to oxidation of the wiring pattern layer 120 and the plating layer 130 .

In the protective layer 140 , the wiring pattern layer 120 and/or the plating layer 130 are electrically connected to the display panel 30 , the main board 40 , the first chip C1 or the second chip C2 . It may be partially disposed in an area except for an area to be connected to.

Accordingly, the protective layer 140 may partially overlap the wiring pattern layer 120 and/or the plating layer 130 .

An area of the protective layer 140 may be smaller than an area of the substrate 110 . The protective layer 140 is disposed in an area excluding the end of the substrate, and may include a plurality of open areas.

The passivation layer 140 may include a first open area OA1 having a hole-like shape. The first open area OA1 may be a non-arranged area of the protective layer 140 in which the wiring pattern layer 120 and/or the plating layer 130 are electrically connected to the first chip C1 .

The passivation layer 140 may include a second open area OA2 having a hole-like shape. The second open area OA2 may be a non-arranged area of the protective layer 140 for electrically connecting the wiring pattern layer 120 and/or the plating layer 130 to the second chip C2 . . Accordingly, in the second open area OA2 , the plating layer 130 may be exposed to the outside.

In the second open area OA2 , the copper content of the plating layer 130 may be 50 atomic percent or more. For example, the content of copper in the plating layer 130 may be 60 atomic% or more. For example, the content of copper in the plating layer 130 may be 60 atomic% to 80 atomic%. In detail, the copper content of the first plating layer 131 measured in the second open area OA2 may be 60 atomic% to 80 atomic%.

The protective layer 140 may not be disposed on the conductive pattern part to be electrically connected to the main board 40 or the display panel 30 . The embodiment may include a third open area OA3 that is a non-arranged area of the protective layer 140 on the conductive pattern portion for being electrically connected to the main board 40 or the display panel 30 . Accordingly, in the third open area OA3 , the plating layer 130 may be exposed to the outside.

In the third open area OA3 , the copper content of the plating layer 130 may be 50 atomic percent or more. Alternatively, in the third open region OA3 , the copper content of the plating layer 130 may be less than 50 atomic %. The third open area OA3 may be located outside the substrate than the first open area OA1 . Also, the third open area OA3 may be located outside the substrate than the second open area OA2 .

The first open area OA1 and the second open area OA2 may be located in a central area of the substrate rather than the third open area OA3 .

The protective layer 140 may be disposed in the bent region. Accordingly, the protective layer 140 may disperse stress that may occur during bending. Therefore, the reliability of the flexible circuit board for the all-in-one chip-on-film according to the embodiment can be improved.

The protective layer 140 may include an insulating material. The protective layer 140 may include various materials that can be cured by heating after being applied to protect the surface of the conductive pattern part. The protective layer 140 may be a resist layer. For example, the protective layer 140 may be a solder resist layer including an organic polymer material. For example, the protective layer 140 may include an epoxy acrylate-based resin. In detail, the protective layer 140 may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acryl-based monomer, and the like. However, the embodiment is not limited thereto, and it goes without saying that the protective layer 140 may be any one of a photosolder resist layer, a cover-lay, and a polymer material.

The protective layer 140 may have a thickness of 1 μm to 20 μm. The protective layer 140 may have a thickness of 1 μm to 15 μm. For example, the thickness of the protective layer 140 may be 5 μm to 20 μm. When the thickness of the protective layer 140 is greater than 20 μm, the thickness of the flexible circuit board for the all-in-one chip-on-film may increase. When the thickness of the protective layer 140 is less than 1 μm, the reliability of the conductive pattern part included in the flexible circuit board for the all-in-one chip-on-film may be deteriorated.

A chip package including the flexible circuit board 100 for a single-sided all-in-one chip-on-film according to an embodiment will be described with reference to FIG. 3B .

The single-sided all-in-one chip-on-film flexible circuit board 100 according to the embodiment partially protects the substrate 110, the conductive pattern portion CP disposed on one surface of the substrate, and a region on the conductive pattern portion CP. The layer 140 may include a protective part PP formed thereon.

The conductive pattern part CP may include the wiring pattern layer 120 and the plating layer 130 .

The protection part PP may not be disposed on an area different from one area on the conductive pattern part CP. Accordingly, the substrate 110 between the conductive pattern part CP and the spaced apart conductive pattern part CP may be exposed on one region and another region on the conductive pattern part CP. A first connection part 70 and a second connection part 80 may be respectively disposed on one region and another region of the conductive pattern part CP. In detail, a first connection part 70 and a second connection part 80 may be respectively disposed on the upper surface of the conductive pattern part CP on which the protection part PP is not disposed.

The first connection part 70 and the second connection part 80 may have different shapes. For example, the first connection part 70 may have a hexahedral shape. In detail, the cross-section of the first connection part 70 may include a rectangular shape. In more detail, the cross-section of the first connection part 70 may include a rectangular or square shape. For example, the second connection part 80 may have a spherical shape. A cross-section of the second connection part 80 may have a circular shape. Alternatively, the second connection part 80 may have a partially or wholly rounded shape. For example, the cross-sectional shape of the second connection part 80 may include a flat surface on one side and a curved surface on the other side opposite to the one side.

The first connection part 70 and the second connection part 80 may have different sizes. The first connection part 70 may be smaller than the second connection part 80 .

The width of the first connection part 70 and the second connection part 80 may be different from each other. For example, a width D1 between both sides of one first connection part 70 may be smaller than a width D2 between both sides of one second connection part 80 .

The first chip C1 may be disposed on the first connection part 70 . The first connection part 70 may include a conductive material. Accordingly, the first connection part 70 includes the first chip C1 disposed on the upper surface of the first connection part 70 and the conductive pattern part CP disposed on the lower surface of the first connection part 70 . can be electrically connected.

The second chip C2 may be disposed on the second connection part 80 . The second connection part 80 may include a conductive material. Accordingly, the second connection part 80 includes the second chip C2 disposed on the upper surface of the second connection part 80 and the conductive pattern part CP disposed on the lower surface of the second connection part 80 . can be electrically connected.

Different types of first and second chips C1 and C2 may be disposed on the same surface of the single-sided all-in-one chip-on-film flexible circuit board 100 according to the embodiment. In detail, one first chip C1 and a plurality of second chips C2 may be disposed on the same surface of the single-sided all-in-one chip-on-film flexible circuit board 100 according to the embodiment. Accordingly, the efficiency of the chip packaging process may be improved.

The first chip C1 may include a drive IC chip.

The second chip C2 may refer to a chip other than a drive IC chip. The second chip C2 may refer to various chips including sockets or devices other than a drive IC chip. For example, the second chip C2 may include at least one of a diode chip, a power supply IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor.

The plurality of second chips C2 disposed on the all-in-one chip-on-film flexible circuit board 100 includes at least one of a diode chip, a power IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor. It may mean to be placed. For example, a plurality of MLCC chips may be disposed on the flexible circuit board 100 for the all-in-one chip-on-film.

Also, the second chip C2 may include at least two of a diode chip, a power supply IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor. That is, a plurality of second chips C2a and C2b of different types may be disposed on the flexible circuit board 100 for the all-in-one chip-on-film. For example, on the flexible circuit board 100 for an all-in-one chip on film, a diode chip, a power IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, a second chip (C2a) of any one of a chip capacitor and a diode chip, A power supply IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor may include a second chip C2b different from any one of the above.

In detail, on the flexible circuit board 100 for the all-in-one chip-on-film, a plurality of second chips C2a of any one of a diode chip, a power IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor may be disposed. and a diode chip, a power supply IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor, wherein the second chip C2b is disposed in plurality. For example, a plurality of MLCC chips C2a and a plurality of power supply IC chips C2b may be included on the flexible circuit board 100 for the all-in-one chip-on-film. For example, a plurality of MLCC chips C2a and a plurality of diode chips C2b may be included on the flexible circuit board 100 for the all-in-one chip-on-film. For example, a plurality of MLCC chips C2a and a plurality of BGA chips C2b may be included on the flexible circuit board 100 for the all-in-one chip-on-film.

In the embodiment, the type of the second chip is not limited to two, and it goes without saying that various chips except for the driving IC chip may all be included in the second chip.

One end of the all-in-one chip-on-film flexible circuit board 100 may be connected to the display panel 30 . One end of the all-in-one chip-on-film flexible circuit board 100 may be connected to the display panel 30 by an adhesive layer 50 . In detail, the display panel 30 may be disposed on an upper surface of the adhesive layer 50 , and the flexible circuit board 100 for the all-in-one chip-on-film may be disposed on a lower surface of the adhesive layer 50 . Accordingly, the display panel 30 and the flexible circuit board 100 for the all-in-one chip-on-film may be vertically bonded with the adhesive layer 50 interposed therebetween.

The other end opposite to the one end of the all-in-one chip-on-film flexible circuit board 100 may be connected to the main board 40 . The other end opposite to the one end of the all-in-one chip-on-film flexible circuit board 100 may be connected to the main board 40 by an adhesive layer 50 . In detail, the main board 40 may be disposed on the upper surface of the adhesive layer 50 , and the flexible circuit board 100 for the all-in-one chip-on-film may be disposed on the lower surface of the adhesive layer 50 . Accordingly, the main board 40 and the flexible circuit board 100 for the all-in-one chip-on-film may be vertically bonded with the adhesive layer 50 interposed therebetween.

The adhesive layer 50 may include a conductive material. The adhesive layer 50 may have conductive particles dispersed in an adhesive material. For example, the adhesive layer 50 may be an anisotropic conductive film (ACF).

Accordingly, the adhesive layer 50 transmits electrical signals between the display panel 30 , the all-in-one chip-on-film flexible circuit board 100 , and the main board 40 , and stably connects the separate components. can be connected

A manufacturing process of a chip package including a flexible circuit board for an all-in-one chip-on-film according to an embodiment will be described with reference to FIGS. 4 to 6 .

Referring to FIG. 4 , a conductive pattern portion CP including a patterned pattern layer 120 , a first plating layer 131 and a second plating layer 132 on one surface of the substrate 100 , and a protective layer 140 . By disposing, it is possible to prepare a flexible circuit board for an all-in-one chip-on-film.

In this case, the passivation layer 140 may include a first open area OA1 and a second open area OA2 .

The second plating layer 132 may be exposed in the first open area OA1 . In addition, the second plating layer 132 may be exposed in the second open area OA2 .

A first step of arranging the first chip C1 and a second step of arranging the second chip C2 on the flexible circuit board for an all-in-one chip-on-film according to the embodiment will be described with reference to FIGS. 5 and 6 . do.

First, the step of disposing the first chip C1 on the flexible circuit board for the all-in-one chip-on-film according to the embodiment will be described.

A first connection part 70 may be disposed in the first open area OA1 of the flexible circuit board for the all-in-one chip-on-film according to the embodiment.

The content of tin (Sn) in the second plating layer 132a in the first open area OA1 may be 50 atomic% or more. In the first open area OA1 , the second plating layer 132a may include pure tin. For example, the content of tin (Sn) in the second plating layer 132a in the first open area OA1 may be 70 atomic% or more. For example, the content of tin (Sn) in the second plating layer 132a in the first open area OA1 may be 90 atomic% or more. For example, the content of tin (Sn) in the second plating layer 132a in the first open area OA1 may be 95 atomic% or more. For example, the content of tin (Sn) in the second plating layer 132a in the first open region OA1 may be 98 atomic% or more. When the content of tin (Sn) in the second plating layer 132 in the first open region OA1 is less than 50 atomic%, the second plating layer 132 and the first chip ( The connection of C1) may be difficult. In detail, when the content of tin (Sn) in the second plating layer 132 in the first open area OA1 is less than 50 atomic %, the second plating layer 132 and the first Connection by bonding of the chip C1 may be difficult.

The first connection part 70 may include gold (Au). The first connection part 70 may be a gold bump.

In order to arrange one first chip C1 on the flexible circuit board for an all-in-one chip-on-film according to the embodiment, a plurality of the first connection parts 70 are formed by the first chip C1 and the second plating layer 132a. can be placed between them.

The second plating layer 132 of the first open region OA1 has excellent adhesion properties to the first connection portion 70 including gold (Au) because the content of tin (Sn) is 50 atomic% or more. can do. In the chip package including the flexible circuit board for the all-in-one chip-on-film according to the embodiment, the electrical connection between the first chip C1 and the conductive pattern through the first connection part 70 may be excellent, and reliability is improved. can be

Next, the step of disposing the second chip C2 on the flexible circuit board for the all-in-one chip-on-film according to the embodiment will be described.

A second connection part 80 is disposed in the second open area OA2 of the flexible circuit board for an all-in-one chip-on-film according to the embodiment.

In order to dispose the second chip C2 on the flexible circuit board for the all-in-one chip-on-film according to the embodiment, only a portion corresponding to the region where the second connection part 80 is disposed through the mask M is selectively heated (H). ) can be supplied. In detail, the embodiment may selectively supply heat to a region where the second connector 80 for connecting the second chip C2 is disposed through a selective reflow process.

In detail, in the flexible circuit board for an all-in-one chip-on-film according to the embodiment, even when the second chip C2 is disposed after the first chip C1 is mounted, a selective reflow process is performed. Partial heat supply may be possible.

That is, the manufacturing process according to the embodiment may prevent the heat of the first open area OA from being exposed through the mask. Accordingly, it is possible to prevent the second plating layer disposed in the first open area OA from being transformed from pure tin into an alloy layer of tin and copper due to heat supply. Accordingly, even when different first and second chips C1 and C2 are mounted on one flexible circuit board 100 for an all-in-one chip on film, the second plating layer ( The content of tin (Sn) in 132a) may be 50 atomic% or more, so that assembly of the driving IC chip may be excellent.

Meanwhile, a hole of the mask may be disposed in an area corresponding to the second open area OA2 . Accordingly, the plating layer exposed by heat in the second open area OA2 may be transformed into an alloy layer of tin and copper.

In detail, a portion of the second plating layer 132 exposed by heat through the hole in the mask may be further subjected to diffusion of tin/copper. Accordingly, the content of tin (Sn) in the second plating layer 132b in the second open region OA2 may be less than 50 atomic%. In the second open area OA2 , the second plating layer 132b may be an alloy layer of copper (Cu) and tin (Sn).

The second connection part 80 may include a metal other than gold (Au). Accordingly, the second connection part 80 has excellent assembly performance with the second chip C2 even when the second plating layer 132b located under the second connection part 80 is not pure tin. can do. In addition, the second connection part 80 may include a metal other than gold (Au), thereby reducing manufacturing cost.

For example, the second connection part 80 may include copper (Cu), tin (Sn), aluminum (Al), zinc (Zn), indium (In), lead (Pb), antimony (Sb), or bismuth (bi). ), silver (Ag), and nickel (Ni) may be included.

The second connection part 80 may be a solder bump. The second connection part 80 may be a solder ball. At the temperature of the reflow process, the solder ball may be melted.

In order to dispose one second chip C2 on the flexible circuit board for an all-in-one chip-on-film according to the embodiment, a plurality of the second connection parts 80 include the second chip C2 and the second plating layer 132b. can be placed between them.

At the temperature of the reflow process, excellent bonding of the second chip C2 to the second plating layer 132b on the second open area OA2 may be possible through the second connection part 80 .

In the flexible circuit board for an all-in-one chip-on-film according to the embodiment, the connection of the first chip C1 through the first connection part 70 in the first open area is excellent, and the second connection part 80 in the second open area ) through the connection of the second chip C2 may be excellent.

The flexible circuit board for an all-in-one chip-on-film according to the embodiment may include plating layers having different Sn contents in the first open area OA1 and the second open area OA2, so that the first chip C1 The assembly performance may be excellent, and the assembly performance of the second chip C2 may be excellent.

As in the comparative example, after the first chip is mounted on the first printed circuit board and the second chip is mounted on the second printed circuit board, the first printed circuit board including the first chip and the second chip are provided In the case of bonding a second printed circuit board with an adhesive layer, a problem due to thermal denaturation of the first chip may not occur.

However, in the case of mounting different first and second chips on one substrate as in the embodiment, as the second plating layer is modified by heat in the first open region of the protective layer for connecting the first chip, There was a problem in that it was difficult to assemble the first chip by the first connection part.

In order to solve this problem, the inventor sequentially arranges the first chip and the second chip on the flexible circuit board for the all-in-one chip-on-film through a selective reflow process. Accordingly, the flexible circuit board for an all-in-one chip-on-film according to an embodiment and a chip package including the same include the tin content of the second plating layer in the first open region and the tin content of the second plating layer in the first open region. content may be different. Accordingly, in the chip package including the flexible circuit board for the all-in-one chip-on-film according to the embodiment, excellent electrical connection between the different first and second chips C1 and C2 may be possible.

The second plating layer including pure tin in the first open region may stably mount the first chip, which is a driving IC chip, through the first connection part including gold (Au). In addition, the second plating layer including the copper and tin alloy layers in the second open region is a diode chip, a power supply IC chip, a touch sensor IC chip, MLCC through a second connection portion containing a metal other than gold (Au). Stable mounting of the second chip, which is at least one of a chip, a BGA chip, and a chip capacitor, may be possible.

Accordingly, the flexible circuit board for the all-in-one chip-on film and the chip package including the same according to the embodiment may enable mounting of different types of first and second chips on one all-in-one flexible circuit board with excellent yield. .

In addition, since a plurality of existing printed circuit boards can be replaced with one all-in-one chip-on-film flexible circuit board, it is possible to reduce the size and thickness of the all-in-one chip-on-film flexible circuit board for connecting the display panel and the main board. there is.

Accordingly, in the electronic device including the flexible circuit board for the all-in-one chip-on-film according to the embodiment, various functional units such as a camera module and an iris recognition module may be easily mounted. In addition, the electronic device including the flexible circuit board for the all-in-one chip-on-film of the embodiment may expand the battery space.

In addition, the flexible circuit board for the all-in-one chip-on film can be manufactured through a roll-to-roll process, and the mounting of the chip on the flexible circuit board for the all-in-one chip-on film can be made possible through a selective reflow process, so the convenience and Manufacturing yield can be improved.

As described above, in a chip package including a single-sided all-in-one chip-on-film flexible circuit board, the first chip, the second chip, the display panel, and the main board may all be connected to the same surface.

In such a single-sided all-in-one chip-on-film flexible circuit board, it may be difficult to implement a circuit having a high resolution (QHD).

Recently, various electronic devices having a display unit, such as a smart phone, a television, a monitor, an electronic paper, a wearable device, are required to implement a high-resolution display.

Accordingly, the flexible circuit board for the all-in-one chip-on-film according to the embodiment may include the flexible circuit board for the double-sided all-in-one chip-on-film.

In the double-sided all-in-one chip-on-film flexible circuit board, conductive pattern layers may be positioned on both sides of the board to realize a high-resolution display.

A double-sided all-in-one chip-on-film flexible circuit board according to an embodiment will be described with reference to FIGS. 7, 8A, 8B, 9 and 10 . The same drawings are given to the same components as those of the flexible circuit board for single-sided all-in-one chip-on-film described above. Descriptions overlapping with those described above, such as the thickness of each component and the material of each component, are excluded.

7, 8A, 8B, and 9 are various cross-sectional views of a flexible circuit board for a double-sided all-in-one chip-on-film according to an embodiment showing the mounting of the first chip as the center. That is, FIGS. 7, 8A, 8B, and 9 are views for explaining various cross-sectional structures of the first conductive pattern part for mounting the first chip.

7, 8A, 8B, 9 and 10, the flexible circuit board 100 for an all-in-one chip on film according to the embodiment has both surfaces having electrode pattern portions on both surfaces. It may be a flexible circuit board for an all-in-one chip-on-film.

The flexible circuit board 100 for an all-in-one chip on film according to the embodiment includes a substrate 110 , a wiring pattern layer 120 disposed on the substrate 110 , a plating layer 130 , and A protective layer 140 may be included.

After disposing the wiring pattern layer 120 , the plating layer 130 , and the protective layer 140 on one surface of the substrate 110 according to the embodiment, the wiring pattern layer 120 and the plating layer are disposed on the other surface opposite to the one surface. 130 and the protective layer 140 may be disposed.

That is, an upper wiring pattern layer, an upper plating layer, and an upper protective layer may be disposed on one surface of the substrate 110 according to the embodiment, and a lower wiring pattern layer, a lower plating layer, and a lower protective layer on the other surface opposite to the one surface. This can be arranged.

The upper wiring pattern layer may include a metal material corresponding to the lower wiring pattern layer. Accordingly, process efficiency may be improved. However, the embodiment is not limited thereto, and of course, other conductive materials may be included.

The thickness of the upper wiring pattern layer may correspond to the thickness of the lower wiring pattern layer. Accordingly, process efficiency may be improved.

The upper plating layer may include a metal material corresponding to the lower plating layer. Accordingly, process efficiency may be improved. However, the embodiment is not limited thereto, and of course, other conductive materials may be included.

The thickness of the upper plating layer may correspond to the thickness of the lower plating layer. Accordingly, process efficiency may be improved.

The substrate 110 may include a through hole. The substrate 110 may include a plurality of through holes. The plurality of through-holes of the substrate 110 may be respectively or simultaneously formed by a mechanical process or a chemical process. For example, the plurality of through-holes of the substrate 110 may be formed by a drilling process or an etching process. For example, the through-hole of the substrate may be formed by punching through a laser and desmearing process. The desmear process may be a process of removing the polyimide smear attached to the inner surface of the through hole. By the desmear process, the inner surface of the polyimide substrate may have an inclined surface similar to a straight line.

A wiring pattern layer 120 , a plating layer 130 , and a protective layer 140 may be disposed on the substrate 110 . In detail, a wiring pattern layer 120 , a plating layer 130 , and a protective layer 140 may be sequentially disposed on both surfaces of the substrate 110 .

The wiring pattern layer 120 may be formed by at least one of evaporation, plating, and sputtering.

For example, the wiring layer for forming the circuit may be formed by electroplating after sputtering. For example, the wiring layer for forming the circuit may be a copper plating layer formed by electroless plating. Alternatively, the wiring layer may be a copper plating layer formed by electroless plating and electrolytic plating.

Next, after laminating a dry film on the wiring layer, a patterned wiring layer may be formed on both surfaces of the flexible printed circuit board, ie, the upper and lower surfaces, through exposure, development, and etching processes. Accordingly, the wiring pattern layer 120 may be formed.

A conductive material may be filled in the via holes V1 , V2 , and V3 passing through the substrate 110 . The conductive material filled in the via hole may correspond to the wiring pattern layer 120 or may be a different conductive material. For example, the conductive material filled in the via hole is copper (Cu), aluminum (Al), chromium (Cr), nickel (Ni), silver (Ag), and molybdenum (Mo). It may include at least one metal among gold (Au), titanium (Ti), and alloys thereof. An electrical signal of the conductive pattern portion CP on the upper surface of the substrate 110 may be transmitted to the conductive pattern portion CP on the lower surface of the substrate 110 through a conductive material filled in the via hole.

Next, a plating layer 130 may be formed on the wiring pattern layer 120 .

After that, the protective part PP may be screen-printed on the conductive pattern part CP.

The conductive pattern part CP may include the wiring pattern layer 120 and the plating layer 130 . The area of the wiring pattern layer 120 may correspond to or be different from that of the plating layer 130 . The area of the first plating layer 131 may correspond to or different from the area of the second plating layer 132 .

Referring to FIG. 7 , the area of the wiring pattern layer 120 may correspond to the plating layer 130 . An area of the first plating layer 131 may correspond to an area of the second plating layer 132 .

Referring to FIG. 8 , the area of the wiring pattern layer 120 may be different from that of the plating layer 130 . An area of the wiring pattern layer 120 may correspond to an area of the first plating layer 131 . An area of the first plating layer 131 may be different from an area of the second plating layer 132 . For example, an area of the first plating layer 131 may be larger than an area of the second plating layer 132 .

Referring to FIG. 9 , the area of the wiring pattern layer 120 may be different from that of the plating layer 130 .

Referring to FIG. 10 , an area of the wiring pattern layer 120 on one surface of the substrate 110 is different from that of the plating layer 130 , and an area of the wiring pattern layer 120 on the other surface of the substrate 110 . silver may correspond to the plating layer 130 .

The protective layer 140 is disposed in direct contact with the substrate 110 , disposed in direct contact with the wiring pattern layer 120 , or disposed in direct contact with the first plating layer 131 , It may be disposed in direct contact with the second plating layer 132 .

Referring to FIG. 7 , the first plating layer 131 is disposed on the wiring pattern layer 120 , the second plating layer 132 is formed on the first plating layer 131 , and the second plating layer The protective layer 140 may be partially disposed on the 132 .

8A and 8B , the first plating layer 131 may be disposed on the wiring pattern layer 120 , and the protective layer 140 may be partially disposed on the first plating layer 131 . there is. The second plating layer 132 may be disposed on the plating layer 131 in an area other than the area where the protective layer 140 is disposed.

The first plating layer 131 in contact with the lower surface of the protective layer 140 may be an alloy layer of copper and tin. The second plating layer 132 in contact with the side surface of the protective layer 140 may include pure tin. Accordingly, it is possible to prevent film removal of the protective layer due to the formation of a cavity between the protective layer 140 and the first plating layer 131 , and it is possible to prevent the formation of whiskers, thereby increasing the adhesion of the protective layer. there is. Accordingly, the embodiment may include two plating layers, thereby providing an electronic device with high reliability.

In addition, when only a single tin plating layer 131 is disposed on the wiring pattern layer 120 and the protective layer 140 is disposed on one tin plating layer 131 , the protective layer 140 is thermally cured. When the tin plating layer 131 is heated, copper may be diffused into the tin plating layer 131 . Accordingly, since the tin plating layer 131 may be an alloy layer of tin and copper, there is a problem in that the first chip having the gold bump cannot be securely mounted. Accordingly, the plating layer 130 according to the embodiment requires a first plating layer 131 and a second plating layer 132 in which the concentration of tin can continuously increase as the distance from the substrate increases.

Referring to FIG. 9 , the first plating layer 131 may be disposed on the wiring pattern layer 120 , and the protective layer 140 may be partially disposed on the first plating layer 131 thereon. . The second plating layer 132 may be disposed on the plating layer 131 in an area other than the area where the protective layer 140 is disposed.

In this case, the wiring pattern layer 120 may include a first wiring pattern layer 121 and a second wiring pattern layer 122 . That is, a plurality of wiring pattern layers may be disposed on the substrate.

In addition, although not shown in the drawings, a metal seed layer for improving adhesion between the substrate 110 and the first wiring pattern layer 121 is provided between the substrate 110 and the first wiring pattern layer 121 . may include more. In this case, the metal seed layer may be formed by sputtering. The metal seed layer may include copper.

The first wiring baton layer 121 and the second wiring pattern layer 122 may correspond to each other or may be formed by different processes.

The first wiring baton layer 121 may be formed by sputtering copper to a thickness of 0.1 μm to 0.5 μm. The first wiring baton layer 121 may be disposed on upper and lower portions of the substrate and on inner surfaces of the through holes. In this case, since the thickness of the first wiring baton layer 121 is thin, inner surfaces of the through-holes may be spaced apart from each other.

Next, the second wiring pattern layer 122 may be disposed on the first wiring pattern layer 121 . In addition, the second wiring pattern layer 122 may be entirely filled in the through hole by plating.

Since the first wiring pattern layer 121 is formed by sputtering, it has an advantage of excellent adhesion to the substrate 110 or the metal seed layer, but due to high manufacturing cost, the first wiring pattern layer ( By forming the second wiring pattern layer 122 by plating again on the 121), the manufacturing cost can be reduced. In addition, copper can be filled in the via hole while disposing the second wiring pattern layer 122 on the first wiring pattern layer 121 without separately filling the through-holes of the substrate with a conductive material, so process efficiency This can be improved. In addition, it is possible to prevent voids from being formed in the via hole, and thus it is possible to provide a highly reliable flexible circuit board for an all-in-one chip-on-film and an electronic device including the same.

Referring to FIG. 10 , a plurality of protective layers 140 may be disposed on one surface of the substrate. The passivation layer may include a first passivation layer 141 and a second passivation layer 142 .

For example, the first passivation layer 141 may be partially disposed on one surface of the substrate, and the wiring pattern layer 120 may be disposed on an area other than the area where the passivation layer 141 is disposed. .

The second passivation layer 142 may be disposed on the passivation layer 141 . The second passivation layer 142 may cover the first passivation layer 141 and the wiring pattern layer 120 , and may be disposed in a larger area than the first passivation layer 141 .

The passivation layer 142 may be disposed on a region corresponding to the passivation layer 141 while surrounding the upper surface of the first passivation layer 141 . The width of the second passivation layer 142 may be greater than that of the passivation layer 141 . Accordingly, a lower surface of the second passivation layer 142 may contact the wiring pattern layer 120 and the first passivation layer 141 . Accordingly, the second passivation layer 142 may relieve stress concentration at the interface between the first passivation layer 141 and the wiring pattern layer 120 . Accordingly, it is possible to reduce the occurrence of film removal or cracks that may occur during bending of the flexible circuit board for the all-in-one chip-on-film according to the embodiment.

The plating layer 130 may be disposed in an area other than the area where the second passivation layer 142 is disposed. In detail, in an area other than the area where the second protective layer 142 is disposed, the first plating layer 131 is disposed on the wiring pattern layer 120 , and on the first plating layer 131 thereon. The second plating layers 132 may be sequentially disposed.

A wiring pattern layer 120 may be disposed on the other surface of the substrate opposite to the one surface. The plating layer 130 may be disposed on the wiring pattern layer 120 . A protective layer 140 may be partially disposed on the plating layer 130 .

The width of the passivation layer disposed on one surface of the substrate and the passivation layer disposed on the other surface of the substrate may correspond to each other or may be different from each other.

Although the drawings illustrate that a plurality of protective layers are disposed only on one surface of the substrate, the embodiment is not limited thereto, and of course, a plurality of protective layers may be included on both surfaces of the substrate, respectively. In addition, it goes without saying that a plurality or one passivation layer may be disposed only on one surface of the substrate.

In addition, it goes without saying that the structure of one or both surfaces of the substrate may be variously disposed by combining the structures of the conductive pattern part and the protective part according to at least one of FIGS. 7, 8A, 9 and 10 .

7, 8A, 8B, 9, 11 and 12, the first chip (C1) mounted on the flexible circuit board 100 for double-sided all-in-one chip-on-film according to the embodiment, the display panel (30) and the connection relationship with the main board (40) will be described.

The flexible circuit board 100 for a double-sided all-in-one chip-on-film according to the embodiment includes: a substrate 100 including a through hole; wiring pattern layers 120 respectively disposed on both surfaces of the substrate including the through-holes; a first plating layer 131 disposed on the wiring pattern layer 120; a second plating layer 132 disposed on the first plating layer 131; and a protective layer 140 partially disposed on the wiring pattern layer.

An area in which the protective layer 140 is disposed in which the protective layer 140 is formed may be the protective part PP. In a region other than the protective part PP in which the protective layer is not formed, the conductive pattern part CP may be exposed to the outside. That is, in the open region of the protective layer or in the region where the protective part is not disposed on the conductive pattern part, the conductive pattern part CP is connected to the first chip C1 , the display panel 30 and the main board 40 . may be electrically connected.

The lead pattern part and the test pattern part of the flexible circuit board for the all-in-one chip-on-film according to the embodiment may not overlap the protection part. That is, the lead pattern part and the test pattern part may mean a conductive pattern part located in an open area not covered by the protective layer, and may be divided into a lead pattern part and a test pattern part according to functions.

The lead pattern part may mean a conductive pattern part connected to the first chip, the second chip, the display panel, or the main board.

The test pattern part may mean a conductive pattern part for checking whether a product of the flexible circuit board for an all-in-one chip-on-film according to an embodiment and a chip package including the same is defective.

The lead pattern part may be divided into an inner lead pattern part and an outer lead pattern part according to a position. A portion of the conductive pattern portion that is relatively close to the first chip C1 and does not overlap by the protective layer may be expressed as an inner lead pattern portion. A region of the conductive pattern portion that is relatively far from the first chip C1 and does not overlap by the protective layer may be expressed as an outer lead pattern portion.

7, 8A, 8B, 9, 11 and 12 , the flexible circuit board 100 for an all-in-one chip-on-film according to the embodiment includes a first inner lead pattern portion I1, a second inner It may include a lead pattern part I2 , a third inner lead pattern part I3 , and a fourth inner lead pattern part I4 .

The flexible circuit board 100 for an all-in-one chip-on-film according to the embodiment includes a first outer lead pattern portion O1, a second outer lead pattern portion O2, a third outer lead pattern portion O3, and a fourth outer lead. A pattern portion O4 may be included.

The flexible circuit board 100 for an all-in-one chip-on-film according to the embodiment may include a first test pattern part T1 and a second test pattern part T2 .

On one surface of the flexible circuit board 100 for an all-in-one chip-on-film according to the embodiment, the first inner lead pattern portion I1, the second inner lead pattern portion I2, and the third inner lead pattern portion I3 are , the first outer lead pattern portion O1 , and the second outer lead pattern portion O2 may be disposed.

On the other surface opposite to the one surface of the flexible circuit board 100 for an all-in-one chip-on-film according to the embodiment, the fourth inner lead pattern portion I4 , the third outer lead pattern portion O3 , and the fourth outer lead It may include a pattern part O4 , the first test pattern part T1 , and the second test pattern part T2 .

The first chip C1 disposed on one surface of the flexible circuit board 100 for an all-in-one chip-on-film according to the embodiment includes the first inner lead pattern portion I1, the first inner lead pattern portion I1 through the first connection portion 70, and the It may be connected to the second inner lead pattern part I2 or the third inner lead pattern part I3 .

The first connection part 70 may include a first sub-second connection part 71 , a second sub-first connection part 72 , and a third sub-first connection part 73 according to a position and/or a function. .

The first chip C1 disposed on one surface of the flexible circuit board 100 for an all-in-one chip-on-film according to the embodiment includes the first inner lead pattern part I1 through the first sub-first connection part 71 . ) can be electrically connected to.

The first inner lead pattern portion I1 may transmit an electrical signal to the first outer lead pattern portion O1 adjacent to the second via hole V2 along the upper surface of the substrate 110 . The second via hole V2 and the first outer lead pattern part O1 may be electrically connected to each other. That is, the first inner lead pattern portion I1 and the first outer lead pattern portion O1 may be one end and the other end of the conductive pattern portion extending in one direction.

For example, the main board 40 may be connected to the first outer lead pattern part O1 through an adhesive layer 50 . Accordingly, the signal transmitted from the first chip may be transmitted to the main board 40 through the first inner lead pattern unit I1 and the first outer lead pattern unit O1 .

In addition, the first inner lead pattern part I1 is electrically connected to the second via hole V2 along the upper surface of the substrate 110, and through the conductive material filled in the second via hole V2, the substrate An electrical signal may be transmitted to the third outer lead pattern portion O3 adjacent to the second via hole V2 along the lower surface of 110 . The second via hole V2 may be electrically connected to the third outer lead pattern part O3 . Accordingly, although not shown in the drawings, it goes without saying that the main board 40 may be electrically connected to the third outer lead pattern part O3 through the adhesive layer 50 .

The first chip C1 disposed on one surface of the all-in-one chip-on-film flexible circuit board 100 according to the embodiment includes the second inner lead pattern part I2 through the second sub-first connection part 72 . ) can be electrically connected to.

The second inner lead pattern portion I2 disposed on the upper surface of the substrate 110 is formed through a conductive material filled in the first via hole V1 located below the second inner lead pattern portion I2. An electrical signal may be transmitted to the fourth inner lead pattern portion I4 adjacent to the first via hole V1 and the first test pattern portion T1 along the lower surface of the 110 . The first via hole V1 , the first test pattern portion T1 , and the fourth inner lead pattern portion I4 may be electrically connected to each other on the lower surface of the substrate.

A display panel 30 may be attached to the fourth inner lead pattern portion I4 and the fourth outer lead pattern portion O4 .

The first test pattern part T1 may check a failure of an electrical signal transmitted through the first via hole V1 . For example, the accuracy of the signal transmitted to the fourth inner lead pattern part I4 may be checked through the first test pattern part T1 . In detail, as the voltage or current is measured in the first test pattern part T1, it is possible to check whether or not a short circuit or a short circuit occurs in the conductive pattern part located between the first chip and the display panel, or the location of the occurrence of the product. can improve the reliability of

The first chip C1 disposed on one surface of the flexible circuit board 100 for an all-in-one chip-on-film according to the embodiment includes the third inner lead pattern part I3 through the third sub-first connection part 73 . ) can be electrically connected to.

The third inner lead pattern portion I3 may transmit an electrical signal to the second outer lead pattern portion O2 adjacent to the third via hole V3 along the upper surface of the substrate 110 . The third via hole V3 and the second outer lead pattern part O2 may be electrically connected to each other. That is, the third inner lead pattern portion I3 and the second outer lead pattern portion O2 may be one end and the other end of the conductive pattern portion extending in one direction.

In addition, the third inner lead pattern part I3 is electrically connected to the third via hole V3 along the upper surface of the substrate 110, and through the conductive material filled in the third via hole V3, the substrate An electrical signal may be transmitted to the fourth outer lead pattern portion O4 and the second test pattern portion T2 adjacent to the third via hole V3 along the lower surface of 110 .

The second via hole V2 , the fourth outer lead pattern part O4 , and the second test pattern part T2 may be electrically connected to the lower surface of the substrate.

As described above, the display panel 30 may be attached to the fourth inner lead pattern portion I4 and the fourth outer lead pattern portion O4 through the adhesive layer 50 .

The second test pattern part T2 may check a failure of an electrical signal that may be transmitted through the third via hole V3 . For example, the accuracy of the signal transmitted to the fourth outer lead pattern unit O4 may be checked through the second test pattern unit T2 . In detail, as the voltage or current is measured in the second test pattern part T2, it is possible to check whether or not a short circuit or a short circuit occurs in the conductive pattern part positioned between the first chip and the display panel, or the location of the occurrence of the product. can improve the reliability of

In the flexible circuit board for an all-in-one chip-on-film according to the embodiment, the display panel 30 may be disposed on the other surface opposite to the one surface on which the first chip C1 is disposed, thereby improving the degree of freedom in design. In addition, by disposing the display panel on the other surface opposite to the one surface on which the plurality of chips are mounted, effective heat dissipation may be possible. Accordingly, the reliability of the flexible circuit board for the all-in-one chip-on-film according to the embodiment may be improved.

Fig. 11 is a plan view of Fig. 8A, and Fig. 12 is a bottom view of Fig. 8A.

11 and 12 , the flexible circuit board 100 for an all-in-one chip-on-film according to the embodiment may include sprocket holes on both sides of the longitudinal direction for convenience in manufacturing or processing. Accordingly, the flexible circuit board 100 for the all-in-one chip-on-film may be wound or unwound by the sprocket hole in a roll-to-roll manner.

The flexible circuit board 100 for the all-in-one chip-on-film may be defined as an inner region IR and an outer region OR based on a cut portion shown by a dotted line.

Conductive pattern portions for connecting the first chip, the second chip, the display panel, and the main board may be disposed in the inner region IR of the all-in-one chip-on-film flexible circuit board 100 .

A chip package including a flexible circuit board 100 for an all-in-one chip-on-film and a chip package including the flexible circuit board 100 for an all-in-one chip-on-film by cutting the portion in which the sprocket hole is formed and placing the chip on the substrate It can be processed into electronic devices.

Referring to FIG. 11 , on the upper surface of the flexible circuit board 100 for the all-in-one chip-on film, the first, which is a region of the conductive pattern part CP, through the first open region OA1 of the protective layer 140 . Inner lead pattern portion I1, the second inner lead pattern portion I2

and the third inner lead pattern portion I3 may be exposed to the outside.

In addition, on the upper surface of the all-in-one chip-on-film flexible circuit board 100 , the first outer lead pattern part, which is a region of the conductive pattern part CP, through the third open region OA3 of the protective layer 140 . (O1) may be exposed to the outside.

The first inner lead pattern portion I1 and the third inner lead pattern portion I3 may be conductive pattern portions to be connected to the chip through the first connection portion.

An end of the first inner lead pattern portion I1 and an end of the third inner lead pattern portion I3 may be arranged in a line. For example, the plurality of first inner lead pattern portions I1 may be spaced apart from each other in a horizontal direction (x-axis direction) of the substrate, and end portions of the first inner lead pattern portions I1 may be arranged in a line. . For example, the plurality of third inner lead pattern portions I3 may be spaced apart from each other in the horizontal direction (x-axis direction) of the substrate, and end portions of the third inner lead pattern portions I3 may be arranged in a line. . Accordingly, the first inner lead pattern portion I1 and the third inner lead pattern portion I3 may have excellent bonding to the first connection portion and the first chip.

In the horizontal direction (x-axis direction) of the substrate, the plurality of second via holes V2 may be spaced apart from each other and arranged in a line. In the horizontal direction (x-axis direction) of the substrate, the plurality of third via holes V3 may be spaced apart from each other and arranged in a line.

An end of the first inner lead pattern portion I1 may be spaced apart from an end of the second inner lead pattern portion I2 .

The second inner lead pattern portion I2 may be a conductive pattern that is not bonded to the first chip. At least one end of one end and the other end of the second inner lead pattern part I2 may not be arranged in a line.

For example, the plurality of second inner lead pattern portions I2 may be spaced apart from each other in the horizontal direction (x-axis direction) of the substrate. In addition, at least one end of one end and the other end of the second inner lead pattern portion I2 has a distance from the end of the first inner lead pattern portion I1 toward the horizontal direction (x-axis direction) of the substrate. can decrease. At least one end of one end and the other end of the second inner lead pattern portion I2 may increase in a distance from the end of the first inner lead pattern portion I1 in the horizontal direction (x-axis direction) of the substrate. can

In the horizontal direction (x-axis direction) of the substrate, the plurality of first via holes V1 may be spaced apart from each other and arranged in different rows.

The length between one end and the other end of the second inner lead pattern portion I2 may include a first set portion of the second inner lead pattern portions I2 that gradually decreases in the horizontal direction (x-axis direction) of the substrate. there is. In detail, the length between one end and the other end of the second inner lead pattern portion I2 is gradually decreased from the first length in the horizontal direction (x-axis direction) of the substrate to become the second length. a first set of (I2). In this case, the first length may be greater than the second length. A plurality of first sets may be disposed on the substrate 110 . Accordingly, the second inner lead pattern portions I2 whose length is gradually reduced from the first length to the second length may be included on the substrate 110 . The second inner lead pattern portion I2 adjacent to the second inner lead pattern portion I2 having the second length may have the first length again. Accordingly, a first set of the second inner lead pattern portions I2 having a length gradually decreasing from a first length to a second length in the horizontal direction (x-axis direction) of the substrate; and a first set portion of the second inner lead pattern portions I2 whose length is gradually reduced from the first length to the second length may be repeatedly disposed.

At least one end of one end and the other end of the second inner lead pattern portion I2 may decrease in a distance from the end of the first inner lead pattern portion I1 toward the horizontal direction (x-axis direction) of the substrate. can

The plurality of first inner lead pattern portions I1 may be spaced apart from each other by a first interval. One end of the second inner lead pattern part I2 may be positioned in a region between two adjacent first inner lead pattern parts I1 that are spaced apart from each other.

In the horizontal direction of the substrate, an end of the first inner lead pattern portion I1 and one end of the second inner lead pattern portion I2 may be alternately disposed.

Referring to FIG. 12 , on the lower surface of the flexible circuit board 100 for the all-in-one chip-on-film, the fourth, which is one region of the conductive pattern part CP, through the third open region OA3 of the protective layer 140 . The inner lead pattern portion I4 and the fourth outer lead pattern portion O4 may be exposed to the outside.

8B and 13 to 17, a chip package including a first chip C1 and a second chip C2 on the flexible circuit board 100 for a double-sided all-in-one chip-on-film according to the embodiment is detailed. explain in detail.

13 is a schematic plan view of a chip package including the flexible circuit board 100 for a double-sided all-in-one chip-on-film according to the embodiment.

13A and 13B , the flexible circuit board 100 for a double-sided all-in-one chip-on-film according to the embodiment may include disposing a first chip C1 and a second chip C2 on the same surface. .

In the double-sided all-in-one chip-on-film flexible circuit board 100 according to the embodiment, a length in a horizontal direction (x-axis direction) may be greater than a length in a vertical direction (y-axis direction). That is, the flexible circuit board 100 for a double-sided all-in-one chip-on-film according to the embodiment may include two long sides in a horizontal direction and two short sides in a vertical direction.

Each of the first chip C1 and the second chip C2 may have a length in a horizontal direction (x-axis direction) greater than a length in a vertical direction (y-axis direction). That is, the first chip C1 and the second chip C2 may include two long sides in a horizontal direction and two short sides in a vertical direction.

The long side of the double-sided all-in-one chip-on-film flexible circuit board 100 according to the embodiment may be disposed parallel to the long side of the first chip C1 and the long side of the second chip C2, respectively, so that a plurality of chips They can be efficiently arranged on a single double-sided all-in-one chip-on-film flexible circuit board 100 .

A transverse length (long side) of the first chip C1 may be greater than a transverse length (long side) of the second chip C2 . A longitudinal length (short side) of the first chip C1 may be smaller than a longitudinal length (short side) of the second chip C2 . Referring to FIG. 13A , the second chip C2 may be disposed under the first chip C1 . A long side of the first chip C1 and a long side of the second chip C2 may overlap vertically.

Referring to FIG. 13B , the second chip C2 may be disposed on the side of the first chip C1 . The long side of the first chip C1 and the long side of the second chip C2 may not overlap vertically.

The first chip C1 is a driving IC chip, and the second chip C2 is a second chip C2a of any one of a diode chip, a power supply IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor. ) and a diode chip, a power supply IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor.

A manufacturing step of a chip package including a flexible circuit board for a double-sided all-in-one chip-on-film according to an embodiment will be described with reference to FIGS. 14 to 17 .

14 is a plan view of the flexible circuit board 100 for a double-sided all-in-one chip-on-film according to the embodiment.

14A and 14B , the protective layer 140 located on one surface of the double-sided all-in-one chip-on-film flexible circuit board 100 according to the embodiment may include a plurality of holes. That is, the protective layer 140 may include a plurality of open regions.

The first open area OA1 of the passivation layer may be an area exposed to be connected to the first connection part 70 . A surface of the conductive pattern part CP exposed in the first open area OA1 of the protective layer toward the first connection part may include pure plating. That is, the content of tin in the second plating layer included in the conductive pattern part CP in the first open area OA1 of the passivation layer may be 50 atomic% or more.

The second open area OA2 of the passivation layer may be an area exposed to be connected to the second connection part 80 . The conductive pattern part CP exposed in the second open area OA2 of the passivation layer may include an alloy layer of copper and tin on a surface facing the second connection part. That is, the content of tin in the second plating layer included in the conductive pattern part CP in the second open area OA2 of the passivation layer may be less than 50 atomic %.

The first open area OA1 may be an area for connecting the first chip. The first inner lead pattern portions I1 extending from the first outer lead pattern portions O1 positioned in the third open area OA3 and facing the inside of the first open area OA1 may correspond to each other or differ from each other. can have a width. For example, a width W1 of the first outer lead pattern portion O1 may correspond to a width W2 of the first inner lead pattern portion I1 . For example, the width W1 of the first outer lead pattern portion O1 may be greater than the width W2 of the first inner lead pattern portion I1 . In detail, the difference between the width W1 of the first outer lead pattern portion O1 and the width W2 of the first inner lead pattern portion I1 may be within 20%.

The first inner lead pattern part I1 and the third inner lead pattern part I3 extending toward the inside of the first open area OA1 may have corresponding widths.

The first outer lead pattern part O1 and the second outer lead pattern part O2 extending from the first open area OA1 toward the outside of the substrate may have a width corresponding to each other. Accordingly, a first chip having a fine line width and requiring a large number of first connections and a second chip having a large line width and requiring a small number of second connections are combined into one all-in-one chip-on-film flexible circuit board. All of them can be mounted on (100). In this case, the fine line width is determined by the line width of any one of the first outer lead pattern part O1 and the second outer lead pattern part O2 being the fifth outer lead pattern part O5 and the sixth outer lead pattern part O6. ) may mean a smaller line width than any one of the line widths. On the other hand, the large line width of any one of the outer lead pattern portion O5 and the sixth outer lead pattern portion O6 is one of the first outer lead pattern portion O1 and the second outer lead pattern portion O2. It may mean that any one line width is relatively larger than the line width of any one of the fifth outer lead pattern part O5 and the sixth outer lead pattern part O6 .

The flexible circuit board 100 for an all-in-one chip-on-film according to the embodiment may include a plurality of second open areas OA2 for connecting different types of second chips C2a and C2b, respectively.

One second open area OA2 may be an area for connecting one second chip C2a. The fifth outer lead pattern portion O5 extending from the fifth inner lead pattern portion I5 positioned in the second open area OA2 toward the outside of the substrate may have different widths. For example, the width W3 of the fifth inner lead pattern portion I5 may be greater than the width W4 of the fifth outer lead pattern portion O5 . In detail, the width W3 of the fifth inner lead pattern portion I5 may be 1.5 times greater than the width W4 of the fifth outer lead pattern portion O5.

The other second open area OA2 may be an area for connecting the other second chip C2b. The sixth outer lead pattern portion O6 extending from the sixth inner lead pattern portion I6 positioned in the second open area OA2 toward the outer edge of the substrate may have different widths. For example, the width W5 of the sixth inner lead pattern portion I6 may be greater than the width W6 of the sixth outer lead pattern portion O6 . In detail, the width W5 of the sixth inner lead pattern portion I6 may be 1.5 times greater than the width W6 of the sixth outer lead pattern portion O6 .

Any one of the width W3 of the fifth inner lead pattern portion I5 exposed through the second open area and the width W5 of the sixth inner lead pattern portion I6 is the width of the first open area It may be larger than the width W2 of the first inner lead pattern portion I1 exposed through the . Accordingly, lead pattern portions corresponding to the first and second connection portions having various sizes/shapes can be formed, thereby improving design freedom. That is, the embodiment may include different types of first chip, inner lead pattern portions having various sizes suitable for the second chip, and inner lead pattern portions having various shapes, so that an optimal chip package may be possible.

The shape of the in-lead pattern part positioned under the first chip may be different from the shape of the in-lead pattern part positioned under the second chip. Accordingly, the embodiment may include in-lead pattern portions having different shapes, each of which may have excellent adhesion characteristics with different types of first and second chips. Accordingly, the flexible circuit board for an all-in-one chip-on-film according to the embodiment may have excellent bonding characteristics between the first chip and the second chip.

That is, the in-lead pattern portions having different shapes may be an optimal pattern design for securing a constant junction resolution by mounting different types of first and second chips on a single substrate.

A shape of the first inner lead pattern portion I1 on a plane may be a rectangular stripe pattern. In detail, the shape of the first inner lead pattern portion I1 on a plane may be a rectangular stripe pattern having a uniform width and extending in one direction. For example, one end and the other end of the first inner lead pattern portion I1 may have the same width.

For example, the shape in the plane of the fifth inner lead pattern portion I5 or the sixth inner lead pattern portion I6 may have various shapes such as polygonal, circular, elliptical, hammer-shaped, T-shaped, and random shapes. may be a protrusion pattern of In detail, the shape in the plane of the fifth inner lead pattern portion I5 or the sixth inner lead pattern portion I6 has a variable width and is a polygon, a circle, an ellipse, and a hammer extending in a direction different from the one direction. It may be a protrusion pattern such as a shape, a T-shape, or a random shape. For example, at least one inner lead pattern portion of the fifth inner lead pattern portion I5 and the sixth inner lead pattern portion I6 may have different widths at one end and the other end. The width of the other end of the fifth inner lead pattern portion I5 and the sixth inner lead pattern portion I6 may be greater than the width of one end close to the protective layer. However, the embodiment is not limited thereto, and the width of the other end of the fifth inner lead pattern portion I5 and the sixth inner lead pattern portion I6 at one end close to the protective layer is greater than the width of the other end at the end farther from the protective layer. Of course, this can be small.

For example, when the second chip is an MLCC chip, the inner lead pattern portion may have the same T-shape as the fifth inner lead pattern portion I5 of FIG. 14B .

For example, when the second chip is a BGA chip, the inner lead pattern portion may have the same circular shape as the sixth inner lead pattern portion I6 of FIG. 14A . Alternatively, when the second chip is a BGA chip, the inner lead pattern portion may have a semicircular shape like the sixth inner lead pattern portion I6 of FIG. 14B or a rounded end shape.

The shape of the first inner lead pattern part and the first connection part may be the same. For example, a top view of the first inner lead pattern part and the first connection part may have a rectangular shape. Here, when the shape of the first inner lead pattern part and the first connection part are the same, it means that they are polygons having the same planar shape, and may include different sizes.

The shapes of the fifth inner lead pattern part and the second connection part may be the same as or different from each other. The shapes of the sixth inner lead pattern part and the second connection part may be the same as or different from each other.

14A and 15A , a planar shape of the fifth inner lead pattern part I5 may be a polygonal shape, and a planar shape of the second connection part may be a circular shape. A planar shape of the sixth inner lead pattern part I6 may be a circular shape, and the second connection part may have a circular shape.

14B and 15B , a planar shape of the fifth inner lead pattern part I5 may be a polygonal shape, and the second connection part may have a rectangular shape or an oval shape having rounded corners. A planar shape of the sixth inner lead pattern part I6 may be a long semicircle shape, and the second connection part may have a circular shape.

The planar shape of the first connection part 70 may have a horizontal length and a vertical length (aspect ratio) corresponding to or different from each other. For example, the planar shape of the first connection part 70 may be a square shape having a horizontal length and a vertical length (aspect ratio) corresponding to each other, or a rectangular shape having different horizontal and vertical lengths (aspect ratio).

The planar shape of the second connection part 80 may have a horizontal length and a vertical length (aspect ratio) corresponding to or different from each other. For example, the planar shape of the second connection part 80 may be a circular shape in which a horizontal length and a vertical length (aspect ratio) correspond to each other, or an elliptical shape in which the horizontal length and vertical length (aspect ratio) are different from each other.

One pitch, which is an interval between the adjacent first outer lead pattern parts O1, is an outer lead of at least one of the adjacent fifth outer lead pattern part O5 and the sixth outer lead pattern part O6. It may be smaller than the second pitch that is the interval between the pattern parts. In this case, the first interval and the second interval may mean an average separation interval between two adjacent conductive pattern portions.

The first gap P1 may be less than 100 μm. For example, the first interval may be less than 30 μm. For example, the first interval may be 1 μm to 25 μm.

The second gap P2 may be 100 μm or more. For example, the second interval may be 100 μm to 500 μm. For example, the second interval may be 100 μm to 300 μm.

Accordingly, interference of signals between the conductive pattern portions respectively connected to the first chip and the second chip can be prevented, and signal accuracy can be improved.

In the first open area OA1 , the planar area of the first inner lead pattern part I1 may correspond to the first connection part 70 or may be different from each other.

The width of the first inner lead pattern part I1 and the width of the first connection part 70 may be the same or have a difference of less than 20%. Accordingly, the first inner lead pattern part I1 and the first connection part 70 may be stably mounted. In addition, adhesion between the first inner lead pattern part I1 and the first connection part 70 may be improved.

In the second open area OA2 , a plane area of any one of the fifth inner lead pattern part I5 and the sixth inner lead pattern part I6 corresponds to the second connection part 80 , may be different.

For example, the width of the second connection part 80 may be 1.5 times or more greater than the width of the inner lead pattern part of any one of the fifth inner lead pattern part I5 and the sixth inner lead pattern part I6 . . Accordingly, the width of the second connection part 80 has improved adhesion between any one of the fifth inner lead pattern part I5 and the sixth inner lead pattern part I6 and the second connection part 80 . can be

A step of disposing the first connection part 70 and the second connection part 80 on the flexible circuit board 100 for the all-in-one chip-on-film according to the embodiment will be described with reference to FIGS. 15A and 15B .

A first connection part 70 may be disposed on the first inner lead pattern part I1 and the third inner lead pattern part I3 exposed through the first open area OA1 , respectively. For example, the first connection part 70 may entirely or partially cover upper surfaces of the first inner lead pattern part I1 and the third inner lead pattern part I3 .

The total number of the plurality of first inner lead pattern portions I1 disposed to be spaced apart from each other and the plurality of third inner lead pattern portions I3 disposed to be spaced apart from each other corresponds to the number of the first connection portions 70 . can be

For example, referring to FIGS. 16A and 16B , the number of the plurality of first inner lead pattern parts I1 arranged to be spaced apart from each other is 9, and the number of the plurality of third inner lead patterns arranged to be spaced apart from each other is 9. The number of parts I3 is 9, and the number of the first connection parts 70 is 9 of the first inner lead pattern parts I1 and a plurality of third inner lead pattern parts I3 spaced apart from each other. ) may be 18, which is the total sum of 9.

A second connection part 80 may be disposed on the fifth inner lead pattern part I5 and the sixth inner lead pattern part I6 exposed through the second open area OA2 , respectively. For example, the second connection part 80 may completely or partially cover upper surfaces of the fifth inner lead pattern part I5 and the sixth inner lead pattern part I6 .

The number of the plurality of fifth inner lead pattern portions I5 disposed to be spaced apart from each other may correspond to the number of the second connection portions 80 disposed on the fifth inner lead pattern portion I5 .

For example, referring to FIGS. 16A and 16B , the number of the plurality of fifth inner lead pattern portions I5 arranged to be spaced apart from each other is two and disposed on the fifth inner lead pattern portion I5 . The number of the second connection parts 80 to be used may be two.

The number of the plurality of sixth inner lead pattern portions I6 disposed to be spaced apart from each other may correspond to the number of the second connection portions 80 disposed on the sixth inner lead pattern portion I6 .

For example, referring to FIGS. 16A and 16B , the number of the plurality of sixth inner lead pattern portions I6 disposed to be spaced apart from each other is three, and the number of the plurality of sixth inner lead pattern portions I6 disposed on the sixth inner lead pattern portion I6 is three. The number of the second connection parts 80 may be three.

The second connection part 80 may be larger than the first connection part 70 . The width of the fifth inner lead pattern portion I5 or the sixth inner lead pattern portion I6 exposed through the second open area is exposed through the first open area, and the first inner lead pattern portion I1 is exposed through the first open area. ), the second connection portion 80 may be larger than the first connection portion 70 .

The steps of disposing the first chip C1 and the second chips C2a and C2b on the flexible circuit board 100 for the all-in-one chip-on-film according to the embodiment will be described with reference to FIGS. 16A and 16B .

A first chip C1 may be disposed on the first connection part 70 .

A first chip C2 may be disposed on the second connection part 80 .

The first chip C1 and the second chip C2 may be disposed to be spaced apart from each other by a certain distance in order to prevent problems such as signal interference, defects such as disconnection, or defects due to heat.

17 is a cross-sectional view of a chip package including a flexible circuit board for a double-sided all-in-one chip-on-film according to FIGS. 16A and 16B.

The first chip C1 and the second chip C2 may have different sizes on the same surface. For example, the second chip C2 may be larger than the first chip C1 .

Via holes may be disposed under the first chip C1 and the second chip C2 . That is, the substrate 110 in an area corresponding to the first open area OA1 and the second open area OA2 may include a via hole.

The electrical signal of the second chip C2 may be transmitted from the upper surface to the lower surface of the substrate through a conductive material disposed in the fourth via hole V4 . Accordingly, the embodiment may include a large number of conductive pattern portions on one substrate.

The flexible circuit board 100 for an all-in-one chip-on-film according to the embodiment may implement a conductive pattern portion having a fine pitch on both sides, and thus may be suitable for an electronic device having a high-resolution display portion.

In addition, since the flexible circuit board 100 for an all-in-one chip-on-film according to the embodiment is flexible, small in size, and thin in thickness, it can be used in various electronic devices.

For example, referring to FIG. 18 , the flexible circuit board 100 for an all-in-one chip-on-film according to the embodiment may have a reduced bezel, and thus may be used for an edge display.

For example, referring to FIG. 19 , the flexible circuit board 100 for an all-in-one chip-on-film according to the embodiment may be included in a flexible electronic device. Accordingly, a touch device apparatus including the same may be a flexible touch device apparatus. Accordingly, the user may bend or bend it by hand. Such a flexible touch window may be applied to a wearable touch or the like.

For example, referring to FIG. 20 , the flexible circuit board 100 for an all-in-one chip-on-film according to the embodiment may be applied to various electronic devices to which a foldable display apparatus is applied. 20A to 20C , in the foldable display device, the foldable cover window may be folded. The foldable display device may be included in various portable electronic products. In detail, the foldable display device may be included in a mobile terminal (cellular phone), a notebook computer (portable computer), or the like. Accordingly, while the display area of the portable electronic product is enlarged, the size of the device can be reduced during storage or movement, thereby enhancing portability. Accordingly, it is possible to improve the convenience of users of portable electronic products. However, embodiments are not limited thereto, and the foldable display device may be used in various electronic products.

Referring to FIG. 20A , the foldable display may include one folded area in the screen area. For example, the foldable display device may have a C-shape in a folded form. That is, in the foldable display device, one end and the other end opposite to the one end may be superimposed on each other. In this case, the one end and the other end may be disposed close to each other. For example, the one end and the other end may be disposed to face each other.

Referring to FIG. 20B , the foldable display device may include two folded areas in the screen area. For example, the foldable display device may have a G-shape in a folded form. That is, as one end and the other end opposite to the one end are folded in a direction corresponding to each other, the foldable display device may be superimposed on each other. In this case, the one end and the other end may be disposed to be spaced apart from each other. For example, the one end and the other end may be disposed parallel to each other.

Referring to FIG. 20C , the foldable display may include two folded areas in the screen area. For example, the foldable display device may have an S-shape in a folded form. That is, one end of the foldable display device and the other end opposite to the one end may be folded in different directions. In this case, the one end and the other end may be disposed to be spaced apart from each other. For example, the one end and the other end may be disposed parallel to each other.

In addition, although not shown in the drawings, the flexible circuit board 100 for an all-in-one chip-on-film according to the embodiment may be applied to a rollable display.

Referring to FIG. 21 , the flexible circuit board 100 for an all-in-one chip-on-film according to the embodiment may be included in various wearable touch devices including a curved display. Accordingly, the electronic device including the flexible circuit board 100 for the all-in-one chip-on-film according to the embodiment may be slimmed down, downsized, or lightened.

Referring to FIG. 22 , the flexible circuit board 100 for an all-in-one chip-on-film according to the embodiment may be used in various electronic devices having a display part, such as a TV, a monitor, and a notebook computer.

However, the embodiment is not limited thereto, and the flexible circuit board 100 for an all-in-one chip-on-film according to the embodiment may be used in various electronic devices having a flat panel or curved display portion.

Features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Furthermore, features, structures, effects, etc. illustrated in each embodiment can be combined or modified for other embodiments by those of ordinary skill in the art to which the embodiments belong. Accordingly, the contents related to such combinations and modifications should be interpreted as being included in the scope of the present invention.

In addition, although the embodiments have been described above, these are merely examples and do not limit the present invention, and those of ordinary skill in the art to which the present invention pertains are exemplified above in a range that does not depart from the essential characteristics of the present embodiment. It can be seen that various modifications and applications that have not been made are possible. For example, each component specifically shown in the embodiments may be implemented by modification. And the differences related to these modifications and applications should be construed as being included in the scope of the present invention defined in the appended claims.

10: first printed circuit board
20: second printed circuit board
C1: first chip
C2: second chip
30: display panel
40: main board
50: adhesive layer
60: battery
70: first connection part
80: second connection part
100: flexible circuit board for all-in-one chip on film
110: substrate
120: wiring pattern layer
130: plating layer
140: protective layer
CP: conductive pattern part
PP: protection
OA1, OA2, OA3: open area
V1, V2, V3: via hole
O1, O2, O3, O4, O5, O6: Outer lead pattern part
I1, I2, I3, I4, I5, I6: Inner lead pattern part
T1, T2: test pattern part

Claims (19)

Board;
a wiring pattern layer disposed on the substrate;
a plating layer including tin (Sn) disposed on the wiring pattern layer; and
a protective layer partially disposed on the wiring pattern layer;
The content of tin (Sn) of the plating layer in the first open region of the passivation layer is greater than the content of tin (Sn) of the plating layer in the second open region of the passivation layer. The method of claim 1,
The plating layer includes a first plating layer disposed on the wiring pattern layer and a second plating layer disposed on the first plating layer,
The flexible circuit board for an all-in-one chip-on-film, wherein a content of tin in the second plating layer in the first open region is greater than a content of tin in the second plating layer in the second open region. 3. The method of claim 2,
The flexible circuit board for an all-in-one chip-on-film, wherein the content of tin (Sn) in the second plating layer in the first open region is 50 atomic% or more. 3. The method of claim 2,
The flexible circuit board for an all-in-one chip on film, wherein the content of tin (Sn) in the second plating layer in the first open region is 70 atomic% or more. 3. The method of claim 2,
The flexible circuit board for an all-in-one chip-on-film, wherein the content of tin (Sn) in the second plating layer in the first open region is 90 atomic % or more. 3. The method of claim 2,
In the second open region, the second plating layer is an alloy layer of copper (Cu) and tin (Sn). Flexible circuit board for all-in-one chip on film,
Board;
a conductive pattern portion disposed on the substrate; and
a protective layer partially disposed on an area on the conductive pattern part;
The conductive pattern part includes a wiring pattern layer and a plating layer disposed on the wiring pattern layer,
The content of tin (Sn) of the plating layer in the first open region of the passivation layer is greater than the content of tin (Sn) of the plating layer in the second open region of the passivation layer;
a first chip disposed in the first open area;
and a flexible circuit board for an all-in-one chip-on-film including a second chip disposed in the second open region. 8. The method of claim 7,
A first connection part and a second connection part are respectively disposed on the one region and the other region on the conductive pattern part,
a first chip is disposed on the first connection part;
and a flexible circuit board for an all-in-one chip-on-film, wherein a second chip is disposed on the second connection part. 8. The method of claim 7,
The first chip is a drive IC chip,
The second chip is a diode chip, a power supply IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, a chip package comprising a flexible circuit board for an all-in-one chip-on-film comprising at least one of a chip capacitor. 9. The method of claim 8,
and a flexible circuit board for an all-in-one chip-on-film, wherein the first and second connectors have different sizes and different shapes. 8. The method of claim 7,
and wherein the first chip and the second chip are disposed on the same surface of the all-in-one chip-on-film flexible circuit board. 9. The method of claim 8,
The first connecting portion includes gold (Au),
and the second connection part includes a flexible circuit board for an all-in-one chip-on-film including a metal other than gold (Au). 8. The method of claim 7,
The plating layer includes a first plating layer disposed on the wiring pattern layer and a second plating layer disposed on the first plating layer,
The content of tin (Sn) in the second plating layer in the first open region of the protective layer is 50 atomic% or more,
and a flexible circuit board for an all-in-one chip on film, wherein the content of tin (Sn) in the second plating layer in the second open region of the protective layer is less than 50 atomic%. 14. The method of claim 13,
and a flexible circuit board for an all-in-one chip-on-film, wherein the content of tin (Sn) in the second plating layer in the first open region is 70 atomic% or more. 14. The method of claim 13,
and a flexible circuit board for an all-in-one chip on film, wherein the content of tin (Sn) in the second plating layer in the first open region is 90 atomic % or more. 14. The method of claim 13,
and a flexible circuit board for an all-in-one chip on film, wherein the second plating layer in the second open region is an alloy layer of copper (Cu) and tin (Sn). Board;
a conductive pattern portion disposed on the substrate; and
a protective layer partially disposed on an area on the conductive pattern part;
The conductive pattern part includes a wiring pattern layer, a first plating layer disposed on the wiring pattern layer, and a second plating layer disposed on the first plating layer,
The all-in-one chip-on film including a content of tin (Sn) in the second plating layer in the first open region of the passivation layer is greater than a content of tin (Sn) in the second plating layer in the second open region of the passivation layer for flexible circuit boards;
a display panel connected to one end of the all-in-one flexible circuit board; and
and a main board connected to the other end opposite to the one end of the all-in-one flexible circuit board. 18. The method of claim 17,
A first connection part and a second connection part are respectively disposed on the one region and the other region on the conductive pattern part,
a first chip is disposed on the first connection part;
and a second chip is disposed on the second connector. 18. The method of claim 17,
The display panel and the main board are disposed to face each other,
and wherein the all-in-one flexible circuit board is bent and disposed between the display panel and the main board.

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