KR20190062948A - Display device - Google Patents

Abstract

According to the present invention, a display device comprises: a substrate including a display region in which a plurality of pixels are defined and a non-display region which surrounds the display region; a plurality of signal wirings disposed in the display region; a pad part disposed in the non-display region and formed of a plurality of pads; a plurality of first data link wirings and a plurality of second data link wirings connecting each of the plurality of signal wirings and each of the plurality of pads; a first capacitance compensation pattern overlapping the plurality of first data link wirings; and a second capacitance compensation pattern overlapping the plurality of second data link wirings and spaced apart from the first capacitance compensation pattern. Therefore, an RC delay deviation between the plurality of data link wirings can be minimized to improve a reliability of the display device.

Description

Display device {DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device capable of preventing an image quality deterioration by making an RC delay (RC delay) according to a length deviation between a plurality of link lines uniform.

A flat panel display device such as a liquid crystal display device, an organic light emitting diode display device, and a quantum dot display device has a thin and low And is receiving the spotlight as a next-generation display device due to power consumption.

The display device may include a driver IC (Driver Integrated Circuit) that provides a signal for driving the plurality of pixels. The driving IC provides a signal to each pixel through a data link wiring arranged in a non-display area of the display device.

However, in order to reduce the size of the non-display area, the data link wiring includes a portion extending in a diagonal direction rather than a linear direction. Accordingly, the length of the data link wiring can be made different from each other depending on the position of the data link wiring or the like. For example, among the plurality of data link wirings receiving signals from the same driver IC, the data link wirings disposed at the center portion are relatively short in length, while the data link wirings disposed at the edge portion are relatively long. Therefore, there is a problem that the wiring resistance of the link wiring disposed at the edge portion is larger than that of the link wiring disposed at the center portion, and the RC delay value due to the link wiring at the edge portion is increased as compared with the center portion.

In particular, as the non-display area is reduced in terms of design and space utilization, the interval between the data link wires arranged at the edge portion can be greatly reduced. In this case, since the length of the link wiring disposed at the edge portion is relatively longer, the size of the capacitance that increases as the spacing of the data link wiring decreases increases as the size of the link wiring disposed at the edge portion becomes largest, The wiring can be the smallest. Therefore, the problem that the RC delay value due to the data link wiring is increased at the edge portion as compared with the central portion may be more serious in a display device in which a non-display region is reduced and a narrow bezel is implemented.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a data distributing method and a data distributing method, which are capable of improving the resistance deviation between data link interconnections arranged at the center portion and data link interconnections disposed at the edge portion, And to provide a display device capable of increasing the capacitance of the link wiring and minimizing the deviation of the RC delay.

Another problem to be solved by the present invention is to provide a display device capable of reducing the RC delay due to a capacitance difference between a plurality of data link lines arranged at a central portion and a plurality of data link lines arranged at an edge portion, And to provide a display device capable of improving the problem of an increase in deviation.

Another problem to be solved by the present invention is to provide a display device in which a plurality of data link wires are formed so as to be alternately arranged in different layers in a non-display area, thereby minimizing the size of the non-display area.

Another object of the present invention is to provide a display device capable of minimizing a variation in capacitance in a display device driven by a column data feeding method.

The problems of the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a display device including a substrate including a display region in which a plurality of pixels are defined and a non-display region surrounding the display region, a plurality of signals A plurality of first data link wirings and a plurality of second data link wirings for connecting each of the plurality of signal wirings and the plurality of pads, A first capacitance compensation pattern overlapping the data link wiring, and a second capacitance compensation pattern overlapping the plurality of second data link wiring lines and spaced apart from the first capacitance compensation pattern. Therefore, in order to minimize the RC delay deviation between the plurality of data link wirings, the capacitance of the data link wiring disposed at the central portion can be increased to improve the reliability of the display device.

According to another aspect of the present invention, there is provided a display device including a substrate including a display region where a plurality of pixels are arranged and a non-display region including a pad portion including a plurality of pads, a plurality of display regions And a plurality of first data link lines, a plurality of first data link lines and a plurality of second data link lines for connecting the plurality of pads of the non-display region and the signal lines of the non- A first capacitance compensation pattern and a second capacitance compensation pattern arranged. Therefore, the wiring resistance of the data link wiring arranged at the edge portion is larger than that of the data link wiring arranged at the center, and the RC delay value due to the link wiring at the edge portion is increased compared with the central portion can be improved .

The details of other embodiments are included in the detailed description and drawings.

The present invention can minimize a RC delay deviation between a plurality of data link wirings by constructing a capacitance compensation pattern so as to overlap with a resistance compensation pattern on a plurality of data link wirings constituting a resistance compensation pattern having a zigzag shape.

Further, according to the present invention, since the first data link wiring and the second data link wiring alternately arranged in the plurality of data link wirings are formed in different layers, the area occupied by the plurality of data link wirings in the non-display area is reduced .

Further, the present invention forms a capacitance compensation pattern on a plurality of data link wirings, thereby compensating for the difference in capacitance increase of the data link wiring between the central part and the edge part, which occurs when the narrow bezel is implemented, Can be improved.

In addition, the present invention can improve the quality of a display device by minimizing the capacitance fluctuation of a plurality of data link wirings in a display device driven by a column inversion method.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the specification.

1 is a plan view of a display device according to an embodiment of the present invention.
2 is an enlarged view of the X region in Fig.
3 is a graph for explaining the effect of the display device according to the embodiment of the present invention.
4 is an enlarged view of a non-display area of a display device according to another embodiment of the present invention.
5 is an enlarged view of a non-display area of a display device according to another embodiment of the present invention.
6 is a graph for explaining the effect of the display device according to another embodiment of the present invention.
7 is an enlarged view of a non-display area of a display device according to another embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Where the terms "comprises", "having", "done", and the like are used in this specification, other portions may be added unless "only" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

It is to be understood that an element or layer is referred to as another element or layer, including both on or between other elements or intervening layers.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

The sizes and thicknesses of the individual components shown in the figures are shown for convenience of explanation and the present invention is not necessarily limited to the size and thickness of the components shown.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other partially or entirely and technically various interlocking and driving is possible as will be appreciated by those skilled in the art, It may be possible to cooperate with each other in association.

Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a plan view of a display device according to an embodiment of the present invention. 1, only the substrate 110, the data driver 120, the gate driver 130, and the link lines DLL (GLL) among the various components of the display device 100 are shown for convenience of explanation.

The substrate 110 is a base member for supporting various components of the display device 100, and may be made of an insulating material. For example, the substrate 110 may be made of a plastic material such as glass or polyimide, but is not limited thereto.

The substrate 110 may define a display area AA and a non-display area NA surrounding the display area AA.

The display area AA is an area where an image is actually displayed in the display device 100 and various display elements and signal lines for driving the display part can be arranged in the display area AA. For example, the display unit may be a liquid crystal display unit that drives the liquid crystal by a pixel electrode made of a transparent conductive material such as ITO (Indium Tin Oxide) or the like and an electric field generated by a voltage applied to the common electrode. However, the present invention is not limited thereto, and the display portion may be an organic light emitting display portion including an organic light emitting element including an anode, an organic layer, and a cathode. In addition, various driving elements such as a thin film transistor, a capacitor, and the like for driving the display portion may be disposed in the display area AA. As shown in Fig. 1, a plurality of signal wirings such as a gate wiring GL, a data wiring DL, and the like can be disposed in the display area AA.

A plurality of pixels are arranged in the display area AA. The plurality of pixels may include a red pixel, a green pixel, and a blue pixel as a minimum unit for emitting light. Each of the plurality of pixels may be connected to the gate wiring GL and the data wiring DL.

The non-display area NA can be defined as an area where no image is displayed, and an area surrounding the display area AA. The non-display area NA may be provided with various components for driving a plurality of pixels arranged in the display area AA. 1, the data driver 120, the gate driver 130, and the link lines GLL and DLL connected to various signal lines of the display area AA are formed on the substrate 110 And can be disposed in the non-display area NA.

The data driver 120 processes data for displaying an image and a driving signal for processing the data, and supplies the signals to a plurality of pixels in the display area AA. The data driver 120 supplies a data voltage to a plurality of pixels of the display area AA through various wirings arranged in the non-display area NA. More specifically, the data driver 120 includes a plurality of data pads DP arranged in the non-display area NA, a plurality of data link wirings (DLL) connected to the plurality of data pads DP, and a plurality of data link wirings The data voltage can be supplied to the plurality of pixels through a plurality of data lines DL connected to the data lines DL. In FIG. 1, a plurality of data drivers 120 are shown. However, the present invention is not limited thereto. One data driver 120 may be disposed on the substrate 110.

Referring to FIG. 1, the data driver 120 may include a base film 121 and a driving IC 122. The base film 121 is a film that supports the data driver 120. The base film 121 may be made of an insulating material, for example, an insulating material having flexibility. The driving IC 122 is configured to process a data voltage for displaying an image and a driving signal for processing the data voltage. The driving IC 122 may be disposed in a manner such as a chip on glass (COG), a chip on film (COF), a tape carrier package (TCP), or the like according to a method of being mounted on the substrate 110 of the display device 100 have. 1, the data driver 120 is a COF type mounted on the base film 121 for convenience of explanation, but the present invention is not limited thereto.

The gate driver 130 outputs a gate signal under the control of the timing controller and can select the pixel to which the data voltage is to be charged through the plurality of gate link lines GLL and the plurality of gate lines GL. The gate driver 130 may sequentially supply the gate signal to the gate line GL using a shift register. In FIG. 1, the gate driving unit 130 is a COF type mounted on the base film 131 for convenience of description, but the present invention is not limited thereto. In addition, although a plurality of gate drivers 130 are shown, the present invention is not limited thereto, and one gate driver 130 may be disposed on the substrate 110.

Hereinafter, the plurality of link lines GLL and DLL in the non-display area NA of the substrate 110 will be described in more detail with reference to FIG.

2 is an enlarged view of the X region in Fig. 2, a plurality of data lines DL, a plurality of data link wirings (DLL), a plurality of data pads DP, a first capacitance compensation pattern CP1, a second capacitance compensation pattern CP2 And a plurality of power supply pads VDDP are shown.

The plurality of link lines DLL and GLL are wirings for connecting a plurality of signal lines arranged in the display area AA and a pad part PA arranged in the non-display area NA. Specifically, the plurality of link wirings (DLL, GLL) include a plurality of gate link wirings (GLL) and a plurality of data link wirings (DLL). Here, the plurality of signal wirings may include a gate wiring GL and a data wiring DL. Although a plurality of data link wirings (DLLs) are described below, the same configuration as that of a plurality of data link wirings (DLLs) may be applied to a plurality of gate link wirings (GLL).

The pad portion PA is a region where a plurality of pads are formed in the non-display area NA. The plurality of pads includes a plurality of data pads (DP) and a plurality of power supply pads (VDDP).

The plurality of data pads DP are pads for receiving data voltages from the data driver 120 and transmitting the data voltages to the data lines DL. The plurality of data pads DP are disposed at the ends of the plurality of data link wirings (DLLs) and connected to a plurality of data link wirings (DLLs).

The plurality of power supply pads VDDP are pads for receiving a common voltage from the data driver 120 and transmitting the same through the first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2. The plurality of power supply pads VDDP are disposed at the ends of the first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2 and connected to the first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2 do.

The pad portion PA is an area where a plurality of pads and an external module, for example, COF, are bonded. As shown in FIG. 2, there are a plurality of pad portions PA, and a data driver 120 may be disposed in each of the pad portions PA.

Referring to FIG. 2, a plurality of data link wirings (DLLs) are wirings that connect the data driver 120 and a plurality of data wirings DL of the display area AA through a plurality of data pads DP.

The plurality of data link wirings (DLLs) include a first data link wiring (DLL1) and a second data link wiring (DLL2). At this time, the first data link wiring DLL1 and the second data link wiring DLL2 are alternately arranged on the same layer.

Referring to FIG. 2, a plurality of first data link lines DLL1 are arranged on the same layer as a plurality of second data link lines DLL2, and are arranged at the same distance between the plurality of second data link lines DLL2 And can be disposed in a spaced apart position. Accordingly, the plurality of first data link lines DLL1 and the plurality of second data link lines DLL2 may be arranged at regular intervals.

The plurality of first data link lines DLL1 and the plurality of second data link lines DLL2 may be formed of the same material as the source electrode and the drain electrode of the thin film transistor arranged in the display area AA. Generally, since the data line DL is formed on the same layer as the source electrode and the drain electrode of the thin film transistor, as shown in FIG. 2, a plurality of first data link lines DLL1 and a plurality of 2 data link wiring DLL2 can be integrally formed without a separate connection structure from the data wiring DL. The plurality of first data link interconnections DLL1 and the plurality of second data link interconnections DLL2 may be formed on the same layer with the same material as the various conductive interconnectors used in the display device 100. However, .

Referring to Fig. 2, a plurality of data link wirings (DLLs) include a first portion S1 and a second portion S2. The first portion S1 of the plurality of data link wirings DLL is connected to the plurality of data pads DP and means a portion of the wirings extending from the plurality of data pads DP in the first direction D1 . The second part S2 of the plurality of data link wirings DLL is connected to the data line DL of the display area AA and is connected to the data line DL in the second direction D2 and the third direction D2, D3, < / RTI > Here, the second direction D2 is a direction in which the second portion S2 of the data link wiring DLL located on the left side among the plurality of data link wiring lines DLL shown in Fig. 2 extends, and the third direction D3 Is a direction in which a second portion S2 of a plurality of data link wirings (DLLs) positioned on the right side among the plurality of data link wirings (DLLs) shown in Fig. 2 extends. That is, the second direction D2 is the left oblique direction with reference to FIG. 2, and the third direction D3 is the right oblique direction with reference to FIG.

Accordingly, the plurality of data link wirings (DLLs) display data voltages from the data driver 120 through the data lines DL of the display area AA through the first part S1 and the second part S2 To the pixels of the area AA.

At least a part of the plurality of data link wirings (DLLs) includes a resistance compensation pattern (RP). In order to solve the problem that the RC delay value generated due to the difference in length between the data link wiring (DLL) arranged at the center portion and the data link wiring (DLL) arranged at the edge portion increases, And is included in at least a part of the link wiring (DLL). One end of the resistance compensation pattern RP is connected to the first portion S1 and the other end is connected to the second portion S2. The plurality of data link wirings (DLLs) including the resistance compensation pattern RP are connected to the data lines DL via the first portion S1, the resistance compensation pattern RP and the second portion S2. . However, since the length of the data link wiring line (DLL) disposed at the outermost portion of the edge portion of the plurality of data link wiring lines (DLL) is the longest, the resistance compensation pattern (RP) Or may include the resistance compensation pattern RP having the shortest length. In addition, since the length of the plurality of data link wirings (DLLs) arranged at the center of the plurality of data link wirings (DLLs) is the shortest, in the case of a plurality of data link wirings (DLLs) And may include a pattern RP.

The resistance compensation pattern RP may be various shapes that can increase the length of the plurality of data link wirings (DLLs). That is, the resistance compensation pattern RP is not a pattern connecting the first portion S1 and the second portion S2 of the data link wiring DLL at the shortest distance. Thus, the resistance compensation pattern RP may have at least one of a zigzag shape, a sine wave shape, and a pulsed wave shape. However, since the longest shape among the various shapes is the shape of a pulse wave, the resistance compensation pattern RP has a shape of a pulse wave in FIG.

Referring to FIG. 2, the length of the resistance compensation pattern RP may increase toward the center of the pad portion PA. Since the resistance compensation pattern RP is a pattern for improving the problem that the RC delay value generated due to the difference in length between the data link wiring (DLL) disposed at the center portion and the data link wiring (DLL) disposed at the edge portion increases, The length of the resistance compensation pattern RP included in the data link wiring line (DLL) disposed at the center portion may be longer than the length of the data link wiring line (DLL) disposed at the edge portion. Accordingly, the resistance compensation patterns RP of the plurality of first data link interconnections DLL1 and the plurality of second data link interconnections DLL2 can assume a triangular shape. That is, the resistance compensation patterns RP of the plurality of first data link wiring DLL1 and the plurality of second data link wiring DLL2 can be arranged in the triangular area.

The display device 100 may be driven in a column data feeding manner. That is, a data voltage of the same polarity may be applied to the data line DL of the display device 100 in units of columns. Therefore, during one frame period, a positive data voltage is applied to some of the data link wirings (DLL) of the plurality of data link wirings (DLL), while a positive (+) data voltage is applied to the other data link wirings May be applied. Hereinafter, it will be assumed that a data voltage having a polarity opposite to that of the plurality of second data link lines DLL2 is transferred to a plurality of first data link lines DLL1 among the plurality of data link interconnections DLLs.

Accordingly, during one frame period, a positive data voltage may be applied to the first data link line DLL1 and a negative data voltage may be applied to the second data link line DLL2, Conversely, a negative (-) data voltage may be applied to the first data link wiring DLL1 and a positive (+) data voltage may be applied to the second data wiring wiring DLL2.

2, a first capacitance compensation pattern CP1 and a second capacitance compensation pattern CP2 are arranged in a region overlapping the resistance compensation pattern RP among a plurality of data link wirings (DLLs) in a non-display area . The first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2 are formed in such a manner that the resistance variation caused by the length difference between the data link wiring DLL arranged at the center portion and the data link wiring DLL arranged at the edge portion Is a conductive pattern for minimizing an increase in the RC delay difference between the data link wiring (DLL) arranged at the center by the wiring pattern (DL) and the data link wiring (DLL) arranged at the edge.

2, a first capacitance compensation pattern CP1 overlaps with a plurality of first data link lines DLL1, a second capacitance compensation pattern CP2 overlaps with a plurality of second data link lines DLL2, do.

Referring to FIG. 2, the first capacitance compensation pattern CP1 includes a plurality of branch patterns SP1 extending from the base pattern BP1 and the base pattern BP1 and overlapping each of the plurality of first data link lines DLL1, . Thus, the first capacitance compensation pattern CP1 may be formed in a fork shape. Here, the base pattern BP1 of the first capacitance compensation pattern CP1 is arranged on the first portion S1 of the first data link wiring DLL1 and the second data link wiring DLL2, and the first capacitance compensation The branch pattern SP1 of the pattern CP1 is arranged so as to overlap with the resistance compensation pattern RP among the plurality of first data link wirings DLL1.

The second capacitance compensation pattern CP2 includes a plurality of branch patterns SP2 extending from the base pattern BP2 and the base pattern BP2 and overlapping each of the plurality of second data link wirings DLL2. Thus, the second capacitance compensation pattern CP2 may be formed in a fork shape. Here, the base pattern BP2 of the second capacitance compensation pattern CP2 is disposed on the second portion S2 of the first data link wiring DLL1 and the second data link wiring DLL2, and the second capacitance compensation The branch pattern SP2 of the pattern CP2 is arranged so as to overlap with the resistance compensation pattern RP among the plurality of second data link wirings DLL2.

The first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2 may be made of the same material as the pixel electrode or the common electrode. Accordingly, the first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2 may be made of a transparent conductive material such as indium tin oxide (ITO). The first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2 may be formed on the first conductive layer 5 and the second conductive layer 5 on the other conductive material ≪ / RTI >

The first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2 may be connected to the power supply pad VDDP to apply the same voltage as the common voltage applied to the common electrode. Specifically, the power supply pad VDDP may receive a common voltage from the data driver 120 and may transmit the first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2. Here, it may be an intermediate voltage between a positive (+) data voltage and a negative (-) data voltage.

In FIG. 2, the first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2 are respectively connected to the two power supply pads VDDP, but the present invention is not limited thereto.

2, a plurality of first capacitance compensation patterns CP1 and a plurality of second capacitance compensation patterns CP2 are formed so as to correspond to the pad portions PA when a plurality of pad portions PA are provided, Can be arranged. At this time, the plurality of first capacitance compensation patterns CP1 and the plurality of second capacitance compensation patterns CP2 may all receive a common voltage through the power supply pad VDDP. Alternatively, only a part of the plurality of first capacitance compensation patterns CP1 may be supplied with a common voltage through the power supply pad VDDP and the other may be supplied through the first capacitor compensation pattern CP1 connected to the power supply pad VDDP A common voltage may be applied. Likewise, only a part of the plurality of second capacitance compensation patterns CP2 is supplied with a common voltage through the power supply pad VDDP and the other part is supplied through the second capacitor compensation pattern CP2 connected to the power supply pad VDDP A common voltage may be applied.

Referring to FIG. 2, a plurality of branch patterns SP1 of the first capacitance compensation pattern CP1 and a plurality of branch patterns SP2 of the second capacitance compensation pattern CP2 may be alternately arranged. 2, the branch pattern SP1 of the first capacitance compensation pattern CP1 and the branch pattern SP2 of the second capacitance compensation pattern CP2 are overlapped with the resistance compensation pattern RP of the plurality of data link wirings DLL The branch pattern SP1 of the first capacitance compensation pattern CP1 and the branch pattern SP2 of the second capacitance compensation pattern CP2 may be implemented in various shapes. For example, the branch pattern SP1 of the first capacitance compensation pattern CP1 and the branch pattern SP2 of the second capacitance compensation pattern CP2 are connected to the resistance compensation pattern RP of the plurality of data link wirings DLL The branch pattern SP2 of the branch pattern SP1 and the second capacitance compensation pattern CP2 of the first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2 is maximized so that the capacitance of the plurality of data link wirings And may have a shape corresponding to the resistance compensation pattern RP.

2, the branch pattern SP1 of the first capacitance compensation pattern CP1 and the branch pattern SP2 of the second capacitance compensation pattern CP2 are arranged such that the branch pattern SP2 of the first capacitance compensation pattern CP1 and the branch pattern SP2 of the second capacitance compensation pattern CP2 are disposed closer to the center of the pad portion PA, . The first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2 are disposed at the center portion because the length of the data link wiring DLL arranged at the edge portion is longer than that of the data link wiring DLL arranged at the central portion A resistance variation occurs between the data link wiring (DLL) and the data link wiring (DLL) disposed at the edge portion, and this is a pattern for solving the problem that the RC delay deviation is generated due to such resistance variation. Therefore, since the data link wiring (DLL) having a relatively short length is disposed at the center portion and the data link wiring (DLL) having a relatively long length is disposed at the edge portion, the branch of the first capacitance compensation pattern CP1 The branch pattern SP1 of the first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2 of the pattern SP1 and the branch pattern SP2 of the second capacitance compensation pattern CP2 are arranged at the edge portion, The branch pattern SP2 of FIG.

Referring to FIG. 2, the base pattern BP1 of the first capacitance compensation pattern CP1 and the base pattern BP2 of the second capacitance compensation pattern CP2 may be opposed to each other. That is, the base pattern BP1 of the first capacitance compensation pattern CP1 and the base pattern BP2 of the second capacitance compensation pattern CP2 may be disposed opposite to each other.

In addition, since the branch pattern SP2 of the second capacitance compensation pattern CP2 is formed in a triangular shape, the base pattern BP1 connected to the end of the branch pattern SP1 of the first capacitance compensation pattern CP1, The base pattern BP2 connected to the end of the branch pattern SP2 of the two-capacitance-compensation pattern CP2 may also have a triangular shape.

In a typical display device, in order to reduce the size of the non-display area, the data link wiring includes a portion extending in a diagonal direction rather than a linear direction. Accordingly, the length of the data link wiring can be made different from each other depending on the position of the data link wiring or the like. For example, among the plurality of data link wirings receiving signals from the same data driver, the data link wirings disposed at the center portion are relatively short in length, while the data link wirings disposed at the edge portion are relatively long. Therefore, there is a problem that the wiring resistance of the link wiring disposed at the edge portion is larger than the wiring resistance of the link wiring disposed at the center, and the RC delay value is increased in the data link wiring of the edge portion as compared with the data link wiring at the center portion.

Accordingly, in the display device 100 according to an embodiment of the present invention, each of the plurality of data link wirings (DLLs) includes a resistance compensation pattern RP. That is, in a method of increasing the length of the data link wiring (DLL) located at the center, in the display device 100 according to an embodiment of the present invention, the RC delay value of the data link wiring (DLL) The resistance variation between the link wirings (DLLs) can be reduced, and the variation of the RC delay value can also be reduced.

However, even if the resistance compensation pattern RP is used, since the length of the second portion S2 of the data link wiring DLL is longer than the length of the resistance compensation pattern RP, There may be a resistance variation between the RC delay value of the edge portion and the data link wiring (DLL) of the edge portion.

Thus, in the display device 100 according to an embodiment of the present invention, a plurality of first data link lines DLL1 and a plurality of first data link lines DL1 are overlapped with a resistance compensation pattern RP of a plurality of data link lines The first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2 are disposed on the second data link wiring DLL2. Therefore, the data link wiring (DLL) in which the data link wiring (DLL) disposed at the center portion overlaps with the first capacitance compensation pattern (CP1) and the second capacitance compensation pattern (CP2) Is larger than the area overlapping the compensation pattern CP1 and the second capacitance compensation pattern CP2. Thus, the amount of increase in the capacitance of the data link wiring (DLL) disposed at the center portion may be greater than the amount of capacitance of the data link wiring (DLL) disposed at the edge portion, and the variation in the RC delay value between the data link wiring Can be reduced.

On the other hand, in a display device, a column data feeding method in which a positive (+) data voltage or a negative (-) data voltage is supplied on a column by column basis on a common voltage is used for a plurality of data wirings. In the case where the column data feeding scheme is used as described above, a positive (+) data voltage is applied to some of the data link wirings and a negative (-) data voltage is applied to some of the other data link wirings . However, in the case of using one capacitance compensation pattern overlapping all the data link wirings in spite of the fact that data voltages of different polarities are applied to each of the plurality of data link wirings, the capacitance variation width in the capacitance compensation pattern becomes positive The capacitance variation width can be excessively increased corresponding to the difference between the positive (+) data voltage and the negative (-) data voltage. That is, a data voltage of positive polarity is applied to one data link wiring that can form one capacitance compensation pattern and a capacitor, and a negative data voltage is applied to another data link wiring , And in the capacitance compensation pattern, the capacitance may excessively fluctuate so as to correspond to the difference between the positive (+) data voltage and the negative (-) data voltage

Accordingly, in the display device 100 according to an embodiment of the present invention, the first capacitance compensation pattern CP1 is arranged to overlap the plurality of first data link lines DLL1 that carry data voltages of the same polarity, The first capacitance compensation pattern CP2 is arranged so as to overlap the plurality of second data link wirings DLL2 which are different from the first data link wiring DLL1 but carry data voltages of the same polarity, CP1 and the second capacitance compensation pattern CP2 can be prevented from increasing excessively. For example, when a plurality of first data link lines DLL1 carry positive data voltages and a plurality of second data link lines DLL2 carry negative data voltages, In the first capacitance compensation pattern CP1, the capacitance changes so as to correspond to the difference between the data voltage of the positive polarity and the common voltage. In the second capacitance compensation pattern CP2, the data voltage of negative polarity and the common voltage The capacitance can be changed to correspond to the difference of the capacitance. Therefore, in the display device 100 according to an exemplary embodiment of the present invention, as described above, the capacitance through the first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2, The display quality of the display device 100 can be more advantageous because the degree of change is small.

3 is a graph for explaining the effect of the display device 100 according to an embodiment of the present invention. 3 is a graph showing the amount of change in RC load according to the position of the data link wiring (DLL) in Comparative Example 1, Comparative Example 2, and Example 1. The X-axis shows the data link wiring (DLL), and the Y axis represents the RC load.

The first embodiment is different from the display device 100 according to the first embodiment of the present invention described above with reference to FIGS. 1 and 2, in which a first capacitance compensation is performed in a data link wiring (DLL) The pattern CP1 and the second capacitance compensation pattern CP2 are applied. Comparative Example 1 is a case where the resistance compensation pattern RP, the first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2 are omitted in the display device 100 according to an embodiment of the present invention. The second comparative example is a case where the first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2 are omitted in the display device 100 according to an embodiment of the present invention. That is, in the comparative example 1, the data link wiring (DLL) is composed of only the first part S1 and the second part S2.

In the case of the comparative example 1, since the resistance compensation pattern RP, the first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2 are not included, the length of the data link wiring line DLL And the length of the data link wiring (DLL) located at the edge portion is relatively long. That is, the length of the data link wiring (DLL) decreases from the edge portion to the central portion, and accordingly, the resistance of the data link wiring (DLL) can also be reduced. Therefore, the RC delay value in the data link wiring (DLL) may decrease as it goes from the edge portion to the center portion. For example, as shown in Fig. 3, the deviation of the RC delay value of the data link wiring (DLL) at the edge portion and the central portion in Comparative Example 1 may be?.

In the case of the comparative example 2, since the resistance compensation pattern RP is further added as compared with the comparative example 1, the resistance of the data link wiring (DLL) disposed at the center of the pad part PA is increased as compared with the comparative example 1, The resistance of the data link wiring (DLL) disposed at the edge portion of the portion PA does not change. Thus, as compared with Comparative Example 1, the resistance of the data link wiring (DLL) disposed at the center can be increased. Therefore, as shown in FIG. 3, the RC delay value increases the most in the data link wiring (DLL) disposed at the center, and the RC delay value increases the smaller the distance to the edge portion as compared with the comparative example 1 . Since the length of the first portion S1 of the data link wiring DLL is shorter than that of the second portion S2, even if the resistance compensation pattern RP is added, the data link wiring DLL ) Is larger than the resistance of the data link wiring (DLL) disposed in the central portion. Assuming that the increment of the RC delay value of the data link wiring (DLL) located at the central portion as compared with the case of Comparative Example 1 is A, the RC delay of the data link wiring (DLL) at the edge portion and the central portion in Comparative Example 2 The deviation of the value may be ② smaller than ①. Thus, in the case of Comparative Example 2, the deviation of the RC delay value at the center portion and the edge portion can be reduced by A as compared with Comparative Example 1.

In the case of the first embodiment, since the first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2 are added as compared with the second comparative example, the capacitance of the data link wiring DLL in the central portion can be increased. At this time, since the lengths of the first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2 increase from the edge portion toward the center portion, the capacitance of the data link wiring DLL disposed at the center portion becomes larger than the capacitance Which is larger than the capacitance of the link wiring (DLL). Therefore, as shown in FIG. 3, the RC delay value for the data link wiring (DLL) disposed at the center can be increased by B. Therefore, in comparison with the case of the comparative example 2, the deviation of the RC delay value of the data link wiring (DLL) at the edge part and the central part in the embodiment 1 can be ③ smaller than ②. Thus, in the case of Embodiment 1, the deviation of the RC delay values in the plurality of data link wiring (DLL) arranged at the center and the plurality of data link wiring (DLL) arranged at the edge portion is B And the deviation of the RC delay value at the center portion and the edge portion can be reduced by A + B as compared with Comparative Example 1. [ Therefore, compared with the case where the first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2 are not included in the first embodiment, the RC delay deviation between the center portion and the edge portion can be reduced, There is an effect that the deterioration in image quality that may occur as the RC delay deviation occurs in the region 100 is improved.

4 is an enlarged view of a non-display area NA of a display device according to another embodiment of the present invention. The display device 200 shown in Fig. 4 is different from the display device 100 shown in Figs. 1 to 3 only in the arrangement relationship of the first data link wiring DLL1 and the second data link wiring DLL2 But the other configurations are substantially the same, so redundant explanations are omitted.

Referring to FIG. 4, a plurality of data link wirings (DLLs) include a plurality of first data link wirings (DLL1) and a plurality of second data link wirings (DLL2) arranged alternately in different layers.

The plurality of first data link lines DLL1 and the plurality of second data link lines DLL2 may be formed of the same material as the various electrodes and / or wires used in the display device 200. [ For example, the plurality of first data link lines DLL1 may be made of the same material as the gate electrodes of the thin film transistors arranged in the display area AA, and the plurality of second data link lines DLL2 may be formed in the display area AA may be made of the same material as the source electrode and the drain electrode of the thin film transistor. The plurality of first data link lines DLL1 and the plurality of second data link lines DLL2 are formed on the same layer with the same materials as the various conductive elements used in the display device 200. However, .

Since the data line DL is formed on the same layer as the source electrode and the drain electrode of the thin film transistor, the plurality of second data link lines DLL2 can be formed without a separate connection structure from the data line DL Or may be integrally formed. However, since the plurality of first data link lines DLL1 are formed on the same layer as the gate electrodes of the thin film transistors, they can be connected to the data lines DL through the contact holes as shown in FIG.

In the display device 200 according to another embodiment of the present invention, a plurality of data link wirings (DLLs) are alternately arranged in different layers, and a plurality of first data link wirings (DLL1) and a plurality of second data link wirings DLL2). Therefore, since the process margin can be secured more than when a plurality of data link wirings (DLLs) are arranged in a single layer, the size of the non-display area NA where a plurality of data link wirings (DLL) , So that the size of the bezel can also be reduced.

5 is an enlarged view of a non-display area of a display device according to another embodiment of the present invention. The display device 300 shown in Fig. 5 has a reduced width W of the non-display area NA where a plurality of data link wirings (DLLs) are arranged, as compared with the display device 200 shown in Fig. 4 And the other configurations are substantially the same, so redundant explanations are omitted.

The width W of the non-display area NA may gradually decrease as the non-display area NA is reduced as the non-display area NA is reduced in terms of design and space utilization. Accordingly, if the width W of the non-display area NA is reduced, the spacings L1 and L2 between the plurality of data link wirings (DLLs) are greatly reduced, and the capacitance of the entire plurality of data link wirings (DLLs) increases. In this case, since the lengths of the plurality of data link wirings (DLLs) arranged at the edge portion are relatively longer than the lengths of the plurality of data link wirings (DLLs) arranged at the central portion, The sizes of the capacitances that increase as the lengths L1 and L2 decrease are the smallest among the plurality of data link wirings (DLLs) arranged at the edge portion and the plurality of data link wirings (DLLs) arranged at the central portion. Thus, the problem that the RC delay value due to the data link wiring (DLL) is increased at the edge portion of the display device as the display device implementing the narrow bezel by reducing the non-display area NA may be more serious.

Accordingly, in the display device 300 according to another embodiment of the present invention, a plurality of first data link lines DLL1 and a plurality of second data link lines DL2 are provided in a region overlapping the resistance compensation pattern RP of a plurality of data link lines (DLLs) A first capacitance compensation pattern CP1 and a second capacitance compensation pattern CP2 are disposed on the second data link wiring DLL2. Therefore, the data link wiring (DLL) in which the data link wiring (DLL) disposed at the center portion overlaps with the first capacitance compensation pattern (CP1) and the second capacitance compensation pattern (CP2) Is larger than the area overlapping the compensation pattern CP1 and the second capacitance compensation pattern CP2. Thus, the amount of increase in the capacitance of the data link wiring (DLL) disposed at the center portion may be greater than the amount of capacitance of the data link wiring (DLL) disposed at the edge portion, and the variation in the RC delay value between the data link wiring Can be reduced. Accordingly, in the display device 300 according to another embodiment of the present invention, even when the narrow bezel is implemented, the RC delay value between the data link wiring (DLL) disposed at the center and the data link wiring Can be reduced. A more detailed description will be made with reference to FIG.

6 is a graph for explaining the effect of the display device according to another embodiment of the present invention. Specifically, FIG. 6 is a graph showing an amount of change in RC load according to the position of a data link wiring (DLL) in Comparative Example 1, Comparative Example 2, Comparative Example 3, and Example 1. The X axis is connected to the same data driver 120 Indicates the position of the data link wiring (DLL), and the Y axis indicates the RC load.

In Comparative Example 3, the width W of the non-display area NA where a plurality of data link wirings (DLLs) are arranged is reduced in Comparative Example 2 described above with reference to Fig. Embodiment 2 is a structure in which a plurality of data link wirings (DLL) having reduced width W of the non-display area NA in the display device 300 according to yet another embodiment of the present invention described above with reference to Fig. 5 The first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2 are further arranged.

Comparative Example 1 and Comparative Example 2 shown in Fig. 6 are the same as Comparative Example 1 and Comparative Example 2 described with reference to Figs. 1 to 3 above.

In the case of Comparative Example 3, since the distance between the plurality of data link wirings (DLLs) is reduced as the width W of the non-display area NA where the plurality of data link wirings (DLLs) are arranged decreases, The capacitance of the data link wiring (DLL) and the plurality of data wiring wiring (DLL) arranged at the edge portion are increased. Compared with the comparative example 2, the RC delay value of the data link wiring (DLL) located at the center can be increased by D in comparison example 3. However, since the data link wiring line (DLL) located at the edge portion is longer than the plurality of data link wiring lines (DLL) arranged at the central portion, the spacing between the plurality of data link wiring lines (DLL) The capacitance of the wiring (DLL) increases relatively much, and the RC delay value of the edge portion is increased by E larger than D. Therefore, as compared with the case of the comparative example 2, the deviation of the RC delay value of the data link wiring (DLL) located at the center and the RC delay value of the data link wiring (DLL) located at the edge part is 4, ②).

In the case of Embodiment 2, since the first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2 are added as compared with Comparative Example 3, the capacitance of a plurality of data link wirings (DLLs) in the central portion can be increased have. At this time, since the lengths of the first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2 increase from the edge portion toward the center portion, the capacitance of the data link wiring DLL disposed at the center portion becomes larger than the capacitance Which is larger than the capacitance of the link wiring (DLL). Therefore, as shown in FIG. 6, the RC delay value for a plurality of data link wirings (DLLs) arranged at the central portion can be increased by C. Therefore, as compared with the case of the comparative example 3, the deviation of the RC delay value of the data link wiring (DLL) at the edge part and the central part in the embodiment 2 can be ⑤ smaller than ④ by C. Thus, in the case of the second embodiment, the deviation of the RC delay values in the plurality of data link wirings (DLLs) arranged at the center and the plurality of data link wirings (DLLs) arranged at the edge portion is C . Therefore, in the second embodiment, the RC delay deviation between the center portion and the edge portion can be reduced as compared with the case where the first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2 are not included, There is an effect that the image quality deterioration that may occur as the RC delay deviation occurs in the region 300 can be improved.

7 is an enlarged view of a non-display area of a display device according to another embodiment of the present invention. The display device 400 shown in Fig. 7 is different from the display device 300 shown in Fig. 5 in that the branch pattern SP1 of the first capacitance compensation pattern CP1 and the branches of the second capacitance compensation pattern CP2 Only the patterns SP2 are alternately arranged in units of groups, and the other structures are substantially the same, and redundant explanations are omitted.

The display device 400 according to another embodiment of the present invention may be driven by a column data feeding method. In this case, during one frame period, the data lines DL to which data voltages of the same polarity are applied may be alternately arranged in a plurality of units. For example, as shown in FIG. 7, a positive (+) or negative (-) data voltage is applied to the two first data link lines DLL1 and two second data link lines DLL2 (-) or positive (+) data voltage is applied to the first data link line DL1 and the second data link line DL2.

The branch pattern SP1 of the first capacitance compensation pattern CP1 and the branch pattern SP2 of the second capacitance compensation pattern CP2 may be alternately arranged in a plurality of units. For example, as shown in Fig. 7, the branch pattern SP1 of the first capacitance compensation pattern CP1 is arranged so as to overlap the two first data link interconnections DLL1, The branch pattern SP2 of the second capacitance compensation pattern CP2 may be arranged so as to overlap the DLL2. In addition, arrangement of branch patterns SP2 of the first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2 can be repeated.

In the display device 400 according to another embodiment of the present invention, a first capacitance compensation pattern CP1 is arranged to overlap with a plurality of first data link lines DLL1 that carry data voltages of the same polarity, The second capacitance compensation pattern CP2 is arranged so as to overlap the plurality of second data link lines DLL2 which are different from the data link wiring DLL1 but carry the data voltage of the same polarity, And the capacitance variation width in the second capacitance compensation pattern CP2 can be prevented from increasing excessively. In particular, when the data lines DL to which the data voltages of the same polarity are applied are alternately arranged in a plurality of units, the branch patterns SP1 and the second capacitance compensation patterns CP2 of the first capacitance compensation pattern CP1, (SP2) can also be alternately arranged in a plurality of units and can be overlapped with the data link wiring (DLL). In the display device 400 according to another embodiment of the present invention, the first capacitance compensation pattern CP1 and the second capacitance compensation pattern CP2 are arranged to correspond to various column data feeding schemes, It is possible to improve the deviation of the RC delay value and to improve the display quality.

In FIG. 7, the data lines DL to which the data voltages of the same polarity are applied are alternately arranged in units of two, but the present invention is not limited to this. The alternating arrangement of the data lines DL to which the data voltages of the same polarity are applied The number of units can be set variously. In FIG. 7, the number of data lines DL to which a positive data voltage is applied is equal to the number of data lines DL to which a negative data voltage is applied. However, And the number of data lines DL to which the data voltage DL having the negative polarity (-) is applied may be different from each other, and the number of data lines DL to which the positive polarity (+ The number may also be set to vary.

An exemplary embodiment of the present invention can be described as follows.

A display device according to an embodiment of the present invention includes a substrate including a display region in which a plurality of pixels are defined and a non-display region surrounding the display region, a plurality of signal lines arranged in the display region, A plurality of signal lines, a plurality of first data link lines and a plurality of second data link lines connecting the plurality of signal lines and a plurality of pads, a first capacitance overlapping the plurality of first data link lines, A compensation pattern, and a second capacitance compensation pattern overlapping the plurality of second data link wirings and spaced apart from the first capacitance compensation pattern.

According to another aspect of the present invention, at least a portion of the plurality of first data link wiring and the plurality of second data link wiring includes a first portion extending in a first direction, a resistance compensation pattern extending from the first portion, And a second portion extending in a second direction or a third direction that is different from the first direction.

According to another aspect of the present invention, the first capacitance compensation pattern includes a base pattern and a plurality of branch patterns extending from the base pattern and overlapping each of the plurality of first data link wirings, and the second capacitance compensation pattern includes a base pattern And a plurality of branch patterns extending from the base pattern and overlapping each of the plurality of second data link wirings.

According to another aspect of the present invention, a plurality of branch patterns of the first capacitance compensation pattern overlap with a resistance compensation pattern of the plurality of first data link wirings, and a plurality of branch patterns of the second capacitance compensation pattern overlap the plurality of second It can be overlapped with the resistance compensation pattern of the data link wiring.

According to another aspect of the present invention, the base pattern of the first capacitance compensation pattern may be opposed to the base pattern of the second capacitance compensation pattern.

According to another aspect of the present invention, the base pattern of the first capacitance compensation pattern and the base pattern of the second capacitance compensation pattern may have a triangular shape.

According to still another aspect of the present invention, a plurality of branch patterns of the first capacitance compensation pattern and a plurality of branch patterns of the second capacitance compensation pattern may be alternately arranged.

According to still another aspect of the present invention, the branch patterns of the first capacitance compensation pattern and the branch pattern of the second capacitance compensation pattern may be longer as they are disposed closer to the center of the pad portion.

According to still another aspect of the present invention, during one frame period, a plurality of first data link wirings can transmit a signal of a polarity different from that of the plurality of second data link wirings to a plurality of signal wirings.

According to still another aspect of the present invention, there is provided a liquid crystal display device including a pixel electrode and a common electrode disposed in a plurality of pixels, wherein the first capacitance compensation pattern and the second capacitance compensation pattern may be made of the same material as the pixel electrode or the common electrode.

According to another aspect of the present invention, a voltage equal to a common voltage applied to the common electrode may be applied to the first capacitance compensation pattern and the second capacitance compensation pattern.

According to still another aspect of the present invention, the plurality of first data link wirings and the plurality of second data link wirings may be disposed on the same layer.

According to another aspect of the present invention, the plurality of first data link wirings and the plurality of second data link wirings may be disposed in different layers.

A display device according to another embodiment of the present invention includes a substrate including a display region in which a plurality of pixels are arranged and a non-display region including a pad portion composed of a plurality of pads, a plurality of signal lines in the display region and a plurality of non- A first capacitance compensation pattern and a second capacitance compensation pattern which are alternately arranged in different layers so as to overlap the first data link wiring and the second data link wiring connecting the pads of the first data link wiring and the second data link wiring, . ≪ / RTI >

According to another aspect of the present invention, a first capacitance compensation pattern includes a branch pattern extending from a base pattern and a base pattern and including a plurality of branch patterns overlapping each of the plurality of first link wirings, The compensation pattern may include a base pattern and a plurality of branch patterns extending from the base pattern and overlapping each of the plurality of second link wirings.

According to another aspect of the present invention, the branch pattern of the first capacitance compensation pattern and the branch pattern of the second capacitance compensation pattern increase in length from the edge portion to the central portion of the pad portion, And the second capacitance compensation pattern connected to the end of the branch pattern of the second capacitance compensation pattern may have a triangular shape.

According to still another aspect of the present invention, a plurality of first data link interconnections may be configured to transfer a data voltage having an opposite polarity to the plurality of second data link interconnections.

According to another aspect of the present invention, the display device may be a liquid crystal display device driven by a column data feeding method.

According to another aspect of the present invention, the plurality of second data link interconnections are disposed in different layers from the plurality of first data link interconnections, and may be disposed in a space between adjacent first plurality of data link interconnections.

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those embodiments and various changes and modifications may be made without departing from the scope of the present invention. . Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100, 200, 300, 400: display device
110: substrate
120: Data driver
121: base film
122: driving IC
130: Gate driver
131: base film
132: driving IC
AA: display area
NA: non-display area
DLL: Multiple data link wiring
DLL1: first data link wiring
DLL2: second data link wiring
GLL: Multiple gate link wiring
DL: Data wiring
GL: gate wiring
D1: the first direction
D2: the second direction
D3: Third direction
PA: pad portion
P: Pad
VDDP: Power supply pad
RP: Resistance compensation pattern
CP1: first capacitance compensation pattern
BP1: Base pattern
SP1: Branch Patterns
CP2: Second Capacitance Compensation Pattern
BP2: Base pattern
SP2: Branch Patterns
S1: First part
S2: second part

Claims (18)

A substrate including a display region in which a plurality of pixels are defined and a non-display region surrounding the display region;
A plurality of signal lines arranged in the display area;
A pad portion arranged in the non-display region and made of a plurality of pads;
A plurality of first link wirings and a plurality of second link wirings connecting each of the plurality of signal wirings and each of the plurality of pads;
A first capacitance compensation pattern overlapping the plurality of first link wirings; And
And a second capacitance compensation pattern overlapping the plurality of second link wirings and spaced apart from the first capacitance compensation pattern. The method according to claim 1,
At least a part of the plurality of first link wirings and the plurality of second link wirings includes a first portion extending in a first direction, a resistance compensation pattern extending from the first portion, And a second portion extending in a second different direction or a third direction. 3. The method of claim 2,
Wherein the first capacitance compensation pattern includes a base pattern and a plurality of branch patterns extending from the base pattern and overlapping each of the plurality of first link wirings,
Wherein the second capacitance compensation pattern includes a base pattern and a plurality of branch patterns extending from the base pattern and overlapping each of the plurality of second link wirings. The method of claim 3,
The plurality of branch patterns of the first capacitance compensation pattern overlap the resistance compensation pattern of the plurality of first link wirings,
And the plurality of branch patterns of the second capacitance compensation pattern overlap with the resistance compensation pattern of the plurality of second link wirings. The method of claim 3,
And the base pattern of the first capacitance compensation pattern faces the base pattern of the second capacitance compensation pattern. The method of claim 3,
Wherein the base pattern of the first capacitance compensation pattern and the base pattern of the second capacitance compensation pattern form a triangular shape. The method of claim 3,
Wherein a plurality of branch patterns of the first capacitance compensation pattern and a plurality of branch patterns of the second capacitance compensation pattern are alternately arranged. The method of claim 3,
Wherein a plurality of branch patterns of the first capacitance compensation pattern and branch patterns of the second capacitance compensation pattern are longer as the branch patterns are disposed closer to the center of the pad section. The method according to claim 1,
Wherein the plurality of first link wirings transmit signals of a polarity different from that of the plurality of second link wirings to the plurality of signal wirings during one frame period. The method according to claim 1,
Further comprising a pixel electrode and a common electrode arranged in the plurality of pixels,
Wherein the first capacitance compensation pattern and the second capacitance compensation pattern are made of the same material as the pixel electrode or the common electrode. 11. The method of claim 10,
Wherein a voltage equal to a common voltage applied to the common electrode is applied to the first capacitance compensation pattern and the second capacitance compensation pattern. The method according to claim 1,
Wherein the plurality of first link wirings and the plurality of second link wirings are disposed in different layers. A substrate including a display region in which a plurality of pixels are arranged and a non-display region including a pad portion composed of a plurality of pads;
A plurality of first data link lines and a plurality of second data link lines connecting the plurality of signal lines of the display area and the plurality of pads of the non-display area; And
And a first capacitance compensation pattern and a second capacitance compensation pattern arranged alternately so as to overlap the plurality of first data link wiring lines and the plurality of second data link wiring lines. 14. The method of claim 13,
Wherein the first capacitance compensation pattern includes a base pattern and branch patterns extending from the base pattern and including a plurality of branch patterns overlapping each of the plurality of first link wirings,
Wherein the second capacitance compensation pattern includes a base pattern and a plurality of branch patterns extending from the base pattern and overlapping each of the plurality of second link wirings. 15. The method of claim 14,
The branch pattern of the first capacitance compensation pattern and the branch pattern of the second capacitance compensation pattern increase in length from the edge portion of the pad portion to the central portion,
The first capacitance compensation pattern connected to the end of the branch pattern of the first capacitance compensation pattern and the second capacitance compensation pattern connected to the end of the branch pattern of the second capacitance compensation pattern, . 14. The method of claim 13,
And the plurality of first data link wirings are configured to transmit a data voltage having an opposite polarity to the plurality of second data link wirings. 14. The method of claim 13,
Wherein the display device is a liquid crystal display device driven by a column data feeding method. 14. The method of claim 13,
Wherein the plurality of second data link wirings are disposed in different layers from the plurality of first data link wirings and are disposed in a space between a plurality of adjacent first plurality of data link wirings.

Images