KR20190043799A - Display panel - Google Patents

Abstract

The present invention relates to a display panel in which a GIP of a gate driving circuit is arranged in a pixel array. The display panel comprises: a display region having data lines and scan lines intersecting and including sub-pixels arranged at each intersection portion; and at least one GIP distributed and arranged in unit pixel regions of each scan line in the display region and supplying a scan pulse to a corresponding gate line, wherein the unit pixel region includes at least three sub-pixel parts, a GIP part in which one element constituting the GIP is disposed, and a GIP internal connection wiring part in which connection wirings for connecting respective elements of the GIP are disposed and wherein each scan line includes a protrusion part protruding to a region having the GIP internal connection wiring part and the respective data lines intersecting and prevents a parasitic capacitance from being generated between the plurality of data lines and the GIP internal connection wirings.

Description

Display panel {Display panel}

The present invention relates to a display panel in which a GIP of a gate driving circuit is arranged in a pixel array and the coupling between the data line and the Q-node of the GIP can be blocked.

As an information-oriented society develops and various portable electronic devices such as a mobile communication terminal and a notebook computer develop, a demand for a flat panel display device that can be applied to the portable electronic device is gradually increasing.

As such a flat panel display device, an OLED display device using a liquid crystal display (LCD) and an organic light emitting diode (OLED) is used.

Such flat panel display devices include a display panel having a plurality of gate lines and a plurality of data lines for displaying an image, and a driving circuit for driving the display panel.

A display panel of the liquid crystal display device among the display devices includes a thin film transistor array substrate on which a thin film transistor array is formed on a glass substrate, a color filter array substrate on which a color filter array is formed, And a liquid crystal layer filled between the array substrate and the color filter array substrate.

The thin film transistor array substrate includes a plurality of gate lines GL extending in a first direction and a plurality of data lines DL extending in a second direction perpendicular to the first direction, And one sub pixel region (Pixel P) is defined by each data line. One thin film transistor and a pixel electrode are formed in one sub pixel region (P).

In the display panel of such a liquid crystal display device, a voltage is applied to an electric field generating electrode (pixel electrode and common electrode) to generate an electric field in the liquid crystal layer, and the arrangement state of the liquid crystal molecules in the liquid crystal layer is adjusted by the electric field, The image is displayed by controlling the polarization.

In the display panel of the OLED display device among the above-described display devices, a plurality of gate lines and a plurality of data lines intersect to define sub-pixels, and each sub-pixel includes an anode and a cathode, And a pixel circuit for independently driving the OLED.

The pixel circuit may be variously configured, but includes at least one switching TFT, a capacitor, and a driving TFT.

The at least one switching TFT charges the capacitor with a data voltage in response to a scan pulse. The driving TFT controls the amount of current supplied to the OLED according to the data voltage charged in the capacitor to control the amount of light emitted from the OLED.

The display panel for a display device is defined as a non-active area (NA) that is a peripheral area of the display area AA and a display area (AA) that provides an image to the user.

The driving circuit for driving the display panel may further include: a gate driving circuit for sequentially supplying gate pulses (or scan pulses) to the plurality of gate lines of the display panel; And a timing controller for supplying video data and various control signals to the gate driving circuit and the data driving circuit, and the like.

The gate driving circuit may be constituted by at least one gate drive IC, but it is preferable that in the process of forming the sub-pixel and the plurality of signal lines (gate lines and data lines) of the display panel, Region can be formed simultaneously.

In other words, a gate-in-panel (hereinafter referred to as " GIP ") method of directly driving the gate driving circuit to the display panel is applied.

The gate driving circuit includes a plurality of stages (hereinafter, referred to as " GIP ") equal to or greater than the number of gate lines in order to sequentially supply scan pulses to the respective gate lines, Oxide semiconductor thin film transistors.

That is, the gate driving circuit includes a plurality of stages (GIP) that are connected in a dependent manner. Each stage GIP is connected to each gate line and receives a clock signal, a gate start signal, a gate high voltage and a gate low voltage applied from the timing controller, and outputs one carry pulse and one scan pulse And an output unit for generating the output.

1 is a block diagram of a general (n) -th GIP.

As shown in FIG. 1, each of the GIPs is set by a start pulse or a carry pulse SET output from the GIP of the preceding stage, and is set by a carry pulse RST output from the GIP of the following stage. A node controller 100 for controlling the voltages of the first and second nodes Q and Qb and a scan pulse output clock signal SCCLKs for a plurality of scan pulse output signals, And one carry pulse (So (n)) according to the voltage levels of the first and second nodes (Q, Qb), and a carry pulse output clock signal of one of the clock signals (CRCLKs) And an output unit 200 for outputting Co (n).

In the case of the GIP driven by the 6-phase clock signal, the node control unit 100 is set by the carry pulse Co (n-3) outputted from the GIP of the third previous stage, and output by the GIP of the third And is reset by the carry pulse Co (n + 3) to control the voltages of the first and second nodes Q and Qb.

Although not shown in the figure, the output unit 200 of the GIP includes a carry pulse output unit and a scan pulse output unit.

The carry pulse output unit includes a first pull-up transistor and a second pull-down transistor connected in series between a carry signal output clock signal for applying a carry pulse output clock signal of a plurality of carry clock signals and a first gate low voltage signal line (VGL1) And a transistor.

The first pull-up transistor is turned on / off according to a voltage level of the first node (Q), and the first pull-down transistor is turned on / off according to a voltage level of the second node (Qb) And outputs the output clock signal as a carry pulse Co (n).

The scan pulse output unit includes a second pull-up transistor connected in series between a clock signal output clock pulse signal for applying one scan pulse output clock signal of the plurality of scan pulse output clock signals and a second gate low voltage terminal (VGL2) A pull-down transistor, and a bootstrap capacitor connected between a gate electrode of the second pull-up transistor and a source electrode.

The second pull-up transistor is turned on / off according to the voltage level of the second node (Qb), and the second pull- And outputs the output clock signal as a scan pulse So (n).

FIG. 2 is a waveform diagram showing the operation of the (n) -th GIP shown in FIG.

2, the node controller 100 sets the carry pulse Co (n-3) output from the third preceding GIP and the carry pulse Co (n-3) (n + 3)) to control the voltages of the first and second nodes Q and Qb.

The (n) -th GIP (GIP (n)) is set by the carry pulse Co (n-3) output from the GIP of the third previous stage to turn the first node Q to the gate high voltage VGH , And discharges the second node (Qb) to a gate low voltage (VGL) state. Therefore, the first pull-up transistor of the carry pulse output unit and the second pull-up transistor of the scan pulse output unit are turned on, and the first pull-down transistor of the carry pulse output unit and the second pull- do.

Clock signals (CRCLK and SCCLK) having the same phase are applied to the drain electrode of the first pull-up transistor of the carry pulse output unit and the drain electrode of the second pull-up transistor of the scan pulse output unit.

When high level clock signals (CRCLK, SCCLK) are applied to the drain electrode of the first pull-up transistor and the drain electrode of the second pull-up transistor, the voltage of the floating first node (Q) And is bootstrapped and raised by 2VGH.

In the state where the first node Q is bootstrapped, the carry pulse output unit and the scan pulse output unit convert the input clock pulses CRCLK and SCCLK into carry pulses Co (n) (So (n)).

The first node Q is reset by the carry pulse Co (n + 3) output from the third rear-end GIP, and the second node Qb becomes a high state. Accordingly, the first pull-up transistor of the carry pulse output unit and the second pull-up transistor of the scan pulse output unit are turned off, and the first pull-down transistor of the carry pulse output unit and the second pull- -, and outputs the gate low voltage VGL to the carry pulse Co (n) and the scan pulse So (n).

Thus, since the conventional gate driving circuit is directly formed in the non-display region of the display panel, it is difficult to design a narrow bezel of the flat panel display device.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a display panel in which a GIP is disposed in a display region of a display panel to minimize a bezel, It has its purpose.

According to an aspect of the present invention, there is provided a display panel including a display region including data lines and scan lines intersecting each other, And a GIP that is disposed in a unit pixel region of each scan line in the display region and supplies a scan pulse to the gate line, wherein the unit pixel region includes at least three sub-pixel portions, And a GIP internal connection wiring portion in which connection wirings for connecting the respective elements of the GIP are disposed. Each of the scan lines is connected to a portion where the GIP internal connection wiring portion intersects each data line And protrusions protruding from the plurality of data lines and interrupting generation of parasitic capacitance between the plurality of data lines and the GIP internal connection wirings.

According to another aspect of the present invention, there is provided a display panel including: a plurality of data lines formed on a substrate; A buffer layer formed on an entire surface of the substrate including the plurality of data lines; A scan line formed on the buffer layer in a direction perpendicular to the plurality of data lines, and a protrusion protruding from the scan line; An interlayer insulating layer formed on the entire surface of the buffer layer including protrusions of the scan lines and the scan lines; And GIP internal connection wirings formed on the interlayer insulating film in a direction parallel to the scan lines, wherein the scan line protrusions are located at a portion where the plurality of data lines and the GIP internal connection wirings overlap. have.

According to another aspect of the present invention, there is provided a display panel including GIP internal connection wirings formed on a substrate; A buffer layer formed on the entire surface of the substrate including the GIP internal connection wirings; A scan line formed on the buffer layer in a direction parallel to the GIP internal connection wirings, and a protrusion protruding from the scan line; An interlayer insulating layer formed on the entire surface of the buffer layer including protrusions of the scan lines and the scan lines; And a plurality of data lines formed on the interlayer insulating film in a direction perpendicular to the scan lines, wherein the scan line protrusions are located in a portion where the plurality of data lines and the GIP internal connection wirings overlap, .

Here, the GIP internal connection wirings include a Q node of the GIP, and the protrusion of each scan line and the Q node of the GIP are superimposed on each other and utilized as a bootstrap capacitor of the scan pulse output unit in the GIP.

And a reference voltage line formed in the same layer as the plurality of data lines.

The display panel according to the present invention having the above-described characteristics has the following effects.

First, since the GIP is distributed and arranged in the display area, the left and right bezels of the display panel can be minimized as compared with the conventional display panel constituting the GIP in the non-display areas on the left and right sides of the display area.

Second, while arranging the GIP in the display area, a scan line is extended and arranged between the connection wirings connecting the plurality of data lines and the respective elements of the GIP, and between the plurality of data lines and the connection wirings of the GIP The generated parasitic capacitance is blocked, so that occurrence of ripple can be prevented.

Third, since a sufficient capacitance can be obtained by overlapping the projecting portion of the scan line and the connection wirings of the GIP, it can be utilized as a bootstrap capacitor of the scan pulse output portion in the GIP.

1 is a block diagram of a general (n) -th GIP;
Fig. 2 is an operation waveform diagram of the (n) -th GIP shown in Fig. 1
Fig. 3 is a diagram showing a display area configuration diagram of the display panel according to the present invention
Fig. 4 is a configuration diagram more specifically showing two adjacent unit pixels arranged in the display area of the display panel of Fig. 3
5 is a layout diagram showing only four data lines (DL1 to DL4), a reference voltage line (Vref), a scan line and a Q node in the unit pixel of FIG.
6 is a cross-sectional view taken along the line II 'in Fig. 5 according to the first embodiment of the present invention
7 is a cross-sectional view taken along line II 'of Fig. 5 according to the second embodiment of the present invention

The applicant of the present invention has applied for the invention of placing a GIP in the display area of the display panel in order to minimize the bezel of the display panel (Korean Patent Application No. 10-2017-0125355 filed on Sep. 2017 27)).

The invention of the aforementioned patent application (10-2017-0125355) will be briefly described as follows.

FIG. 3 is a diagram showing the configuration of a display area of a display panel according to the present invention, and FIG. 4 is a diagram showing more specifically two adjacent unit pixel areas arranged in a display area of the display panel of FIG.

That is, Fig. 3 corresponds to Fig. 6 of the above-mentioned pending patent application (10-2017-000000), Fig. 4 corresponds to Fig. 7 of the above-mentioned pending patent application (10-2017-000000) do.

As shown in FIGS. 3 and 4, when the GIP is arranged in the display region of the display panel, the unit pixel region of the display region includes at least three sub-pixel portions (R, G, B, and W) ), A GIP internal connection wiring portion 32, and the like.

The plurality of data lines DL1 to DL8, the plurality of reference voltage lines Vref and the first and second constant voltage lines EVDD and EVSS are connected to the vertical And a plurality of gate lines (scan lines) are arranged in the horizontal direction.

The GIP unit 31 corresponds to one unit element (transistor or capacitor) constituting a GIP circuit. That is, one unit element (transistor or capacitor) constituting a GIP circuit is dispersed in a unit pixel region composed of red (R), green (G), blue (B) and white .

That is, at least one GIP for driving one gate line (scan line) is dispersedly disposed in a plurality of unit pixel regions driven by the corresponding gate line (scan line).

The GIP internal connection wiring portion 32 is an area where connection wirings (a Q node, a QB node, and the like) for connecting the respective elements of the GIP are disposed.

4, the plurality of data lines DL1 to DL8 for driving the sub-pixel portions R, G, B, and W are arranged in the vertical direction And the connection wirings (Q node, QB node, etc.) connecting the respective elements of the GIP are arranged in the horizontal direction. Therefore, a connection for connecting the plurality of data lines (DL1 to DL8) The wirings (Q node, QB node, etc.) overlap each other.

Since the connection wirings (Q node, QB node, etc.) connecting the plurality of data lines DL1 to DL8 with the respective elements of the GIP overlap each other, the plurality of data lines DL1 And the connection wirings (Q node, QB node, etc.) connecting the respective elements of the GIP are generated.

That is, the parasitic capacitance between the data line and the connection lines (Q node, QB node, etc.) of the GIP in one sub-pixel is about 0.42 fF, the total parasitic capacitance generated in one GIP is about 37 fF, The parasitic capacitance between the data lines and the connection lines (Q node, QB node, etc.) of the GIP in the entire display panel is about 2.58 pF.

Since the parasitic capacitance is generated between the connection lines (the Q node, the QB node, and the like) connecting the plurality of data lines DL1 to DL8 with the respective elements of the GIP, the data voltage applied to the gate line (Q node, QB node, and the like) connecting the elements of the GIP are shaken, so that ripples may occur.

Therefore, a gate line (scan line) is extended between connection lines (Q node, QB node, etc.) connecting the plurality of data lines DL1 to DL8 with the respective elements of the GIP, The parasitic capacitance generated between the lines DL1 to DL8 and the connection wirings (Q node, QB node, etc.) of the GIP is blocked.

In addition, the connection wirings (Q node, QB node, etc.) of the GIP and the extended gate line (scan line) are overlapped with each other so that they can be used as bootstrap capacitors of the scan pulse output unit in the GIP.

This will be described in more detail with reference to the accompanying drawings.

5 is a layout view showing only four data lines DL1 to DL4, a reference voltage line Vref, a scan line and a Q node in the unit pixel of FIG. 4, and FIG. 6 is a cross- 5 according to the second embodiment of the present invention, and Fig. 7 is a cross-sectional view taken along line II 'of Fig. 5 according to the second embodiment of the present invention.

A plurality of data lines DL1 to DL4 and a reference voltage line Vref are arranged in a vertical direction and a gate line SCAN is arranged in a horizontal direction in order to display an image.

As described above, the connection wirings (Q, only the Q nodes in FIGS. 5 to 7) connecting the elements of the GIP are arranged in the horizontal direction in parallel with the gate lines (scan lines, SCAN) do.

Here, the gate line (scan line, SCAN) includes a protrusion P protruding to a portion where the plurality of data lines DL1 to DL4 and the connection wirings Q of the GIP overlap.

The protrusion P of the gate line (scan line, SCAN) protrudes between the plurality of data lines DL1 to DL4 and the connection wirings (Q node, QB node, etc.) of the GIP, And covers the plurality of data lines DL1 to DL4 of the region overlapping with the data lines Q. Thus, the coupling characteristics of the data lines DL1 to DL4 are cut off.

That is, the protrusion P of the gate line (scan line, SCAN) prevents the parasitic capacitance from occurring between the plurality of data lines DL1 to DL4 and the connection wirings (Q node, QB node, etc.) of the GIP do.

In addition, the protrusion P of the scan line SCAN overlaps the internal connection wiring (Q node) of the GIP and can be utilized as a bootstrap capacitor of the scan pulse output unit in the GIP.

That is, the parasitic capacitance between the protrusion P of the scan line SCAN and the Q node of the GIP is about 132 fF in one sub-pixel, and the parasitic capacitance of the scan line SCAN The total parasitic capacitance generated between the protrusion P and the connection node (Q node) of the GIP is about 12 pF. Therefore, since the capacitance between the protrusion P of the scan line SCAN and the Q node of the GIP is sufficient in one GIP, it can be sufficiently utilized as a bootstrap capacitor of the scan pulse output portion in the GIP. have.

Sectional structures of connection lines (Q nodes) of the four data lines DL1 to DL4, the reference voltage line Vref, the scan lines and the GIP according to the first embodiment of the present invention will be described.

6, a plurality of data lines DL1 to DL4 and a reference voltage line Vref are formed on a substrate in a vertical direction, the plurality of data lines DL1 to DL4, A buffer layer is formed on the entire surface of the substrate including the reference voltage line Vref.

A protrusion SCAN (P) of a scan line and a scan line is formed on the buffer layer in the horizontal direction and an interlayer insulating film (not shown) is formed on the entire surface of the buffer including the SCAN (P) (ILD) is formed, and connection wirings (Q nodes) of the GIP are formed in the horizontal direction on the interlayer insulating film (ILD).

Sectional structures of connection lines of four data lines DL1 to DL4, a reference voltage line Vref, a scan line and a GIP according to the second embodiment of the present invention will be described.

As shown in FIG. 7, connection wirings (Q nodes) of the GIP are formed on a substrate in a horizontal direction, and a buffer layer (not shown) is formed on a front surface of a substrate (Buffer) is formed.

A protrusion SCAN (P) of a scan line and a scan line is formed on the buffer layer in the horizontal direction and an interlayer insulating film (not shown) is formed on the entire surface of the buffer including the SCAN (P) A plurality of data lines DL1 to DL4 and a reference voltage line Vref are formed in the vertical direction on the interlayer insulating layer ILD.

5 to 7, a protrusion P of the gate line (scan line, SCAN) protrudes from a portion where the reference voltage line Vref overlaps with the connection wirings Q of the GIP, (Vref) and the connection wirings (Q node) of the GIP are prevented from being generated.

However, the present invention is not limited thereto. The protrusion P of the gate line (scan line, SCAN) may not protrude from a portion where the reference voltage line Vref overlaps with the connection wirings Q of the GIP.

As described above, the protrusion P of the gate line (scan line, SCAN) is connected between the plurality of data lines DL1 to DL4 and the connection wirings (Q node, QB node, etc.) of the GIP by the parasitic capacitance The parasitic capacitance between the data lines and the connecting lines (Q node, QB node, etc.) of the GIP in the entire display panel is remarkably lowered to about 0.16 pF (about 93.7% reduction).

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

31: GIP circuit part 32: GIP internal connection wiring part
SCAN: scan line DL1 to DL8: data line
Q: Q node

Claims (8)

A display region including data lines and scan lines intersecting each other and including sub-pixels arranged at the intersections; And
And at least one GIP that is disposed in a unit pixel area of each scan line in the display area and supplies a scan pulse to the corresponding gate line,
Wherein the unit pixel region includes at least three sub-pixel portions, a GIP portion in which one element constituting the GIP is disposed, and a GIP internal connection wiring portion in which connection wirings connecting the elements of the GIP are arranged,
Each of the scan lines includes a protrusion protruding from a portion where the GIP internal connection wiring portion intersects with the data lines to prevent parasitic capacitance from being generated between the plurality of data lines and the GIP internal connection wiring. The method according to claim 1,
Wherein the GIP internal connection wirings include a Q node of the GIP and the protrusion of each scan line and the Q node of the GIP overlap each other and serve as a bootstrap capacitor of a scan pulse output portion in the GIP. A plurality of data lines formed on a substrate;
A buffer layer formed on an entire surface of the substrate including the plurality of data lines;
A scan line formed on the buffer layer in a direction perpendicular to the plurality of data lines, and a protrusion protruding from the scan line;
An interlayer insulating layer formed on the entire surface of the buffer layer including protrusions of the scan lines and the scan lines; And
And GIP internal connection wirings formed on the interlayer insulating film in a direction parallel to the scan lines,
Wherein the scan line protrusion is located at a portion where the plurality of data lines and the GIP internal connection wirings overlap. The method of claim 3,
Wherein the GIP internal connection wirings include a Q node of the GIP and the protrusion of each scan line and the Q node of the GIP overlap each other and serve as a bootstrap capacitor of a scan pulse output portion in the GIP. GIP internal connection wirings formed on the substrate;
A buffer layer formed on the entire surface of the substrate including the GIP internal connection wirings;
A scan line formed on the buffer layer in a direction parallel to the GIP internal connection wirings, and a protrusion protruding from the scan line;
An interlayer insulating layer formed on the entire surface of the buffer layer including protrusions of the scan lines and the scan lines; And
And a plurality of data lines formed on the interlayer insulating film in a direction perpendicular to the scan lines,
Wherein the scan line protrusion is located at a portion where the plurality of data lines and the GIP internal connection wirings overlap. 6. The method of claim 5,
Wherein the GIP internal connection wirings include a Q node of the GIP and the protrusion of each scan line and the Q node of the GIP overlap each other and serve as a bootstrap capacitor of a scan pulse output portion in the GIP. The method according to claim 3 or 5,
And a reference voltage line formed in the same layer as the plurality of data lines. 8. The method of claim 7,
Wherein the scan line protrusion is located at a portion where the reference voltage line and the GIP internal connection wirings overlap.

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