JP2023142982A - display device - Google Patents

Abstract

To provide a display device capable of upgrading a display characteristic.SOLUTION: A display device includes a pixel array 10 that is disposed in a display area 4 where an image is displayed and that includes plural pixels, plural scan lines GL that are disposed in the pixel array 10 and extend in a first direction, a gate driver GD that is disposed in the display area 4, connected to the plural scan lines GL, and includes plural first transistors, and a reflection film 41 covering the plural first transistors.SELECTED DRAWING: Figure 10

Description

The present invention relates to a display device.

An active matrix liquid crystal display device or an organic EL (electroluminescence) display device uses thin film transistors (TFTs) as active elements and includes a substrate (referred to as a TFT substrate) on which TFTs are arranged in a matrix. . The TFT substrate has a plurality of signal lines each extending in the column direction and into which image signals are input, and a plurality of scanning lines each extending in the row direction.

In recent years, gate drivers for driving scanning lines have been formed on TFT substrates to reduce the cost of driver ICs and to make display panels have narrow bezels. Furthermore, by forming the gate driver on the TFT substrate, there are no restrictions on routing the scanning lines, making it a useful technology for irregular-shaped displays (non-rectangular displays) that are in high demand for automotive applications. There is. Such technology is called GIP (Gate driver in panel) or GOA (Gate driver on array).

GIP is an extremely important technology for realizing narrow frame and irregularly shaped displays at low cost. However, in the case of a configuration in which the gate driver is disposed in the frame, there is a limit to the narrowing of the frame because a region for arranging the gate driver is required. Furthermore, in consideration of reliability issues (particularly light leakage), a frame with a certain area must be allowed.

Under such circumstances, a technique has been proposed in which a gate driver is mounted within a display area. A technique for mounting a gate driver in a display area is called, for example, GIA (Gate driver in Active array) or GDM (Gate driver monolithic circuitry). GIA is attracting attention as a technology that can be applied to narrow frame and irregularly shaped displays. Additionally, GIA has been developed as a technology for forming a multi-panel display by connecting a plurality of narrow-framed display panels and a technology for forming a foldable display structure.

However, when attempting to form a drive circuit using TFTs on a TFT substrate, such as GIP, variations in the characteristics of the TFTs tend to cause malfunctions of the gate drivers. As a means for correcting variations in TFT characteristics, there is a technique in which the TFT has a dual gate structure and the threshold voltage is corrected using a back gate voltage. However, if a TFT having a dual gate structure is applied to a gate driver, the configuration of the display device becomes complicated.

Patent No. 6077704 Patent No. 5178801 Patent No. 6312947

The present invention provides a display device that can improve display characteristics.

According to a first aspect of the present invention, a pixel array provided in a display area for displaying an image and having a plurality of pixels; a plurality of scanning lines provided in the pixel array and extending in a first direction; A display device is provided, including: a gate driver provided with a gate driver, connected to the plurality of scanning lines, and including a plurality of first transistors; and a first reflective film covering the plurality of first transistors.

According to a second aspect of the present invention, there is provided the display device according to the first aspect, wherein each of the plurality of first transistors includes a first gate electrode and a second gate electrode.

According to a third aspect of the present invention, the invention further includes a first electrode that covers the plurality of first transistors, the first reflective film is provided on the first electrode, and the first electrode is configured to cover the first transistors. A display device according to a second aspect is provided, which functions as the second gate electrode of a transistor.

According to a fourth aspect of the present invention, the first transistor includes a first semiconductor layer, and the first gate electrode of the first transistor is provided below the first semiconductor layer with an insulating film interposed therebetween; A display device according to a third aspect is provided, wherein the second gate electrode of the first transistor is provided above the first semiconductor layer with an insulating film interposed therebetween.

According to a fifth aspect of the present invention, there is provided a display device according to the third or fourth aspect, further comprising a control circuit that applies a voltage to the first electrode.

According to a sixth aspect of the present invention, the display according to the fifth aspect, wherein the control circuit applies a positive voltage to the first electrode during a scanning operation and applies a negative voltage to the first electrode when stopping scanning. Equipment is provided.

According to a seventh aspect of the present invention, the pixel array includes a plurality of subarrays, the gate driver includes a plurality of gate drivers respectively provided in the plurality of subarrays, and the first electrode is arranged for each of the subarrays. There is provided a display device according to any one of the third to sixth aspects, in which the display device is electrically isolated from the display device.

According to an eighth aspect of the present invention, each of the plurality of pixels includes a second transistor, and the second transistor is covered with a second reflective film. A display device is provided.

According to a ninth aspect of the present invention, there is provided the display device according to the eighth aspect, wherein the second transistor includes a first gate electrode and a second gate electrode.

According to a tenth aspect of the present invention, the invention further includes a second electrode covering the second transistor, the second reflective film being provided on the second electrode, and the second electrode covering the second transistor. A display device according to a ninth aspect is provided, which functions as the second gate electrode.

According to an eleventh aspect of the present invention, the second transistor includes a second semiconductor layer, and the first gate electrode of the second transistor is provided below the second semiconductor layer with an insulating film interposed therebetween; A display device according to a tenth aspect is provided, wherein the second gate electrode of the second transistor is provided above the second semiconductor layer with an insulating film interposed therebetween.

According to a twelfth aspect of the present invention, the gate driver includes a shift register having a plurality of cascade-connected core circuits, and each of the plurality of core circuits receives an input signal corresponding to an output signal of a preceding core circuit. a first inverter circuit that is enabled by a first frame signal and holds an inverted signal of the first node at a second node; and a first inverter circuit that is complementary to the first frame signal. There is provided a display device according to any one of the first to eleventh aspects, including a second inverter circuit that is enabled by a two-frame signal and holds an inverted signal of the first node at a third node.

According to a thirteenth aspect of the present invention, the core circuit includes an output section, the output section includes an output transistor and a capacitor, and the output transistor has a gate connected to the first node and a clock The capacitor has a first terminal for receiving a signal and a second terminal connected to a scanning line, and the capacitor has a first electrode connected to the first node and a second electrode connected to the scanning line. A display device according to a twelfth aspect is provided, having the following.

According to the present invention, it is possible to provide a display device that can improve display characteristics.

FIG. 1 is a schematic layout diagram of a liquid crystal display device according to a first embodiment. FIG. 2 is a block diagram of a liquid crystal display device. FIG. 3 is a schematic diagram of the display area. FIG. 4 is a schematic diagram of the pixel array shown in FIG. 2. FIG. 5 is a schematic diagram of the gate driver group shown in FIG. 2. FIG. 6 is a circuit diagram of the subarray shown in FIG. 4. FIG. 7 is a block diagram of a shift register included in the gate driver. FIG. 8 is a circuit diagram of the core circuit shown in FIG. 7. FIG. 9 is a schematic diagram illustrating the arrangement area of the gate driver. FIG. 10 is a plan view of the subarray and gate driver. FIG. 11 is a cross-sectional view of the subarray and gate driver along line AA' in FIG. 10. FIG. 12 is a cross-sectional view of the subarray and gate driver along line BB' in FIG. 10. FIG. 13 is a cross-sectional view of the subarray and gate driver along line CC' in FIG. 10. FIG. 14 is a cross-sectional view of the subarray and gate driver along line DD' in FIG. 10. FIG. 15 is a cross-sectional view of the subarray and gate driver along line EE' in FIG. 10. FIG. 16 is a diagram illustrating the configuration of the storage capacitor electrode. FIG. 17 is a diagram illustrating wiring of a plurality of divided areas. FIG. 18 is a schematic diagram illustrating an example of the display area. FIG. 19 is a graph illustrating the characteristics of a dual-gate TFT. FIG. 20 is a graph illustrating the characteristics of a dual gate TFT. FIG. 21 is a diagram illustrating the behavior of falling voltage when a scanning line is selected. FIG. 22 is a graph illustrating the behavior of falling voltage when a scanning line is selected. FIG. 23 is a timing diagram illustrating the scanning operation of divided areas according to the first embodiment. FIG. 24 is a timing diagram illustrating the operation of stopping scanning of divided areas according to the first embodiment. FIG. 25 is a schematic diagram illustrating the driving pattern 1 of the liquid crystal display device according to the first embodiment. FIG. 26 is a schematic diagram illustrating drive pattern 2 of the liquid crystal display device according to the first embodiment. FIG. 27 is a timing diagram illustrating the operation of the shift register. FIG. 28 is a schematic diagram illustrating the inverter operation of the core circuit during the selection period. FIG. 29 is a diagram illustrating wiring of a plurality of divided regions according to the second embodiment. FIG. 30 is a timing diagram illustrating the scanning operation of divided areas according to the second embodiment. FIG. 31 is a timing diagram illustrating the operation of stopping scanning of divided areas according to the second embodiment. FIG. 32 is a schematic diagram of a display area according to the third embodiment. FIG. 33 is a schematic diagram illustrating the driving pattern 1 of the liquid crystal display device according to the third embodiment. FIG. 34 is a schematic diagram illustrating drive pattern 2 of the liquid crystal display device according to the third embodiment.

Hereinafter, embodiments will be described with reference to the drawings. However, the drawings are schematic or conceptual, and the dimensions, proportions, etc. of each drawing are not necessarily the same as those in reality. Further, even when the same parts are shown in two drawings, the relationships and ratios of the dimensions may be different. In particular, some of the embodiments shown below illustrate devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is is not specified. In the following description, elements having the same functions and configurations are denoted by the same reference numerals, and redundant description will be omitted.

In this embodiment, a liquid crystal display device will be described as an example of the display device. The liquid crystal display device of this embodiment has a configuration in which a gate driver is arranged within a display area. Further, the liquid crystal display device of this embodiment is a transflective liquid crystal display device that can perform reflective display using external light and transmissive display using a backlight.

[1] First Embodiment [1-1] Configuration of Liquid Crystal Display Device 1 FIG. 1 is a schematic layout diagram of a liquid crystal display device 1 according to a first embodiment of the present invention. In FIG. 1, the X direction is the row direction in which the scanning lines GL extend, and the Y direction is the column direction in which the signal lines SL extend. The liquid crystal display device 1 includes a TFT substrate 2, an integrated circuit (IC) 3, a pixel array 10, and a gate driver group 11.

The TFT substrate 2 is made of a transparent insulating substrate, such as a glass substrate or a plastic substrate. A pixel array 10, a gate driver group 11, and an integrated circuit 3 are provided on the TFT substrate 2. A counter substrate (not shown) is arranged above the TFT substrate 2, and a liquid crystal layer (not shown) is arranged between the TFT substrate 2 and the counter substrate.

The pixel array 10 is provided with a plurality of scanning lines GL, each extending in the X direction, and a plurality of signal lines SL, each extending in the Y direction. The area where the pixel array 10 is arranged constitutes the display area 4. Display area 4 is an area where images are displayed.

Gate driver group 11 is arranged within display area 4 . Gate driver group 11 is connected to multiple scanning lines GL. Note that a part of the gate driver group 11 is arranged in a peripheral area around the display area 4. The peripheral area corresponds to the frame of the liquid crystal display device 1. The frame is covered with, for example, a black light-shielding layer, and is visually recognized by the viewer as a black area.

Integrated circuit 3 is connected to multiple signal lines SL. The integrated circuit 3 is also connected to a gate driver group 11 . The integrated circuit 3 is composed of an IC chip.

FIG. 2 is a block diagram of the liquid crystal display device 1. As shown in FIG. The liquid crystal display device 1 includes a pixel array 10, a gate driver group 11, a source driver 12, a common electrode driver 13, a voltage generation circuit 14, a control circuit 15, and a backlight 16. The integrated circuit 3 shown in FIG. 1 includes the source driver 12, common electrode driver 13, voltage generation circuit 14, and control circuit 15 shown in FIG.

The backlight 16 constitutes a surface light source. The backlight 16 is configured with, for example, a sidelight type or direct type lighting device. The backlight 16 is arranged on the side of the TFT substrate 2 opposite to the side on which the liquid crystal layer is arranged. The backlight 16 emits illumination light and irradiates the pixel array 10 with this illumination light.

The pixel array 10 includes a plurality of pixels arranged in a matrix. Furthermore, the pixel array 10 includes a plurality of subarrays arranged in a matrix. The specific configuration of the subarray will be described later. The pixel array 10 is provided with a plurality of scanning lines GL, each extending in the X direction, and a plurality of signal lines SL, each extending in the Y direction. Pixels are arranged in the intersection area of the scanning line GL and the signal line SL.

Gate driver group 11 is connected to multiple scanning lines GL. The gate driver group 11 includes a plurality of gate drivers provided corresponding to a plurality of subarrays. The specific configuration of the gate driver will be described later. Based on the control signal sent from the control circuit 15, the gate driver group 11 sends a plurality of scanning signals to the pixel array 10 for turning on/off switching elements included in the pixels.

The source driver 12 is connected to a plurality of signal lines SL. The source driver 12 receives a control signal and image data from the control circuit 15. The source driver 12 sends a plurality of gradation signals (a plurality of drive voltages) corresponding to image data to the pixel array 10 based on the control signal.

The common electrode driver 13 generates a common voltage Vcom and supplies this common voltage Vcom to the common electrode within the pixel array 10. The common electrode is an electrode provided to face a plurality of pixel electrodes provided for each of a plurality of pixels with a liquid crystal layer interposed therebetween.

The voltage generation circuit 14 generates various voltages necessary for the operation of the liquid crystal display device 1, and supplies these voltages to corresponding circuits.

The control circuit 15 centrally controls the operation of the liquid crystal display device 1 . Control circuit 15 receives image data DT and control signal CNT from the outside. The control circuit 15 generates various control signals based on the image data DT, and sends these control signals to corresponding circuits.

[1-1-1] Configuration of Display Area 4 FIG. 3 is a schematic diagram of the display area 4 shown in FIG. 1.

The display area 4 includes a plurality of divided areas DI_(1,1) to DI_(m,n) arranged in a matrix (m rows×n columns). "m" and "n" are each an integer of 2 or more. The number of divided areas DI included in the display area 4 can be set arbitrarily. In this embodiment, the description of the reference numeral DI without subscripts (m, n) is commonly applied to a plurality of divided regions. The same applies to other reference signs with subscripts.

Each divided region DI is provided with a subarray SA and a gate driver GD.

FIG. 4 is a schematic diagram of the pixel array 10 shown in FIG. 2. The pixel array 10 includes a plurality of subarrays SA_(1,1) to SA_(m,n) arranged in a matrix (m rows×n columns). A plurality of sub-arrays SA_(1,1) to SA_(m,n) are provided in divided regions DI_(1,1) to DI_(m,n), respectively.

Each subarray SA includes a plurality of pixels PX arranged in a matrix. A plurality of scanning lines GL are arranged in one subarray SA. That is, the plurality of subarrays SA can be individually scanned. A plurality of subarrays SA included in each column (that is, a plurality of subarrays SA lined up in the column direction) are connected to a common signal line SL.

FIG. 5 is a schematic diagram of the gate driver group 11 shown in FIG. 2. The gate driver group 11 includes a plurality of gate drivers GD_(1,1) to GD_(m,n) arranged in a matrix (m rows×n columns). Gate drivers GD_(1,1) to GD_(m,n) are provided in divided regions DI_(1,1) to DI_(m,n), respectively. Each gate driver GD is connected to a plurality of scanning lines GL arranged in a corresponding sub-array SA, and scans the plurality of scanning lines GL. FIG. 5 schematically shows how a plurality of circuit elements constituting the gate driver GD are distributed and arranged within the divided region DI.

FIG. 6 is a circuit diagram of subarray SA shown in FIG. 4. Sub-array SA is provided with a plurality of scanning lines GL1 to GLi and a plurality of signal lines SL1 to SLj. “i” and “j” are each an integer of 2 or more.

The pixel PX includes a switching element (active element) 17, a liquid crystal capacitor (liquid crystal element) Clc, and a storage capacitor Cs.

As the switching element 17, for example, a TFT (Thin Film Transistor) is used, and an n-channel TFT is used. Furthermore, the switching element 17 is constituted by a dual gate TFT having a first gate electrode and a second gate electrode. The first gate electrode is the upper gate electrode in the circuit diagram, and the second gate electrode is the lower gate electrode in the circuit diagram. The second gate electrode functions as a back gate of the TFT. Note that the source and drain of a transistor change depending on the direction of current flowing through the transistor, but in the following description, an example of a connection state of the transistor will be described. However, it goes without saying that the source and drain are not fixed as their names suggest.

A first gate electrode of the TFT 17 is connected to the scanning line GL, and a second gate electrode of the TFT 17 is connected to a storage capacitor line (also referred to as a storage electrode) CsL. The drain of the TFT 17 is connected to the signal line SL, and the source thereof is connected to one electrode of the liquid crystal capacitor Clc. A liquid crystal capacitor Clc as a liquid crystal element is composed of a pixel electrode, a common electrode, and a liquid crystal layer sandwiched therebetween. A common voltage Vcom is applied by a common electrode driver 13 to the other electrode of the liquid crystal capacitor Clc.

One electrode of the storage capacitor Cs is connected to one electrode of the liquid crystal capacitor Clc. The other electrode of the storage capacitor Cs is connected to the storage capacitor line CsL. The storage capacitor Cs has a function of suppressing potential fluctuations occurring in the pixel electrode and holding the drive voltage applied to the pixel electrode until a drive voltage corresponding to the next signal is applied. The storage capacitor Cs is composed of a pixel electrode, a storage capacitor line CsL, and an insulating film sandwiched therebetween. A storage capacitor voltage Vcs is applied to the storage capacitor line CsL by a voltage generating circuit 14. The storage capacitance voltage Vcs is set, for example, to the same voltage as the common voltage Vcom during a period in which the pixel PX performs a display operation.

[1-1-2] Configuration of Gate Driver GD Next, the configuration of the gate driver GD will be described. Gate driver GD includes a shift register SR. FIG. 7 is a block diagram of the shift register SR included in the gate driver GD.

Shift register SR includes a plurality of core circuits RG1 to RGi. Core circuits RG1 to RGi are provided corresponding to scanning lines GL1 to GLi, respectively.

The plurality of core circuits RG1 to RGi are connected in cascade. Each core circuit RG functions as a register that temporarily stores input data. The shift register SR operates in synchronization with a clock signal, and operates to sequentially shift input data (pulse signals).

Each core circuit RG is configured to output a pulse signal according to the conditions of a plurality of signals input thereto. Each core circuit RG includes an input terminal V_IN, an output terminal OUT, a frame terminal Fr_o, a frame terminal Fr_e, a clock terminal CLK, a clear terminal CR, and a reset terminal RST_IN.

The plurality of core circuits RG1 to RGi are connected in cascade such that the output terminal OUT of any core circuit RG is connected to the input terminal V_IN of the subsequent core circuit RG. Note that the start signal ST is input to the input terminal V_IN of the first stage core circuit RG1.

A frame signal Frame_o is input to the frame terminals Fr_o of the core circuits RG1 to RGi. A frame signal Frame_e is input to frame terminals Fr_e of the core circuits RG1 to RGi. A clear signal CLR is input to the clear terminals CR of the core circuits RG1 to RGi.

A clock signal ClkA is input to the clock terminal CLK of the odd-numbered core circuits RG1, RG3, . . . . A clock signal ClkB is input to the clock terminal CLK of the even-numbered core circuits RG2, RG4, . . . . Clock signal ClkA and clock signal ClkB have a complementary phase relationship.

The output terminal OUT of any core circuit RG is connected to the reset terminal RST_IN of the preceding core circuit RG. A clear signal CLR is input to the reset terminal RST_IN of the final stage core circuit RGi.

Output terminals OUT of the plurality of core circuits RG1 to RGi are connected to scanning lines GL1 to GLi, respectively. A capacitor connected to each scanning line GL in FIG. 7 is a simplified representation of the capacitance of a pixel connected to the scanning line.

The control circuit 15 generates the aforementioned frame signal Frame_o, frame signal Frame_e, clock signal ClkA, clock signal ClkB, and clear signal CLR, and supplies these signals to the shift register SR.

[1-1-3] Specific configuration of core circuit RG Next, a specific configuration of core circuit RG will be described. FIG. 8 is a circuit diagram of the core circuit RG shown in FIG. 7. Core circuit RG includes an input section 20, a register section 21, an output section 22, a pull-down section 23, and a clear section 24.

The core circuit RG is composed of TFTs having the same configuration as the TFTs 17 of the pixel array 10. That is, the TFTs included in the core circuit RG are composed of N-channel TFTs and are composed of dual-gate TFTs. In FIG. 8, illustration of the back gate (second gate electrode) of the TFT is omitted to avoid complicating the drawing. Similar to the pixel array 10, the back gate of the TFT is connected to the storage capacitor line CsL. Hereinafter, a TFT may be simply referred to as a transistor. In this specification, one of the source and drain of a transistor may be referred to as a first terminal, and the other may be referred to as a second terminal.

Input section 20 is a circuit for receiving input signal VIN. The input section 20 includes two transistors M2 and M5. The input signal VIN is input to the gate of the transistor M2 via the input terminal V_IN. The input signal VIN corresponds to the output signal of the preceding core circuit RG. The drain of transistor M2 is connected to its gate. That is, transistor M2 is diode-connected. The source of transistor M2 is connected to node An. The transistor M2 transfers the input signal VIN to the node An when the input signal VIN is at a high level, and turns off when the input signal VIN is at a low level.

A reset signal RST is input to the gate of the transistor (also referred to as a reset transistor) M5 via a reset terminal RST_IN. The reset signal RST corresponds to the output signal of the subsequent core circuit RG. The drain of transistor M5 is connected to node An. The source of transistor M5 is connected to a power supply terminal to which voltage Vgl is supplied. The voltage Vgl is a reference voltage for setting the signal to a low level, and is lower than the high level voltage of the signal. Voltage Vgl is, for example, a negative voltage lower than ground voltage GND, and is set in the range of -10V to -20V.

The register section 21 is a circuit for holding the voltage applied to the capacitor Cb in a selected state and a non-selected state. The register section 21 includes two inverter circuits 21o and 21e and a transistor M1b.

The inverter circuit 21o includes three transistors M1o, M6o, and M7o. A frame signal Frame_o is input to the gate of the transistor M1o via a frame terminal Fr_o. The drain of transistor M1o is connected to its own gate. The source of transistor M1o is connected to node Bno. The transistor M1o transfers the frame signal Frame_o to the node Bno when the frame signal Frame_o is at a high level, and turns off when the frame signal Frame_o is at a low level. That is, the inverter circuit 21o is enabled when the frame signal Frame_o is at a high level.

The gate of transistor M6o is connected to node Bno. The drain of transistor M6o is connected to node An. The source of transistor M6o is connected to a power supply terminal to which voltage Vgl is supplied. Transistor M6o has a function of pulling down the potential of node An.

The gate of transistor M7o is connected to node An. The drain of transistor M7o is connected to node Bno. The source of transistor M7o is connected to a power supply terminal to which voltage Vgl is supplied. Transistor M7o has a function of pulling down the potential of node Bno.

The inverter circuit 21e includes three transistors M1e, M6e, and M7e. A frame signal Frame_e is input to the gate of the transistor M1e via a frame terminal Fr_e. The drain of transistor M1e is connected to its own gate. The source of transistor M1e is connected to node Bne. The transistor M1e transfers the frame signal Frame_e to the node Bne when the frame signal Frame_e is at a high level, and turns off when the frame signal Frame_e is at a low level. That is, the inverter circuit 21e is enabled when the frame signal Frame_e is at a high level.

The gate of transistor M6e is connected to node Bne. The drain of transistor M6e is connected to node An. The source of transistor M6e is connected to a power supply terminal to which voltage Vgl is supplied. Transistor M6e has a function of pulling down the potential of node An.

The gate of transistor M7e is connected to node An. The drain of transistor M7e is connected to node Bne. The source of transistor M7e is connected to a power supply terminal to which voltage Vgl is supplied. Transistor M7e has a function of pulling down the potential of node Bne.

The gate of transistor M1b is connected to node An. One end of the current path of transistor M1b is connected to node Bno. The other end of the current path of transistor M1b is connected to node Bne. Transistor M1b connects nodes Bno and Bne when node An is at high level.

The output unit 22 is a circuit for outputting an output signal to the scanning line GL. The output section 22 includes a transistor (also referred to as an output transistor) M3 and a capacitor Cb. The gate of transistor M3 is connected to node An. A clock signal Clk is input to the drain of the transistor M3. The clock signal Clk is either clock signal ClkA or ClkB, and in the case of odd-numbered core circuits RG, it is the clock signal ClkA, and in the case of even-numbered core circuits RG, it is the clock signal ClkB. The source of transistor M3 is connected to node Qn.

One electrode of capacitor Cb is connected to node An, and the other electrode of capacitor Cb is connected to node Qn. Node Qn is connected to corresponding scanning line GL.

The pull-down section 23 is a circuit for pulling down the potential of the node Qn. The pull-down section 23 includes two transistors (also referred to as pull-down transistors) M4o and M4e. The gate of transistor M4o is connected to node Bno. The drain of transistor M4o is connected to node Qn. The source of transistor M4o is connected to a power supply terminal to which voltage Vgl is supplied.

The gate of transistor M4e is connected to node Bne. The drain of transistor M4e is connected to node Qn. The source of transistor M4e is connected to a power supply terminal to which voltage Vgl is supplied.

The clear unit 24 is a circuit for clearing the node An and the node Qn. The clear section 24 includes two transistors M8 and M9. A clear signal CLR is input to the gate of the transistor M8 via a clear terminal CR. The drain of transistor M8 is connected to node Qn. The source of transistor M8 is connected to a power supply terminal to which voltage Vgl is supplied.

A clear signal CLR is input to the gate of the transistor M9 via a clear terminal CR. The drain of transistor M9 is connected to node An. The source of transistor M9 is connected to a power supply terminal to which voltage Vgl is supplied.

[1-1-4] Arrangement of Gate Driver GD Next, the arrangement of the gate driver GD will be explained. FIG. 9 is a schematic diagram illustrating the arrangement area of the gate driver GD.

A region between pixels PX adjacent to each other in the X direction and a region between pixels PX adjacent to each other in the Y direction are used as a gate driver arrangement region GA.

Gate driver GD includes multiple active elements (including multiple dual gate TFTs and multiple capacitors). The plurality of active elements are arranged in the gate driver arrangement area GA.

In the example of FIG. 9, a wiring AnL forming a node An and a power supply line VglL for supplying a voltage Vgl are arranged in the gate driver arrangement area GA. FIG. 9 shows transistors M6e and M7e as an example. The connection relationship between transistors M6e and M7e is the same as in FIG. 8. Transistors M6e and M7e are composed of dual gate TFTs. The back gates (second gate electrodes) of transistors M6e and M7e are connected to storage capacitor line CsL.

[1-1-5] Detailed configuration of sub-array SA and gate driver GD FIG. 10 is a plan view of sub-array SA and gate driver GD. FIG. 11 is a cross-sectional view of the subarray SA and gate driver GD taken along line AA' in FIG. FIG. 12 is a cross-sectional view of the subarray SA and gate driver GD taken along line BB' in FIG. FIG. 13 is a cross-sectional view of the subarray SA and gate driver GD along the line CC' in FIG. 10. FIG. 14 is a cross-sectional view of the subarray SA and gate driver GD along line DD' in FIG. 10. FIG. 15 is a cross-sectional view of the subarray SA and gate driver GD along the line EE' in FIG. In FIG. 10, six pixels PX included in the sub-array SA and arranged in the X direction are extracted and shown. Further, FIG. 10 shows extracted transistors M6e and M7e included in the gate driver GD.

(Configuration of subarray SA)
First, the configuration of pixels PX included in sub-array SA will be described.
The liquid crystal display device 1 includes a TFT substrate 2 on which switching elements, pixel electrodes, etc. are formed, and a color filter substrate (referred to as a CF substrate) 31 placed opposite to the TFT substrate 2 and on which color filters and the like are formed. Each of the TFT substrate 2 and the CF substrate 31 is made of a transparent and insulating substrate (eg, a glass substrate or a plastic substrate).

The liquid crystal layer 32 is sandwiched and filled between the TFT substrate 2 and the CF substrate 31. Specifically, the liquid crystal layer 32 is enclosed within a display area surrounded by the TFT substrate 2, the CF substrate 31, and a sealant (not shown). The sealing material is made of, for example, an ultraviolet curing resin, a thermosetting resin, or a combination of ultraviolet and heat curing resin, and after being applied to the TFT substrate 2 or the CF substrate 31 in the manufacturing process, it is cured by ultraviolet irradiation, heating, etc. I am made to do so.

The optical properties of the liquid crystal material constituting the liquid crystal layer 32 change as the alignment of liquid crystal molecules is manipulated in accordance with the applied electric field. The liquid crystal display device 1 of this embodiment is, for example, a VA mode using a vertical alignment (VA) type liquid crystal. As the liquid crystal layer 32, a negative type (N type) nematic liquid crystal having negative dielectric constant anisotropy is used. The liquid crystal layer 32 is vertically aligned in the initial state. The liquid crystal molecules are aligned almost perpendicularly to the main surface of the substrate when there is no voltage (no electric field). When a voltage is applied (an electric field is applied), the directors of liquid crystal molecules tilt toward the horizontal direction (direction parallel to the main surface of the substrate). Note that the liquid crystal mode is not limited to VA mode, and various liquid crystal modes such as TN (Twisted Nematic) mode and homogeneous mode can be applied.

Next, the configuration on the TFT substrate 2 side will be explained. On the liquid crystal layer 32 side of the TFT substrate 2, a dual gate TFT 17 is provided for each pixel. The TFT 17 includes a first gate electrode 33, a gate insulating film 34, a semiconductor layer 35, a source electrode 36, a drain electrode 37, and a second gate electrode (storage capacitor electrode) 40. The TFT 17 is sometimes called a transistor.

On the TFT substrate 2, a scanning line GL and a first gate electrode 33 connected to the scanning line GL are provided. The scanning line GL extends in the X direction. The first gate electrode 33 extends in the Y direction from the scanning line GL. The scanning line GL and the first gate electrode 33 are made of, for example, any one of aluminum (Al), molybdenum (Mo), chromium (Cr), and tungsten (W), or an alloy containing one or more of these. be done.

A gate insulating film 34 is provided on the scanning line GL and the first gate electrode 33. The gate insulating film 34 is made of a transparent insulating material, such as silicon nitride (SiN).

A semiconductor layer 35 is provided on the gate insulating film 34. In FIG. 10, the semiconductor layer 35 is hatched. The semiconductor layer 35 is made of, for example, amorphous silicon.

A source electrode 36 and a drain electrode 37 are provided on the semiconductor layer 35 and spaced apart in the X direction. A connection electrode 38 extending from the source electrode 36 in the X direction is provided on the gate insulating film 34 . A signal line SL extending in the Y direction is provided on the gate insulating film 34. Drain electrode 37 is connected to signal line SL. The source electrode 36, the drain electrode 37, the connection electrode 38, and the signal line SL are made of, for example, any one of aluminum (Al), molybdenum (Mo), chromium (Cr), and tungsten (W), or one or more of these. It is composed of alloys containing.

An insulating layer 39 is provided on the source electrode 36 and the drain electrode 37. The insulating layer 39 is made of a transparent insulating material, such as silicon nitride (SiN).

A storage capacitor electrode (Cs electrode) 40 is provided on the insulating layer 39. The storage capacitor electrode 40 also serves as the second gate electrode of the TFT 17. The storage capacitor electrode 40 is made of a transparent electrode, for example made of ITO (indium tin oxide). The storage capacitor electrode 40 has an opening 40A for each pixel PX. The storage capacitor electrode 40 is configured to surround the pixel PX. The storage capacitor electrode 40 includes an electrode portion that covers the semiconductor layer 35, and the electrode portion substantially functions as a second gate electrode. The storage capacitor electrode 40 is configured to cover the scanning line GL and the signal line SL. In this embodiment, the storage capacitor electrode 40 is electrically separated for each divided region DI. That is, the storage capacitor voltage Vcs applied to the storage capacitor electrode 40 can be controlled for each subarray SA.

A reflective film 41 is provided on the storage capacitor electrode 40 . The reflective film 41 is made of, for example, aluminum (Al), silver (Ag), or an alloy containing one or more of these. The reflective film 41 has an opening 41A for each pixel PX. The reflective film 41 is configured to surround the pixel PX. The reflective film 41 is configured to cover the semiconductor layer 35. Thereby, the TFT 17 is shielded from light by the reflective film 41. Further, the reflective film 41 is configured to cover the scanning line GL and the signal line SL. The region of the pixel PX where the reflective film 41 is provided is the reflective region, and the region where the reflective film 41 is not provided (the region occupied by the opening 41A of the reflective film 41) is the transmissive region. The reflective area is an area where reflective display is performed using external light including sunlight, and the transmissive area is an area where transparent display is performed using light from a backlight.

In this embodiment, the planar shape of the reflective film 41 is the same as the planar shape of the storage capacitor electrode 40. However, the present invention is not limited to this, and the reflective film 41 and the storage capacitor electrode 40 may not have the same planar shape. For example, the area of the storage capacitor electrode 40 may be larger than the area of the reflective film 41. The reflective film 41, like the storage capacitor electrode 40, is electrically isolated for each divided region DI.

An insulating layer 42 is provided on the reflective film 41. The insulating layer 42 is made of a transparent insulating material, such as silicon nitride (SiN).

A pixel electrode 43 is provided on the insulating layer 42 . The pixel electrode 43 is made of a transparent electrode, for example made of ITO. The pixel electrode 43 is provided over the entire area defined as a pixel. Pixel PX corresponds to the area occupied by pixel electrode 43.

The storage capacitor electrode 40 described above is configured to partially overlap the pixel electrode 43. A portion where the pixel electrode 43 and the storage capacitor electrode 40 overlap constitutes a storage capacitor.

A contact 44 connecting the pixel electrode 43 and the connection electrode 38 is provided in the insulating layers 39 and 42. The contact 44 is made of the same material as the pixel electrode 43.

An alignment film (not shown) for controlling the alignment of the liquid crystal layer 32 is provided on the pixel electrode 43.

Next, the configuration on the CF board 31 side will be explained.
A light shielding layer (also referred to as a black matrix or black mask) 45 is provided on the liquid crystal layer 32 side of the CF substrate 31. The black matrix 45 is arranged at the boundary of the pixel PX. The black matrix 45 is formed, for example, in a mesh shape so as to surround the pixel PX. The black matrix 45 has a function of blocking unnecessary light generated at the boundaries of the pixels PX and improving contrast.

A plurality of color filters are provided on the CF substrate 31 and the black matrix 45. The plurality of color filters (color members) include a plurality of red filters 46R, a plurality of green filters 46G, and a plurality of blue filters 46B. A typical color filter is composed of the three primary colors of light: red (R), green (G), and blue (B). A set of adjacent three colors R, G, and B is a unit of display (pixel), and a monochromatic portion of any one of R, G, and B in one pixel is the smallest unit called a subpixel (subpixel). It is a driving unit. A TFT and a pixel electrode are provided for each subpixel. In the description of this specification, a sub-pixel will be referred to as a pixel unless it is particularly necessary to distinguish between a pixel and a sub-pixel. As the color filter arrangement, any arrangement including a stripe arrangement, a mosaic arrangement, and a delta arrangement can be applied.

A common electrode 47 is provided on the color filters 46R, 46G, and 46B. The common electrode 47 is formed in a planar shape over the entire display area of the liquid crystal display device 1 . The common electrode 47 is made of a transparent electrode, for example made of ITO. A structure such as a protrusion may be formed on the common electrode 47 in order to control the orientation of the liquid crystal layer 32 when voltage is applied.

An alignment film (not shown) for controlling the alignment of the liquid crystal layer 32 is provided on the common electrode 47 .

Note that the liquid crystal display device 1 includes two polarizing plates (not shown) arranged to sandwich the TFT substrate 2 and the CF substrate 31. The configuration of the polarizing plate is appropriately set depending on the display mode (normally white or normally black) and liquid crystal orientation.

(Configuration of gate driver GD)
Next, the configuration of the gate driver GD will be explained. The gate driver GD is arranged in the gate driver arrangement area GA described above. The gate driver placement area GA includes gate driver placement areas GA1 and GA2 shown in FIG. 10.

In the gate driver arrangement area GA1, a wiring AnL extending in the X direction and a wiring BneL having a zigzag shape and extending in the X direction are provided on the TFT substrate 2. The wiring BneL constitutes a node Bne.

First, the configuration of transistor M7e will be explained. A first gate electrode 50 connected to the wiring AnL is provided on the TFT substrate 2. A semiconductor layer 51 is provided above the first gate electrode 50 with the gate insulating film 34 interposed therebetween. In FIG. 10, the semiconductor layer 51 is hatched. The semiconductor layer 51 is made of, for example, amorphous silicon. A source electrode 52 and a drain electrode 53 are provided on the semiconductor layer 51. In the example of FIG. 10, the source electrode 52 is composed of two electrodes sandwiching a drain electrode 53.

A power supply line VglL_1 that crosses the pixel PX in the Y direction is provided on the gate insulating film 34. The source electrode 52 is connected to the power supply line VglL_1. Drain electrode 53 is connected to wiring BneL via contact 54.

A storage capacitor electrode 40 is provided above the semiconductor layer 51 with an insulating layer 39 interposed therebetween. The storage capacitor electrode 40 also serves as the second gate electrode of the transistor M7e. Specifically, the storage capacitor electrode 40 includes an electrode portion that covers the semiconductor layer 51, and this electrode portion substantially functions as a second gate electrode. In this way, transistor M7e is configured with a dual gate type TFT.

A reflective film 41 is provided on the storage capacitor electrode 40 . The reflective film 41 is provided over the entire gate driver arrangement areas GA1 and GA2. That is, the TFT included in the gate driver GD is shielded from light by the reflective film 41.

Next, the configuration of transistor M6e will be explained. A first gate electrode 55 connected to the wiring BneL is provided on the TFT substrate 2. A semiconductor layer 56 is provided above the first gate electrode 55 with the gate insulating film 34 interposed therebetween. In FIG. 10, the semiconductor layer 56 is hatched. The semiconductor layer 56 is made of, for example, amorphous silicon. A source electrode 57 and a drain electrode 58 are provided on the semiconductor layer 56. In the example of FIG. 10, the source electrode 57 is composed of two electrodes sandwiching a drain electrode 58. Source electrode 57 is connected to power supply line VglL_1. Drain electrode 58 is connected to wiring AnL via contact 59.

A storage capacitor electrode 40 is provided above the semiconductor layer 56 with an insulating layer 39 interposed therebetween. The storage capacitor electrode 40 also serves as the second gate electrode of the transistor M6e. Specifically, the storage capacitor electrode 40 includes an electrode portion that covers the semiconductor layer 56, and this electrode portion substantially functions as a second gate electrode. In this way, transistor M6e is configured as a dual-gate TFT.

Next, an example of other wiring provided in the gate driver arrangement area GA will be described.
In the gate driver arrangement area GA2, a power line VglL_2 extending in the X direction is provided on the TFT substrate 2. A plurality of power lines VglL_1 extending in the Y direction are connected to a power line VglL_2 via a plurality of contacts 60.

A power supply line VglL_3 is provided on the gate insulating film 34, crossing the gate driver arrangement areas GA1 and GA2 in the Y direction. Power line VglL_3 is connected to power line VglL_2 via contact 60.

In the gate driver arrangement area GA2, a gate wiring 61 extending in the X direction is provided on the TFT substrate 2. A wiring 63 is provided on the gate insulating film 34 to cross the pixel PX in the Y direction. The wiring 63 is connected to the gate wiring 61 via the contact 62.

In the gate driver arrangement area GA1, a gate wiring 65 extending in the X direction is provided on the TFT substrate 2. The wiring 63 is connected to a gate wiring 65 via a contact 64.

[1-1-6] Configuration of storage capacitor electrode 40 Next, the configuration of the storage capacitor electrode 40 will be described.

FIG. 16 is a diagram illustrating the configuration of the storage capacitor electrode 40. In the following, a case where the display area 4 is composed of nine (=3×3) divided areas DI_(1,1) to DI_(3,3) will be described as an example.

A plurality of scanning lines GL1, GL2, GL3, . . . are arranged in each of the divided regions DI_(1,1) to DI_(1,3) in the first row. A plurality of scanning lines GLp, GL(p+1), GL3(p+2), . . . are arranged in each of the second row divided regions DI_(2,1) to DI_(2,3). A plurality of scanning lines GLq, GL(q+1), GL3(q+2), . . . are arranged in each of the third row divided regions DI_(3,1) to DI_(3,3).

The storage capacitor electrode 40 is composed of nine storage capacitor electrodes 40_(1,1) to 40_(3,3). The storage capacitor electrodes 40_(1,1) to 40_(3,3) are arranged in the divided regions DI_(1,1) to DI_(3,3), respectively. The storage capacitor electrodes 40_(1,1) to 40_(3,3) are electrically isolated from each other. Note that in this embodiment, the reflective film 41 is electrically isolated for each divided region DI, similarly to the storage capacitor electrode 40. Thereby, the plurality of storage capacitor electrodes 40 can be electrically isolated.

The control circuit 15 can individually control the voltage of the storage capacitor electrodes 40_(1,1) to 40_(3,3). Further, the control circuit 15 can individually control the storage capacitor voltage Vcs applied to the storage capacitor electrodes 40_(1,1) to 40_(3,3). Thereby, the control circuit 15 can control the voltage of the second gate electrode of the dual gate TFT for each divided region DI.

[1-2] Wiring of multiple divided regions DI Next, wiring of multiple divided regions DI will be explained.

FIG. 17 is a diagram illustrating wiring of a plurality of divided regions DI. In the following, a case where the display area 4 is composed of nine (=3×3) divided areas DI_(1,1) to DI_(3,3) will be described as an example. In the following description, the wiring for supplying the voltage Vgl, frame signal Frame_e, clear signal CLR, start signal ST, clock signal ClkA, and clock signal ClkB will be referred to as the Vgl line, Frame_e line, Frame_o line, CLR line, They are called the ST line, ClkA line, and ClkB line.

Wiring to the plurality of divided regions DI is performed as follows.
- The gate driver GD is arranged for each divided region DI.
- Wire only the Vgl line for the power supply line.
- The Frame_e line and Frame_o line are wired as common signals for the entire screen.
- The CLR line is wired for each divided region DI.
- The ST line, ClkA line, and ClkB line are wired for each divided area DI in the scanning line direction (X direction).

The start signal ST is composed of three start signals ST1 to ST3. Start signals ST1 to ST3 are supplied using three lines ST1 to ST3, respectively.

Clock signal ClkA is composed of three clock signals ClkA1 to ClkA3. Clock signals ClkA1 to ClkA3 are supplied using three ClkA1 lines to ClkA3 lines, respectively.

Clock signal ClkB is composed of three clock signals ClkB1 to ClkB3. Clock signals ClkB1 to ClkB3 are supplied using three ClkB1 lines to ClkB3 lines, respectively.

The clear signal CLR is composed of nine clear signals CLR11 to CLR33. Clear signals CLR11 to CLR33 are supplied using nine CLR11 lines to CLR33 lines.

The start signal ST1 is input to the first row divided areas DI_(1,1), DI_(1,2), and DI_(1,3). The start signal ST2 is input to the divided areas DI_(2,1), DI_(2,2), and DI_(2,3) in the second row. The start signal ST3 is input to the third row divided areas DI_(3,1), DI_(3,2), and DI_(3,3). Start control of the nine divided areas DI_(1,1) to DI_(3,3) can be performed on a line-by-row basis.

Clock signals ClkA1 and ClkB1 are input to the first row divided areas DI_(1,1), DI_(1,2), and DI_(1,3). The clock signals ClkA2 and ClkB2 are input to the divided regions DI_(2,1), DI_(2,2), and DI_(2,3) in the second row. Clock signals ClkA3 and ClkB3 are input to the third row divided areas DI_(3,1), DI_(3,2), and DI_(3,3). The nine divided areas DI_(1,1) to DI_(3,3) can be clock-controlled on a row-by-row basis.

The nine clear signals CLR11 to CLR33 are input to the nine divided areas DI_(1,1) to DI_(3,3), respectively. Nine divided areas DI_(1,1) to DI_(3,3) use nine clear signals CLR11 to CLR33 to individually stop scanning and prevent data from being rewritten (display ) is possible.

The frame signal Frame_e is input to all divided areas DI. The frame signal Frame_o is input to all divided areas DI. The Vgl line is wired to all divided regions DI.

[1-3] Example of display area 4 Next, an example of display area 4 will be described. FIG. 18 is a schematic diagram illustrating an example of the display area 4. Let m be the row number of the divided area DI, the column number n of the divided area DI, and the scanning line number i within the divided area DI.

The display area 4 has, for example, (480×640) pixels. The display area 4 has nine divided areas DI_(1,1) to DI_(3,3).

The number of scanning lines in each divided area DI is 160. The number of columns of the first column of divided regions DI is 213. The number of columns of the second column of divided regions DI is 214. The number of columns of the third column of divided regions DI is 213. The number of columns in the divided area DI corresponds to the number of signal lines SL.

[1-4] Operation The operation of the liquid crystal display device 1 configured as described above will be explained.

[1-4-1] Characteristics of dual-gate TFT The characteristics of dual-gate TFT will be explained. In this embodiment, the TFT 17 included in the pixel PX and the TFT configuring the gate driver GD are dual gate type TFTs.

FIG. 19 is a graph illustrating the characteristics of a dual-gate TFT. The vertical axis in FIG. 19 is the drain current Id (A) of the dual-gate TFT, and the horizontal axis is the gate voltage (also referred to as first gate voltage) Vgs (V) of the first gate electrode. Gate voltage means the voltage between the gate and the source. The conditions in FIG. 19 are drain voltage Vd=1V and W/L=10. Drain voltage means the voltage between the drain and source. W/L is the ratio of channel width W to channel length L.

A storage capacitance voltage Vcs is applied to the second gate electrode. FIG. 19 shows graphs in which the storage capacitance voltage Vcs is changed to -5V, -3V, -2V, 0V, 1V, and 2V.

As can be understood from FIG. 19, the characteristics of the dual gate TFT can be changed by changing the voltage of the second gate electrode. Moreover, as the voltage of the second gate electrode becomes higher, the drain current Id becomes larger, that is, the driving ability becomes higher.

FIG. 20 is a graph illustrating the characteristics of a dual gate TFT. The vertical axis in FIG. 20 is the drain current Id (A) of the dual-gate TFT, and the horizontal axis is the gate voltage (also referred to as second gate voltage) (V) of the second gate electrode. The conditions in FIG. 20 are that the gate voltage Vgs of the first gate electrode is 20V, and the drain voltage Vd is 1V.

As can be understood from FIG. 20, as the voltage of the second gate electrode becomes higher, the drain current Id becomes larger, that is, the driving ability becomes higher.

In this embodiment, the first gate electrode of the dual-gate TFT is used to turn the TFT on and off, and the second gate electrode is used to adjust the characteristics of the TFT. In this embodiment, the storage capacitor electrode 40 used as the second gate electrode is electrically isolated for each divided region DI. That is, the storage capacitor voltage Vcs applied to the storage capacitor electrode 40 can be controlled for each divided region DI.

By using a structure in which the voltage of the second gate electrode can be controlled for each divided region DI, when performing a display operation, the second gate voltage is increased to increase the driving ability of the TFT. Furthermore, when stopping scanning, the second gate voltage is lowered to lower the current Iss. The current Iss is a drain current when the gate voltage Vgs=0V. This suppresses leakage current of the TFT.

Further, when a negative bias is applied to the second gate electrode, the fall behavior of the first gate voltage changes significantly, so it is also possible to control the feed-through voltage of the pixel TFT. That is, the second gate voltage can also be used to adjust the display characteristics of the liquid crystal display device.

FIG. 21 is a diagram illustrating the falling behavior of the voltage when the scanning line GL is selected. FIG. 22 is a graph explaining the falling behavior of the voltage when the scanning line GL is selected. “R” and “C” shown in each of the scanning line GL and signal line SL represent the resistance and capacitance of the wiring.

When the scanning line GL becomes high level (voltage Vgh), the TFT 17 is turned on and the drain current Id flows. When the voltage of the scanning line GL falls from the voltage Vgh to the voltage Vgl, potential fluctuation occurs at the pixel electrode via the parasitic capacitance Cgs between the first gate electrode of the TFT 17 and the pixel electrode. Assuming that the voltage of the signal line SL is Vlcd, the TFT 17 is in an on state until the first gate voltage reaches Vlcd, so a drain current Id flows according to the potential difference due to the parasitic capacitance Cgs. Finally, a voltage smaller than Vlcd by ΔV is applied to the pixel electrode.

The time required for the voltage of the scanning line GL to fall from the voltage Vgh to the voltage Vgl is assumed to be Δt. ΔV is expressed by the following formula (1).

From the above description, it can be seen that a small potential difference between the first gate voltage Vgs and the drain voltage Vd determines the voltage written to the pixel electrode. In this embodiment, since the storage capacitance voltage Vcs can be controlled for each divided region DI, it is possible to control the voltages written to the pixel electrodes in the plurality of divided regions DI to be approximately the same. Thereby, differences in display (for example, differences in brightness) at the boundaries of the divided regions DI can be reduced.

[1-4-2] Scanning operation of display area 4 First, the scanning operation of one divided area DI will be explained. FIG. 23 is a timing diagram illustrating the scanning operation of the divided area DI.

The control circuit 15 receives a vertical synchronization signal Vsync from the outside. The period from when the vertical synchronizing signal Vsync once becomes low level until it becomes low level again (or the period during which the vertical synchronizing signal Vsync is high level) is one frame. One frame is a period in which all scanning lines included in the sub-array SA are scanned once, and is also a period in which one image is displayed in the divided area DI.

Clock signals ClkAm, ClkBm, a start signal STm, and a clear signal CLRmn are input to any divided region DI_(m, n).

At time t1, the vertical synchronization signal Vsync transitions from low level to high level. At time t1, the control circuit 15 sets the start signal STm to a high level. In response to the start signal STm, the gate driver GD_(m,n) starts a scan operation.

At time t2, the control circuit 15 inputs the clock signals ClkAm and ClkBm to the divided area DI_(m, n). Clock signal ClkAm and clock signal ClkBm have a complementary phase relationship. In response to the clock signals ClkAm and ClkBm, the gate driver GD_(m,n) executes a scanning operation, that is, sequentially sets the plurality of scanning lines GL to a high level.

At time t3, the last scanning line GLi transitions from high level to low level. At time t3, the control circuit 15 sets the clear signal CLRmn to a high level. As a result, the shift register SR of the gate driver GD_(m,n) is cleared, that is, the output of the shift register SR becomes low level. In this way, the data in the divided area DI_(m, n) is rewritten.

Furthermore, the control circuit 15 transitions the storage capacitor voltage Vcs applied to the storage capacitor electrode 40_(m, n) from the low level Vcs_Lo to the high level Vcs_Hi in the divided region DI_(m, n) in which the scanning operation is performed. Specifically, at time t2 (the timing at which scanning of the divided area DI_(m, n) is started), the control circuit 15 lowers the storage capacitor voltage Vcs applied to the storage capacitor electrode 40_(m, n). Transition from level Vcs_Lo to high level Vcs_Hi. Low level Vcs_Lo is a negative voltage lower than ground voltage GND, and high level Vcs_Hi is a positive voltage higher than ground voltage GND. At time t4 (timing at which scanning of the divided area DI_(m, n) ends), the control circuit 15 changes the storage capacitor voltage Vcs applied to the storage capacitor electrode 40_(m, n) from the high level Vcs_Hi to the low level Vcs_Lo. Transition to.

A high level Vcs_Hi is applied to the second gate electrodes of the plurality of dual-gate TFTs included in the divided region DI_(m, n). This improves the driving ability of the dual gate TFT. The control circuit 15 can optimally set the low level Vcs_Lo and high level Vcs_Hi of the storage capacitance voltage Vcs according to the characteristics of the dual gate TFT. Furthermore, the control circuit 15 can optimally set the low level Vcs_Lo and high level Vcs_Hi of the storage capacitance voltage Vcs for each divided region DI.

Next, the scanning stop operation for one divided area DI will be explained. FIG. 24 is a timing diagram illustrating the scanning stop operation of the divided area DI. FIG. 24 shows the operation of the divided areas in which data is not rewritten among the divided areas in the same row to which the start signal STm is input.

At time t1, the vertical synchronization signal Vsync transitions from low level to high level. At time t1, the control circuit 15 sets the start signal STm to a high level.

At time t2, the control circuit 15 changes the start signal STm from high level to low level. At time t2, the control circuit 15 sets the clear signal CLRmn to a high level. That is, the control circuit 15 inputs the clear signal CLRmn immediately after the start signal STm. Thereby, the start signal STm can be substantially invalidated. After that, no pulse is input to the scanning line GL. In this case, the divided area DI_(m, n) is not scanned and its display is maintained.

At time t3, the control circuit 15 changes the clear signal CLRmn from high level to low level. Furthermore, at time t3, the control circuit 15 inputs the clock signals ClkAm and ClkBm to the divided area DI_(m, n).

Further, the control circuit 15 transitions the storage capacitor voltage Vcs applied to the storage capacitor electrode 40_(m, n) from the high level Vcs_Hi to the low level Vcs_Lo in the divided region DI_(m, n) in which the scan stop operation is performed. . Specifically, at time t4 (timing at which scanning of another divided area in which the scanning operation is performed), the control circuit 15 changes the storage capacitance voltage Vcs applied to the storage capacitor electrode 40_(m, n) to Transition from high level Vcs_Hi to low level Vcs_Lo. At time t5 (timing at which scanning of other divided regions ends), the control circuit 15 transitions the storage capacitor voltage Vcs applied to the storage capacitor electrode 40_(m, n) from the low level Vcs_Lo to the high level Vcs_Hi.

A low level Vcs_Lo is applied to the second gate electrodes of the plurality of dual-gate TFTs included in the divided region DI_(m, n). As a result, the leakage current of the dual-gate TFT can be reduced, and the holding capacity of the dual-gate TFT can be improved.

[1-4-3] Driving Pattern Next, the driving pattern of the liquid crystal display device 1 will be described. Below, as an example, the operation of nine divided areas DI_(1,1) to DI_(3,3) where m=3 and n=3 will be described.

FIG. 25 is a schematic diagram illustrating the drive pattern 1 of the liquid crystal display device 1. The control circuit 15 enables the start signal ST1 (high level) in the first frame. The control circuit 15 enables the clear signals CLR11, CLR12, and CLR13 (high level) at the time when the first frame ends. As a result, the scanning operation of the divided areas DI_(1,1) to DI_(1,3) in the first row is executed.

The control circuit 15 enables the start signal ST2 in the second frame following the first frame. The control circuit 15 enables the clear signals CLR21, CLR22, and CLR23 at the time when the second frame ends. As a result, the scanning operation of the divided areas DI_(2,1) to DI_(2,3) in the second row is executed.

The control circuit 15 enables the start signal ST3 in the third frame following the second frame. The control circuit 15 enables the clear signals CLR31, CLR32, and CLR33 at the time when the third frame ends. As a result, the scanning operation of the divided areas DI_(3,1) to DI_(3,3) in the third row is executed.

FIG. 26 is a schematic diagram illustrating the drive pattern 2 of the liquid crystal display device 1. The control circuit 15 enables the start signal ST1 in the first frame. The control circuit 15 enables the clear signals CLR12 and CLR13 immediately after the start signal ST1. As a result, scanning of the divided areas DI_(1, 2) and DI_(1, 3) is stopped. The control circuit 15 enables the clear signal CLR11 at the time when the first frame ends. In this way, the scanning operation of the divided area DI_(1,1) is executed, and the data of the divided area DI_(1,1) is rewritten. Furthermore, the divided areas DI_(1, 2) and DI_(1, 3) hold the display.

The control circuit 15 enables the start signal ST2 in the second frame following the first frame. The control circuit 15 enables the clear signals CLR22 and CLR23 immediately after the start signal ST2. As a result, scanning of the divided areas DI_(2, 2) and DI_(2, 3) is stopped. The control circuit 15 enables the clear signal CLR21 at the time when the second frame ends. In this way, the scanning operation of the divided area DI_(2,1) is executed, and the data of the divided area DI_(2,1) is rewritten. Furthermore, the divided areas DI_(2, 2) and DI_(2, 3) hold the display.

Similarly, the start signal STm is enabled, and any divided area DI included in the m rows executes the scanning operation. Further, the clear signal CLR corresponding to the remaining divided area DI included in the m rows is enabled, and scanning of the remaining divided area DI is stopped.

As a result, the first to ninth frames are sequentially driven, and the data in the divided areas DI_(1,1) to DI_(3,3) are rewritten.

Note that FIGS. 25 and 26 show an example in which data in all divided areas DI is rewritten. By controlling the start signal ST and the clear signal CLR, it is also possible to display an image in the display area 4 by skipping scanning of any divided area DI.

[1-4-4] Operation of shift register SR Next, the operation of shift register SR will be explained. FIG. 27 is a timing diagram illustrating the operation of shift register SR. As shown in FIG. 7, frame signals Frame_o and Frame_e are input to the shift register SR.

The frame signals Frame_o and Frame_e are alternately enabled (high level) for each arbitrary frame, with the minimum unit being one frame. The two inverter circuits 21o and 21e operate alternately according to the frame signals Frame_o and Frame_e. The control circuit 15 switches the states of the frame signals Frame_o and Frame_e while the vertical synchronization signal Vsync is at a low level.

As an example, assume that the frame signal Frame_o is enabled (high level). The frame signal Frame_e is at low level. When the frame signal Frame_o becomes high level, the transistor M1o of the inverter circuit 21o is turned on, and the inverter circuit 21o is enabled. Transistor M1e of inverter circuit 21e is turned off, and inverter circuit 21e is disabled.

After the frame signal Frame_o becomes high level, the start signal ST becomes high level. As a result, the input signal VIN of the first stage core circuit RG1 becomes high level. Then, the transistor M2 of the input section 20 is turned on, and the node An becomes high level.

When the node An becomes high level, the transistor M7o of the inverter circuit 21o is turned on, and the node Bno becomes low level. That is, the inverter circuit 21o holds the inverted data of the node An at the node Bno. As a result, the transistor M4o of the pull-down section 23 is turned off, and the pull-down operation of the node Qn is stopped.

Furthermore, when the node An becomes high level, the transistor M3 of the output section 22 is turned on. Subsequently, the clock signal ClkA becomes high level. Then, the scanning line GL1 becomes high level.

The second stage core circuit RG2 receives an output signal from the previous stage core circuit RG1 as an input signal VIN. Subsequently, the clock signal ClkB becomes high level. Then, the core circuit RG2 sets the scanning line GL2 to a high level.

The first stage core circuit RG1 receives the output signal of the second stage core circuit RG2 as a reset signal RST. The reset signal RST is input to the gate of the transistor M5 of the input section 20. Then, the transistor M5 is turned on and the node An becomes low level.

When the node An becomes low level, the transistor M7o of the inverter circuit 21o is turned off, and the node Bno becomes high level. That is, the inverter circuit 21o holds the inverted data of the node An at the node Bno. When node Bno becomes high level, transistor M6o is turned on and node An is held at low level. As a result, the transistor M4o of the pull-down section 23 is turned on, and the node Qn becomes low level.

Further, when the node An becomes low level, the transistor M3 of the output section 22 is turned off. As a result, the scanning line GL1 becomes low level.

Note that, as a detailed design, adjacent core circuits RG are prevented from operating at the same time. Therefore, the edges of the clock signal ClkA and the clock signal ClkB are spaced apart so that the pulses of the clock signal ClkA and the clock signal ClkB do not overlap.

Similarly, the core circuits RG3 to RGi sequentially output pulse signals.

After the final stage core circuit RGi outputs the pulse signal, the clear signal CLR is set to high level. When the clear signal CLR becomes high level, the transistors M8 and M9 of the clear section 24 are turned on. Then, the node Qn and the node An become low level. Thereby, the core circuit RGi sets the scanning line GLi to a low level.

After that, the frame signal Frame_e is set to high level, and the frame signal Frame_o is set to low level. Then, the inverter circuit 21e of the core circuit RG is enabled. Thereafter, the scanning operation by the shift register SR is repeated.

By such an operation, it is possible to eliminate a transistor to which a positive bias is continuously applied in the core circuit RG. Thereby, it is possible to suppress deterioration of the characteristics of the transistors forming the core circuit RG. In particular, when a TFT is used as a transistor, if a positive bias continues to be applied, the threshold voltage Vth will shift. However, in this embodiment, deterioration of the TFT characteristics can be suppressed.

[1-4-5] Operation of Core Circuit RG Next, the operation of the core circuit RG included in the shift register SR will be described. The selection period is a period during which a scanning line is selected, and a period during which the scanning line outputs a pulse signal. The non-selection period is a period other than the selection period, and is a period in which the scanning line does not output a pulse signal.

FIG. 28 is a schematic diagram illustrating the inverter operation of the core circuit RG during the selection period. As an example, it is assumed that the frame signal Frame_o is enabled (high level ("Hi" in FIG. 28)) and the inverter circuit 21o performs an inverter operation. The frame signal Frame_e is at a low level (“Lo” in FIG. 28).

A high-level (“ON” in FIG. 28) input signal VIN is input from the previous stage core circuit RG to the gate of the transistor M2. Therefore, the transistor M2 is turned on, and the node An becomes high level ("Hi" in FIG. 28).

A high-level frame signal Frame_o is input to the gate of the transistor M1o. Therefore, transistor M1o is turned on, and inverter circuit 21o is enabled.

Since the node An is at a high level, the transistor M7o is turned on and the node Bno is pulled down. The arrows in FIG. 28 indicate current.

Furthermore, the transistor M7e of the inverter circuit 21e can also be operated for the inverter operation during the selection period. That is, since the node An is at a high level, the transistors M1b and M7e are turned on. Therefore, node Bno is also pulled down through the path of transistor M1b, node Bne, and transistor M7e. Thereby, node Bno can be reliably set to a low level.

The driving ability of transistor M6o is set larger than that of transistor M7o. During the non-selection period, the node An is pulled down by the transistor M6o, and the node An can be reliably set to a low level.

As conditions for realizing the above inverter operation, transistors M6 and M7 are set to satisfy the following conditions. Transistor M6 means transistors M6o and M6e, respectively, and transistor M7 means transistors M7o and M7e, respectively. The channel widths of transistors M6 and M7 are expressed as W6 and W7, respectively. Channel width is also called gate width.

W7≦W6≦2×W7
By setting "W6≦2×W7", the combined driving ability of transistors M7o and M7e becomes larger than the driving ability of transistor M6o (or transistor M6e). Thereby, the node Bno can be reliably set to a low level during the selection period.

By setting "W7≦W6", the driving ability of the transistor M6 becomes greater than the driving ability of the transistor M7. Thereby, the node An can be reliably set to a low level during the non-selection period.

We will focus on the inverter circuit included in the core circuit RG near the final stage. The potential of the node Bne of the disabled inverter circuit (for example, the inverter circuit 21e) among the inverter circuits 21o and 21e decreases due to the leakage current of the transistor M1e. Therefore, in the core circuit RG near the final stage, by turning on the transistor M1b during the selection period, the enabled node Bno becomes conductive with the node Bne, so that it can be set to a low level more steadily. It has become.

[1-5] Effects of the first embodiment According to the first embodiment, the transistors forming the gate driver GD can be covered with the reflective film 41. Thereby, the operational performance of the gate driver GD can be improved. In turn, the display characteristics of the liquid crystal display device 1 can be improved.

Further, the transistor included in the gate driver GD is configured as a dual gate TFT having a first gate electrode and a second gate electrode. By controlling the voltage applied to the second gate electrode (storage capacitance voltage Vcs), the driving ability of the dual gate TFT can be improved and leakage current can be reduced. Thereby, the operational performance of the gate driver GD can be improved.

Further, the transistor included in the pixel PX is configured as a dual-gate TFT having a first gate electrode and a second gate electrode. By controlling the voltage applied to the second gate electrode (storage capacitance voltage Vcs), the driving ability of the dual gate TFT can be improved and leakage current can be reduced. Thereby, the characteristics of the pixel PX can be improved.

Further, it is possible to realize a transflective liquid crystal display device in which each pixel includes a reflective area and a transmissive area. Thereby, the image displayed on the screen of the liquid crystal display device 1 can be visually recognized regardless of the illuminance of the environment in which the liquid crystal display device 1 is used.

Furthermore, the gate driver placement area GA where the gate driver GD is placed is covered with a reflective film 41. Thereby, the brightness of reflective display can be improved.

Further, the display area 4 is configured by being divided into a plurality of divided areas DI arranged in a matrix. A subarray SA and a gate driver GD are arranged in each of the plurality of divided regions DI. Thereby, the liquid crystal display device 1 that can have a narrow frame can be realized. Further, the display area 4 can be driven in divisions for each divided area DI. Furthermore, scanning can be performed freely for each divided area DI.

Furthermore, by scanning each divided area DI, the frame frequency can be lowered compared to scanning the entire screen as one frame. This reduces power consumption due to charging and discharging using the clock signal. Furthermore, since the write time for writing data (driving voltage) to the pixel can be extended, the current for driving the TFT included in the pixel can be reduced, and the size of the TFT can also be reduced. As a result, it is possible to reduce the current supplied to the scanning line GL and signal line SL, thereby reducing power consumption.

Further, clock signals ClkA and ClkB can be driven by time division for each divided region DI. This makes it possible to reduce power consumption compared to the case where a clock signal is supplied to the entire screen.

Further, each core circuit RG includes two inverter circuits 21o and 21e, and the inverter circuits 21o and 21e are enabled alternately according to the frame signals Frame_o and Frame_e. Therefore, it is possible to prevent voltage from being continuously applied to the transistors forming the shift register SR. Thereby, a gate driver GD with high breakdown voltage can be realized.

[2] Second Embodiment The second embodiment is another example regarding the wiring of the display area 4. In the second embodiment, different clock signals are wired for each column of a plurality of divided regions DI.

[2-1] Wiring of multiple divided regions DI FIG. 29 is a diagram illustrating wiring of multiple divided regions DI according to the second embodiment. In the following, a case where the display area 4 is composed of nine (=3×3) divided areas DI_(1,1) to DI_(3,3) will be described as an example.

Wiring to the plurality of divided regions DI is performed as follows.
- The gate driver GD is arranged for each divided region DI.
- Wire only the Vgl line for the power supply line.
- The Frame_e line and Frame_o line are wired as common signals for the entire screen.
- The CLR line is wired for each divided area DI.
- The ST line is wired for each divided area DI in the scanning line direction (X direction).
- The ClkA line and the ClkB line are wired for each divided area DI in the signal line direction (Y direction).

The start signal ST is composed of three start signals ST1 to ST3. Start signals ST1 to ST3 are supplied using three lines ST1 to ST3, respectively.

Clock signal ClkA is composed of three clock signals ClkA1 to ClkA3. Clock signals ClkA1 to ClkA3 are supplied using three ClkA1 lines to ClkA3 lines, respectively.

Clock signal ClkB is composed of three clock signals ClkB1 to ClkB3. Clock signals ClkB1 to ClkB3 are supplied using three ClkB1 lines to ClkB3 lines, respectively.

The clear signal CLR is composed of nine clear signals CLR11 to CLR33. Clear signals CLR11 to CLR33 are supplied using nine CLR11 lines to CLR33 lines.

The start signal ST1 is input to the first row divided areas DI_(1,1), DI_(1,2), and DI_(1,3). The start signal ST2 is input to the divided areas DI_(2,1), DI_(2,2), and DI_(2,3) in the second row. The start signal ST3 is input to the third row divided areas DI_(3,1), DI_(3,2), and DI_(3,3). Start control of the nine divided areas DI_(1,1) to DI_(3,3) can be performed on a line-by-row basis.

Clock signals ClkA1 and ClkB1 are input to the first column divided regions DI_(1,1), DI_(2,1), and DI_(3,1). The clock signals ClkA2 and ClkB2 are input to the second column divided regions DI_(1,2), DI_(2,2), and DI_(3,2). Clock signals ClkA3 and ClkB3 are input to the third column divided regions DI_(1,3), DI_(2,3), and DI_(3,3). The nine divided areas DI_(1,1) to DI_(3,3) can be clock-controlled on a column-by-column basis.

The nine clear signals CLR11 to CLR33 are input to the nine divided areas DI_(1,1) to DI_(3,3), respectively. Nine divided areas DI_(1,1) to DI_(3,3) use nine clear signals CLR11 to CLR33 to individually stop scanning and prevent data from being rewritten (display ) is possible.

The frame signal Frame_e is input to all divided areas DI. The frame signal Frame_o is input to all divided areas DI. The Vgl line is wired to all divided regions DI.

[2-2] Scanning operation of display area 4 Next, the scanning operation of one divided area DI will be described. FIG. 30 is a timing diagram illustrating the scanning operation of the divided area DI.

The control circuit 15 receives a vertical synchronization signal Vsync from the outside. Clock signals ClkAm, ClkBm, a start signal STm, and a clear signal CLRmn are input to any divided region DI_(m, n). The scanning operation of the divided area DI in the second embodiment is the same as that in FIG. 23 of the first embodiment.

Next, the scanning stop operation for one divided area DI will be explained. FIG. 31 is a timing diagram illustrating the scanning stop operation of the divided area DI. FIG. 31 shows the operation of the divided areas in which data is not rewritten among the divided areas in the same row to which the start signal STm is input.

At time t1, the vertical synchronization signal Vsync transitions from low level to high level. At time t1, the control circuit 15 sets the start signal STm to a high level.

At time t2, the control circuit 15 changes the start signal STm from high level to low level. At time t2, the control circuit 15 sets the clear signal CLRmn to a high level. That is, the control circuit 15 inputs the clear signal CLRmn immediately after the start signal STm. Thereby, the start signal STm can be substantially invalidated. After that, no pulse is input to the scanning line GL. In this case, the divided area DI_(m, n) is not scanned and its display is maintained.

At time t3, the control circuit 15 changes the clear signal CLRmn from high level to low level.

Divided regions DI adjacent in the row direction operate with different clock signals ClkA (and different clock signals ClkB). As shown in FIG. 31, no clock signal is input to a divided area where data is not rewritten among divided areas adjacent in the row direction.

Further, the control circuit 15 sets the storage capacitor voltage Vcs applied to the storage capacitor electrode 40_(m, n) to a low level Vcs_Lo in the divided region DI_(m, n) where the scan stop operation is performed. Specifically, after time t3 (after the clear signal CLRmn is input), the control circuit 15 sets the storage capacitor voltage Vcs applied to the storage capacitor electrode 40_(m, n) to the low level Vcs_Lo. At time t4 (timing at which scanning of other divided regions ends), the control circuit 15 changes the storage capacitor voltage Vcs applied to the storage capacitor electrode 40_(m, n) from the low level Vcs_Lo to the high level Vcs_Hi.

A low level Vcs_Lo is applied to the second gate electrodes of the plurality of dual-gate TFTs included in the divided region DI_(m, n). As a result, the leakage current of the dual-gate TFT can be reduced, and the holding capacity of the dual-gate TFT can be improved.

The driving pattern described in the first embodiment can also be executed in the liquid crystal display device 1 according to the second embodiment. The effects of the second embodiment are also the same as those of the first embodiment.

[3] Third Embodiment In the third embodiment, some of the plurality of divided areas obtained by dividing the display area 4 are configured as non-display areas in which no image is displayed.

FIG. 32 is a schematic diagram of the display area 4 according to the third embodiment. FIG. 32 shows, as an example, a case where the display area 4 includes nine divided areas.

The display area 4 includes one or more non-display areas ND. FIG. 32 shows, as an example, a case where the display area 4 includes three non-display areas ND. Pixels and gate drivers are not provided in the non-display area ND.

Display area 4 has six divided areas that can display images: DI_(2,1), DI_(3,1), DI_(1,2), DI_(3,2), DI_(1,3), DI_(2,3) is provided. A subarray SA and a gate driver GD are arranged in the divided region DI.

FIG. 33 is a schematic diagram illustrating the drive pattern 1 of the liquid crystal display device 1. In FIG. 33, for example, it is assumed that the wiring of the display area 4 in the first embodiment is included. No wiring (including scanning lines and signal lines) is provided in the non-display area ND.

The control circuit 15 enables the start signal ST1 (high level) in the first frame. The control circuit 15 enables the clear signals CLR12 and CLR13 (high level) at the time when the first frame ends. As a result, the scanning operation of the divided areas DI_(1, 2) and DI_(1, 3) in the first row is executed.

The control circuit 15 enables the start signal ST2 in the second frame following the first frame. The control circuit 15 enables the clear signals CLR21 and CLR23 at the time when the second frame ends. As a result, the scanning operation of the divided areas DI_(2, 1) and DI_(2, 3) in the second row is executed.

The control circuit 15 enables the start signal ST3 in the third frame following the second frame. The control circuit 15 enables the clear signals CLR31 and CLR32 at the time when the third frame ends. As a result, the scanning operation of the divided areas DI_(3,1) and DI_(3,2) in the third row is executed.

FIG. 34 is a schematic diagram illustrating the drive pattern 2 of the liquid crystal display device 1. In FIG. 34, for example, it is assumed that the wiring of the display area 4 in the second embodiment is included. No wiring (including scanning lines and signal lines) is provided in the non-display area ND.

The control circuit 15 enables the start signal ST2 in the first frame. The control circuit 15 enables the clear signal CLR23 immediately after the start signal ST2. As a result, scanning of the divided area DI_(2, 3) is stopped. The control circuit 15 enables the clear signal CLR21 at the time when the first frame ends. In this way, the scanning operation of the divided area DI_(2,1) is executed, and the data of the divided area DI_(2,1) is rewritten. Furthermore, the divided area DI_(2,3) holds the display.

The control circuit 15 enables the start signal ST3 in the second frame following the first frame. The control circuit 15 enables the clear signal CLR32 immediately after the start signal ST3. As a result, scanning of the divided area DI_(3,2) is stopped. The control circuit 15 enables the clear signal CLR31 at the time when the second frame ends. In this way, the scanning operation of the divided area DI_(3,1) is executed, and the data of the divided area DI_(3,1) is rewritten. Furthermore, the divided area DI_(3,2) holds the display.

Similarly, the start signal STm is enabled, and any divided area DI included in the m rows executes the scanning operation. Further, the clear signal CLR corresponding to the remaining divided area DI included in the m rows is enabled, and scanning of the remaining divided area DI is stopped.

As a result, the six divided areas DI_(2,1), DI_(3,1), DI_(1,2), DI_(3,2), DI_(1,3), DI_(2,3) are The data of the divided areas DI_(2,1), DI_(3,1), DI_(1,2), DI_(3,2), DI_(1,3), DI_(2,3) are sequentially driven. Can be rewritten.

The non-display area ND is, for example, always displayed in black. Furthermore, by arranging a color filter of a desired color in the non-display area ND, the non-display area ND may be displayed in a color other than black.

In the third embodiment, a plurality of scanning lines and gate drivers GD are arranged for each divided region DI. Therefore, even if the non-display area ND is provided between the divided areas DI in the column direction, all the divided areas DI can be scanned using the gate driver GD.

Furthermore, in the third embodiment, it is possible to realize an irregularly shaped display that is not rectangular. In addition, it is possible to optimally drive an irregularly shaped display.

Note that each of the above embodiments shows a configuration example in which the pixel array includes a plurality of subarrays, and a gate driver is arranged in each of the plurality of subarrays. However, the configuration is not limited to this example, and the pixel array does not need to be divided into a plurality of subarrays. That is, a liquid crystal display device may be configured with one pixel array and one gate driver. In the case of this modification, the signals for individually controlling the plurality of partial regions DI described in the embodiment are not required.

Furthermore, in each of the above embodiments, the case where all the transistors are composed of N-type transistors has been described. However, the present invention is not limited to this, and by inverting the polarities of the power supply voltage and the clock signal, it is also possible to configure all the transistors with P-type transistors.

Further, the shift register SR included in the gate driver GD is not limited to the configuration described in each of the above embodiments. It is also possible to use other types of shift registers that can sequentially output pulses to multiple scanning lines GL.

Further, in each of the above embodiments, a transflective liquid crystal display device is used as an example, but the invention is not limited to this, and the application may also be applied to a reflective liquid crystal display device that performs display using external light. It is possible. In a reflective liquid crystal display device, the entire pixel is covered with a reflective film.

Furthermore, in each of the above embodiments, a liquid crystal display device is used as an example of the display device. However, the present invention is not limited thereto, and can be applied to other display devices such as organic EL display devices.

Furthermore, each of the above embodiments has been described using a display device as an example. However, the present invention is not limited to this, and can also be applied to a sensor equipped with a shift register.

The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the invention at the implementation stage. Moreover, each embodiment may be implemented in combination as appropriate, and in that case, the combined effect can be obtained. Furthermore, the embodiments described above include various inventions, and various inventions can be extracted by combinations selected from the plurality of constituent features disclosed. For example, if a problem can be solved and an effect can be obtained even if some constituent features are deleted from all the constituent features shown in the embodiment, the configuration from which these constituent features are deleted can be extracted as an invention.

DESCRIPTION OF SYMBOLS 1...Liquid crystal display device, 2...TFT substrate, 3...Integrated circuit, 4...Display area, 10...Pixel array, 11...Gate driver group, 12...Source driver, 13...Common electrode driver, 14...Voltage generation circuit, 15 ... Control circuit, 16... Backlight, 17... Switching element, 20... Input section, 21... Register section, 21e... Inverter circuit, 21o... Inverter circuit, 22... Output section, 23... Pull-down section, 24... Clear section, 31 ...CF substrate, 32...Liquid crystal layer, 33...Gate electrode, 34...Gate insulating film, 35...Semiconductor layer, 36...Source electrode, 37...Drain electrode, 38...Connection electrode, 39...Insulating layer, 40...Storage capacitor electrode , 40A... opening, 41... reflective film, 41A... opening, 42... insulating layer, 43... pixel electrode, 44... contact, 45... black matrix, 46R, 46G, 46B... color filter, 47... common electrode, 50 ...gate electrode, 51...semiconductor layer, 52...source electrode, 53...drain electrode, 54...contact, 55...gate electrode, 56...semiconductor layer, 57...source electrode, 58...drain electrode, 59...contact, 60...contact , 61...gate wiring, 62...contact, 63...wiring, 64...contact, 65...gate wiring, GL...scanning line, SL...signal line, GD...gate driver, SR...shift register, RG...core circuit, GA... Gate driver placement area.

Claims (13)

a pixel array provided in a display area for displaying an image and having a plurality of pixels;
a plurality of scanning lines provided in the pixel array and extending in a first direction;
a gate driver provided in the display area, connected to the plurality of scanning lines, and including a plurality of first transistors;
a first reflective film covering the plurality of first transistors;
A display device comprising: The display device according to claim 1 , wherein each of the plurality of first transistors includes a first gate electrode and a second gate electrode. further comprising a first electrode covering the plurality of first transistors,
the first reflective film is provided on the first electrode,
The display device according to claim 2, wherein the first electrode functions as the second gate electrode of the first transistor. The first transistor includes a first semiconductor layer,
the first gate electrode of the first transistor is provided below the first semiconductor layer with an insulating film interposed therebetween;
The display device according to claim 3, wherein the second gate electrode of the first transistor is provided above the first semiconductor layer with an insulating film interposed therebetween. The display device according to claim 3 or 4, further comprising a control circuit that applies a voltage to the first electrode. The display device according to claim 5, wherein the control circuit applies a positive voltage to the first electrode during a scanning operation, and applies a negative voltage to the first electrode when stopping scanning. The pixel array includes a plurality of subarrays,
The gate driver includes a plurality of gate drivers respectively provided in the plurality of subarrays,
The display device according to any one of claims 3 to 6, wherein the first electrode is electrically isolated for each subarray. Each of the plurality of pixels includes a second transistor,
The display device according to claim 1 , wherein the second transistor is covered with a second reflective film. The display device according to claim 8, wherein the second transistor includes a first gate electrode and a second gate electrode. further comprising a second electrode covering the second transistor,
the second reflective film is provided on the second electrode,
The display device according to claim 9 , wherein the second electrode functions as the second gate electrode of the second transistor. The second transistor includes a second semiconductor layer,
the first gate electrode of the second transistor is provided below the second semiconductor layer with an insulating film interposed therebetween;
The display device according to claim 10, wherein the second gate electrode of the second transistor is provided above the second semiconductor layer with an insulating film interposed therebetween. The gate driver includes a shift register having a plurality of cascaded core circuits,
Each of the plurality of core circuits is
an input section that transfers an input signal corresponding to the output signal of the preceding core circuit to the first node;
a first inverter circuit that is enabled by a first frame signal and holds an inverted signal of the first node at a second node;
and a second inverter circuit that is enabled by a second frame signal that is complementary to the first frame signal and holds an inverted signal of the first node at a third node. Display device as described. The core circuit includes an output section,
The output section includes an output transistor and a capacitor,
The output transistor has a gate connected to the first node, a first terminal receiving a clock signal, and a second terminal connected to a scanning line,
The display device according to claim 12, wherein the capacitor has a first electrode connected to the first node and a second electrode connected to the scanning line.