KR20180102763A - Semiconductor device and semiconductor device package - Google Patents

Abstract

The present invention relates to a semiconductor device, a semiconductor device manufacturing method, and a semiconductor device package. According to an embodiment of the present invention, the semiconductor device comprises a light emitting structure, a first electrode, a second electrode, a first insulation reflective layer, a second insulation reflective layer, a first bonding pad, and a second bonding pad. The light emitting structure includes a first conductive semiconductor layer and a second conductive semiconductor layer. The first electrode is provided on the first conductive semiconductor layer, and is electrically connected to the first conductive semiconductor layer. The second electrode is provided on the second conductive semiconductor layer, and is electrically connected to the second conductive semiconductor layer. The first insulation reflective layer is arranged on the first electrode and the second electrode, and includes a first opening unit to expose an upper surface of the first electrode. The second insulation reflective layer is arranged on the first electrode and the second electrode to be separated from the first insulation reflective layer, and includes a second opening unit which exposes an upper surface of the second electrode. The first bonding pad is arranged on the first insulation reflective layer and is electrically connected to the first electrode through the first opening unit. The second bonding pad is arranged on the second insulation reflective layer to be separated from the first bonding pad, and is electrically connected to the second electrode through the second opening unit. When the semiconductor device is viewed in an upper direction, a sum of an area of the first bonding pad and an area of the second bonding pad is equal to or less than 70% of the total area of the upper surface of the semiconductor device on which the first bonding pad and the second bonding pad are arranged. The present invention is able to enhance light extraction efficiency and electrical characteristics.

Description

[0001] DESCRIPTION [0002] SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PACKAGE [

The embodiment relates to a semiconductor element and a method of manufacturing a semiconductor element, and a semiconductor element package.

Semiconductor devices including compounds such as GaN and AlGaN have many merits such as wide and easy bandgap energy, and can be used variously as light emitting devices, light receiving devices, and various diodes.

Particularly, a light emitting device such as a light emitting diode or a laser diode using a Group III-V or Group II-VI compound semiconductor material can be used for a variety of applications such as red, Blue and ultraviolet rays can be realized. In addition, a light emitting device such as a light emitting diode or a laser diode using a Group III-V or Group-VI-VI compound semiconductor material can realize a white light source having high efficiency by using a fluorescent material or combining colors. Such a light emitting device has advantages of low power consumption, semi-permanent lifetime, fast response speed, safety, and environment friendliness compared with conventional light sources such as fluorescent lamps and incandescent lamps.

In addition, when a light-receiving element such as a photodetector or a solar cell is manufactured using a Group III-V or Group-VI-VI compound semiconducting material, development of a device material absorbs light of various wavelength regions to generate a photocurrent , It is possible to use light in various wavelength ranges from the gamma ray to the radio wave region. Further, such a light receiving element has advantages of fast response speed, safety, environmental friendliness and easy control of element materials, and can be easily used for power control or microwave circuit or communication module.

Accordingly, the semiconductor device can be replaced with a transmission module of an optical communication means, a light emitting diode backlight replacing a cold cathode fluorescent lamp (CCFL) constituting a backlight of an LCD (Liquid Crystal Display) display device, White light emitting diode (LED) lighting devices, automotive headlights, traffic lights, and gas and fire sensors. In addition, semiconductor devices can be applied to high frequency application circuits, other power control devices, and communication modules.

The light emitting device can be provided as a pn junction diode having a characteristic in which electric energy is converted into light energy by using a group III-V element or a group II-VI element in the periodic table, Various wavelengths can be realized by adjusting the composition ratio.

For example, nitride semiconductors have received great interest in the development of optical devices and high power electronic devices due to their high thermal stability and wide bandgap energy. Particularly, a blue light emitting element, a green light emitting element, an ultraviolet (UV) light emitting element, and a red (RED) light emitting element using a nitride semiconductor are commercially available and widely used.

For example, in the case of an ultraviolet light emitting device, it is a light emitting diode that generates light distributed in a wavelength range of 200 nm to 400 nm. It is used for sterilizing and purifying in the wavelength band, short wavelength, Can be used.

 Ultraviolet rays can be divided into UV-A (315nm ~ 400nm), UV-B (280nm ~ 315nm) and UV-C (200nm ~ 280nm) in the long wavelength order. UV-A (315nm ~ 400nm) is applied in various fields such as UV curing for industrial use, curing of printing ink, exposure machine, discrimination of counterfeit, photocatalytic disinfection and special illumination (aquarium / ) Area is used for medical use, and UV-C (200nm ~ 280nm) area is applied to air purification, water purification, sterilization products and the like.

On the other hand, a semiconductor device capable of providing a high output has been requested, and a semiconductor device capable of increasing a power by applying a high power source has been studied.

In addition, studies are being made on a method of continuously increasing the light extraction efficiency of a semiconductor device in a semiconductor device package and improving the light intensity in a package stage. In addition, studies have been made on a method for improving the bonding strength between a package electrode and a semiconductor device in a semiconductor device package.

Embodiments can provide a semiconductor device, a semiconductor device manufacturing method, and a semiconductor device package that can improve light extraction efficiency and electrical characteristics.

The embodiment can provide a semiconductor element, a semiconductor element manufacturing method, and a semiconductor element package capable of improving bonding strength between a package electrode and a semiconductor element.

The embodiment can provide a semiconductor element, a semiconductor element manufacturing method, and a semiconductor element package which can prevent the current concentration phenomenon from occurring and improve the reliability.

A semiconductor device according to an embodiment includes a light emitting structure including a first conductive semiconductor layer and a second conductive semiconductor layer; A first electrode disposed on the first conductive semiconductor layer and electrically connected to the first conductive semiconductor layer; A second electrode disposed on the second conductive semiconductor layer and electrically connected to the second conductive semiconductor layer; A first insulating reflective layer disposed on the first electrode and the second electrode, the first insulating reflective layer including a first opening exposing an upper surface of the first electrode; A second insulating reflection layer disposed on the first electrode and the second electrode so as to be spaced apart from the first insulating reflection layer and including a second opening exposing an upper surface of the second electrode; A first bonding pad disposed on the first insulating reflective layer and electrically connected to the first electrode through the first opening; A second bonding pad disposed on the second insulating reflection layer and spaced apart from the first bonding pad, the second bonding pad being electrically connected to the second electrode through the second opening; Wherein a sum of an area of the first bonding pad and an area of the second bonding pad is larger than a sum of an area of the first bonding pad and an area of the second bonding pad, May be provided equal to or less than 70% of the total area of the top surface.

The sum of the area of the first bonding pad and the area of the second bonding pad may be equal to or greater than 30% of the total area of the semiconductor device when viewed from the upper direction of the semiconductor device have.

According to the embodiment, the first bonding pad or the second bonding pad is provided along the major axis direction of the semiconductor element at a length of x, is provided along the minor axis direction of the semiconductor element at a length of y, The ratio of y may be provided from 1: 1.5 to 1: 2.

According to an embodiment, the distance between the first bonding pad and the second bonding pad may be equal to or greater than 125 micrometers and equal to or less than 300 micrometers.

According to the embodiment, the first bonding pad or the second bonding pad is disposed at a distance of b from the adjacent side surface disposed in the major axis direction of the semiconductor element, and the adjacent side surface , A is equal to or greater than 40 micrometers, and b can be provided equal to or greater than 40 micrometers.

According to an embodiment of the present invention, light generated in the light emitting structure can be transmitted through an area of 30% or more of the upper surface of the semiconductor device on which the first bonding pad and the second bonding pad are disposed.

According to an embodiment of the present invention, light generated in the light emitting structure can be transmitted through four side surfaces of an upper surface, a lower surface, and the like of the semiconductor device.

According to an embodiment of the present invention, there is provided a semiconductor device comprising: a first region provided between the first bonding pad and the second bonding pad; a second region provided between the first bonding pad or the second bonding pad, Light generated in the light emitting structure can be transmitted and emitted in a second region, a third region provided between the side surface disposed in the minor axis direction of the semiconductor element and the neighboring first bonding pad or the second bonding pad .

A semiconductor device package according to an embodiment includes: a package body including a first package electrode and a second package electrode; And a semiconductor device disposed on the package body, wherein the semiconductor device includes: a light emitting structure including a first conductive semiconductor layer and a second conductive semiconductor layer; A first electrode disposed on the first conductive semiconductor layer and electrically connected to the first conductive semiconductor layer; A second electrode disposed on the second conductive semiconductor layer and electrically connected to the second conductive semiconductor layer; A first insulating reflective layer disposed on the first electrode and the second electrode, the first insulating reflective layer including a first opening exposing an upper surface of the first electrode; A second insulating reflection layer disposed on the first electrode and the second electrode so as to be spaced apart from the first insulating reflection layer and including a second opening exposing an upper surface of the second electrode; A first bonding pad disposed on the first insulating reflective layer and electrically connected to the first electrode through the first opening; A second bonding pad disposed on the second insulating reflection layer and spaced apart from the first bonding pad, the second bonding pad being electrically connected to the second electrode through the second opening; Wherein a sum of an area of the first bonding pad and an area of the second bonding pad is larger than a sum of an area of the first bonding pad and an area of the second bonding pad, Wherein the first bonding pad of the semiconductor element is electrically connected to the first package electrode and the second bonding pad of the semiconductor element is provided to the second package, And may be electrically connected to the electrode.

According to the semiconductor device, the semiconductor device manufacturing method, and the semiconductor device package according to the embodiments, light extraction efficiency and electrical characteristics can be improved.

According to the semiconductor device, the semiconductor device manufacturing method, and the semiconductor device package according to the embodiments, the bonding strength between the package electrode and the semiconductor device can be improved.

According to the semiconductor device, the semiconductor device manufacturing method, and the semiconductor device package according to the embodiments, it is possible to prevent the current concentration phenomenon from occurring and improve the reliability.

According to the semiconductor device, the semiconductor device manufacturing method, and the semiconductor device package according to the embodiments, the electrodes, the insulating reflection layer, and the bonding pads are disposed so as to be suitable for the flip chip bonding method to facilitate the bonding process and the transmittance and reflectance So that the light extraction efficiency can be improved.

1 is a plan view of a semiconductor device according to an embodiment of the present invention.
2 is another cross-sectional view taken along the line AA of the semiconductor device shown in Fig.
3 is a view showing an example of arrangement of a first electrode and a second electrode applied to a semiconductor device according to an embodiment of the present invention.
4 is a view showing an example of the arrangement of first bonding pads and second bonding pads applied to a semiconductor device according to an embodiment of the present invention.
FIGS. 5A and 5B are diagrams illustrating a step in which a semiconductor layer and a current diffusion layer are formed by a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIGS. 6A and 6B are diagrams illustrating a step in which an ohmic contact layer is formed by a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIGS. 7A and 7B illustrate a step of forming a first electrode and a second electrode according to a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIGS. 8A and 8B are diagrams illustrating a step of forming a protective layer by a method for fabricating a semiconductor device according to an embodiment of the present invention.
FIGS. 9A and 9B are diagrams illustrating a step in which a first insulating reflection layer and a second insulating reflection layer are formed by a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIGS. 10A and 10B illustrate a step of forming a first bonding pad and a second bonding pad by the method of manufacturing a semiconductor device according to an embodiment of the present invention.
11 is a plan view showing another example of the semiconductor device according to the embodiment of the present invention.
12 is a cross-sectional view of the semiconductor device shown in FIG. 11 taken along line BB.
13 is a cross-sectional view of the semiconductor device shown in Fig. 11 along the CC line.
FIG. 14 is a view showing an arrangement example of a first electrode and a second electrode applied to another example of the semiconductor device according to the embodiment of the present invention.
FIGS. 15A, 15B, and 15C are diagrams illustrating a step in which a semiconductor layer and a current diffusion layer are formed by a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIGS. 16A, 16B, and 16C are diagrams illustrating a step in which an ohmic contact layer is formed by a semiconductor device manufacturing method according to an embodiment of the present invention.
FIGS. 17A, 17B, and 17C are diagrams illustrating a step of forming a protective layer by a method of fabricating a semiconductor device according to an embodiment of the present invention.
FIGS. 18A, 18B, and 18C are diagrams illustrating a step in which a first electrode and a second electrode are formed by a method of fabricating a semiconductor device according to an embodiment of the present invention.
FIGS. 19A, 19B, and 19C are diagrams illustrating a step in which a first insulating reflective layer and a second insulating reflective layer are formed by a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIGS. 20A, 20B and 20C are diagrams for explaining a step of forming a first bonding pad and a second bonding pad by the method of manufacturing a semiconductor device according to the embodiment of the present invention.
21 is a view for explaining a semiconductor device package according to an embodiment of the present invention.
22 and 23 are diagrams for explaining a change in luminous intensity depending on a thickness of a semiconductor device according to an embodiment of the present invention.
24 is a view showing a lighting apparatus according to an embodiment of the present invention.

Hereinafter, embodiments will be described with reference to the accompanying drawings. In the description of the embodiments, it is to be understood that each layer (film), area, pattern or structure may be referred to as being "on" or "under" the substrate, each layer Quot; on "and" under "are intended to include both" directly "or" indirectly " do. In addition, the criteria for the top, bottom, or bottom of each layer will be described with reference to drawings, but the embodiment is not limited thereto.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device, a semiconductor device manufacturing method, and a semiconductor device package according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line A-A of the semiconductor device shown in FIG.

1, a first electrode (not shown) disposed under the first bonding pad 171 and the second bonding pad 172 but electrically connected to the first bonding pad 171 141 and the second electrode 142 electrically connected to the second bonding pad 172 can be seen.

A semiconductor device 100 according to an embodiment may include a light emitting structure 110 disposed on a substrate 105, as shown in FIGS. 1 and 2.

The substrate 105 may be selected from the group consisting of a sapphire substrate (Al ₂ O ₃ ), SiC, GaAs, GaN, ZnO, Si, GaP, InP and Ge. For example, the substrate 105 may be provided as a patterned sapphire substrate (PSS) having a concavo-convex pattern formed on its upper surface.

The light emitting structure 110 may include a first conductive semiconductor layer 111, an active layer 112, and a second conductive semiconductor layer 113. The active layer 112 may be disposed between the first conductive semiconductor layer 111 and the second conductive semiconductor layer 113. For example, the active layer 112 may be disposed on the first conductive semiconductor layer 111, and the second conductive semiconductor layer 113 may be disposed on the active layer 112.

The first conductivity type semiconductor layer 111 may be provided as an n-type semiconductor layer, and the second conductivity type semiconductor layer 113 may be provided as a p-type semiconductor layer. Of course, according to another embodiment, the first conductivity type semiconductor layer 111 may be provided as a p-type semiconductor layer, and the second conductivity type semiconductor layer 113 may be provided as an n-type semiconductor layer.

Hereinafter, the first conductive semiconductor layer 111 is provided as an n-type semiconductor layer and the second conductive semiconductor layer 113 is provided as a p-type semiconductor layer for convenience of description .

In the above description, the case where the first conductive type semiconductor layer 111 is disposed in contact with the substrate 105 has been described. However, a buffer layer may be further disposed between the first conductive type semiconductor layer 111 and the substrate 105. For example, the buffer layer can reduce the difference in lattice constant between the substrate 105 and the light emitting structure 110 and improve the crystallinity.

The light emitting structure 110 may be provided as a compound semiconductor. The light emitting structure 110 may be formed of, for example, a Group 2-VI-VI or Group III-V compound semiconductor. For example, the light emitting structure 110 may include at least two elements selected from aluminum (Al), gallium (Ga), indium (In), phosphorus (P), arsenic (As) .

The first conductive semiconductor layer 111 may be formed of, for example, a Group 2-VI compound semiconductor or a Group 3B-5 compound semiconductor. For example, the first conductive semiconductor layer 111 may be a semiconductor having a composition formula of In _x Al _y Ga _1-xy N (0? X? 1, 0? _Y? 1, 0? _X + Material or a semiconductor material having a composition formula of (Al _x Ga _{1 -x} ) _y In _{1 -y} P (0? _X ? 1, 0? _Y? 1). For example, the first conductive semiconductor layer 111 may be selected from the group consisting of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, AlInP, GaInP, And an n-type dopant selected from the group including Si, Ge, Sn, Se, Te and the like can be doped.

The active layer 112 may be formed of, for example, a Group 2-VI compound semiconductor or a Group 3B-5 compound semiconductor. For example, the active layer 112 may be a semiconductor material having a composition formula of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + Al _x Ga _{1 -x} ) _y In _{1 -y} P (0? _X? 1, 0 _{? Y?} 1). For example, the active layer 112 may be selected from the group consisting of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, AlInP, GaInP, For example, the active layer 112 may be provided in a multi-well structure, and may include a plurality of barrier layers and a plurality of well layers.

The second conductivity type semiconductor layer 113 may be formed of, for example, a Group 2-VI compound semiconductor or a Group 3-V compound semiconductor. For example, the second conductivity type semiconductor layer 113 may be a semiconductor having a composition formula of In _x Al _y Ga _1-xy N (0? X? 1, 0? _Y? 1, 0? _X + Material or a semiconductor material having a composition formula of (Al _x Ga _{1 -x} ) _y In _{1 -y} P (0? _X ? 1, 0? _Y? 1). For example, the second conductive semiconductor layer 113 may be selected from the group including GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, AlInP, GaInP, And a p-type dopant selected from the group including Mg, Zn, Ca, Sr, Ba, etc. may be doped.

The semiconductor device 100 according to the embodiment may include the current diffusion layer 120 and the ohmic contact layer 130 as shown in FIG. The current diffusion layer 120 and the ohmic contact layer 130 can improve current diffusion to increase light output. The arrangement position and shape of the current diffusion layer 120 and the ohmic contact layer 130 will be further described with reference to a method of manufacturing a semiconductor device according to an embodiment.

For example, the current diffusion layer 120 may be provided as an oxide or a nitride. The horizontal width of the current diffusion layer 120 may be greater than the horizontal width of the second electrode 142 disposed above. Accordingly, the current diffusion layer 120 can improve the luminous flux by preventing the current concentration below the second electrode 142 and improving the electrical reliability.

In addition, the ohmic contact layer 130 may include at least one selected from the group consisting of a metal, a metal oxide, and a metal nitride. The ohmic contact layer 130 may include a light-transmitting material. For example, the ohmic contact layer 130 may include at least one of ITO (indium tin oxide), IZO (indium zinc oxide), IZON (indium zinc oxide), IZTO (indium zinc tin oxide), IAZO zinc oxide (IGTO), aluminum zinc oxide (AZO), antimony tin oxide (ATO), gallium zinc oxide (GZO), IrOx, RuOx, RuOx / ITO, Ni / IrOx / / Au / ITO, Pt, Ni, Au, Rh, and Pd.

The semiconductor device 100 according to the embodiment may include a first electrode 141 and a second electrode 142, as shown in FIGS.

The first electrode 141 may be electrically connected to the first conductive semiconductor layer 111. The first electrode 141 may be disposed on the first conductive type semiconductor layer 111. For example, in the semiconductor device 100 according to the embodiment, the first electrode 141 penetrates the second conductive type semiconductor layer 113 and the active layer 112 to form the first conductive type semiconductor layer 111 may be disposed on a top surface of the first conductivity type semiconductor layer 111 in a recess disposed to a partial region of the first conductivity type semiconductor layer 111.

The second electrode 142 may be electrically connected to the second conductive type semiconductor layer 113. The second electrode 142 may be disposed on the second conductive type semiconductor layer 113. The current diffusion layer 120 may be disposed between the second electrode 142 and the second conductive type semiconductor layer 113.

The first electrode 141 and the second electrode 142 may have a single-layer structure or a multi-layer structure. For example, the first electrode 141 and the second electrode 142 may be ohmic electrodes. For example, the first electrode 141 and the second electrode 142 may be formed of one selected from the group consisting of ZnO, IrOx, RuOx, NiO, RuOx / ITO, Ni / IrOx / Au, , At least one of Cr, Ti, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au and Hf or an alloy of two or more of them.

The semiconductor device 100 according to the embodiment may include a protective layer 150, as shown in FIGS.

The passivation layer 150 may be disposed on the second electrode 142. The passivation layer 150 may include a first opening h1 that exposes a portion of the second electrode 142.

In addition, the passivation layer 150 may be disposed on the first electrode 141. The passivation layer 150 may include a second opening h2 for exposing a portion of the first electrode 141 on the first electrode 141.

For example, the protective layer 150 may be provided as an insulating material. For example, the passivation layer 150 may include SiO ₂ , SiO _x , SiO _x N _y , Si ₃ N ₄ , Al ₂ O ₃ And at least one material selected from the group consisting of:

The semiconductor device 100 according to the embodiment may include a first insulating reflection layer 161 and a second insulating reflection layer 162 as shown in FIGS. 1 and 2. The first insulating reflective layer 161 and the second insulating reflective layer 162 may be disposed on the passivation layer 150.

The first insulating reflection layer 161 may be disposed on the first electrode 141 and the second electrode 142. The first insulating reflection layer 161 may include a fourth opening h4 exposing a portion of the first electrode 141. The first insulating reflection layer 161 may include a fourth opening h4 provided corresponding to an area where the second opening h2 of the protection layer 150 is formed.

For example, the maximum width of the fourth opening h4 may be larger than the maximum width of the second opening h2. When the fourth opening h4 included in the first insulating reflection layer 161 is disposed to be narrower than the width of the second opening h2 disposed on the protection layer 150, May be disposed along the step of the second opening h2 disposed on the protective layer 150. [ If the first insulating reflective layer 161 is disposed along the step of the second opening h2, cracks may be generated in the first insulating reflective layer 161, and reliability of the semiconductor element may be lowered .

The maximum width of the recess may be greater than the width of the second opening h2 and the fourth opening h4. When the maximum width of the recess is larger than the second opening h2 and the fourth opening h4, the first electrode 141 is electrically connected to the first conductive type semiconductor layer 111 The area can be sufficiently secured to improve the electrical characteristics and a process margin for arranging the second opening h2 and the fourth opening h4 so as to vertically overlap with the recess can be ensured.

The second insulating reflection layer 162 may be disposed on the first electrode 141 and the second electrode 142. The second insulating reflective layer 162 may be spaced apart from the first insulating reflective layer 161. The second insulating reflection layer 162 may include a third opening h3 for exposing an upper surface of the second electrode 142. [ The second insulating reflection layer 162 may include a third opening h3 provided corresponding to an area where the first opening h1 of the protection layer 150 is formed.

For example, the maximum width of the third opening h3 may be greater than the maximum width of the first opening h1. When the third opening h3 included in the second insulating reflection layer 162 is disposed to be narrower than the width of the first opening h1 disposed on the protection layer 150, May be disposed along the step of the first opening h1 disposed on the protective layer 150. [ When the second insulating reflective layer 162 is disposed along the step of the first opening h1, cracks may be generated in the second insulating reflective layer 162, thereby decreasing the reliability of the semiconductor device The first insulating reflection layer 161 and the second insulating reflection layer 162 may be provided as a distributed Bragg reflector (DBR) layer or an ODR (Omni Directional Reflector) layer.

According to the embodiment, the first insulating reflection layer 161 may be disposed on a side surface and a part of the upper surface of the first electrode 141. In addition, a part of the upper surface of the first electrode 141 may be exposed in the fourth opening h4. The second insulating reflection layer 162 may be disposed on a side surface and a part of the upper surface of the second electrode 142. In addition, a part of the upper surface of the second electrode 142 may be exposed and disposed in the third opening h3.

The first insulating reflection layer 161 and the second insulating reflection layer 162 reflect light emitted from the active layer 112 of the light emitting structure 110 to form a first bonding pad 161, It is possible to minimize the occurrence of light absorption at the pad 162 and to improve the light intensity Po.

For example, the first insulating reflective layer 161 and the second insulating reflective layer 162 may be made of an insulating material and may be formed of a material having a high reflectivity such as a DBR Structure.

The first insulating reflective layer 161 and the second insulating reflective layer 162 may have a DBR structure in which materials having different refractive indexes are repeatedly arranged. For example, the first insulating reflective layer 161 and the second insulating reflective layer 162 may be formed of a material containing at least one of TiO ₂ , SiO ₂ , Ta ₂ O ₅ , and HfO ₂ .

The first insulating reflective layer 161 and the second insulating reflective layer 162 may have various configurations in order to enhance the reflectivity of the wavelength emitted from the active layer 112. For example, It can be freely designed.

The semiconductor device 100 according to the embodiment may include a first bonding pad 171 disposed on the first insulating reflection layer 161, as shown in FIGS. 1 and 2. In addition, the semiconductor device 100 according to the embodiment may include a second bonding pad 172 disposed on the second insulating reflection layer 162. The second bonding pad 172 may be spaced apart from the first bonding pad 171.

The first bonding pad 171 may contact a part of the upper portion of the first electrode 141 through the fourth opening h4 and the second opening h2. The second bonding pad 172 may contact a portion of the upper portion of the second electrode 142 through the third opening h3 and the first opening h1.

The semiconductor device according to the embodiment may be connected to an external power source in a flip chip bonding manner. For example, in fabricating a semiconductor device package, the top surface of the first electrode pad 171 and the top surface of the second electrode pad 172 may be disposed to attach to a submount, leadframe, have.

For example, the first bonding pad 171 and the second bonding pad 172 are formed of Au, AuTi, or the like, so that the packaging factory can be stably operated. The first bonding pad 171 and the second bonding pad 172 may be formed of a metal such as Ti, Al, In, Ir, Ta, Pd, Co, Cr, Mg, Zn, Ni, Si, Layer or multilayer structure using at least one material or alloy selected from Au, Hf, Pt, Ru, Rh, ZnO, IrOx, RuOx, NiO, RuOx / ITO, Ni / IrOx / Au, and Ni / IrOx / .

When the semiconductor device according to the embodiment is mounted by a flip-chip bonding method and is implemented as a semiconductor device package, the light provided by the light emitting structure 110 may be emitted through the substrate 105. Light emitted from the light emitting structure 110 may be reflected by the first insulating reflective layer 161 and the second insulating reflective layer 162 and may be emitted toward the substrate 105. Also, the light emitted from the light emitting structure 110 may be emitted in the lateral direction of the light emitting structure 100. The light emitted from the light emitting structure 110 may be transmitted through the first bonding pad 171 and the second bonding pad 172 from the first bonding pad 171 and the second bonding pad 172, The pad 172 may be discharged to the outside through an area where the pad 172 is not provided. Accordingly, the semiconductor device 100 according to the embodiment can emit light in six directions surrounding the light emitting structure 100, and the light intensity can be remarkably improved.

In addition, according to the semiconductor device and the semiconductor device package according to the embodiment, since the first electrode pad 171 and the second electrode pad 172 having a large area can be directly bonded to the circuit board providing power, The chip bonding process can be performed easily and stably.

In the description of the semiconductor device according to the embodiment, the case where the ohmic contact layer 130 is provided on the second conductivity type semiconductor layer 113 has been described. However, according to another embodiment, the ohmic contact layer 130 may be omitted and the second electrode 142 may be directly contacted with the second conductive semiconductor layer 113.

4, the arrangement relationship of the first bonding pad 171 and the second bonding pad 172 applied to the semiconductor device 100 according to the embodiment will be described in further detail. 4 is a view showing an example of the arrangement of the first bonding pad 171 and the second bonding pad 172 applied to the semiconductor device according to the embodiment of the present invention.

The sum of the areas of the first bonding pad 171 and the second bonding pad 172 in the upper direction of the semiconductor element 100 is smaller than the sum of the areas of the first bonding pad 171 and the second bonding pad 172, May be equal to or smaller than 70% of the total area of the upper surface of the semiconductor device 100 on which the bonding pads 171 and the second bonding pads 172 are disposed.

For example, the total area of the upper surface of the semiconductor device 100 may correspond to an area defined by a lateral length and a longitudinal length of the lower surface of the first conductive semiconductor layer 111 of the light emitting structure 100 . The total area of the upper surface of the semiconductor device 100 may correspond to the area of the upper surface or the lower surface of the substrate 105.

By providing the sum of the areas of the first bonding pad 171 and the second bonding pad 172 equal to or smaller than 70% of the total area of the semiconductor device 100, The amount of light emitted to the surface where the pads 171 and the second bonding pads 172 are disposed can be increased. Accordingly, according to the embodiment, since the amount of light emitted in the six surface direction of the semiconductor device 100 is increased, the light extraction efficiency can be improved and the light intensity Po can be increased.

The sum of the area of the first bonding pad 171 and the area of the second bonding pad 172 is preferably less than 30% of the total area of the semiconductor device 100, The same or larger.

By thus providing the sum of the areas of the first bonding pads 171 and the second bonding pads 172 equal to or greater than 30% of the total area of the semiconductor device 100, Stable mounting can be performed through the pads 171 and the second bonding pads 172 to ensure that the electrical characteristics of the semiconductor device 100 are not degraded.

The semiconductor device 100 according to the embodiment may have a structure in which the sum of the areas of the first bonding pad 171 and the second bonding pad 172 is greater than the sum of the areas of the first bonding pad 171 and the second bonding pad 172 in consideration of securing stability of light extraction efficiency, May be selected to be not less than 30% and not more than 70% of the total area of the semiconductor element 100.

That is, when the sum of the areas of the first bonding pads 171 and the second bonding pads 172 is 30% or more to 100% or less of the total area of the semiconductor device 100, The electrical characteristics can be ensured and the bonding force to be mounted on the semiconductor device package can be secured, so that stable mounting can be performed.

When the sum of the areas of the first bonding pad 171 and the second bonding pad 172 is more than 0% to 70% of the total area of the semiconductor device 100, the first bonding pad 171 The light extraction efficiency of the semiconductor device 100 can be improved and the light intensity Po can be increased by increasing the amount of light emitted to the surface on which the second bonding pad 172 and the second bonding pad 172 are disposed.

In order to secure the electrical characteristics of the semiconductor device 100 and the bonding force to be mounted on the semiconductor device package and increase the light intensity, the area of the first bonding pad 171 and the second bonding pad 172 Of the total area of the semiconductor element 100 is not less than 30% and not more than 70% of the total area of the semiconductor element 100.

In order to secure the electrical characteristics and bonding force of the semiconductor device 100 according to another embodiment, the semiconductor device 100 may be configured to have a thickness of more than 70% to 100% And less than 30%.

The first bonding pad 171 is provided along the major axis direction of the semiconductor device 100 at a length of x1 and is provided along the minor axis direction of the semiconductor device 100 at a length of y1 . At this time, the ratio of x1 and y1 may be, for example, 1: 1.5 to 1: 2.

The second bonding pad 172 may be provided along the major axis direction of the semiconductor device 100 at a length of x2 and may be provided along the minor axis direction of the semiconductor device 100 at a length of y2. At this time, the ratio of x2 and y2 may be, for example, 1: 1.5 to 1: 2.

For example, the minimum distance d between the first bonding pad 171 and the second bonding pad 172 may be equal to or greater than 125 micrometers. The minimum distance d between the first bonding pad 171 and the second bonding pad 172 is determined by considering the interval between the second electrode pad and the first electrode pad of the package body on which the semiconductor device 100 is mounted Can be selected.

By way of example, the minimum spacing between the second electrode pad and the first electrode pad of the package body may be provided at a minimum of 125 micrometers and may be provided at a maximum of 200 micrometers. In this case, considering the process error, the distance d between the first bonding pad 171 and the second bonding pad 172 may be 125 micrometers or more and 300 micrometers or less.

 The distance d between the first bonding pad 171 and the second bonding pad 172 should be greater than 125 micrometers so that the first bonding pad 171 and the second bonding pad The light emitting area for improving the light extraction efficiency can be secured and the light intensity Po of the semiconductor device 100 can be increased.

If the distance d between the first bonding pad 171 and the second bonding pad 172 is less than 300 micrometers, the first electrode pad and the second electrode pad of the semiconductor device package, The first bonding pad 171 and the second bonding pad 172 of the device can be bonded with a sufficient bonding force and the electrical characteristics of the semiconductor device 100 can be secured.

The minimum distance d between the first bonding pad 171 and the second bonding pad 172 is set to be larger than 125 micrometers in order to secure the optical characteristics and the reliability by the electrical characteristic and the bonding force is secured Lt; RTI ID = 0.0 > 300 < / RTI >

The embodiment provides a minimum interval (d) of not less than 125 micrometers and not more than 300 micrometers, but is not limited thereto. In order to improve the electrical characteristics or reliability of the semiconductor device package, it may be arranged to be smaller than 125 micrometers, And may be arranged larger than 300 micrometers to improve the characteristics.

The first bonding pad 171 is disposed at a distance b1 from the adjacent side surface of the semiconductor element 100 in the major axis direction and the first bonding pad 171 is disposed in the minor axis direction of the semiconductor element 100 May be spaced apart from the neighboring side by a length of a1 or a3. Herein, a1 or a3 may be equal to or greater than 40 micrometers, for example, and b1 may be provided equal to or greater than 40 micrometers.

The second bonding pad 172 is disposed at a distance of b2 from the adjacent side surface of the semiconductor element 100 disposed in the longitudinal direction of the semiconductor element 100, Lt; RTI ID = 0.0 > a2 < / RTI > or a4. Here, a2 or a4 may be equal to or greater than 40 micrometers, for example, and b2 may be provided equal to or greater than 40 micrometers.

According to the embodiment, a1, a2, a3, and a4 may be provided with the same value. In addition, b1 and b2 may be provided with the same value. According to another embodiment, at least two of a1, a2, a3 and a4 may have different values, and b1 and b2 may have different values.

According to the semiconductor device 100 of this embodiment, light generated in the light emitting structure 110 is transmitted through the first region provided between the first bonding pad 171 and the second bonding pad 172 And can be released. At this time, the first region may be a region corresponding to a minimum distance d between the first bonding pad 171 and the second bonding pad 172.

The semiconductor device 100 may further include a second region provided between the first bonding pad 171 or the second bonding pad 172 adjacent to the long side of the semiconductor device 100, The light can be transmitted and emitted. At this time, the second region may be a region corresponding to b1 and b2.

In addition, light generated in the light emitting structure may be incident on a third region provided between the first bonding pad 171 or the second bonding pad 172 which is adjacent to the side surface of the semiconductor device 100 in the short axis direction And can be transmitted and discharged. At this time, the third region may be a region corresponding to a1, a2, a3, and a4.

For example, in the case where the longitudinal direction length of the semiconductor device 100 according to the embodiment is 1250 mm and the minor axis length is 750 mm, the above-mentioned variables may have the following values.

When the area of the first bonding pad 171 is equal to the area of the second bonding pad 172 and the sum thereof is 30%, x1: y1 = 1: 2 and the value of d is 125 micrometers If provided, the value of x1 is provided at 265 micrometers, and the value of y1 may be provided at 530 micrometers. Thus, the value of a1 may be less than or equal to 110 micrometers for example, and the value of b1 may be provided as less than or equal to 300 micrometers as an example.

That is, the sum of the area of the first bonding pad 171 and the area of the second bonding pad 172 is determined according to the size of the semiconductor device 100, and the sum of the area of the first bonding pad 171 / Once the vertical ratio and the value of d are determined, the remaining variables can be calculated. Accordingly, the upper limit values of a1, a2, a3, a4, b1, b2, etc. are not shown.

According to the embodiment, the size of the first insulating reflection layer 161 may be several micrometers larger than the size of the first bonding pad 171. For example, the area of the first insulating reflection layer 161 may be sufficiently large to cover the area of the first bonding pad 171. The length of one side of the first insulating reflection layer 161 may be greater than the length of one side of the first bonding pad 171 by about 4 micrometers to 10 micrometers, for example.

The size of the second insulating reflection layer 162 may be several micrometers larger than the size of the second bonding pad 172. For example, the area of the second insulating reflection layer 162 may be sufficiently large to cover the area of the second bonding pad 172. The length of one side of the second insulating reflection layer 162 may be greater than the length of one side of the second bonding pad 172 by about 4 micrometers to 10 micrometers, for example.

The light emitted from the light emitting structure 110 may be transmitted through the first bonding pad 171 and the second bonding pad 162 by the first insulating reflective layer 161 and the second insulating reflective layer 162, (Not shown). Accordingly, the areas of the first insulating reflection layer 161 and the second insulating reflection layer 162 are equal to or larger than the area of the first bonding pad 171 and the second bonding pad 172, The light generated and emitted from the light emitting structure 110 can be minimized by being incident on the first bonding pad 171 and the second bonding pad 172.

Hereinafter, a method of manufacturing a semiconductor device according to an embodiment will be described with reference to the accompanying drawings. In explaining the semiconductor device manufacturing method according to the embodiment, description overlapping with those described with reference to FIGS. 1 to 4 may be omitted.

5A and 5B, a light emitting structure 110 and a current diffusion layer 120 may be formed on a substrate 105. Referring to FIG. 5A is a plan view showing the shapes of the light emitting structure 110 and the current diffusion layer 120 formed according to the method of manufacturing a semiconductor device according to the embodiment, and FIG. 5B is a sectional view of the semiconductor device shown in FIG. .

According to the embodiment, the light emitting structure 110 may be formed on the substrate 105. For example, the first conductive semiconductor layer 111, the active layer 112, and the second conductive semiconductor layer 113 may be formed on the substrate 105.

The current diffusion layer 120 may be formed on a portion of the second conductivity type semiconductor layer 113. For example, the current diffusion layer 120 may be formed in a plurality of linear shapes.

Next, as shown in FIGS. 6A and 6B, an ohmic contact layer 130 may be formed. FIG. 6A is a plan view showing the shape of the ohmic contact layer 130 formed according to the method of manufacturing a semiconductor device according to the embodiment, and FIG. 6B is a process sectional view along the line A-A of the semiconductor device shown in FIG. 6A.

According to the embodiment, the ohmic contact layer 130 may be formed on the second conductive semiconductor layer 113. The ohmic contact layer 130 may be formed on the current diffusion layer 120. Meanwhile, according to the embodiment, a part of the first conductivity type semiconductor layer 111 may be exposed through a mesa etching process. The ohmic contact layer 130 may include a mesa opening M for exposing the first conductivity type semiconductor layer 111 by a mesa etching. For example, the mesa opening M may be provided in a plurality of linear shapes. The mesa opening M may also be referred to as a recess.

Then, as shown in FIGS. 7A and 7B, the first electrode 141 and the second electrode 142 may be formed. FIG. 7A is a plan view showing the shapes of the first electrode 141 and the second electrode 142 formed according to the method of manufacturing a semiconductor device according to the embodiment, FIG. 7B is a plan view showing the process according to the AA line of the semiconductor device shown in FIG. Fig.

According to the embodiment, the first electrode 141 may be formed on the first conductive semiconductor layer 111 exposed by the recess M. The first electrode 141 may be formed in a linear shape, for example. In addition, the first electrode 141 may include an N region having a relatively larger area than other linear regions. The N region of the first electrode 141 may be electrically connected to the first bonding pad 171 to be formed later.

Also, the second electrode 142 may be formed on the current diffusion layer 120. The second electrode 142 may be formed, for example, in a linear shape. In addition, the second electrode 142 may include a P region having a relatively larger area than other linear regions. The P region of the second electrode 142 may be electrically connected to the second bonding pad 172 to be formed later.

Next, as shown in FIGS. 8A and 8B, a protective layer 150 may be formed. FIG. 8A is a plan view showing the shape of the protective layer 150 formed according to the method of manufacturing a semiconductor device according to the embodiment, and FIG. 8B is a process sectional view along the line A-A of the semiconductor device shown in FIG. 8A.

According to the embodiment, the passivation layer 150 may be formed on the first electrode 141 and the second electrode 142. The passivation layer 150 may include a plurality of openings. For example, the protective layer 150 may include a plurality of first openings h1. A portion of the P region of the second electrode 142 may be exposed through the plurality of first openings h1. In addition, the protective layer 150 may include a plurality of second openings h2. A portion of the N region on the first electrode 141 may be exposed through the plurality of second openings h2.

As shown in FIGS. 9A and 9B, the first insulating reflection layer 161 and the second insulating reflection layer 162 may be formed. 9A is a plan view showing the shapes of the first insulating reflection layer 161 and the second insulating reflection layer 162 formed according to the method of manufacturing a semiconductor device according to the embodiment, FIG.

According to the embodiment, the first insulating reflective layer 161 and the second insulating reflective layer 162 may be formed on the passivation layer 150.

The first insulating reflection layer 161 may include a plurality of fourth openings h4. For example, the plurality of fourth openings h4 may be provided corresponding to the positions where the plurality of second openings h2 are formed. A portion of the N region of the first electrode 141 may be exposed through the plurality of fourth openings h4 and the plurality of second openings h2.

In addition, the second insulating reflection layer 162 may include a plurality of third openings h3. For example, the plurality of third openings h3 may be provided corresponding to positions where the plurality of first openings h1 are formed. A portion of the P region of the second electrode 142 may be exposed through the plurality of third openings h3 and the plurality of first openings h1.

Then, as shown in FIGS. 10A and 10B, a first bonding pad 171 and a second bonding pad 172 may be formed. 10A is a plan view showing the shapes of the first bonding pad 171 and the second bonding pad 172 formed according to the method of manufacturing a semiconductor device according to the embodiment, And Fig.

According to the embodiment, the first electrode pad 171 and the second electrode pad 172 may be formed in the shape shown in FIG. 10A. The first electrode pad 171 may be disposed on the first insulating reflective layer 161. The second electrode pad 172 may be disposed on the second insulating reflection layer 162.

The lower surface of the first electrode pad 171 may be in contact with the upper surface of the first electrode 141. A portion of the first electrode pad 171 may be disposed in the fourth opening h4 and the second opening h2 to contact a portion of the N region of the first electrode 141. [

The lower surface of the second electrode pad 172 may be in contact with the upper surface of the second electrode 142. A portion of the second electrode pad 172 may be disposed in the third opening h3 and the first opening h1 to contact a portion of the P region of the second electrode 142. [

According to the embodiment, when the power is applied to the first electrode pad 171 and the second electrode pad 172, the light emitting structure 110 can emit light.

The semiconductor device according to the embodiment may be connected to an external power source in a flip chip bonding manner. For example, the upper surface of the first electrode pad 171 and the upper surface of the second electrode pad 172 may be arranged to be attached to a submount, a lead frame, a circuit board, or the like.

When the semiconductor device according to the embodiment is mounted by a flip-chip bonding method and is implemented as a semiconductor device package, the light provided by the light emitting structure 110 may be emitted through the substrate 105. Light emitted from the light emitting structure 110 may be reflected by the first insulating reflective layer 161 and the second insulating reflective layer 162 and may be emitted toward the substrate 105. Also, the light emitted from the light emitting structure 110 may be emitted in the lateral direction of the light emitting structure 100. The light emitted from the light emitting structure 110 may be transmitted through the first bonding pad 171 and the second bonding pad 172 from the first bonding pad 171 and the second bonding pad 172, The pad 172 may be discharged to the outside through an area where the pad 172 is not provided. Accordingly, the semiconductor device 100 according to the embodiment can emit light in six directions surrounding the light emitting structure 100, and the light intensity can be remarkably improved.

The sum of the areas of the first bonding pad 171 and the second bonding pad 172 in the upper direction of the semiconductor element 100 is smaller than the sum of the areas of the first bonding pad 171 and the second bonding pad 172, May be equal to or smaller than 70% of the total area of the upper surface of the semiconductor device 100 on which the bonding pads 171 and the second bonding pads 172 are disposed.

For example, the total area of the upper surface of the semiconductor device 100 may correspond to an area defined by a lateral length and a longitudinal length of the lower surface of the first conductive semiconductor layer 111 of the light emitting structure 100 . The total area of the upper surface of the semiconductor device 100 may correspond to the area of the upper surface or the lower surface of the substrate 105.

By providing the sum of the areas of the first bonding pad 171 and the second bonding pad 172 equal to or smaller than 70% of the total area of the semiconductor device 100, The amount of light emitted to the surface where the pads 171 and the second bonding pads 172 are disposed can be increased. Accordingly, according to the embodiment, since the amount of light emitted in the six surface direction of the semiconductor device 100 is increased, the light extraction efficiency can be improved and the light intensity Po can be increased.

The sum of the area of the first bonding pad 171 and the area of the second bonding pad 172 is preferably less than 30% of the total area of the semiconductor device 100, The same or larger.

By thus providing the sum of the areas of the first bonding pads 171 and the second bonding pads 172 equal to or greater than 30% of the total area of the semiconductor device 100, Stable mounting can be performed through the pads 171 and the second bonding pads 172.

The sum of the areas of the first bonding pads 171 and the second bonding pads 172 may be greater than the sum of the areas of the semiconductor devices 100 ) And not more than 70%.

That is, when the sum of the areas of the first bonding pads 171 and the second bonding pads 172 is 30% or more to 100% or less of the total area of the semiconductor device 100, The electrical characteristics can be ensured and the bonding force to be mounted on the semiconductor device package can be secured, so that stable mounting can be performed.

When the sum of the areas of the first bonding pad 171 and the second bonding pad 172 is more than 0% to 70% of the total area of the semiconductor device 100, the first bonding pad 171 The light extraction efficiency of the semiconductor device 100 can be improved and the light intensity Po can be increased by increasing the amount of light emitted to the surface on which the second bonding pad 172 and the second bonding pad 172 are disposed.

In order to secure the electrical characteristics of the semiconductor device 100 and the bonding force to be mounted on the semiconductor device package and increase the light intensity, the area of the first bonding pad 171 and the second bonding pad 172 Of the total area of the semiconductor element 100 is not less than 30% and not more than 70% of the total area of the semiconductor element 100.

In order to secure the electrical characteristics and bonding force of the semiconductor device 100 according to another embodiment, the semiconductor device 100 may be configured to have a thickness of more than 70% to 100% And less than 30%.

According to the semiconductor device 100 of this embodiment, light generated in the light emitting structure 110 is transmitted through the first region provided between the first bonding pad 171 and the second bonding pad 172 And can be released.

The semiconductor device 100 may further include a second region provided between the first bonding pad 171 or the second bonding pad 172 adjacent to the long side of the semiconductor device 100, The light can be transmitted and emitted.

In addition, light generated in the light emitting structure may be incident on a third region provided between the first bonding pad 171 or the second bonding pad 172 which is adjacent to the side surface of the semiconductor device 100 in the short axis direction And can be transmitted and discharged.

The semiconductor device and the semiconductor device manufacturing method according to the embodiments can provide a flip chip bonding type semiconductor device and a method of manufacturing a semiconductor device that can be applied to products requiring high voltage and high output.

Next, another example of the semiconductor device according to the embodiment of the present invention will be described with reference to FIG. 11 to FIG. In describing the semiconductor device according to the embodiment with reference to FIG. 11 to FIG. 14, description of elements overlapping with those described above may be omitted.

11 is a plan view showing another example of the semiconductor device according to the embodiment of the present invention, FIG. 12 is a cross-sectional view along BB line of the semiconductor device shown in FIG. 11, FIG. 14 is a view showing an example of the arrangement of the first electrode and the second electrode applied to another example of the semiconductor device according to the embodiment of the present invention.

11, a first electrode (not shown) disposed under the first bonding pad 171 and the second bonding pad 172 but electrically connected to the first bonding pad 171 141 and the second electrode 142 electrically connected to the second bonding pad 172 can be seen.

A semiconductor device 100 according to an embodiment may include a light emitting structure 110 disposed on a substrate 105, as shown in FIGS. 11 to 13.

The light emitting structure 110 may include a first conductive semiconductor layer 111, an active layer 112, and a second conductive semiconductor layer 113. The active layer 112 may be disposed between the first conductive semiconductor layer 111 and the second conductive semiconductor layer 113. For example, the active layer 112 may be disposed on the first conductive semiconductor layer 111, and the second conductive semiconductor layer 113 may be disposed on the active layer 112.

The first conductivity type semiconductor layer 111 may be provided as an n-type semiconductor layer, and the second conductivity type semiconductor layer 113 may be provided as a p-type semiconductor layer. Of course, according to another embodiment, the first conductivity type semiconductor layer 111 may be provided as a p-type semiconductor layer, and the second conductivity type semiconductor layer 113 may be provided as an n-type semiconductor layer.

Hereinafter, the first conductive semiconductor layer 111 is provided as an n-type semiconductor layer and the second conductive semiconductor layer 113 is provided as a p-type semiconductor layer for convenience of description .

The semiconductor device 100 according to the embodiment may include the current diffusion layer 120 and the ohmic contact layer 130, as shown in FIGS. 12 and 13. The current diffusion layer 120 and the ohmic contact layer 130 can improve current diffusion to increase light output. The arrangement position and shape of the current diffusion layer 120 and the ohmic contact layer 130 will be further described with reference to a method of manufacturing a semiconductor device according to an embodiment.

For example, the current diffusion layer 120 may be provided as an oxide or a nitride. The current diffusion layer 120 can improve the luminous flux by preventing the current concentration at the lower side of the second electrode 142 and improving the electrical reliability.

In addition, the ohmic contact layer 130 may include at least one selected from the group consisting of a metal, a metal oxide, and a metal nitride. The ohmic contact layer 130 may include a light-transmitting material.

The semiconductor device 100 according to the embodiment may include a protective layer 150, as shown in FIGS.

The protective layer 150 may include a plurality of first openings h1 for exposing the ohmic contact layer 130. [ The current diffusion layer 120 may be disposed under the region provided with the plurality of first openings h1.

In addition, the passivation layer 150 may include a plurality of second openings h2 exposing the first conductive semiconductor layer 111. Referring to FIG.

The semiconductor device 100 according to the embodiment may include a first electrode 141 and a second electrode 142, as shown in FIGS.

The first electrode 141 may be electrically connected to the first conductive semiconductor layer 111. The first electrode 141 may be disposed on the first conductive type semiconductor layer 111. For example, in the semiconductor device 100 according to the embodiment, the first electrode 141 is formed by removing a part of the second conductive type semiconductor layer 113 and a part of the active layer 112, And may be disposed on the upper surface of the conductive type semiconductor layer 111.

The first electrode 141 may be electrically connected to the upper surface of the first conductive semiconductor layer 111 through a second opening h2 provided in the passivation layer 150. [ For example, the first electrode 141 may be in contact with the upper surface of the first conductivity type semiconductor layer 111 in a plurality of N regions, as shown in FIGS. 11 to 14.

The second electrode 142 may be electrically connected to the second conductive type semiconductor layer 113. The second electrode 142 may be disposed on the second conductive type semiconductor layer 113. The current diffusion layer 120 may be disposed between the second electrode 142 and the second conductive type semiconductor layer 113.

The second electrode 142 may be electrically connected to the upper surface of the second conductive type semiconductor layer 113 through a first opening h1 provided in the passivation layer 150. [ For example, the second electrode 142 may be electrically connected to the second conductive type semiconductor layer 113 in a part of a plurality of P regions, as shown in FIGS.

According to the embodiment, as shown in FIGS. 11 to 14, the first electrode 141 and the second electrode 142 may be spaced apart from each other.

The first electrode 141 may include a plurality of first branched electrodes 141a extending in a direction in which the second electrode 142 is disposed. A plurality of N regions may be formed in a part of the plurality of first branched electrodes 141a. The first electrode 141 may be electrically connected to the first conductive type semiconductor layer 111 through a part of the plurality of N regions.

The second electrode 142 may include a plurality of second branched electrodes 142a extending in a direction in which the first electrode 141 is disposed. A plurality of P regions may be formed in a part of the plurality of second branched electrodes 142a. The second electrode 142 may be electrically connected to the second conductive type semiconductor layer 113 through a portion of the plurality of P regions.

The semiconductor device 100 according to the embodiment may include a first insulating reflective layer 161 and a second insulating reflective layer 162, as shown in FIGS. 11 to 13. The first insulating reflective layer 161 and the second insulating reflective layer 162 may be disposed on the passivation layer 150. The first insulating reflective layer 161 and the second insulating reflective layer 162 may be disposed on the first electrode 141 and the second electrode 142.

The first insulating reflection layer 161 may be disposed on the first electrode 141 and the second electrode 142. The first insulating reflection layer 161 may include a fourth opening h4 for exposing an upper surface of the first electrode 141. [

The second insulating reflection layer 162 may be disposed on the first electrode 141 and the second electrode 142. The second insulating reflective layer 162 may be spaced apart from the first insulating reflective layer 161. The second insulating reflection layer 162 may include a third opening h3 for exposing an upper surface of the second electrode 142. [

For example, the first insulating reflective layer 161 and the second insulating reflective layer 162 may be provided as a DBR (Distributed Bragg Reflector) layer or an ODR (Omni Directional Reflector) layer.

The first insulating reflection layer 161 may be disposed on the first electrode 141 to expose the upper surface of the first electrode 141 on a side surface and a part of the upper surface of the first electrode 141. The second insulating reflection layer 162 may be disposed on the side surface and a part of the upper surface of the second electrode 142 to expose the upper surface of the second electrode 142.

The first insulating reflection layer 161 and the second insulating reflection layer 162 reflect light emitted from the active layer 112 of the light emitting structure 110 to form a first bonding pad 161, It is possible to minimize the occurrence of light absorption at the pad 162 and to improve the light intensity Po.

For example, the first insulating reflective layer 161 and the second insulating reflective layer 162 may be made of an insulating material and may be formed of a material having a high reflectivity such as a DBR Structure.

The first insulating reflective layer 161 and the second insulating reflective layer 162 may have a DBR structure in which materials having different refractive indexes are repeatedly arranged. For example, the first insulating reflective layer 161 and the second insulating reflective layer 162 may be formed of TiO ₂ , SiO ₂ , Ta ₂ O ₅ , HfO ₂ Or < RTI ID = 0.0 > a < / RTI >

The first insulating reflective layer 161 and the second insulating reflective layer 162 may have various configurations in order to enhance the reflectivity of the wavelength emitted from the active layer 112. For example, It can be freely designed.

The semiconductor device 100 according to the embodiment may include a first bonding pad 171 disposed on the first insulating reflection layer 161, as shown in FIGS. 11 to 13. In addition, the semiconductor device 100 according to the embodiment may include a second bonding pad 172 disposed on the second insulating reflection layer 162. The second bonding pad 172 may be spaced apart from the first bonding pad 171.

The first bonding pad 171 may be in contact with the upper surface of the first electrode 141 through the fourth opening h4 provided in the first insulating reflection layer 161 in a plurality of NB regions. The second bonding pad 172 may contact the upper surface of the second electrode 142 through the third opening h3 provided in the second insulating reflection layer 162 in a plurality of PB regions.

According to the semiconductor device 100 of the embodiment, the first bonding pad 171 and the first electrode 141 can be contacted in a plurality of regions. Also, the second bonding pad 172 and the second electrode 142 may be in contact with each other in a plurality of regions. Thus, according to the embodiment, power can be supplied through a plurality of regions, so that current dispersion effect is generated according to increase of the contact area and dispersion of the contact region, and operation voltage can be reduced.

The semiconductor device according to the embodiment may be connected to an external power source in a flip chip bonding manner. For example, in fabricating a semiconductor device package, the top surface of the first electrode pad 171 and the top surface of the second electrode pad 172 may be disposed to attach to a submount, leadframe, have.

When the semiconductor device according to the embodiment is mounted by a flip-chip bonding method and is implemented as a semiconductor device package, the light provided by the light emitting structure 110 may be emitted through the substrate 105. Light emitted from the light emitting structure 110 may be reflected by the first insulating reflective layer 161 and the second insulating reflective layer 162 and may be emitted toward the substrate 105. Also, the light emitted from the light emitting structure 110 may be emitted in the lateral direction of the light emitting structure 100. The light emitted from the light emitting structure 110 may be transmitted through the first bonding pad 171 and the second bonding pad 172 from the first bonding pad 171 and the second bonding pad 172, The pad 172 may be discharged to the outside through an area where the pad 172 is not provided. Accordingly, the semiconductor device 100 according to the embodiment can emit light in six directions surrounding the light emitting structure 100, and the light intensity can be remarkably improved.

In addition, according to the semiconductor device and the semiconductor device package according to the embodiment, since the first electrode pad 171 and the second electrode pad 172 having a large area can be directly bonded to the circuit board providing power, The chip bonding process can be performed easily and stably.

4, the first bonding pads 171 and the second bonding pads 172 are formed on the upper surface of the semiconductor device 100. The first bonding pads 171 and the second bonding pads 172, May be equal to or smaller than 70% of the total area of the upper surface of the semiconductor device 100 on which the first bonding pad 171 and the second bonding pad 172 are disposed.

For example, the total area of the upper surface of the semiconductor device 100 may correspond to an area defined by a lateral length and a longitudinal length of the lower surface of the first conductive semiconductor layer 111 of the light emitting structure 100 . The total area of the upper surface of the semiconductor device 100 may correspond to the area of the upper surface or the lower surface of the substrate 105.

By providing the sum of the areas of the first bonding pad 171 and the second bonding pad 172 equal to or smaller than 70% of the total area of the semiconductor device 100, The amount of light emitted to the surface where the pads 171 and the second bonding pads 172 are disposed can be increased. Accordingly, according to the embodiment, since the amount of light emitted in the six surface direction of the semiconductor device 100 is increased, the light extraction efficiency can be improved and the light intensity Po can be increased.

The sum of the area of the first bonding pad 171 and the area of the second bonding pad 172 is preferably less than 30% of the total area of the semiconductor device 100, The same or larger.

By thus providing the sum of the areas of the first bonding pads 171 and the second bonding pads 172 equal to or greater than 30% of the total area of the semiconductor device 100, Stable mounting can be performed through the pads 171 and the second bonding pads 172.

The sum of the areas of the first bonding pads 171 and the second bonding pads 172 may be greater than the sum of the areas of the semiconductor devices 100 ) And not more than 70%.

That is, when the sum of the areas of the first bonding pads 171 and the second bonding pads 172 is 30% or more to 100% or less of the total area of the semiconductor device 100, The electrical characteristics can be ensured and the bonding force to be mounted on the semiconductor device package can be secured, so that stable mounting can be performed.

When the sum of the areas of the first bonding pad 171 and the second bonding pad 172 is more than 0% to 70% of the total area of the semiconductor device 100, the first bonding pad 171 The light extraction efficiency of the semiconductor device 100 can be improved and the light intensity Po can be increased by increasing the amount of light emitted to the surface on which the second bonding pad 172 and the second bonding pad 172 are disposed.

In order to secure the electrical characteristics of the semiconductor device 100 and the bonding force to be mounted on the semiconductor device package and increase the light intensity, the area of the first bonding pad 171 and the second bonding pad 172 Of the total area of the semiconductor element 100 is not less than 30% and not more than 70% of the total area of the semiconductor element 100.

In order to secure the electrical characteristics and bonding force of the semiconductor device 100 according to another embodiment, the semiconductor device 100 may be configured to have a thickness of more than 70% to 100% And less than 30%.

According to the semiconductor device 100 of this embodiment, light generated in the light emitting structure 110 is transmitted through the first region provided between the first bonding pad 171 and the second bonding pad 172 And can be released. At this time, the first region may correspond to a minimum gap between the first bonding pad 171 and the second bonding pad 172.

The semiconductor device 100 may further include a second region provided between the first bonding pad 171 or the second bonding pad 172 adjacent to the long side of the semiconductor device 100, The light can be transmitted and emitted.

In addition, light generated in the light emitting structure may be incident on a third region provided between the first bonding pad 171 or the second bonding pad 172 which is adjacent to the side surface of the semiconductor device 100 in the short axis direction And can be transmitted and discharged.

Hereinafter, a method of manufacturing a semiconductor device according to an embodiment will be described with reference to the accompanying drawings. In describing the method of manufacturing a semiconductor device according to the embodiment, description overlapping with those described with reference to FIGS. 1 to 14 may be omitted.

15A to 15C, a light emitting structure 110 and a current diffusion layer 120 may be formed on a substrate 105. Referring to FIG. 15A is a plan view showing the shapes of the light emitting structure 110 and the current diffusion layer 120 formed according to the method of manufacturing a semiconductor device according to the embodiment, and FIG. 15B is a process sectional view along the BB line of the semiconductor device shown in FIG. And FIG. 15C is a process sectional view taken along the line CC of the semiconductor device shown in FIG. 15A.

According to the embodiment, the light emitting structure 110 may be formed on the substrate 105. For example, the first conductive semiconductor layer 111, the active layer 112, and the second conductive semiconductor layer 113 may be formed on the substrate 105.

The current diffusion layer 120 may be formed on a portion of the second conductivity type semiconductor layer 113. For example, the current diffusion layer 120 may be formed in a plurality of dot shapes. For example, the current diffusion layer 120 may be formed in a plurality of circular shapes having a predetermined size.

Next, as shown in FIGS. 16A to 16C, an ohmic contact layer 130 may be formed. 16A is a plan view showing the shape of the ohmic contact layer 130 formed in accordance with the method of manufacturing a semiconductor device according to the embodiment, FIG. 16B is a sectional view of the process according to the BB line of the semiconductor device shown in FIG. 16A, Is a process sectional view taken along the line CC of the semiconductor device shown in Fig. 16A.

According to the embodiment, the ohmic contact layer 130 may be formed on the second conductive semiconductor layer 113. The ohmic contact layer 130 may be formed on the current diffusion layer 120.

Meanwhile, according to the embodiment, a part of the first conductivity type semiconductor layer 111 may be exposed through a mesa etching process. The light emitting structure 110 may include a recess for exposing the first conductive semiconductor layer 111. For example, the light emitting structure 110 may include a plurality of circular recesses.

Next, as shown in FIGS. 17A to 17C, a protective layer 150 may be formed. 17A is a plan view showing the shape of the protective layer 150 formed according to the method of manufacturing a semiconductor device according to the embodiment, FIG. 17B is a process sectional view along the BB line of the semiconductor device shown in FIG. 17A, 17A is a cross-sectional view of a process according to the CC line of the semiconductor device shown in Fig. 17A.

The passivation layer 150 may include a plurality of openings. For example, the protective layer 150 may include a plurality of first openings h1. The current diffusion layer 120 may be exposed through the plurality of first openings h1. In addition, the protective layer 150 may include a plurality of second openings h2. The upper surface of the first conductive type semiconductor layer 111 may be exposed through the plurality of second openings h2. The plurality of second openings h2 may be provided corresponding to the plurality of recesses M.

Next, as shown in FIGS. 18A to 18C, a first electrode 141 and a second electrode 142 may be formed. 18A is a plan view showing the shapes of the first electrode 141 and the second electrode 142 formed according to the method of manufacturing a semiconductor device according to the embodiment, FIG. 18B is a plan view showing a process according to the BB line of the semiconductor device shown in FIG. And Fig. 18C is a process sectional view taken along the line CC of the semiconductor device shown in Fig. 18A.

According to the embodiment, the first electrode 141 and the second electrode 142 may be spaced apart from each other.

The first electrode 141 may include a plurality of first branched electrodes 141a extending in a direction in which the second electrode 142 is disposed. A plurality of N regions may be formed in a part of the plurality of first branched electrodes 141a. The first electrode 141 may be electrically connected to the first conductive type semiconductor layer 111 through the plurality of N regions.

The second electrode 142 may include a plurality of second branched electrodes 142a extending in a direction in which the first electrode 141 is disposed. A plurality of P regions may be formed in a part of the plurality of second branched electrodes 142a. The second electrode 142 may be electrically connected to the second conductive type semiconductor layer 113 through the plurality of P regions.

The N region of the first electrode 141 may be formed on the first conductive semiconductor layer 111 exposed by the second opening h2 and the recesses M according to the embodiment.

In addition, a P region of the second electrode 142 may be formed on the current diffusion layer 120 exposed by the first opening h1.

19A to 19C, the first insulating reflection layer 161 and the second insulating reflection layer 162 may be formed. 19A is a plan view showing the shapes of the first insulating reflection layer 161 and the second insulating reflection layer 162 formed according to the method of manufacturing a semiconductor device according to the embodiment, And FIG. 19C is a process sectional view taken along the line CC of the semiconductor device shown in FIG. 19A.

The first insulating reflective layer 161 and the second insulating reflective layer 162 may be formed on the first electrode 141 and the second electrode 142. Referring to FIG.

The first insulating reflection layer 161 may be disposed on the first electrode 141 and the second electrode 142. The first insulating reflection layer 161 may include a plurality of fourth openings h4. For example, a portion of the upper surface of the first electrode 141 may be exposed through the plurality of fourth openings h4.

In addition, the second insulating reflection layer 162 may be disposed on the first electrode 141 and the second electrode 142. The second insulating reflection layer 162 may include a plurality of third openings h3. For example, a portion of the upper surface of the second electrode 142 may be exposed through the plurality of third openings h3.

The semiconductor device 100 according to the embodiment further includes a third insulating reflection layer 163 disposed on the first branched electrode 141a and a fourth insulating reflection layer 164 disposed on the second branched electrode 142a. .

The first insulating reflection layer 161 may be disposed on the first electrode 141 to expose the upper surface of the first electrode 141 on a side surface and a part of the upper surface of the first electrode 141. The second insulating reflection layer 162 may be disposed on the side surface and a part of the upper surface of the second electrode 142 to expose the upper surface of the second electrode 142.

Then, as shown in FIGS. 20A to 20C, a first bonding pad 171 and a second bonding pad 172 may be formed. 20A is a plan view showing the shapes of the first bonding pad 171 and the second bonding pad 172 formed according to the method of manufacturing a semiconductor device according to the embodiment, And FIG. 20C is a process sectional view taken along the line CC of the semiconductor device shown in FIG. 20A.

According to the embodiment, the first electrode pad 171 and the second electrode pad 172 may be formed in the shape shown in FIG. 20A. The first electrode pad 171 may be disposed on the first insulating reflective layer 161. The second electrode pad 172 may be disposed on the second insulating reflection layer 162. The second bonding pad 172 may be spaced apart from the first bonding pad 171.

The first bonding pad 171 may be in contact with the upper surface of the first electrode 141 through the fourth opening h4 provided in the first insulating reflection layer 161 in a plurality of NB regions. The second bonding pad 172 may contact the upper surface of the second electrode 142 through the third opening h3 provided in the second insulating reflection layer 162 in a plurality of PB regions.

The semiconductor device according to the embodiment may be connected to an external power source in a flip chip bonding manner. For example, in fabricating a semiconductor device package, the top surface of the first electrode pad 171 and the top surface of the second electrode pad 172 may be disposed to attach to a submount, leadframe, have.

When the semiconductor device according to the embodiment is mounted by a flip-chip bonding method and is implemented as a semiconductor device package, the light provided by the light emitting structure 110 may be emitted through the substrate 105. Light emitted from the light emitting structure 110 may be reflected by the first insulating reflective layer 161 and the second insulating reflective layer 162 and may be emitted toward the substrate 105. Also, the light emitted from the light emitting structure 110 may be emitted in the lateral direction of the light emitting structure 100. The light emitted from the light emitting structure 110 may be transmitted through the first bonding pad 171 and the second bonding pad 172 from the first bonding pad 171 and the second bonding pad 172, The pad 172 may be discharged to the outside through an area where the pad 172 is not provided. Accordingly, the semiconductor device 100 according to the embodiment can emit light in six directions surrounding the light emitting structure 100, and the light intensity can be remarkably improved.

In addition, according to the semiconductor device and the semiconductor device package according to the embodiment, since the first electrode pad 171 and the second electrode pad 172 having a large area can be directly bonded to the circuit board providing power, The chip bonding process can be performed easily and stably.

4, the first bonding pads 171 and the second bonding pads 172 are formed on the upper surface of the semiconductor device 100. The first bonding pads 171 and the second bonding pads 172, May be equal to or smaller than 70% of the total area of the upper surface of the semiconductor device 100 on which the first bonding pad 171 and the second bonding pad 172 are disposed.

For example, the total area of the upper surface of the semiconductor device 100 may correspond to an area defined by a lateral length and a longitudinal length of the lower surface of the first conductive semiconductor layer 111 of the light emitting structure 100 . The total area of the upper surface of the semiconductor device 100 may correspond to the area of the upper surface or the lower surface of the substrate 105.

By providing the sum of the areas of the first bonding pad 171 and the second bonding pad 172 equal to or smaller than 70% of the total area of the semiconductor device 100, The amount of light emitted to the surface where the pads 171 and the second bonding pads 172 are disposed can be increased. Accordingly, according to the embodiment, since the amount of light emitted in the six surface direction of the semiconductor device 100 is increased, the light extraction efficiency can be improved and the light intensity Po can be increased.

The sum of the area of the first bonding pad 171 and the area of the second bonding pad 172 is preferably less than 30% of the total area of the semiconductor device 100, The same or larger.

By thus providing the sum of the areas of the first bonding pads 171 and the second bonding pads 172 equal to or greater than 30% of the total area of the semiconductor device 100, Stable mounting can be performed through the pads 171 and the second bonding pads 172.

The sum of the areas of the first bonding pads 171 and the second bonding pads 172 may be greater than the sum of the areas of the semiconductor devices 100 ) And not more than 70%.

That is, when the sum of the areas of the first bonding pads 171 and the second bonding pads 172 is 30% or more to 100% or less of the total area of the semiconductor device 100, The electrical characteristics can be ensured and the bonding force to be mounted on the semiconductor device package can be secured, so that stable mounting can be performed.

When the sum of the areas of the first bonding pad 171 and the second bonding pad 172 is more than 0% to 70% of the total area of the semiconductor device 100, the first bonding pad 171 The light extraction efficiency of the semiconductor device 100 can be improved and the light intensity Po can be increased by increasing the amount of light emitted to the surface on which the second bonding pad 172 and the second bonding pad 172 are disposed.

In order to secure the electrical characteristics of the semiconductor device 100 and the bonding force to be mounted on the semiconductor device package and increase the light intensity, the area of the first bonding pad 171 and the second bonding pad 172 Of the total area of the semiconductor element 100 is not less than 30% and not more than 70% of the total area of the semiconductor element 100.

In order to secure the electrical characteristics and bonding force of the semiconductor device 100 according to another embodiment, the semiconductor device 100 may be configured to have a thickness of more than 70% to 100% And less than 30%.

According to the semiconductor device 100 of this embodiment, light generated in the light emitting structure 110 is transmitted through the first region provided between the first bonding pad 171 and the second bonding pad 172 And can be released. At this time, the first region may be a region corresponding to the interval between the first bonding pad 171 and the second bonding pad 172.

The semiconductor device 100 may further include a second region provided between the first bonding pad 171 or the second bonding pad 172 adjacent to the long side of the semiconductor device 100, The light can be transmitted and emitted.

In addition, light generated in the light emitting structure may be incident on a third region provided between the first bonding pad 171 or the second bonding pad 172 which is adjacent to the side surface of the semiconductor device 100 in the short axis direction And can be transmitted and discharged.

The semiconductor device according to the embodiment described above can be applied to a semiconductor device package. The semiconductor device according to an embodiment may be electrically connected to a substrate or a lead electrode through a flip chip bonding method, a die bonding method, a wire bonding method, or the like to be provided as a semiconductor device package.

21 is a view illustrating a semiconductor device package according to an embodiment of the present invention. Referring to FIG. 21, in explaining the semiconductor device package according to the embodiment, description overlapping with those described with reference to FIGS. 1 to 20 may be omitted.

A semiconductor device package according to an embodiment includes a package body 205, a first package electrode 211 and a second package electrode 212 disposed on the package body 205, a semiconductor package 210 disposed on the package body 205, A device 100, and a molding part 230 provided with a phosphor disposed on the semiconductor device 100. For example, the semiconductor device 100 may be a semiconductor device according to the embodiment described with reference to FIGS.

For example, the package body 205 may be formed of a material selected from the group consisting of polyphthalamide (PPA), polychloro tri phenyl (PCT), liquid crystal polymer (LCP), polyamide 9T, silicone, epoxy molding compound (EMC) , A material including a metal, a ceramic, a photo sensitive glass (PSG), a sapphire (Al2O3), and a printed circuit board (PCB). In addition, the package body 205 may include a high refractive index filler such as TiO ₂ and SiO ₂ .

The first package electrode 211 and the second package electrode 212 may include a conductive material. For example, the first package electrode 211 and the second package electrode 212 may include at least one of Ti, Cu, Ni, Au, Cr, Ta, Pt, Sn, Ag, P, Fe, Sn, And may be a single layer or multiple layers.

The semiconductor device 100 may be electrically connected to the first package electrode 211 and the second package electrode 212. For example, the semiconductor device 100 may be electrically connected to the first package electrode 211 and the second package electrode 212 through the first bump 221 and the second bump 222. The first bonding pad and the second bonding pad of the semiconductor device 100 may be electrically connected to the first package electrode 211 and the second package electrode 212, respectively.

The first bump 221 and the second bump 222 may be formed of at least one of a high-reflectivity metal such as Ag, Au, or Al, or an alloy thereof, to prevent light absorption by the electrode, The efficiency can be improved. For example, the first bump 221 and the second bump 222 may be formed of a material selected from the group consisting of Ti, Cu, Ni, Au, Cr, Ta, And may be formed of at least one of platinum (Pt), tin (Sn), silver (Ag), phosphorus (P), or a selective alloy thereof.

Also, the semiconductor device 100 may be mounted on the first package electrode 211 and the second package electrode 212 by bending without a bump.

As described above, the semiconductor device 100 according to the embodiment can emit light in six plane directions. The light emitted in the downward direction in which the first bonding pads and the second bonding pads of the semiconductor device 100 are disposed is reflected on the bottom surface of the package body 205 to be provided in the upper direction of the package body 205 .

The semiconductor device 100 according to the embodiment may be manufactured by a method such as that described with reference to FIGS. 1 to 20 in order to provide sufficient bonding force with the first package electrode 211 and the second package electrode 212 The area of the first bonding pad and the area of the second bonding pad were selected. In addition, the semiconductor device 100 according to the embodiment may have a structure in which light is transmitted through a region where first bonding pads and second bonding pads are disposed, in order to improve efficiency of light emission in a downward direction as well as bonding power The area of the first bonding pad and the area of the second bonding pad were selected in consideration of the size.

4, the sum of the areas of the first bonding pads and the second bonding pads in the upper direction of the semiconductor element 100 is the sum of the areas of the first bonding pads and the second bonding pads, May be provided to be equal to or smaller than 70% of the total area of the upper surface of the semiconductor element 100 on which the bonding pads and the second bonding pads are disposed.

By thus providing the sum of the areas of the first bonding pads and the second bonding pads equal to or smaller than 70% of the total area of the semiconductor device 100, the first bonding pads and the second bonding pads are arranged The amount of light emitted to the surface can be increased. Accordingly, according to the embodiment, since the amount of light emitted in the six surface direction of the semiconductor device 100 is increased, the light extraction efficiency can be improved and the light intensity Po can be increased.

The sum of the area of the first bonding pad and the area of the second bonding pad may be equal to or greater than 30% of the total area of the semiconductor device 100 when viewed from above the semiconductor device.

By thus providing the sum of the areas of the first bonding pad and the second bonding pad equal to or greater than 30% of the total area of the semiconductor device 100, So that the mounting can be performed.

The semiconductor device 100 according to the embodiment may have a structure in which the sum of the areas of the first bonding pad and the second bonding pad is 30 % And not more than 70%.

That is, when the sum of the areas of the first bonding pads 171 and the second bonding pads 172 is 30% or more to 100% or less of the total area of the semiconductor device 100, The electrical characteristics can be ensured and the bonding force to be mounted on the semiconductor device package can be secured, so that stable mounting can be performed.

When the sum of the areas of the first bonding pad 171 and the second bonding pad 172 is more than 0% to 70% of the total area of the semiconductor device 100, the first bonding pad 171 The light extraction efficiency of the semiconductor device 100 can be improved and the light intensity Po can be increased by increasing the amount of light emitted to the surface on which the second bonding pad 172 and the second bonding pad 172 are disposed.

In order to secure the electrical characteristics of the semiconductor device 100 and the bonding force to be mounted on the semiconductor device package and increase the light intensity, the area of the first bonding pad 171 and the second bonding pad 172 Of the total area of the semiconductor element 100 is not less than 30% and not more than 70% of the total area of the semiconductor element 100.

In order to secure the electrical characteristics and bonding force of the semiconductor device 100 according to another embodiment, the semiconductor device 100 may be configured to have a thickness of more than 70% to 100% And less than 30%.

According to the semiconductor device 100 of this embodiment, the light generated in the light emitting structure 110 can be transmitted through the first region provided between the first bonding pad and the second bonding pad. At this time, the first region may be a region corresponding to an interval between the first bonding pad and the second bonding pad.

In addition, light generated in the light emitting structure 110 may be transmitted through a second region provided between a side surface of the semiconductor device 100 in the major axis direction and a neighboring first bonding pad or a second bonding pad, have.

In addition, light generated in the light emitting structure 110 may be transmitted to a third region provided between a side surface of the semiconductor device 100 in a short axis direction and a neighboring first bonding pad or a second bonding pad. have.

The light emitted in the direction of the six sides of the semiconductor device 100 is reflected by the bottom surface and the side surface of the package body 205 and is provided in the upper direction of the package body 205 .

22 and 23 are views for explaining a change in luminous intensity depending on the thickness of a semiconductor device according to an embodiment of the present invention.

The semiconductor device according to an embodiment may include a light emitting structure 110 and an insulating reflective layer 160 disposed below the light emitting structure 110, as shown in FIG. For example, the insulating reflective layer 160 may be the second insulating reflective layer described with reference to FIGS.

The light emitting structure 110 may include a first conductive semiconductor layer 111, an active layer 112, and a second conductive semiconductor layer 113. For example, the first conductive semiconductor layer 111 may be provided as an n-GaN layer, and the second conductive semiconductor layer 113 may be provided as a p-GaN layer.

The light generated in the active layer 112 may travel downward and reflect upward in the insulating reflection layer 160. Accordingly, the light reflected from the insulating reflection layer 160 may interfere with the light generated in the active layer 112. For example, light reflected from the insulating reflection layer 160 may cause constructive interference with light generated in the active layer 112 depending on the thickness of the second conductive type semiconductor layer 113.

In the semiconductor device according to the embodiment, as shown in [Table 1], the electrical and optical characteristics may be changed depending on the thickness of the second conductivity type semiconductor layer 113. 23 is a graph showing a change in the luminous intensity Po according to the thickness variation of the second conductivity type semiconductor layer.

p-GaN thickness (nm) 95 110 (Ref.) 125 Integral sphere
(Median) If (mA) 65 150 65 150 65 150 Wd (nm) 454.4 453.9 454.9 454.4 454.8 454.3 Vf (V) 2.82 3.04 2.82 3.08 2.81 3.03 Po (mW) 114.3
(101.6%) 245.8 112.5
(Ref.) 240.5 113.1 244.2

In the case of a conventional semiconductor device, it is recommended that the thickness of the second conductivity type semiconductor layer 113 is generally 110 nm or more in order to ensure good electrical characteristics. However, in the semiconductor device according to the embodiment, as shown in [Table 1] and FIG. 23, when the thickness of the second conductivity type semiconductor layer 113 is from 90 nanometers to 100 nanometers, It can be seen that it is improved and detected. This is because between the light reflected from the insulating reflection layer 160 and the light generated and emitted from the active layer 112 when the thickness of the second conductivity type semiconductor layer 113 is 90 nanometers to 100 nanometers, It is interpreted that the constructive interference occurs.

For reference, although not shown in [Table 1] and FIG. 23, when the thickness of the second conductivity type semiconductor layer 113 is reduced to 90 nm or less, it was detected that the light intensity characteristic is lowered again.

Meanwhile, a plurality of semiconductor device packages according to the embodiments described above may be arrayed on a substrate, and a light guide plate, a prism sheet, a diffusion sheet, and the like, which are optical members, may be disposed on the optical path of the semiconductor device package. These semiconductor device packages, substrates, and optical members can function as light units.

Further, the display device, the indicating device, and the lighting device including the semiconductor device package according to the embodiment can be realized.

Here, the display device includes a bottom cover, a reflector disposed on the bottom cover, a light emitting module that emits light and includes a semiconductor element, a light guide plate disposed forward of the reflector and guiding light emitted from the light emitting module forward, An image signal output circuit which is connected to the display panel and supplies an image signal to the display panel; and an image signal output circuit arranged in front of the display panel, Gt; color filter < / RTI > Here, the bottom cover, the reflection plate, the light emitting module, the light guide plate, and the optical sheet may form a backlight unit.

The lighting device includes a light source module including a substrate and semiconductor devices according to the embodiments, a heat sink for dissipating heat of the light source module, and a power supply unit for processing or converting an electrical signal provided from the outside and providing the light source module can do. For example, the lighting device may include a lamp, a head lamp, or a streetlight.

The head lamp includes a light emitting module including a semiconductor element disposed on a substrate, a reflector for reflecting light emitted from the light emitting module in a predetermined direction, for example, forward, a lens for refracting light reflected by the reflector forward, And a shade that reflects the light reflected by the reflector and blocks or reflects a part of the light directed toward the lens to form a desired light distribution pattern by a designer.

24 is an exploded perspective view of the illumination device according to the embodiment.

The lighting apparatus according to the embodiment may include a cover 2100, a light source module 2200, a heat discharger 2400, a power supply unit 2600, an inner case 2700, and a socket 2800. Further, the illumination device according to the embodiment may further include at least one of the member 2300 and the holder 2500. The light source module 2200 may include a semiconductor device or a semiconductor device package according to an embodiment.

The light source module 2200 may include a light source unit 2210, a connection plate 2230, and a connector 2250. The member 2300 is disposed on the upper surface of the heat discharging body 2400 and has guide grooves 2310 through which the plurality of light source portions 2210 and the connector 2250 are inserted.

The holder 2500 blocks the receiving groove 2719 of the insulating portion 2710 of the inner case 2700. Therefore, the power supply unit 2600 housed in the insulating portion 2710 of the inner case 2700 is sealed. The holder 2500 has a guide protrusion 2510.

The power supply unit 2600 may include a protrusion 2610, a guide 2630, a base 2650, and an extension 2670. The inner case 2700 may include a molding part together with the power supply part 2600. The molding part is a hardened portion of the molding liquid so that the power supply unit 2600 can be fixed inside the inner case 2700.

The features, structures, effects and the like described in the embodiments are included in at least one embodiment and are not necessarily limited to one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments can be combined and modified by other persons having ordinary skill in the art to which the embodiments belong. Accordingly, the contents of such combinations and modifications should be construed as being included in the scope of the embodiments.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. It can be seen that the modification and application of branches are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention.

100 semiconductor device
105 substrate
110 luminescent structure
111 first conductive type semiconductor layer
112 active layer
113 second conductive semiconductor layer
120 current diffusion layer
130 ohmic contact layer
141 First electrode
142 Second electrode
150 protective layer
161 First insulating reflective layer
162 Second insulating reflective layer
163 Third insulating reflective layer
164 fourth insulating reflective layer
171 1st bonding pad
172 2nd bonding pad

Claims (9)

A light emitting structure including a first conductivity type semiconductor layer and a second conductivity type semiconductor layer;
A first electrode disposed on the first conductive semiconductor layer and electrically connected to the first conductive semiconductor layer;
A second electrode disposed on the second conductive semiconductor layer and electrically connected to the second conductive semiconductor layer;
A first insulating reflective layer disposed on the first electrode and the second electrode, the first insulating reflective layer including a first opening exposing an upper surface of the first electrode;
A second insulating reflection layer disposed on the first electrode and the second electrode so as to be spaced apart from the first insulating reflection layer and including a second opening exposing an upper surface of the second electrode;
A first bonding pad disposed on the first insulating reflective layer and electrically connected to the first electrode through the first opening;
A second bonding pad disposed on the second insulating reflection layer and spaced apart from the first bonding pad, the second bonding pad being electrically connected to the second electrode through the second opening;
Lt; / RTI >
The sum of the areas of the first bonding pads and the area of the second bonding pads is larger than the sum of the total area of the upper surface of the semiconductor element on which the first bonding pads and the second bonding pads are disposed Of the semiconductor device. The method according to claim 1,
Wherein the sum of the area of the first bonding pad and the area of the second bonding pad is greater than or equal to 30% of the total area of the semiconductor element when viewed from the upper direction of the semiconductor element. The method according to claim 1,
Wherein the first bonding pad or the second bonding pad is provided along the major axis direction of the semiconductor element at a length of x and is provided along the minor axis direction of the semiconductor element at a length of y,
Wherein the ratio of x to y is 1: 1.5 to 1: 2. The method according to claim 1,
Wherein an interval between the first bonding pad and the second bonding pad is equal to or greater than 125 micrometers and equal to or less than 300 micrometers. The method according to claim 1,
The first bonding pad or the second bonding pad is disposed at a distance of b from the adjacent side surface disposed in the major axis direction of the semiconductor element, and the length of a from the adjacent side surface disposed in the minor axis direction of the semiconductor element Lt; / RTI >
Wherein a is equal to or greater than 40 micrometers, and b is equal to or greater than 40 micrometers. The method according to claim 1,
Wherein light generated in the light emitting structure is transmitted and emitted at an area of 30% or more of the upper surface of the semiconductor element in which the first bonding pad and the second bonding pad are disposed. The method according to claim 6,
Wherein light generated in the light emitting structure is transmitted through the upper surface, the lower surface, and the four lateral directions of the semiconductor element and is emitted. The method according to claim 1,
A first region provided between the first bonding pad and the second bonding pad, a second region provided between the side surface disposed in the major axis direction of the semiconductor element and the neighboring first bonding pad or the second bonding pad, Wherein light generated in the light emitting structure is transmitted and emitted in a third region provided between a side surface of the semiconductor element in the minor axis direction and the neighboring first bonding pad or the second bonding pad. A package body including a first package electrode and a second package electrode;
A semiconductor element according to any one of claims 1 to 8 arranged on the package body;
Lt; / RTI >
The first bonding pad of the semiconductor device is electrically connected to the first package electrode,
And the second bonding pad of the semiconductor device is electrically connected to the second package electrode.

Images