KR20180067105A - Scan driver and display device using the same - Google Patents

Abstract

The present invention relates to a scan driver and a display device using the same which can reduce the circuit area by simplifying its configuration. According to an embodiment of the present invention, an N^th (N is a natural number) of the scan driver includes a first to a fifth transistor. The first transistor is controlled by a set terminal to switch the current path between the set terminal and a Q node. A second transistor is controlled by a reset terminal to switch the current path between the Q node and a power line to supply a gate off voltage. The third transistor is controlled by the Q node to switch the current path between a clock terminal and an output terminal. The fourth transistor is controlled by the output terminal to switch the current path between the output terminal and the clock terminal. The fifth transistor is controlled by the reset terminal to switch the current path between the output terminal and the power line. The set terminal is connected to a start signal line or an output terminal of a previous stage. The clock terminal and the reset terminal are connected to two clock lines among three clock lines to transmit three-phase clock signals with different phases.

Description

[0001] SCAN DRIVER AND DISPLAY DEVICE USING THE SAME [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan driver capable of reducing a circuit area by simplifying a circuit configuration and a display using the scan driver.

2. Description of the Related Art [0002] Flat panel display devices that have recently become popular as display devices include liquid crystal displays (LCDs) using liquid crystals, OLED display devices using organic light emitting diodes (OLEDs) Display devices (ElectroPhoretic Display; EPD), and the like.

A flat panel display device includes a display panel for displaying an image using a pixel array in which each pixel is independently driven by a thin film transistor (TFT), a data driver for driving data lines of the display panel, A scan driver for driving the gate lines, and the like.

The scan driver uses a shift register composed of stages for sequentially driving gate lines, and each stage is composed of a plurality of transistors. Recently, the scan driver is formed with the transistors of the pixel array to mainly use the gate-in-panel (GIP) method embedded in the display panel.

For the Narrow Bezel of the display device, a scheme has been proposed in which a node driver of the QB node and a node controller for controlling the QB node are shared by the output driver buffer of the 2-channel scan driver. However, There is a disadvantage that the number of wirings for supplying clock pulses increases as the buffer unit uses different clock pulses.

As the bezel size of the display device is reduced, the weight of the drive wiring in the scan driver becomes larger, so that a scan driver capable of reducing the number of transistors and using a small number of drive wiring is required.

The present invention provides a scan driver capable of reducing a circuit area by simplifying a circuit configuration and a display device using the same.

In the scan driver according to the embodiment of the present invention, the Nth (N is a natural number) stage is composed of the first to fifth transistors. The first transistor is controlled by the set terminal to switch the current path between the set terminal and the Q node. The second transistor is controlled by the reset terminal to switch the current path between the Q node and the power supply line supplying the gate-off voltage. The third transistor is controlled by the Q node to switch the current path between the clock terminal and the output terminal. The fourth transistor is controlled by the output terminal to switch the current path between the output terminal and the clock terminal. The fifth transistor is controlled by a reset terminal to switch the current path between the output terminal and the power supply line. The set terminal is connected to the start signal line for supplying the start signal or the output terminal of the front stage for supplying the output of the front stage. The clock terminal and the reset terminal are respectively connected to two clock lines out of three clock lines transmitting three-phase clock signals of different phases.

The start signal supplied to the set terminal or the output of the front stage is supplied with the second clock signal having the N + 1th pulse at the clock terminal and the Nth pulse of the first clock signal among the three-phase clock signals, And a third clock signal having an (N + 2) th pulse is supplied to the reset terminal.

The first transistor is connected in a diode structure between the set terminal and the Q node, and the fourth transistor is connected in a diode structure between the output terminal and the clock terminal.

In the first period, the first transistor sets the Q node to the gate-on voltage of the set signal using the set signal supplied to the set terminal. In the second period, the third and fourth transistors output the second clock signal supplied to the clock terminal through the output terminal. In the third period, the second and fifth transistors reset the third clock signal supplied to the reset terminal to the gate off voltage of the power supply line.

The second and fifth transistors according to an embodiment periodically respond to the third clock signal to reset the Q node and the output terminal to the gate off voltage of the power supply line.

The display device according to an embodiment of the present invention includes the above-described scan driver which is embedded in a non-display area of the display panel and drives the gate lines of the pixel array, and is embedded between the scan driver and the pixel array, And a light emission control driver for driving the light emission control lines.

The scan driver and the display device using the scan driver according to the embodiment of the present invention can provide a stable scan output while each stage for individually driving the gate lines has five transistors and uses a two-phase clock among three-phase clocks. Accordingly, the scan driver and the display device using the scan driver according to the embodiment of the present invention minimize the number of transistors and the number of drive wires in each stage, thereby reducing the circuit area. Therefore, the size of the bezel of the display device .

FIG. 1 is a block diagram schematically showing the configuration of some stages of a scan driver according to an embodiment of the present invention. Referring to FIG.
2 is a circuit diagram illustrating a configuration of an Nth stage of a scan driver according to an embodiment of the present invention.
3 is a driving waveform diagram of the N-th stage shown in FIG.
4 is a block diagram schematically illustrating a configuration of a display device using a scan driver according to an embodiment of the present invention.
5 is a block diagram schematically illustrating a configuration of a display device using a scan driver according to an embodiment of the present invention.
FIG. 6 is a block diagram schematically showing the configuration of some of the stages of the scan driver according to the embodiment of the present invention.
7 is a waveform diagram showing a simulation result of driving a scan driver according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram schematically showing the configuration of some stages of a scan driver according to an embodiment of the present invention. Referring to FIG.

The scan driver shown in FIG. 1 has a plurality of stages, which are connected to each other and generate a separate scan output (SCAN). For convenience, FIG. 1 shows the (N-1) th to (N + N-1] to S-ST [N + 2], and N is a natural number of 2 or more).

Hereinafter, "front stage" means any one of at least one stage located at a previous (upper) position of the stage, and "rear stage" means at least one stage Which means either.

Each stage S-ST has a set terminal S, a reset terminal R, a clock terminal CK, a power supply terminal PT, and an output terminal OUT.

The set terminal S of each stage S-ST is supplied with the set signal as the front end signal supplied from the start signal VST supplied through the start signal line SL or the output terminal OUT of the front stage.

The clock terminal CK and the reset terminal R of each stage S-ST are supplied through the first to third clock lines CL1 to CL3 and are sequentially shifted in phase while circulating three-phase clock signals CLK1 To CLK3).

For example, the N-1th stage S-ST [N-1] and the N + 1th stage S- ST [N + 1] And receives the first clock signal CLK1 to the reset terminal R. The N-th stage (S-ST [N]) and the (N + 2) -th stage (S-ST [N + 2]) receive the second clock signal CLK2 at the clock terminal CK, CLK3 are supplied to the reset terminal R.

The power supply terminal PT of each stage S-ST is supplied with the gate off voltage Voff supplied through the power supply line PL.

The output terminal OUT of each stage S-ST is connected to a gate line of the display panel to output a scan output SCAN and a set terminal of a subsequent stage to supply a scan output SCAN as a carry signal do.

FIG. 2 is a circuit diagram showing a configuration of an Nth stage (S-ST [N]) of the scan driver according to the embodiment of the present invention shown in FIG. 1, -ST [N]).

The N-th stage (S-ST [N]) shown in FIG. 2 is composed of five transistors T1 to T5. The transistors T1 to T5 use an amorphous transistor using an amorphous silicon semiconductor layer, a poly transistor using a polysilicon semiconductor layer, or an oxide transistor using a metal oxide semiconductor layer. The transistors T1 to T5 may be composed of P-channel or N-channel type transistors together with the transistors of the display panel. Hereinafter, only the case where the transistors T1 to T5 and the transistors of the display panel are composed of P-channel type transistors will be described as an example, but N-channel type transistors may also be applied.

The first transistor T1 sets the Q node to the gate on voltage Von of the set signal using the set signal supplied to the set terminal S. [ The set signal S is supplied with the start signal VST or the front end scan output SCAN [N-1] supplied from the front stage as a set signal. The first transistor T1 is connected in a diode structure between the set terminal S and the Q node and switches the current path between the set terminal S and the Q node under the control of the set terminal S. The first transistor T1 is turned on when the set signal supplied to the set terminal S is the gate on voltage Von to set the Q node to the gate on voltage Von of the set signal, And is turned off when the gate-off voltage Voff.

The second transistor T2 responds to the clock signal having the (N + 2) -th pulse supplied to the reset terminal R, for example, the third clock signal CLK3, ). The second transistor T2 switches the current path between the Q node and the power supply terminal PT under the control of the reset terminal R. The second transistor T2 is turned on when the third clock signal CLK3 supplied to the reset terminal R is the gate-on voltage Von to turn on the Q node to the gate-off voltage Voff of the power supply terminal PT. And is turned off when the third clock signal CLK3 is the gate-off voltage Voff.

The third transistor T3 is connected to the output terminal OUT in response to the clock signal having the (N + 1) th pulse supplied to the clock terminal CK in response to the control of the Q node, for example, the second clock signal CLK2. And outputs the second clock signal CLK2 as a scan output SCAN [N]. The third transistor T3 switches the current path between the clock terminal CK and the output terminal OUT under the control of the Q node. The third transistor T3 is turned on when the Q node is at the gate-on voltage Von and outputs the second clock signal CLK2 of the clock terminal CK to the scan output SCAN [N] through the output terminal OUT. And is turned off when the Q node is at the gate-off voltage Voff.

The fourth transistor T4 is responsive to the control of the output terminal OUT to output a clock signal having the (N + 1) th pulse supplied to the clock terminal CK, for example, the second clock signal CLK2 to the output terminal OUT And outputs it as a scan output (SCAN [N]). The fourth transistor T4 is connected in a diode structure between the output terminal OUT and the clock terminal CK and the current path between the output terminal OUT and the clock terminal CK is controlled by the control of the output terminal OUT. / RTI > The fourth transistor T4 is turned on when the scan output (SCAN [N]) of the output terminal OUT is the gate-on voltage Von and is connected to the output terminal OUT together with the third transistor T3, The clock signal CLK2 is output as the scan output SCAN [N] and turned off when the scan output SCAN [N] is the gate-off voltage Vff.

The fifth transistor T5 responds to the clock signal having the (N + 2) -th pulse supplied to the reset terminal R, for example, the third clock signal CLK3, and outputs the output terminal OUT to the gate- Reset to the voltage Voff. The fifth transistor T5 switches the current path between the output terminal OUT and the power supply terminal PT under the control of the reset terminal R. The fifth transistor T5 is turned on when the third clock signal CLK3 supplied to the reset terminal R is at the gate-on voltage Von so that the output terminal OUT is connected to the gate- (Voff), and is turned off when the third clock signal CLK3 is the gate-off voltage Voff.

The driving process of the N-th stage (S-ST [N]) shown in FIG. 2 with reference to the driving waveform shown in FIG. 3 will be described below.

Referring to FIG. 3, the three-phase clock signals CLK1 to CLK3 have a pulse shape in which a gate on voltage Von of 1/3 period and a gate off voltage Voff of 2/3 cycle are alternately repeated And the pulse interval of the gate-on voltage Von is sequentially shifted without overlapping. Since the transistors T1 to T5 shown in FIG. 2 are all of the P-channel type, the gate-on voltage Von is a low voltage level and the gate-off voltage Voff has a high voltage level.

3, the clock signal having the N + 1th pulse output from the Nth stage (S-ST [N]) to the scan output (SCAN [N]) is the second clock (CLK2) And the clock signal having the (+2) th pulse is the third clock (CLK3). The start signal VST or the (N-1) th previous scan output SCAN [N-1] used as the set signal is synchronized with the Nth pulse of the first clock CLK1.

The gate-on voltage Von of the start signal VST supplied as the set signal to the set terminal S or the previous scan output SCAN [-1] from the (N-1) The first transistor T1 is turned on by the pulse and the Q node is set to the gate on voltage Von of the set signal. The third transistor T3 is turned on by the Q node set to the gate-on voltage Von so that the gate-off voltage Voff of the second clock signal CLK2 becomes the gate-off voltage of the scan output SCAN [N] And is output as a voltage Voff.

During the second period t2, the first transistor T1 is turned off by the gate-off voltage Voff of the start signal VST or the scan signal SCAN [N-1] supplied as the set signal The Q node floats at the gate-on voltage (Von). Accordingly, the third transistor T3, which maintains the turn-on state, outputs the gate-on voltage Von of the second clock signal CLK2 to the gate of the scan output SCAN [N] through the output terminal OUT And outputs it as a voltage Von. At this time, the fourth transistor T4 is also turned on by the gate-on voltage Von of the scan output SCAN [N] to turn on the gate-on voltage of the second clock signal CLK2 together with the third transistor T3 Von to the output terminal OUT.

The second transistor T2 is turned on by the gate-on voltage Von of the third clock signal CLK3 supplied as a reset signal to the reset terminal R during the third period t3, The fifth transistor T5 is reset to the gate off voltage Voff of the terminal PT and the output terminal OUT is reset to the gate off voltage Voff of the power supply terminal PT. Thus, the third and fourth transistors T3 and T5 are turned off. At this time, the (N + 1) th stage (S-ST [N + 1]) outputs the third clock signal CLK3 as a scan output (SCAN [n + 1]).

During the fourth and fifth periods t4 and t5 the Q node maintains the gate off voltage Voff and the third and fourth transistors T3 and T4 remain in the turn- (Voff) state.

Then, the third to fifth periods (t3 to t5) described above are repeated, and the second and fifth transistors T2 are periodically turned on by the third clock signal CLK3, It is possible to prevent output failure such as ripple by resetting the output terminal OUT to the gate off voltage Voff of the power supply terminal PT. The third to fifth periods t3 to t5 are repeated until the set signal of the gate-on voltage Von is supplied in the next frame, so that the output terminal OUT maintains the gate-off voltage Voff.

As described above, in the scan driver according to the embodiment of the present invention, each stage (S-ST) is composed of five transistors (T1 to T5), the drive shafts include three clock lines (CL1 to CL3) (PL) and the start signal line (SL), so that the circuit area occupied by the scan driver can be minimized.

4 is a block diagram schematically illustrating a configuration of a display device having a scan driver according to an exemplary embodiment of the present invention.

4 includes a display panel 400 including a pixel array 100 and a scan driver 200, a data driver 500, a timing controller 600, and a power unit (not shown).

The timing controller 600 inputs the basic timing control signal together with the video data supplied from the host set. The timing controller 600 modulates the image data using various data processing methods for image quality compensation and power consumption reduction, and outputs the modulated image data to the data driver 500.

The timing controller 600 generates a data control signal for controlling the operation timing of the data driver 500 and a gate control signal for controlling the operation timing of the scan driver 200 using the basic timing control signal, 500 and supplies the gate driver 200 with a gate control signal.

A level shifter may be additionally provided between the timing controller 600 and the scan driver 200, and the level shifter may be incorporated in the power supply unit. The level shifter controls the gate control voltage (gate transistor) of the pixel array 100 to the gate-on voltage (gate-low voltage) and the gate-off voltage Level (gate high voltage) and supplies it to the scan driver 200.

The data driver 500 receives data control signals and image data from the timing controller 600. The data driver 500 is driven in accordance with the data control signal to divide the reference gamma voltage supplied from the gamma voltage generator into gray voltages corresponding to the gray scale values of the data, and then, using the subdivided gray voltages, Converts the image data into analog image data signals, and supplies the analog image data signals to the data lines of the display panel 400, respectively.

The data driver 500 includes a plurality of data drive ICs for dividing and driving the data lines of the display panel 400. Each data drive IC includes a tape carrier package (TCP), a chip on film (COF) Circuit or the like may be mounted on a circuit film such as a tape or the like to be attached to the display panel 400 by a tape automatic bonding (TAB) method or on a display panel 400 by a COG (Chip On Glass) method.

The display panel 400 displays an image through the pixel array 100 in which pixels are arranged in a matrix. Each pixel of the pixel array 100 typically has a combination of R (Red), G (Green) and B (Blue) sub-pixels to implement a desired color and further includes a W do. Each sub-pixel is independently driven by a transistor. As the display panel 400, a liquid crystal panel (LCD), an organic light emitting diode (OLED) panel, or the like can be used.

The scan driver 200 is formed with the pixel array 100 and is composed of a GIP type embedded in a non-display area of the display panel 400, that is, a non-display area adjacent to one side or both sides of the pixel array 100. The scan driver according to the embodiment described above with reference to FIGS. 1 to 3 is applied to the scan driver 200 that drives the gate lines of the pixel array 100 individually. Accordingly, the scan driver 200 can minimize the number of transistors of each stage (S-ST) to five (T1 to T5) and minimize the number of drive wiring lines to five (CL1 to CL3, PL, SL) , The size of the bezel where the scan driver 200 is located can be minimized.

FIG. 5 is a block diagram schematically showing the configuration of another display device incorporating a scan driver according to an embodiment of the present invention. FIG. 6 is a diagram illustrating a configuration of a scan driver and a light emission control (EM) Fig.

The display device of FIG. 5 further includes an emission control (EM) driver 300 between the scan driver 200 and the pixel array 100, as compared with the display device of FIG.

The pixel circuit for driving the OLED element in each pixel of the pixel array 100 includes a driving transistor for driving the OLED element, a storage capacitor for storing a driving voltage of the driving transistor, and a driving voltage for supplying a driving voltage corresponding to the data signal to the storage capacitor And an EM transistor which is connected between the driving transistor and the OLED element and controls the light emitting period of the OLED element. In this case, the switching transistor of each pixel circuit is controlled by the gate line connected to the scan driver 200, and the EM transistor is controlled by the emission control line connected to the EM driver 300. [

6, the scan output (SCAN [N]) of the Nth stage (S-ST [N]) in the scan driver 200 is divided into the Nth pixel P [N] (SCAN [N + 1]) of the (N + 1) -th stage (S [N + 1] And the (N + 2) -th pixel.

The output EM [M] of the Mth stage EM-ST [M] in the EM driver 300 is supplied to the Nth pixel P [N] and the N + 1th pixel P [N + 1] .

As the scan driver 200, a scan driver according to the embodiment described above with reference to FIGS. 1 to 3 is applied. Accordingly, the scan driver 200 can minimize the number of transistors of each stage (S-ST) to five (T1 to T5) and minimize the number of drive wiring lines to five (CL1 to CL3, PL, SL) The scan driver 200, and the EM driver 300 may be minimized.

7 is a waveform diagram showing a simulation result of driving a scan driver according to an embodiment of the present invention.

Referring to FIG. 7, a scan driver (not shown) according to an embodiment of the present invention may be used in which the temperature mode is changed to the SS mode (-20 ° C), the TT mode (27 ° C), and the FF mode As a result, it can be seen that a normal output occurs at both the rising time and the polling time.

As such, since the number of transistors and the number of driving wirings can be reduced in the scan driver and the display device using the scan driver according to the embodiment of the present invention, the size of the bezel region of the display panel in which the scan driver is embedded can be reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: pixel array 200: scan driver
300: emission control driver 400: display panel
500: Data driver 600: Timing controller

Claims (7)

In a scan driver having a plurality of stages connected to each other in a dependent manner,
The Nth (N is a natural number)
A first transistor controlled by a set terminal to switch a current path between the set terminal and the Q node;
A second transistor which is controlled by a reset terminal to switch a current path between the Q node and a power supply line which supplies a gate-off voltage;
A third transistor controlled by the Q node to switch a current path between a clock terminal and an output terminal;
A fourth transistor controlled by the output terminal to switch a current path between the output terminal and the clock terminal,
And a fifth transistor controlled by the reset terminal to switch a current path between the output terminal and the power supply line,
The set terminal is connected to an output terminal of a start signal line for supplying a start signal or a front stage for supplying an output of the front stage,
Wherein the clock terminal and the reset terminal are respectively connected to two clock lines of three clock lines transmitting a three-phase clock signal having different phases. The method according to claim 1,
The three-phase clock signals have a form in which a pulse of 1/3 period is sequentially shifted and circulated,
The start signal supplied to the set terminal or the output of the front stage is synchronized with the Nth pulse of the first clock signal among the three phase clock signals,
A second clock signal having an (N + 1) -th pulse of the three-phase clock signals is supplied to the clock terminal,
And a third clock signal having an (N + 2) -th pulse of the three-phase clock signals is supplied to the reset terminal. The method of claim 2,
The first transistor is connected in a diode structure between the set terminal and the Q node,
And the fourth transistor is connected in a diode structure between the output terminal and the clock terminal. The method of claim 3,
In the first period, the first transistor sets the Q node to the gate-on voltage of the set signal using a set signal supplied to the set terminal,
In the second period, the third and fourth transistors output the second clock signal supplied to the clock terminal through the output terminal,
And in the third period, the second and fifth transistors reset the third clock signal supplied to the reset terminal to the gate off voltage of the power supply line. The method of claim 4,
And the second and fifth transistors periodically respond to the third clock signal to reset the Q node and the output terminal to a gate off voltage of the power supply line. A display panel including a display region in which the pixel array is located and a non-display region surrounding the display region;
The display device according to any one of claims 1 to 5, which is embedded in a non-display area of the display panel and drives gate lines of the pixel array. The method of claim 6,
And a light emission control driver embedded between the scan driver and the pixel array in a non-display area of the display panel, the light emission control driver driving the light emission control lines of the pixel array.

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