KR20180036425A - Shift register and display device using the same - Google Patents

Abstract

The present invention relates to a shift register capable of increasing reliability by reducing a delay of scan output. According to one embodiment of the present invention, in the shift register, each stage comprises: a set unit controlled by a set terminal to charge a Q node; a reset unit controlled by a reset terminal to discharge the Q node; a pull-up unit controlled by the Q node, and including a first pull-up TFT for outputting a first clock, supplied to a first clock terminal, as a scan output through an output terminal, and a second pull-up TFT for outputting a second clock, supplied to a second clock terminal, as a carry signal through a carry terminal; a pull-down unit controlled by a third clock terminal to which a third clock is supplied and including a first pull-down TFT for outputting a first gate low voltage to the output terminal and a second pull-down TFT for outputting a second gate low voltage, lower than the first gate low voltage, to the carry terminal; a scan capacitor connected between the Q node and the output terminal; and a carry capacitor connected between the Q node and the carry terminal.

Description

[0001] SHIFT REGISTER AND DISPLAY DEVICE USING THE SAME [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register capable of improving reliability by reducing the delay of a scan output and a display using the shift register.

2. Description of the Related Art [0002] Flat panel display devices that have recently become popular as display devices include liquid crystal displays (LCDs) using liquid crystals, OLED display devices using organic light emitting diodes (OLEDs) Display devices (ElectroPhoretic Display; EPD), and the like.

A flat panel display device includes a display panel for displaying an image of a pixel array in which each pixel is independently driven by a thin film transistor (TFT), a panel driver for driving the display panel, a timing controller for controlling the panel driver . The panel driver includes a gate driver for driving the gate lines of the display panel, and a data driver for driving the data lines of the display panel.

The gate driver includes a shift register composed of stages for separately driving gate lines of the display panel, and each stage is composed of a plurality of TFTs. Recently, the gate driver is formed together with the TFT array of the pixel array to mainly use a gate-in-panel (GIP) method built in the display panel.

In each stage, the pull-up TFT operates during the pull-up period under the control of the Q node, outputs the clock through the output terminal to the scan output, and outputs the carry signal through the carry terminal. Since the scan output is connected to the gate line of the pixel array, the RC load is large and basically, the delay of the scan output is large.

In order to solve this problem, there is applied a method of improving the delay of the scan output by providing a capacitor between the Q node and the output terminal of the pull-up TFT so as to raise the voltage of the Q node.

However, as the display device has a higher resolution, the RC load of the scan output increases and the delay of the scan output increases, so that the data charging time is shortened.

The present invention provides a shift register capable of improving the reliability by reducing the delay of the scan output and a display device using the shift register.

In the shift register according to the embodiment of the present invention, each stage is controlled by a set terminal to set up a Q node; A reset unit controlled by the reset terminal to discharge the Q node; A first pull-up TFT which is controlled by a Q node and outputs a first clock supplied to a first clock terminal to a scan output through an output terminal; and a second pull-up TFT which supplies a second clock supplied to the second clock terminal to a carry signal A pull-up section having a second pull-up TFT for outputting the pull-up TFT; A first pull down TFT controlled by a third clock terminal supplied with a third clock and outputting a first gate low voltage to an output terminal and a second pull down TFT outputting a second gate low voltage lower than the first gate low voltage to a carry terminal A pull-down section having a second pull-down TFT; A scan capacitor connected between the Q node and the output terminal, and a carry capacitor connected between the Q node and the carry terminal.

Each stage according to an embodiment is controlled by a second clock terminal and a carry terminal so that during a second period except for a first period during which the pull-up unit outputs the first clock and the second clock, An inverter output node; A first noise eliminator controlled by the inverter output node to discharge the Q node to a second gate off voltage; And a second noise canceling unit controlled by the inverter output node to discharge the output terminal and the carry terminal to the first and second gate-off voltages, respectively.

The pull-up unit may include a first pull-up TFT controlled by the Q node and outputting a first clock supplied to a first clock terminal to a scan output through an output terminal, And a second pull-up TFT for outputting the second pull-up TFT.

The inverter according to the embodiment is controlled by the first clock terminal and the carry terminal so that the inverter output synchronized with the first clock is output to the inverter output node during the second period except for the first period in which the pull- Output.

Each stage according to an embodiment is controlled by a stabilization signal supplied in the blanking period of the vertical synchronization signal and discharges the Q node, the carry terminal, the inverter output node, and the control node in the inverter to a second gate off voltage And a stabilizing unit for discharging the output terminal to the first gate-off voltage.

The display device according to an exemplary embodiment includes the above-described shift register which is incorporated in a non-display area of the display panel and independently drives the gate lines of the display panel.

The shift register and the display device using the same according to an embodiment of the present invention include a capacitor between a Q node of a second pull-up TFT for outputting a carry signal and a carry terminal having a smaller RC load than an output terminal, By shortening the rising time, the rising delay of the scan output output through the first pull-up TFT can be reduced.

A shift register according to an embodiment of the present invention and a display device using the same include first and second capacitors between a Q node and an output terminal of a first pull-up TFT and a Q node and a carry terminal of a second pull- The first pull-up TFT outputs the clock having the Nth phase as a scan output and the second pull-up TFT outputs a clock having the (N + 1) th phase as a carry signal, thereby delaying the polling time of the Q node and the carry signal, Lt; / RTI >

Therefore, the shift register according to the embodiment of the present invention and the display device using the same can improve the reliability of the scan output even when the high-resolution model is driven at high speed by improving the rising or falling delay of the scan output. The life can be increased.

1 is a block diagram schematically illustrating a configuration of a display device incorporating a shift register according to an embodiment of the present invention.
2 is a circuit diagram illustrating the configuration of an Nth stage in a shift register according to an embodiment of the present invention.
3 is a driving waveform diagram of the N-th stage shown in FIG.
FIG. 4 is a diagram illustrating a simulation result of driving waveforms when a stage according to an embodiment of the present invention includes a scan capacitor and a carry capacitor. FIG.
5 is a circuit diagram illustrating a configuration of an Nth stage in a shift register according to an embodiment of the present invention.
6 is a driving waveform diagram of the N-th stage shown in FIG.
FIG. 7 is a diagram illustrating simulation results of driving waveforms when a stage according to an embodiment of the present invention includes a dual capacitor and only a scan capacitor. FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram schematically showing a configuration of a display device incorporating a shift register according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a stage of a shift register according to an embodiment of the present invention, 3 is a driving waveform diagram of the stage shown in Fig.

1 includes a display panel 500 including a pixel array 600 and a gate driver 400, a data driver 300, a timing controller 100, and a power supply (not shown).

The timing controller 100 inputs the basic timing control signal together with the video data supplied from the host set. The timing controller 100 modulates the image data using various data processing methods for image quality compensation and power consumption reduction, and outputs the modulated image data to the data driver 300.

The timing controller 100 generates a data control signal for controlling the operation timing of the data driver 300 and a gate control signal for controlling the operation timing of the gate driver 400 using the basic timing control signal, 300 and supplies a gate control signal to the gate driver 400. [ The basic timing control signal may include a dot clock signal and a data enable signal, and may further include a horizontal synchronization signal and a vertical synchronization signal. The data control signal includes a source start pulse and a source shift clock for controlling the latch timing of the video data in the data driver 300 and a source output enable signal for controlling the output period of the video data signal. (Source Output Enable) signal. The gate control signal includes a gate start pulse for controlling the operation timing of the gate driver 400 and a gate clock for use as an output signal or a shift control signal.

A level shifter LS may be additionally provided between the timing controller 100 and the gate driver 400 and the level shifter 200 may be incorporated in a power supply unit. The level shifter 200 outputs a gate control signal from the timing controller 100, that is, a gate start pulse and a TTL (transistor transistor logic) voltage of clocks to a gate high voltage for driving the TFT of the pixel array 600 And gate-off voltage (gate-off voltage), and supplies the level-shifted voltage to the gate driver 400.

The data driver 300 receives data control signals and image data from the timing controller 100. The data driver 300 is driven in accordance with the data control signal to divide the set of reference gamma voltages supplied from the gamma voltage generator into gradation voltages corresponding to the gradation values of the data, and then, using the subdivided gradation voltages, Converts the image data into analog image data signals, and supplies the analog image data signals to the data lines of the display panel 500, respectively.

The data driver 300 includes a plurality of data driver ICs for dividing and driving the data lines of the display panel 500. Each data driver IC includes a tape carrier package (TCP), a chip on film (COF) Circuit or the like to be mounted on a display panel 500 by a tape automatic bonding (TAB) method or a COG (Chip On Glass) method on a display panel 500.

The display panel 500 displays an image through a pixel array 600 in which pixels are arranged in a matrix. Each pixel of the pixel array 600 typically has a combination of R (Red), G (Green), and B (Blue) sub-pixels to implement a desired color and further includes a W do. Each sub-pixel is independently driven by a TFT. As the TFT, an amorphous TFT using an amorphous silicon semiconductor layer, a poly TFT using a polysilicon semiconductor layer, or an oxide TFT using a metal oxide semiconductor layer is used. As the display panel 500, a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an electrophoretic display (EPD), or the like can be used.

The gate driver 400 includes a GIP type shift register embedded in a non-display area of the display panel 500, that is, a non-display area adjacent to one side or both sides of the pixel array 600. The shift register includes a plurality of stages ST1, ST2, ST3, etc. that individually drive the gate lines of the pixel array 600 and are connected to each other in a dependent manner. Each stage ST includes a TFT array of the pixel array 600 Together with a plurality of TFTs formed on the substrate. The TFTs constituting each stage use an amorphous TFT, a poly TFT, or an oxide TFT.

Each stage ST is set by a start signal or a preceding carry signal supplied from a preceding stage, and outputs the clock as a scan output and a carry signal. Each stage ST is reset by a reset signal or a subsequent carry signal supplied from a subsequent stage to output a gate off voltage of the scan output and the carry signal.

Hereinafter, "front stage" means any one of at least one stage located at a previous (upper) position of the stage, and "rear stage" means at least one stage Which means either.

2, the Nth (N is a natural number) stage includes a set unit 410, a reset unit 420, a pullup unit 430, a pull down unit 440, a first noise removing unit 450, A noise removing unit 460, a stabilizing unit 470, and an inverter 480.

The Nth (N is a natural number) stage is supplied with a plurality of clock signals among i-phase (i is an even number) clock signals having different phases. For example, as shown in FIG. 3, the N-th stage is supplied with two clock signals CLK1 to CLK8 that do not overlap with each other among the eight-phase clock signals CLK1 to CLK8 whose phases are sequentially delayed and the high- Can receive.

Referring to FIG. 3, in each of the 8-phase clock signals CLK1 to CLK8, the high logic (gate-on voltage) period of the 4H period and the low logic (gate-off voltage) period of the 4H period are alternately repeated. The 8-phase clock signals CLK1 to CLK8 are sequentially phase delayed by the 1H period in the high logic period, and each of the 3H, 2H, and 1H periods of the high logic period is synchronized with the high logic period of each of the adjacent clocks Overlapping. Since the 8-phase clock signals CLK1 to CLK8 are sequentially output to the scan output Gout and each scan output Gout has a high period of the 4H period, sufficient charge time can be provided in high-speed operation. The clock having the Nth phase and the clock having the (N + 4) th phase, for example, the first clock CLK and the fifth clock CLK in the 8-phase clock signals CLK1 through CLK8 are inverted from each other .

3 shows a case where the clock signal CLK (N) having the Nth phase output from the scan output (Gout (N)) and the carry signal (CRY (N)) in the Nth stage is the fifth clock (CLK5) . (N-4) th previous carry signal CRY (N-4) used as the set signal and the (N + 4) < th > The clock CLK (N + 4) having the N + 4th phase controlling the pull-down unit 440 and the signal CRY (N + 4) do not overlap with the high period.

The set unit 410 responds to the control of the set terminal S to which the start signal or the (N-4) th carry signal CRY (N-4) supplied from the (N-4) (Charges) the Q node to the high voltage of the set signal. For convenience sake, the case where the set terminal S is supplied with the N-4th carry signal CRY (N-4) as a set signal will be described. The set portion 410 includes at least one set TFT (TS). The set TFT (TS) has a diode structure in which a gate electrode and a drain electrode are connected to a set terminal (S), and a source electrode is connected to a Q node. The set TFT TS is turned on during the high voltage period t1 of the N-4th carry signal CRY (N-4) supplied as the set signal to set the Q node to the N-4th carry signal CRY (N -4)).

The reset section 420 responds to the control of the reset terminal R to which the reset pulse or the (N + 4) th carry signal CRY (N + 4) supplied from the (N + (Discharges) a node, an output terminal OUT for outputting the scan output Gout (N), and a carry terminal CR for outputting the carry signal CRY (N). For convenience sake, the case where the N + 4th carry signal (CRY (N + 4)) is supplied as the reset signal to the reset terminal R will be described. The reset section 420 includes first to third reset TFTs Trs1, Trs2 and Trs3 which are controlled by a reset signal CRY (N + 4) to reset the Q node and the output terminal OUT, respectively. The first to third reset TFTs Trs1, Trs2 and Trs3 are simultaneously turned on during the high voltage period t3 of the (N + 4) th carry signal CRY (N + 4) supplied as the reset signal. The first reset TFT Trs1 discharges the Q node to the low potential voltage VSS. The second reset TFT Trs2 discharges the output terminal OUT to the gate low voltage VGL. The third reset TFT Trs3 discharges the carry terminal CR to the low potential voltage VSS.

Up unit 430 is pulled up by the control of the Q node to output the clock signal CLK (N) having the Nth phase supplied to the first clock terminal CK1 to the scan output Gout (N) And outputs it as a carry signal (CRY (N)) along with the output box. The pull-up section 430 includes first and second pull-up TFTs Tpu1 and Tpu2. In the first pull-up TFT (Tpu1), a gate electrode is connected to the Q node, a drain electrode is connected to the first clock terminal (CK1), and a source electrode is connected to the output terminal (OUT). In the second pull-up TFT Tpu2, a gate electrode is connected to the Q node, a drain electrode is connected to the first clock terminal CK1, and a source electrode is connected to the carry terminal CR. The first pull-up TFT Tpu1 is turned on by the high voltage of the Q node to output the clock signal CLK (N) having the Nth phase to the scan output Gout (N) through the output terminal OUT And the second pull-up TFT Tpu2 is turned on by the high voltage of the Q node to output the clock signal CLK (N) having the Nth phase to the carry signal CRY (N) through the carry terminal CR. . The first and second pull-up TFTs Tpu1 and Tpu2 are turned on during the high voltage period t1 and t2 of the Q node and the clock signal CLK (N) having the Nth phase in the first period t1, Of the clock signal CLK (N) having the Nth phase in the second period t2 is output as the low voltage of the scan output (Gout (N)) and the carry signal (CRY And outputs the voltage to the high voltage of the scan output (Gout (N)) and the carry signal (CRY (N)).

Down section 440 is pulled down under the control of the second clock terminal CK2 to which the clock signal CLK (N + 4) having the (N + 4) th phase is supplied and is supplied to the output terminal OUT and the carry terminal CR, And outputs the gate low voltage VGL and the low potential voltage VSS, respectively. The pull-down section 440 includes first and second pull-down TFTs Tpd1 and Tpd2. The first pull-down TFT Tpd1 has a gate electrode connected to the second clock terminal CK2, a drain electrode connected to the output terminal OUT, and a source electrode PT1 connected to the supply terminal PT1 of the gate low voltage VGL Respectively. The second pull-down TFT Tpd2 has a gate electrode connected to the second clock terminal CK2, a drain electrode connected to the carry terminal CR and a source electrode PT connected to the supply terminal PT2 of the low voltage VSS Respectively. The first pull-down TFT Tpd1 is turned on during the third period t3 by the high voltage of the clock signal CLK (N + 4) CLK1 having the (N + 4) th phase to turn on the gate low voltage VGL And the second pull-down TFT Tpd2 outputs the low voltage of the scan output Gout (N) by the high voltage of the clock signal CLK (N + 4): CLK4 having the (N + 4) (t3) to output the low potential voltage VSS as a low voltage of the carry signal CRY (N). The clock signal CLK (N + 4) having the N + 4th phase supplied to the second clock terminal CK2 is supplied to the clock signal CLK (N) supplied to the first clock terminal CK1, ) And an inverted phase.

The inverter 480 is controlled by the first clock terminal CK1 and the carry terminal CR to which the clock signal CLK (N) having the Nth phase is supplied and the pull-up unit 430 has the Nth phase During the remaining pull-down period except for the pull-up period t2 in which the clock signal CLK (N) is output as the scan output Gout (N) and the carry signal CRY (N) (Vinv (N)) which is the same as the inverter output node VN (CLK (N)).

The inverter 480 includes the first to fourth inverter TFTs Ti1 to Ti4. The first inverter TFT Ti1 has a diode structure in which a gate electrode and a drain electrode are connected to a first clock terminal CK to which a clock signal CLK (N) having an Nth phase is supplied, Is connected to the source electrode. The second inverter TFT (Ti2) has a gate electrode connected to the control node CN, a drain electrode connected to the first clock terminal (CK1), and a source electrode connected to the inverter output node (VN). In the third inverter TFT (Ti3), the gate electrode is connected to the carry terminal CR, the drain electrode is connected to the control node CN, and the source electrode is connected to the supply terminal PT2 of the low potential voltage VSS. In the fourth inverter TFT (Ti4), the gate electrode is connected to the carry terminal CR, the drain electrode is connected to the inverter output node VN, and the source electrode is connected to the supply terminal PT2 of the low potential voltage VSS .

The first inverter TFT Ti1 charges the control node CN with a high voltage of the clock signal CLK (N) having the Nth phase and supplies the high voltage of the second inverter TFT Ti2 are turned on to output the clock signal CLK (N) having the Nth phase to the inverter output Vinv (N). The third and fourth inverter TFTs Ti3 are turned on by the carry signal CRY (N) to discharge the control node CN and the inverter output node VN to the low potential voltage VSS. Therefore, even if the first and second inverter TFTs Ti1 and Ti2 are turned on during the pull-up period t2 during which the pull-up unit 430 outputs the clock signal CLK (N) having the Nth phase, - The inverter output Vinv (N) outputs the low potential voltage VSS by the turned-on third and fourth inverter TFTs Ti3 and Ti4.

The first noise eliminator 450 discharges the Q node to the low potential voltage VSS in response to the control of the inverter output node VN to which the Nth inverter output Vinv (N) is supplied. The first noise removing unit 450 includes at least one first noise removing TFT (Tnq). The first noise removing TFT Tnq has a gate electrode connected to the inverter output node VN, a drain connected to the Q node, and a source electrode connected to the low potential voltage supply terminal PT2. The first noise removing TFT Tnq is turned on every time a high voltage of the N-th inverter output Vinv (N) is supplied in synchronization with the clock signal CLK (N) having the N-th phase during the pull-down period By discharging the Q node to the low potential voltage VSS, the ripple of the Q node due to the coupling of the clock signal CLK (N) having the Nth phase can be removed.

The second noise eliminator 460 discharges the carry terminal CR and the output terminal OUT in response to control of the inverter output node VN to which the Nth inverter output Vinv (N) is supplied. The second noise eliminator 460 includes a 2-1 noise removing TFT (Tnc) controlled by the Nth inverter output Vinv (N) to discharge the carry terminal CR to the low electric potential voltage VSS, And a second -2 noise removing TFT (Tno) controlled by the Nth inverter output Vinv (N) to discharge the output terminal OUT to the gate low voltage VGL. Thus, every time a high voltage of the N-th inverter output Vinv (N) is supplied in synchronization with the clock signal CLK (N) having the N-th phase during the pull-down period, And the 2-2 noise removing TFT Tno are turned on to remove the multiple outputs of the carry signal CRY (N) and the scan output Gout (N).

The stabilization unit 470 is responsive to the stabilization signal Vstable for resetting the Q node, the carry terminal CR, the output terminal OUT, the inverter output node VN, and the inverter 480 control node CN, 1 to 5th stabilization TFTs Tst1 to Tst5. The first to fifth stabilization TFTs Tst1 to Tst5 are simultaneously turned on by the stabilization signal Vstable supplied to the stabilization terminal ST every vertical blanking period of the vertical synchronization signal. The first stabilizing TFT Tst1 discharges the Q node to the low potential voltage VSS and the second stabilizing TFT Tst2 discharges the carry terminal CR to the low potential VSS, Tst3 discharge the output terminal OUT to the gate low voltage VGL and the fourth stabilization TFT Tst4 discharges the inverter output node VN to the low potential voltage VSS and the fifth stabilization TFT Tst5 ) Initializes all the main nodes of the stage by discharging the control node CN of the inverter 480 to the low potential voltage VSS.

The gate-low voltage VGL and the low-potential voltage VSS supplied to each stage can be respectively expressed by the first and second gate-off voltages with a low potential voltage of negative polarity capable of turning off the TFT. The low-potential voltage VSS is a second gate-off voltage used for the carry signal, and a gate-low voltage VGL used for the scan output, that is, a voltage lower than the first gate-off voltage is used. Accordingly, the low potential voltage (VSS) of the carry signal at another stage using the carry signal as a control signal such as a set signal or a reset signal can reduce the leakage current by stably turning off the TFT concerned.

Each stage has a carry capacitor CBc connected between the gate electrode and the source electrode of the second pull-up TFT (Tpu2), that is, between the Q node and the carry terminal CR. The carry capacitor CBc amplifies the high voltage of the Q node when the second pull-up TFT Tpu2 is pulled up by the control of the Q node to output a high voltage of the clock signal CLK (N) Rising time can be reduced. As a result, the first pull-up TFT Tpu1 supplies the high voltage of the clock signal CLK (N) to the scan output Gout (N) faster due to the rapid rise of the Q node voltage, N) can be reduced.

The carry capacitor CBc is connected to the carry terminal CR having a small RC load relative to the output terminal OUT for outputting the scan output Gout (N), thereby shortening the rising time of the voltage amplified at the Q node. In other words, in comparison with the scan capacitor CBo between the gate electrode (Q node) and the source electrode (output terminal) of the first pull-up TFT (Tpu1) shown by a dotted line in Fig. 2, The carry capacitor CBc has a very small RC load because the capacitance R and the capacitance C are small. For example, the RC load on the carry terminal CR is only 0.1% of the RC load on the output terminal OUT. As described above, the carry capacitor CBc having a relatively small RC load has a voltage change of the clock CLK (N) having the Nth phase output to the carry terminal CR via the second pull-up TFT Tpu2 , The rising time of the Q node voltage can be shortened when the voltage of the floating Q node is amplified. As a result, the carry capacitor CBc with a very small RC load can reduce the rising delay of the scan output Gout (N), as compared to the relatively large scan capacitor CBo of the RC load.

FIG. 4 is a diagram illustrating a simulation result of driving waveforms when a stage according to an embodiment of the present invention includes a scan capacitor and a carry capacitor. FIG.

Referring to FIG. 4, when the stage has a carry capacitor CBc having a small RC load (solid line), the case where the RC load has a relatively large scan capacitor CBo (dotted line) It can be seen that the voltage of the Q node and the rising time of the scan output Gout (N) are decreased during the pull-up period, and the rising time of the carry output (CRY (N)) is also somewhat reduced.

5 is a circuit diagram showing a configuration of an Nth stage in a shift register according to an embodiment of the present invention, and FIG. 6 is a driving waveform diagram of an Nth stage shown in FIG.

In contrast to the N-th stage shown in FIG. 2, the pull-up unit 432 of the N-th stage shown in FIG. 5 includes a dual capacitor composed of a scan capacitor CBo and a carry capacitor CBc, The clock CLK (N) supplied to the first pull-up TFT Tpu1 is different from the clock CLK (N + 1) supplied to the second pull-up TFT Tpu2 and the inverter 482, (N + 3) th rear carry signal CRY (N + 4) supplied from the (N + 3) th rear stage is supplied to the reset terminal R and the remaining components are the same, Is omitted.

5 includes a scan capacitor CBo connected between the Q node and the output terminal OUT of the first pull-up TFT Tpu1, a Q node of the second pull-up TFT Tpu2, And a carry capacitor CBc connected between the terminals CR.

The clock signal CLK (N + 1) (N + 1) having the N + 1th phase which is supplied to the second pull-up TFT Tpu2 through the first-second clock terminal CK12 and output as the carry signal CRY (For example, CLK6) is compared with the clock signal CLK (N) (for example, CLK5) supplied to the first pull-up TFT Tpu1 and having the Nth phase output to the scan output Gout (N) , The phase is delayed by 1 H period and the high period of 3H overlaps with each other as shown in FIG.

The first pull-up TFT Tpu1 outputs the clock CLK (N) having the N-th phase from the 1-1th clock terminal CK11 to the scan output Gout (N) in response to the control of the Q-node On the other hand, the second pull-up TFT Tpu2 outputs the clock CLK (N + 1) having the (N + 1) th phase as the carry signal CRY (N). The inverter 482 also uses the clock CLK (N + 1) (for example, CLK (N + 1)) having the N + 1th phase during the pull down period using the clock CLK (Vinv (N)) synchronized with the inverter output Vinv (N).

The clock signal CLK (N) having the Nth phase by outputting the clock signal CLK (N + 1) with the N + 1th phase as the carry signal CRY (N) by the second pull-up TFT Tpu2, The polling time of the carry signal CRY (N) can be delayed within the 1H period as shown in Fig. 6, as compared with the case where the carry signal CRY (N) is output as the carry signal CRY Accordingly, the polling time of the Q node is delayed by the coupling of the carry capacitor CBc, and the turn-on time (pull-up time) of the first and second pull-up TFTs Tpu1 and Tpu2 can be further secured. Accordingly, the clock signal (CLK (N)) having the Nth phase transitioned from the high level to the low level during the polling time of the Q node is delayed by the scan output (Gout (N)), the polling time of the scan output (Gout (N)) can be reduced. The reset unit 420 controlled by the (N + 3) th succeeding carry signal CRY (N + 4) discharges the Q node and the output terminal OUT and the carry terminal CR, thereby generating the scan output Gout ) Can be reduced.

FIG. 7 is a diagram illustrating a simulation result of driving waveforms when a stage according to an embodiment of the present invention includes a dual capacitor and only a scan capacitor. FIG.

5, a stage according to an embodiment includes a dual capacitor and outputs a clock signal CLK (N) having an N-th phase as a scan output Gout (N) (Solid line) when the clock signal CLK (N + 1) having the nth phase is used as the carry signal CRY (N), only the scan capacitor CBo is provided as shown by the dotted line in FIG. The polling time of the Q node voltage and the carry time of the carry signal CRY (N (N)) are compared with the case of using the clock signal CLK (N) as the scan output Gout (N) and the carry signal (CRY ) Is delayed and the polling time of the scan output Gout (N), that is, the polling delay is decreased. When the polling delay of the scan output (Gout (N)) is reduced, data interference can be prevented at high-speed driving of a high-resolution model.

7, the clock signal CLK (N + 1) having the (N + 1) th phase is output as the scan output Gout (N) The time required for the maximum voltage to be applied to the Q node is longer than the case where the voltage of the Q node rises in two steps (the dotted line) by the rise of the voltage of the Q node by CLK (N ) And CLK (N + 1), and as a result, the stress of the Q node is reduced and the lifetime can be improved.

As described above, the shift register according to the embodiment of the present invention and the display device using the shift register can improve the reliability of the scan output by improving the rising delay or the polling delay of the scan output. Therefore, Can increase the lifetime with reliability.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: timing controller 200: level shifter (LS)
300: Data driver 400: Gate driver
500: display panel 600: pixel array
410: SET unit 420:
430, 432: pull-up part 440: pull-down part
450: first noise removing unit 460: second noise removing unit
470: Stabilizer 480, 482: Inverter

Claims (8)

In a shift register having a plurality of stages connected to each other in a dependent manner,
In each stage,
A set portion that is controlled by the set terminal to charge the Q node;
A reset unit controlled by a reset terminal to discharge the Q node;
A first pull-up TFT which is controlled by the Q node and outputs a first clock supplied to a first clock terminal through an output terminal as a scan output; and a second pull-up TFT which carries a second clock supplied to the second clock terminal through a carry terminal, A pull-up section having a second pull-up TFT outputting a signal;
A first pull-down TFT controlled by a third clock terminal supplied with a third clock and outputting a first gate low voltage to the output terminal, and a second pull-down TFT controlled by a second gate low voltage A pull-down section having a second pull-down TFT for outputting the pull-down TFT;
A scan capacitor connected between the Q node and the output terminal,
And a carry capacitor connected between the Q node and the carry terminal. The method according to claim 1,
Each of the stages
And a second clock terminal and a carry terminal for outputting an inverter output synchronized with the second clock during a second period except for a first period in which the pull-up unit outputs the first clock and the second clock, An inverter for outputting an output signal;
A first noise eliminator controlled by the inverter output node to discharge the Q node to the second gate off voltage;
And a second noise eliminator controlled by the inverter output node to discharge the output terminal and the carry terminal to the first and second gate-off voltages, respectively. The method of claim 2,
Each of the stages
Wherein the control signal is controlled by a stabilization signal supplied during a blanking period of the vertical synchronization signal and discharges the Q node, the carry terminal, the inverter output node, and the control node in the inverter to the second gate off voltage, And discharging the terminal to the first gate-off voltage. The method according to claim 1,
The shift register is supplied with a plurality of clocks whose phases are successively delayed while partially overlapping the high-
When the stage is the N-th stage,
Wherein the first clock is a clock having an Nth (N is a natural number) phase of the plurality of clocks, the second clock is a clock having an (N + 1) th phase delayed by a 1H period from the first clock, Is an N + 4th clock phase delayed by 4H from the first clock, the first clock and the third clock have inverted phases,
The set terminal is supplied with the (N-4) th carry signal or the start signal supplied from the (N-4)
And an (N + 3) -th carry signal or a reset signal supplied from an (N + 3) -th stage is supplied to the reset terminal. In a shift register having a plurality of stages connected to each other in a dependent manner,
In each stage,
A set portion that is controlled by the set terminal to charge the Q node;
A reset unit controlled by a reset terminal to discharge the Q node;
A first pull-up TFT controlled by the Q node and outputting a first clock supplied to the first clock terminal to a scan output through an output terminal; and a second pull-up TFT controlled by the Q node to output the first clock as a carry signal through a carry terminal, A pull-up section having a pull-up TFT;
A first pull-down TFT which is controlled by a second clock terminal supplied with a second clock whose phase is inverted from the first clock, and which outputs a first gate low voltage to the output terminal; A pull-down section having a second pull-down TFT for outputting a second gate-low voltage lower than a low voltage;
And an inverter output which is controlled by the first clock terminal and the carry terminal and is synchronized with the first clock during a second period except for a first period in which the pull-up section outputs the first clock is outputted to an inverter output node An inverter;
A first noise eliminator controlled by the inverter output node to discharge the Q node to the second gate off voltage;
A second noise eliminator controlled by the inverter output node to discharge the output terminal and the carry terminal to the first and second gate-off voltages, respectively;
And a carry capacitor connected between the Q node and the carry terminal. The method of claim 5,
Each of the stages
Wherein the control signal is controlled by a stabilization signal supplied during a blanking period of the vertical synchronization signal and discharges the Q node, the carry terminal, the inverter output node, and the control node in the inverter to the second gate off voltage, And discharging the terminal to the first gate-off voltage. The method of claim 5,
An 8-phase clock is sequentially supplied to the shift register, the phase of which is sequentially delayed,
Each of the 8-phase clocks has a waveform in which a high section of the 4H period and a low section of the 4H period are alternated,
When the stage is the N-th stage,
Wherein the first clock is a clock having an Nth (N is a natural number) phase of the 8-phase clock, the third clock is a clock having an (N + 4) th phase delayed by 4H from the first clock,
The set terminal is supplied with the (N-4) th carry signal or the start signal supplied from the (N-4)
And the reset terminal is supplied with an (N + 4) th carry signal or a reset signal supplied from the (N + 4) th stage. A display panel;
The display device according to any one of claims 1 to 7, wherein the shift register is built in a non-display area of the display panel and drives the gate lines of the display panel individually.

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