KR20180060952A - Self-aligned spacers and method forming same - Google Patents

Abstract

According to the present invention, a method comprises a step of forming a lower source/drain contact plug within a lower interlayer dielectric. The lower source/drain contact plug is electrically coupled to a source/drain area of a transistor. The method further comprises a step of forming an interlayer dielectric on the lower source/drain contact plug. A source/drain contact open portion is formed within the interlayer dielectric, such that the lower source/drain contact plug is exposed through the source/drain contact open portion. A dielectric spacer layer is formed to have a first area extended into the source/drain contact open portion, and a second area on the interlayer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a residual vertical portion of the dielectric spacer layer forms a source/drain contact spacer. A residual portion of the source/drain contact open portion is filled in order to form an upper source/drain contact plug.

Description

[0001] SELF-ALIGNED SPACERS AND METHOD FORMING SAME [0002]

Priority claim and cross-reference

This application claims the benefit of the following provisional U.S. patent application. U.S. Provisional Patent Application No. 62 / 427,377, filed November 29, 2016, entitled " Self-Aligned Spacers and Method Forming Same ", which is incorporated herein by reference.

As the size of integrated circuits becomes smaller and smaller, individual forming processes are also becoming increasingly difficult, and problems may arise where there have been no problems in the past. For example, in the formation of a fin field effect transistor (FinFET), the metal gate and the adjacent source and drain regions can be electrically shorted to each other. The contact plug of the metal gate may also be shorted to the contact plug of the adjacent source and drain regions.

Embodiments of the present invention are best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. Indeed, the dimensions of the various features may be increased or decreased arbitrarily for clarity of explanation.
1 to 25 illustrate cross-sectional views of intermediate steps in forming a top interconnect structure with a transistor in accordance with some embodiments.
Figure 26 shows a process flow for forming a top interconnect structure with transistors in accordance with some embodiments.

The following disclosure provides a number of different embodiments, or embodiments, that implement various features of the present invention. Specific embodiments of components and arrangement that outline the subject matter are described below. Of course, these specific embodiments are by way of example only and are not intended to be limiting. For example, in the following description, forming the first feature on or on the second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and the first feature and the second feature Embodiments in which additional features may be formed between the first feature and the second feature such that they are not in direct contact may also be included. In addition, the present disclosure may repeat the reference numerals and / or characters in various embodiments. Such repetition is for the sake of simplicity, and does not indicate the relationship between the various embodiments and / or configurations that are discussed in nature.

It will also be appreciated that space-related terms such as "lower," "lower," "lower," "upper," "upper," and the like, Quot;) < / RTI > for convenience of description. These space-related terms are intended to encompass the various orientations of the device during use or operation as well as the orientations shown in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), so that the space-related description phrases used herein can be similarly interpreted.

Transistors and their upper interconnect structures and methods for forming them are provided in accordance with various exemplary embodiments. In accordance with some embodiments, intermediate steps in forming an upper interconnect structure with a transistor are illustrated. Several variations of some embodiments have been discussed. Throughout the various drawings and the exemplary embodiments, like reference numerals are used to denote like elements.

1 to 25 illustrate cross-sectional views of intermediate steps in forming an upper interconnect structure with transistors in accordance with some embodiments of the present disclosure. The steps shown in Figs. 1 to 25 are also schematically reflected in the process flow 200 shown in Fig. Exemplary embodiments use the formation of a fin field effect transistor (FinFET) as an example. It is recognized that the structure and method of formation herein are readily applicable to planar transistors and respective contact plugs.

Referring to FIG. 1, a pneumatic structure is formed on a semiconductor substrate 20, which is a part of the semiconductor wafer 2. According to some embodiments herein, the semiconductor substrate 20 is formed of crystalline silicon. Other commonly used materials such as carbon, germanium, gallium, boron, arsenic, nitrogen, indium, phosphorus, and / or the like may also be included in the semiconductor substrate 20. Further, the semiconductor substrate 20 may be a compound semiconductor substrate containing a III-V group compound semiconductor or silicon germanium.

According to some embodiments of the present disclosure, the initial structure is a portion of the FinFET formed based on the semiconductor fin 22, and is higher than the top surface of a shallow trench isolation (STI) region (not shown) on either side of the semiconductor fin 22 And includes a part of the protruding FinFET. Line 21 is shown to show the level of the top surface of the STI region, and semiconductor pin 22 is higher than line 21.

The gate stack 32 is formed on the semiconductor fin 22 and has a portion extending over the top surface and sidewalls of the semiconductor fin 22. According to some embodiments of the present disclosure, the gate stack 32 is a replacement gate stack formed by forming a dummy gate stack (not shown) and then replacing the dummy gate stack with a replacement gate. The gate stack 32 includes an interfacial oxide layer 26 in contact with the top surface and sidewalls of the semiconductor fin 22, a gate dielectric 28 overlying the interfacial oxide layer 26, (Not shown). A hard mask 34 is formed over the gate electrode 30 to protect the gate stack 32 in a plurality of subsequent processes. The hard mask 34 may also be considered as part of the gate stack. The interfacial oxide layer 26 may be formed by thermally oxidizing the surface layer of the semiconductor fin 22. The gate dielectric 28 may be formed of a high-k dielectric material (s) such as silicon oxide, silicon nitride, hafnium oxide, lanthanum oxide, aluminum oxide, etc., combinations thereof, or multiple layers thereof. The gate electrode 30 may be a metal gate including, for example, cobalt, aluminum, titanium nitride, tantalum nitride, tungsten, tungsten nitride, tantalum carbide, silicon tantalum nitride, can do. Depending on whether each transistor is a P-type metal oxide semiconductor (PMOS) transistor or an N-type metal oxide semiconductor (NMOS) transistor, the material of the gate electrode 30 can be selected to have a work function suitable for each MOS transistor .

A gate spacer 36 is formed on the side wall of the gate stack 32 and the hard mask 34. According to some embodiments of the present disclosure, the gate spacer 36 includes a plurality of layers, e.g., a layer 36A and a layer 36B. Although not shown, more layers may be included in the gate spacer 36. The material of the gate spacer 36 includes silicon oxide, silicon nitride, silicon oxynitride, carbonitride-silicon nitride and / or the like. The layers 36A and 36B may comprise different elements, for example, one layer is formed of silicon oxide and the other layer is formed of silicon nitride. Alternatively, layers 36A and 36B contain the same elements (e.g., silicon and nitrogen) in different compositions (in different ratios). According to some embodiments, the gate spacer 36 may be in contact with the top surface and the sidewalls of the semiconductor fin 22.

A contact etch stop layer (CESL) 38 is formed to cover the substrate 20 and may extend over the sidewalls of the gate spacers 36. According to some embodiments of the present disclosure, the CESL 38 is formed of silicon nitride, silicon carbide, or other dielectric material. An interlevel dielectric (ILD) 40 is formed over the CESL 38 and the gate stack 32. Since ILD 40 is the lowest ILD in a plurality of ILDs, it is hereinafter referred to as ILDO. ILDO 40 may be formed of an oxide such as phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), tetraethylorthosilicate (TEOS) have. Such formation may include, for example, chemical vapor deposition (CVD), fluidized CVD (FCVD), spin-on coating, and the like. Planarization such as chemical mechanical polishing (CMP) or the like may be performed to flatten the top surfaces of the hard mask layer 34, the gate spacers 36, the CESL 38 and the ILDO 40 to be coplanar with each other have.

Source and drain regions (hereinafter referred to as source / drain regions) 42, in which at least a lower portion of the source / drain region 42 extends into the semiconductor substrate 20, are formed. According to some embodiments of the present disclosure, the source / drain regions 42 include p-type or n-type impurities, depending on whether each transistor is a p-type transistor or an n-type transistor. The source / drain regions 42 may include SiP when each transistor is an n-type MOS transistor, or SiGe when each transistor is a p-type MOS transistor. The formation of the source / drain region 42 may include etching the semiconductor fin 22 to form a recess and epitaxially growing the source / drain region 42 within the recess. When a p-type transistor is formed, the epitaxial region 42 may be doped with a p-type impurity such as boron or indium. When the n-type transistor is formed, the n-type impurity such as phosphorus can be doped into the epitaxial region 42. The p-type or n-type impurity may be doped in-situ when epitaxy is performed, and / or may be implanted after epitaxy.

Figures 2 to 6 show the formation of the lower source / drain contact plug. According to some embodiments of the present disclosure, as shown in FIG. 2, after the sacrificial dielectric layer 46 is formed, a photoresist 48 is applied and patterned. According to alternative embodiments herein, the formation of sacrificial dielectric layer 46 is omitted. The patterned photoresist 48 may be a single layer photoresist or a three layer photoresist comprising an inorganic layer separating the two photoresists and the two photoresists. The sacrificial dielectric layer 46, ILDO 40, and CESL 38 are then etched to form a contact opening 50. Thereafter, the source / drain silicide regions 52 are formed, for example, through a self-aligned silicidation process. Thereafter, the photoresist 48 is removed.

The source / drain contact openings 50 may be formed in a single lithography process, or may be formed in a double patterning process that includes two lithographic processes, and the source / drain contact openings 50 on the left side of the alternate gate stack 32 The pattern of the source / drain contact openings 50 on the right side of the alternate gate stack 32 is in a second lithography mask (not shown) do.

Referring to FIG. 3, a dielectric spacer layer 54 is deposited. The dielectric spacer layer 54 may be formed of a dielectric material such as SiN, SiCN, SiC, AlON, HfOx, or the like. The dielectric spacer layer 55 is formed using conformal deposition techniques such as atomic layer deposition (ALD), chemical vapor deposition (CVD), and the like. Thus, the dielectric spacer layer 54 extends into the opening 50, and the thickness of the vertical portion of the dielectric spacer layer 54 is substantially equal to the thickness of the horizontal portion.

4, an anisotropic etch is performed to remove the horizontal portion of the dielectric spacer layer 54 leaving a vertical portion of the dielectric spacer layer 54 within the contact opening 50. [ Throughout this specification, the remaining vertical portions are referred to as contact spacers 56. This individual step is represented by step 202 in the process flow shown in Fig. In a top view of the wafer 2, a contact spacer 56 forms a ring surrounding each contact opening 50. The upper portion of the inner edge of the contact spacer may be tapered and may also be curved so that the curved inner edge faces the contact opening 50. The lower portion of the inner edge may be substantially straight.

The contact opening 50 is then filled with conductive material (s) 58, as shown in Fig. The top surface of the conductive material is higher than the top surface of the sacrificial dielectric layer 46. 6 shows a planarization process in which portions of the conductive material (s) 58 above ILDO 40 are removed. Also, the sacrificial dielectric layer 46, if formed, is removed in the planarization process. The remaining portion of the conductive material (s) 58 is the source / drain contact plug 60. This individual step is shown in step 204 in the process flow shown in FIG. According to some embodiments herein, each source / drain contact plug 60 includes a conductive barrier layer formed of titanium, titanium nitride, tantalum, or tantalum nitride, and a conductive barrier layer formed of tungsten, aluminum, Metal. In accordance with alternative embodiments herein, the contact plugs 60 are formed as a single layer of homogeneous material or alloy such as tungsten or the like. According to some embodiments, the top surface of the contact plug 60 may be coplanar with the top surface of the ILDO 40 and the hard mask 34.

Figures 7 to 12 show the formation of the upper source / drain contact plug. Referring to FIG. 7, after the etch stop layer 62 is formed, the ILD 64 is formed. Throughout this specification, ILD 64 is alternatively referred to as ILD1. The etch stop layer 62 may also be formed of silicon carbide, silicon oxynitride, silicon carbide, combinations thereof, or a composite layer thereof. The etch stop layer 62 may be formed using a deposition method such as CVD, plasma enhanced chemical vapor deposition (PECVD), ALD, and the like. ILD1 64 may comprise a material selected from PSG, BSG, BPSG, fluorine-doped silicon glass (FSG), TEOS, or other nonporous low-k dielectric materials. ILD1 64 may be formed using spin coating, FCVD, or the like, or may be formed using a deposition method such as CVD, PECVD, low pressure chemical vapor deposition (LPCVD), or the like.

Figure 8 shows the formation of openings 66 formed through etching. 9, a dielectric spacer layer 68 is formed through the deposition, for example, the difference in thickness between the horizontal portion and the vertical portion is less than about 10% of the thickness of the horizontal portion, Is formed as an isotropic layer. Deposition can be achieved through ALD, CVD, and the like. The dielectric spacer layer 68 may be formed of a dielectric material selected from SiN, SiON, SiCN, SiC, SiOCN, AlON, AlN, HfOx, combinations thereof, and / or multiple layers thereof.

10 shows an anisotropic etch that removes the horizontal portion of dielectric spacer layer 68 to form contact spacers 70 as shown in FIG. This individual step is shown in step 206 in the process flow shown in Fig. The remaining openings 66 may have a width W1 at the top and a width W2 at the bottom due to anisotropic etching of the dielectric spacer layer 68 (Figure 9), wherein the ratio W1 / W2 is between about 1.0 and about 2.0 < / RTI > The upper portion of the inner edge of the contact spacer 70 may be tapered and may also be curved so that the curved portions face the opening 66. The lower portion of the contact spacer 70 may have a substantially straight edge facing the opening 66. In the plan view of the wafer 2, the contact spacer 70 is a ring surrounding each opening 66.

The contact opening 66 is then filled with a conductive material (s) 72, as shown in Fig. Thereafter, a planarization process (e.g., CMP) is performed in which portions of the conductive material (s) 72 above ILD1 64 are removed. The remaining portion of the conductive material (s) 72 remains after planarization and is referred to as the upper source / drain contact plug 74 as shown in FIG. The tapered top portion of the contact spacer 70 is removed from the planarization and the remaining contact spacers 70 have a substantially straight inner edge that contacts the contact plugs 74. In accordance with some embodiments of the present disclosure, This individual step is represented by step 208 in the process flow shown in FIG.

According to alternative embodiments of the present disclosure, the tapered top portion of the contact spacer 70 has a remaining portion (not shown) after planarization, and the inner edge of the remaining contact spacer 70 Has a curved top portion that is in physical contact with the contact plug 74 (as shown in FIG. According to some embodiments of the invention, the material of the upper source / drain contact plug 74 is similar to that of the source / drain contact plug 60. For example, the source / drain contact plug 74 may comprise a conductive barrier layer and a metal such as tungsten, aluminum, copper, etc. on top of the diffusion barrier layer.

Figures 13-20 illustrate the formation of gate contact plugs and additional source / drain contact plugs. 13, after an etch stop layer 76 is formed in accordance with some embodiments of the present disclosure, a dielectric layer 78 is formed, throughout this specification, This dielectric layer can be referred to as ILD2 (78). According to alternative embodiments herein, the etch stop layer 76 is not formed and the dielectric layer 78 is in contact with the ILDl 64. Thus, the etch stop layer 76 is shown using dotted lines to indicate that it may or may not be formed. The etch stop layer 76 and the dielectric layer 78 are formed of a material selected from the same group as the etch stop layer 62 and the group of candidate materials of the dielectric layer 64. In some embodiments, According to alternative embodiments herein, the dielectric layer 78 is formed of a low-k dielectric material that includes a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl Silsesquioxane (MSQ), or the like.

14, a photolithography process is performed using patterned lithography mask 80 to etch through layers 78, 76, 64 and 62 to form gate contact openings 82. As shown in FIG. The lithography mask 80 may include a lower layer 80A formed of a photoresist, an intermediate layer 80B formed of an inorganic material, and an upper layer 80C formed of another photoresist. Thereafter, the exposed portions of the hard mask 34 (FIG. 13) are removed so that the gate contact openings 82 extend into the space between both gate spacers 36. This individual step is shown in step 210 in the process flow shown in FIG. According to some embodiments herein, the formation of the gate contact opening 82 includes anisotropic etching. The sidewalls of the gate spacers 36 may be exposed to the gate contact openings 82. The etchant may be selected such that the etchant does not attack the gate spacer 36 and thus the exposed gate spacer 36 is not etched. The gate contact opening 82 is narrower than the hard mask 34 such that a portion of the edge of the hard mask 34 (not shown) is exposed to one or both sides of the gate contact opening 82. [ It remains. 14 shows the intermediate layer 80B and the upper layer 80C but actually the intermediate layer 80B and the upper layer 80C may already be consumed at the time when the gate contact opening 82 is formed . Thereafter, the remaining lithography mask 80 is removed, and the resulting wafer 2 is shown in Fig.

16, another patterned lithographic mask 84 is formed that extends into the gate contact opening 82 (Fig. 15). This individual step is indicated in step 212 in the process flow shown in Fig. The patterned lithographic mask 84 is used as an etch mask to further etch the layers 78,76 to form the source / drain contact openings 86. [ The contact plug 74 and the contact spacer 70 are exposed through the contact opening 86. Similarly, by the time contact openings 86 are formed, the intermediate and upper layers of the lithography mask 84 may already be consumed. The remaining lithography mask 84 is then removed and the resulting wafer 2 is shown in Fig.

Figure 18 shows the formation of a dielectric spacer layer 88 that extends into the gate contact opening 82 and the source / drain contact opening 86. The method and material for forming the dielectric spacer layer 88 may be selected from the same group as the candidate group of methods and materials of the method and materials for forming the dielectric spacer layer 68 (FIG. 9), respectively. For example, candidate materials for forming the dielectric spacer layer 88 include, but are not limited to, SiN, SiON, SiCN, SiC, SiOCN, AlON, AlN, and HfOx. The dielectric spacer layer 88 may also be conformal or substantially conformal. The dielectric spacer layer 88 also extends into both the gate contact opening 82 and the source / drain contact opening 86.

Anisotropic etching is then performed and a portion of the remaining dielectric spacer layer 88 forms contact spacers 90 and 92, as shown in FIG. This individual step is shown in step 214 in the process flow shown in FIG. The conductive material 94 is then deposited to fill the remaining contact openings 82, 86 (Figure 18). A planarization process is then performed and the remaining conductive material 94 forms a source / drain contact plug 96 and a gate contact plug 98 as shown in FIG. This individual step is represented by step 216 in the process flow shown in Fig. The formation of the contact plugs 96 and 98, as shown in Figures 15-19, includes forming the respective contact openings 82,86 (Figure 17) using a double patterning process, 82, 86 can be positioned close to each other without causing optical proximity effects. Meanwhile, the contact openings 82 and 86 are simultaneously charged so as to reduce the manufacturing cost.

Figure 20 also shows the distance (spacing) between neighboring contact plugs 96, 98 and the width of the contact plugs 96, 98. The width of the contact plug 96 is W3 and the width of the contact plug 98 is W3 '. The distance between neighboring contact plugs 96, 98 is S1. According to some embodiments herein, ratio S1 / W3 and ratio S2 / W3 'range from about 1.0 to 2.0.

21 to 25 show forming a lower metal layer (hereinafter referred to as a metal layer 1 or M1) and upper vias through a single damascene process. Referring to FIG. 21, an etch stop layer 102 and a dielectric layer 104 are formed. The etch stop layer 102 is formed of a material selected from the same group as the group of candidate materials of the etch stop layer 76 and the dielectric layer 104 is formed of a material having a dielectric constant of less than 3.8 -k dielectric material. For example, the low-k dielectric layer 104 may be formed of a carbon-containing low-k dielectric material, HSQ, MSQ, or the like.

22 shows the formation of trench 106, including etching low-k dielectric layer 104 and etch stop layer 102 to expose contact plugs 96 and 98. Then, as shown in FIG. 23, metal lines 108 and metal line spacers 110 are formed. This individual step is represented by step 218 in the process flow shown in FIG. This forming process may be similar to the formation of the contact spacers 70 and the contact plugs 74, respectively, so the details of this forming process are not repeated here. A metal line spacer 110 may be formed from a dielectric material selected from the same group as the group of candidate materials for forming the contact spacers 70. The metal line 108 may comprise a conductive diffusion barrier and a copper containing metal material on top of the conductive diffusion barrier.

Vias are then formed on the metal line 108 through a damascene process. Referring to FIG. 23, an etch stop layer 112 and a dielectric layer 114 are formed. According to some embodiments herein, the etch stop layer 112 is formed of a material selected from the same group as the group of candidate materials of the etch stop layer 76,102, and the dielectric layer 114 is formed of a low- Lt; / RTI > may be formed of a low-k dielectric material similar to the material of layer 104 of FIG. 24 shows the formation of the via opening 115 and dielectric layer 116, which is an isotropic layer or a substantially conformal layer deposited using ALD, CVD, or the like. The dielectric layer 116 extends into the via opening 115.

Figure 25 shows the formation of vias 118 and via spacers 120. This individual step is represented by step 220 in the process flow shown in FIG. This forming process may be similar to the formation of the contact spacers 70 and the contact plugs 74, respectively, so the details of this forming process are not repeated here. Via spacers 120 may be formed of a dielectric material selected from the same materials as the candidate materials for forming the contact spacers 70. Vias 118 may include conductive diffusion barriers and a copper-containing metal material on top of each conductive diffusion barrier. In subsequent processes, the process of forming the metal line 108, the metal line spacers 110, the vias 118 and the via spacers 120 is repeated to form the metal lines 108, M2, M3, M4, ..., Mtop, Upper metal lines and vias can be formed. The upper metal lines and vias may be formed using a single damascene process or a dual damascene process (as shown in Figures 21-25) such that each via and metal line is filled in the via opening and trench, respectively Prior to this, a dielectric layer is deposited and etched anisotropically.

Embodiments of the present application have several beneficial features. By forming the contact spacers, metal line spacers, and / or via spacers, there is an additional dielectric spacer to prevent electrical shorting of the upper conductive features to the lower conductive features, in the presence of an overlay shift. Thus, the process window is increased.

According to some embodiments of the present disclosure, a method includes forming a lower source / drain contact plug in a lower interlayer dielectric. The lower source / drain contact plug is electrically coupled to the source / drain region of the transistor. The method further includes forming an interlayer dielectric over the lower source / drain contact plug. A source / drain contact opening is formed in the interlevel dielectric such that the lower source / drain contact plug is exposed through the source / drain contact opening. A dielectric spacer layer is formed having a first portion extending into the source / drain contact opening and a second portion overlying the interlevel dielectric. An anisotropic etch is performed on the dielectric spacer layer, and the remaining vertical portion of the dielectric spacer layer forms a source / drain contact spacer. The remaining portion of the source / drain contact opening is filled to form an upper source / drain contact plug.

The method of the above embodiment includes: etching the first interlayer dielectric to form a gate contact opening; Etching the hardmask between the gate spacers to extend the gate contact openings between the gate spacers of the transistor; Forming a second spacer layer having a portion extending into the gate contact opening; Etching the second spacer layer to form a gate contact spacer within the gate contact opening; Forming a gate contact plug in the gate contact opening; Forming a second interlayer dielectric over the first interlayer dielectric; Etching the second interlayer dielectric to form a second source / drain contact opening, the second spacer layer further extending into the second source / drain contact opening, and the step of etching the second spacer layer , Forming a second source / drain contact spacer in the second source / drain contact opening; And forming a second source / drain contact plug in the second source / drain contact opening.

The method of the above-described embodiment includes: forming a first low-k dielectric layer on the first interlayer dielectric; Forming a metal line in the first low-k dielectric layer, wherein the metal line is electrically coupled to the source / drain region; Forming a dielectric metal line spacer surrounding the metal line; Forming a second low-k dielectric layer over the first low-k dielectric layer; Forming a metal via in the second row-k dielectric layer, wherein the via is electrically coupled to the source / drain region; And forming dielectric via spacers surrounding the metal vias.

According to some embodiments of the present disclosure, a method includes forming a first source / drain contact plug in a first interlayer dielectric that is electrically coupled to a source / drain region of a transistor; Forming a second interlayer dielectric over the first interlayer dielectric; Forming a second source / drain contact plug in the second interlayer dielectric; Forming a third interlayer dielectric over the second interlayer dielectric; And etching the second interlayer dielectric and the third interlayer dielectric to form a gate contact opening. The gate electrode of the transistor is exposed to the gate contact opening. A gate contact spacer is formed in the gate contact opening. The gate contact spacer penetrates the second interlayer dielectric and the third interlayer dielectric. A gate contact plug is formed in the gate contact opening, and the gate contact plug is surrounded by the gate contact spacer.

In the above embodiment, the step of forming the gate contact spacer and the step of forming the source / drain contact spacer may share a cavity forming process and a cavity etching process.

The method of the above embodiment may further comprise etching the second interlayer dielectric and the third interlayer dielectric to form the gate contact openings and then etching the gate spacers to extend the gate contact openings between the gate spacers of the transistors. Etching the hardmask between the gate contact spacer and the gate contact plug, wherein the gate contact spacer and the gate contact plug extend to a lower level than the top surface of the gate spacer.

The method of the above-described embodiment includes: forming a first low-k dielectric layer on the third interlayer dielectric; Forming a metal line in the first low-k dielectric layer, wherein the metal line is electrically coupled to the source / drain region; And forming a dielectric metal line spacer surrounding the metal line.

Forming a second low-k dielectric layer over the first low-k dielectric layer; Forming a via in the second row-k dielectric layer, wherein the via is electrically coupled to the source / drain region; And forming dielectric via spacers surrounding the vias.

According to some embodiments of the present application, a device comprises: a semiconductor substrate; A gate electrode on the semiconductor substrate; A source / drain region on one side of the gate electrode; A first interlayer dielectric overlying the source / drain region, wherein at least a portion of the gate electrode is within the first interlayer dielectric; A second interlayer dielectric overlying the first interlayer dielectric; A third interlayer dielectric overlying the second interlayer dielectric; A gate contact spacer penetrating the second interlayer dielectric and the third interlayer dielectric; And a gate contact plug electrically coupled to the gate electrode. The gate contact plug is surrounded by the gate contact spacer.

The device of the above embodiment may further include gate spacers on both sides of the gate electrode, wherein the top surface of the gate spacer is higher than the top surface of the gate electrode, and the gate contact spacer extends between the gate spacers .

In the device of the above embodiment, the gate contact spacer may be one which continuously extends from the upper end face of the third interlayer dielectric to the lower end face of the second interlayer dielectric without a separable interface.

The device of the above embodiment includes: a first source / drain contact plug in the first interlayer dielectric; And a second source / drain contact plug in said second interlayer dielectric, said second source / drain contact plug having a separable interface between said first source / drain contact plug and said second source / ; And a source / drain contact spacer within the second interlayer dielectric and surrounding the second source / drain contact plug.

The device of the above embodiment includes: a low-k dielectric layer over the third interlayer dielectric; A metal line in the low-k dielectric layer, the metal line being electrically coupled to the source / drain region; And a dielectric metal line spacer surrounding the metal line.

In order that those skilled in the art will be better able to understand aspects of the present disclosure, the foregoing is intended to provide an overview of features of the various embodiments. Those skilled in the art will readily appreciate that the disclosure herein may be used as a basis for designing or modifying other processes and structures to achieve the same advantages of the embodiments disclosed herein and / or to perform the same purpose. Those skilled in the art will also appreciate that various modifications, substitutions and alterations can be made herein without departing from the spirit and scope of equivalents, and without departing from the spirit and scope of the invention.

Claims (10)

As a method,
Forming a lower source / drain contact plug in the lower interlayer dielectric electrically coupled to the source / drain regions of the transistor;
Forming a first interlayer dielectric over the lower source / drain contact plug;
Forming a first source / drain contact opening in the first interlayer dielectric, wherein the lower source / drain contact plug is exposed through the first source / drain contact opening;
Forming a first dielectric spacer layer comprising a first portion extending into the first source / drain contact opening and a second portion overlying the first interlayer dielectric;
Performing an anisotropic etch on the first dielectric spacer layer, wherein the remaining vertical portion of the first dielectric spacer layer forms a first source / drain contact spacer; And
Filling the remaining portion of the first source / drain contact opening to form a first source / drain contact plug
≪ / RTI > 2. The method of claim 1, further comprising forming a first etch stop layer in contact with the gate spacer of the transistor and the lower source / drain contact plug, wherein the first interlayer dielectric comprises a first etch stop layer Being in contact with the top. The method according to claim 1,
Etching the first interlayer dielectric to form a gate contact opening;
Etching the hardmask between the gate spacers to extend the gate contact openings between the gate spacers of the transistor;
Forming a second spacer layer having a portion extending into the gate contact opening;
Etching the second spacer layer to form a gate contact spacer within the gate contact opening; And
Forming a gate contact plug in the gate contact opening
≪ / RTI > The method according to claim 1,
Forming a first low-k dielectric layer over the first interlayer dielectric;
Forming a metal line in the first low-k dielectric layer, wherein the metal line is electrically coupled to the source / drain region; And
Further comprising forming a dielectric metal line spacer surrounding the metal line. The method according to claim 1,
Forming a sacrificial layer over the gate stack of the transistor;
Etching the sacrificial layer and the lower interlayer dielectric to form a lower source / drain contact opening;
Forming a lower contact spacer in the lower source / drain contact opening;
Filling the lower source / drain contact opening with a conductive material; And
Performing planarization to remove the portion of the conductive material overlying the lower interlevel dielectric and the sacrificial layer to form the lower source / drain contact plug
≪ / RTI > As a method,
Forming a first source / drain contact plug in the first interlayer dielectric that is electrically coupled to a source / drain region of the transistor;
Forming a second interlayer dielectric over the first interlayer dielectric;
Forming a second source / drain contact plug in the second interlayer dielectric;
Forming a third interlayer dielectric over the second interlayer dielectric;
Etching the second interlayer dielectric and the third interlayer dielectric to form a gate contact opening, the gate electrode of the transistor being exposed to the gate contact opening;
Forming a gate contact spacer in the gate contact opening, the gate contact spacer penetrating the second interlayer dielectric and the third interlayer dielectric; And
Forming a gate contact plug in the gate contact opening, wherein the gate contact plug is surrounded by the gate contact spacer
≪ / RTI > The method according to claim 6,
Etching the third interlayer dielectric to form a source / drain contact opening, wherein the second source / drain contact plug is exposed through the source / drain contact opening;
Forming a source / drain contact spacer in the source / drain contact opening; And
And forming a third source / drain contact plug in the source / drain contact opening, wherein the second source / drain contact plug is surrounded by the source / drain contact spacer.
≪ / RTI > 7. The method of claim 6, wherein forming the gate contact spacer comprises:
Depositing a dielectric spacer layer extending into the gate contact opening and through the second interlayer dielectric and the third interlayer dielectric; And
Performing an anisotropic etch on the dielectric spacer layer, wherein the remaining portion of the dielectric spacer layer forms the gate contact spacer
≪ / RTI > 7. The method of claim 6, further comprising, after etching the second interlayer dielectric and the third interlayer dielectric to form the gate contact openings, between the gate spacers to extend the gate contact openings between the gate spacers of the transistor ≪ / RTI > further comprising etching the hardmask. As a device,
A semiconductor substrate;
A gate electrode on the semiconductor substrate;
A source / drain region on one side of the gate electrode;
A first interlayer dielectric overlying the source / drain region, wherein at least a portion of the gate electrode is within the first interlayer dielectric;
A second interlayer dielectric overlying the first interlayer dielectric;
A third interlayer dielectric overlying the second interlayer dielectric;
A gate contact spacer penetrating the second interlayer dielectric and the third interlayer dielectric; And
A gate contact plug electrically coupled to the gate electrode and surrounded by the gate contact spacer,
/ RTI >

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