DE102017118475A1 - SELF-ADJUSTED SPACERS AND METHOD FOR THE PRODUCTION THEREOF - Google Patents

Abstract

One method includes forming a lower source / drain contact pin in a lower interlayer dielectric. The lower source / drain contact pin is electrically connected to a source / drain region of a transistor. The method further includes forming an interlayer dielectric over the lower source / drain contact pin. In the inter-layer dielectric, a source / drain contact opening is made exposing the lower source / drain contact pin through the source / drain contact opening. A dielectric spacer layer is fabricated to have a first portion that extends into the source / drain contact opening and a second portion over the interlayer dielectric. Anisotropic etch is performed on the dielectric spacer layer with a remaining vertical portion of the dielectric spacer layer forming a source / drain contact spacer. The remaining portion of the source / drain contact opening is filled to form an upper source / drain contact pin.

Description

Priority claim and cross reference

This application claims priority from US Provisional Patent Application Serial No. 62 / 427,477, filed Nov. 29, 2016, entitled "Self-Aligned Spacers and Method Forming Same", which is incorporated herein by reference is included.

Background of the invention

As the sizes of integrated circuits become smaller and smaller, the respective manufacturing processes become more and more difficult, and problems may occur where conventionally no problems have occurred. For example, in the fabrication of fin field effect transistors (FinFETs), the metal gates and the adjacent source and drain regions may be electrically shorted. In addition, the contact pins of the metal gates can be shorted to the contact pins of the adjacent source and drain regions.

list of figures

• Die 1 bis 25 zeigen Schnittansichten von Zwischenstufen bei der Herstellung eines Transistors und einer darüber befindlichen Verbindungsstruktur gemäß einigen Ausführungsformen.
• 26 zeigt einen Prozessablauf zur Herstellung eines Transistors und einer darüber befindlichen Verbindungsstruktur gemäß einigen Ausführungsformen.

Aspects of the present invention will be best understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, according to common practice in the industry, various elements are not drawn to scale. Rather, for the sake of clarity of the discussion, the dimensions of the various elements can be arbitrarily increased or reduced.

• The 1 to 25 12 show sectional views of intermediate stages in the fabrication of a transistor and an overlying interconnect structure, according to some embodiments.
• 26 FIG. 12 shows a process flow for fabricating a transistor and overlying interconnect structure according to some embodiments.

Detailed description

The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Hereinafter, specific examples of components and arrangements will be described in order to simplify the present invention. Of course these are just examples and should not be limiting. For example, the fabrication of a first element over or on a second element in the description below may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements are interposed between the first and second elements the second element can be formed so that the first and the second element are not in direct contact. Moreover, in the present invention, reference numerals and / or letters may be repeated in the various examples. This repetition is for simplicity and clarity and as such does not dictate any relationship between the various embodiments and / or configurations discussed.

Moreover, spatially relative terms such as "underlying", "below", "lower" / "lower", "above", "upper", "upper", and the like, may be simply used Description of the relationship of an element or a structure to one or more other elements or structures are used, which are shown in the figures. The spatially relative terms are intended to include, in addition to the orientation shown in the figures, other orientations of the device in use or in service. The device may be reoriented (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may also be interpreted accordingly.

According to various exemplary embodiments, there is provided a transistor and overlying interconnect structure and method of making the same. The intermediate stages in the fabrication of the transistor and the overlying interconnect structure are illustrated in accordance with some embodiments. Some modifications of some embodiments will be discussed. In all illustrations and illustrative embodiments, similar reference symbols are used to denote similar elements.

The 1 to 25 10 illustrate cross-sectional views of intermediate stages in the fabrication of a transistor and overlying interconnect structure in accordance with some embodiments of the present invention. The steps in the 1 to 25 are also shown in the process flow 200 who in 26 shown is shown schematically. In the illustrative embodiments, the fabrication of a fin field effect transistor (FinFET) is used as an example. It will be understood that the structure and manufacturing methods of the present invention can be readily used for planar transistors and respective contact pins.

In 1 becomes an initial structure on a semiconductor substrate 20 made part of a semiconductor wafer 2 is. In some embodiments of the present invention, the semiconductor substrate is 20 made of crystalline silicon. Other common materials such as carbon, germanium, gallium, boron, arsenic, nitrogen, indium, phosphorus and the like may also be present in the semiconductor substrate 20 be included. The substrate 20 may also be a compound semiconductor substrate comprising a III-V compound semiconductor or silicon germanium.

In some embodiments of the present invention, the initial structure has a portion of a FinFET based on a semiconductor fin 22 (STI: shallow trench isolation) (not shown) on opposite sides of the semiconductor fin 22 survives. A line 21 is used to represent the level of the top of the STI regions, wherein the semiconductor fin 22 higher than the line 21 is.

A gate stack 32 becomes on the semiconductor fin 22 made, and he has parts on the top and side walls of the semiconductor fin 22 run. In some embodiments of the present invention, the gate stack is 32 a replacement gate stack made by fabricating a dummy gate stack (not shown) and then replacing the dummy gate stack with a replacement gate. The gate stack 32 may include: an oxide interlayer 26 that cover the top and sidewalls of the semiconductor fin 22 contacted; a gate dielectric 28 over the oxide interlayer 26 ; and a gate electrode 30 above the gate dielectric 28. Above the gate electrode 30 becomes a hard mask 34 to protect the gate stack 32 produced in a variety of subsequent processes. The hard mask 34 can be considered as part of the gate stack. The oxide interlayer 26 can by thermal oxidation of a surface layer of the semiconductor fin 22 getting produced. The gate dielectric 28 may be silicon oxide, silicon nitride, one or more high-k dielectrics, such as hafnium oxide, lanthana or alumina, or combinations thereof or multiple layers thereof. The gate electrode 30 may be a metal gate comprising, for example, cobalt, aluminum, titanium amide, tantalum nitride, tungsten, tungsten nitride, tantalum carbide, tantalum silicon nitride, or the like, and may include multiple layers of different materials. Depending on whether the respective transistor is a p-metal oxide semiconductor transistor (PMOS transistor) or an n-metal oxide semiconductor transistor (nMOS transistor), the material of the gate electrode 30 be chosen so that it has a work function, which is suitable for the respective MOS transistor.

On the side walls of the gate stack 32 and the hard mask 34 become gate spacers 36 produced. In some embodiments of the present invention, the gate spacers include 36 a plurality of layers, for example a layer 36A and a layer 36B , Although not shown, the gate spacers 36 may include more layers. The materials for the gate spacers 36 include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and the like. The layers 36A and 36B may have elements that are different from one another, wherein, for example, the one layer consists of silicon oxide and the other layer consists of silicon nitride. Alternatively, the layers can 36A and 36B have the same elements (such as silicon and nitrogen) with different compositions (different percentages). The gate spacers 36 In some embodiments, they may be in contact with the tops and sidewalls of the semiconductor fin 22 be.

A contact etch stop layer (CESL) 38 is made to cover the substrate 20 and may be on the sidewalls of the gate spacers 36 run. In some embodiments of the present invention, the CESL 38 silicon nitride, silicon carbide or other dielectric material. About the CESL 38 and the gate stack 32 becomes an interlayer dielectric (ILD) 40 produced. The ILD 40 hereinafter referred to as ILDo, since it is the lowest ILD of a plurality of ILDs. The ILDo 40 may be made of an oxide such as phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS) oxide, or the like. The preparation can be carried out, for example, by chemical vapor deposition (CVD), flowable CVD (FCVD), spin coating or the like. Planarization, such as chemical mechanical polishing (CMP), may be performed around the tops of the hardmask layer 34 , the gate spacer 36 , the CESL 38 and the ILDo 40 so that they are coplanar with each other.

There will be source and drain areas 42 (hereinafter referred to as source / drain regions 42 are designated), wherein at least lower parts of the source / drain regions 42 in the semiconductor substrate 20 reach into it. In some embodiments of the present invention, the source / drain regions 42 a p- or an n-type dopant, depending on whether the respective transistor is a p-type transistor or an n-type transistor. The source / drain regions 42 may have SiP when the respective transistor is an n-type MOS transistor, or SiGe, when the respective transistor is a p-type MOS transistor. The preparation of the source / drain regions 42 may be the etching of the semiconductor fin 22 for making recesses and epitaxially growing the source / drain regions 42 in the recesses. If a p-type transistor is to be made, the epitaxy regions can 42 doped with a p-type dopant such as boron or indium. If an n-type transistor is to be produced, the epitaxy regions can 42 doped with an n-type dopant such as phosphorus. The p- or n-type dopant may be doped in situ when performing epitaxy, or may be implanted after epitaxy.

The 2 to 6 show the preparation of lower source / drain pins. In some embodiments of the present invention, which are disclosed in U.S. Pat 2 is a sacrificial dielectric layer 46 and this is followed by the application and patterning of a photoresist 48 at. In alternative embodiments of the present invention, the fabrication of the sacrificial dielectric layer 46 omitted. The textured photoresist 48 may be a single layer photoresist, or it may be a triple layer with two photoresists and an inorganic layer separating the two photoresists. Then, the sacrificial dielectric layer becomes 46 , the ILDo 40 and the CESL 38 etched to contact openings 50 manufacture. Subsequently, source / drain silicide regions 52 made, for example, with a process for the formation of self-adjusting silicides. Then the photoresist 48 away.

It should be clear that the source / drain contact openings 50 can be made with a single lithographic process or with a double structuring process with two lithographic processes, the structure of the source / drain contact opening 50 on the left side of the replacement gate stack 32 in a first lithographic mask (not shown) and the structure of the source / drain contact opening 50 on the right side of the replacement gate stack 32 in a second lithographic mask (not shown).

In 3 becomes a dielectric spacer layer 54 deposited. The dielectric spacer layer 54 can be prepared by a conformal deposition method such as atomic layer deposition (ALD), chemical vapor deposition (CVD) or the like. Therefore, the dielectric spacer layer is enough 54 into the openings 50, and the thickness of the vertical parts of the dielectric spacer layer 54 is substantially equal to the thickness of the horizontal parts.

In 4 Anisotropic etching is performed to form the horizontal portions of the dielectric spacer layer 54 remove so that the vertical parts of the dielectric spacer layer 54 in the contact openings 50 remain. The remaining vertical parts are referred to throughout the specification as contact spacers 56 designated. The corresponding step is through the step 202 represented in the in 26 indicated process flow is indicated. In the plan view of the wafer 2 form the contact spacers 56 Rings containing the respective contact openings 50 enclose. The upper portions of the inner edges of the contact spacers may be tapered and curved, with the curved inner edges leading to the openings 50 demonstrate. The lower parts of the inner edges may be substantially straight.

Then the contact openings 50 with one or more conductive materials 58 filled, as in 5 is shown. The top of the conductive material is higher than the top of the sacrificial dielectric layer 46 , 6 FIG. 12 shows a planarization process in which the portions of the one or more conductive materials 58 above the ILDo 40 are removed. In the planarization, the dielectric sacrificial layer also becomes 46 removed when it has been manufactured. The remaining parts of the conductive materials 58 are source / drain pins 60 , The corresponding step is through the step 204 represented in the in 26 indicated process flow is indicated. In some embodiments of the present invention, the source / drain pins include 60 each a conductive barrier layer consisting of titanium, titanium amide, tantalum or tantalum nitride, and a metal such as tungsten, aluminum, copper or the like over the diffusion barrier layer. In alternative embodiments of the present invention, the contact pins are made 60 from a single layer consisting of a homogeneous material, such as tungsten, or an alloy. The tops of the contact pins 60 In some embodiments, coplanar with the tops of the ILDo 40 and the hardmask 34 be.

The 7 to 12 show the preparation of upper source / drain pins. In 7 becomes an etch stop layer 62 and then becomes an ILD 64 produced. Throughout the description, the ILD 64 alternatively referred to as ILD1. The etch stop layer 62 may be silicon carbide, silicon oxynitride, silicon carbonitride, combinations thereof, or composite layers thereof. The etch stop layer 62 can be prepared using a deposition method such as CVD, plasma enhanced chemical vapor deposition (PECVD), ALD or the like. The ILD 64 can be a material that comes from the Group PSG, BSG, BPSG, fluorosilicate glass (FSG) and TEOS, or other non-porous low-k dielectric materials. The ILD 64 can be made by spin coating, FCVD or the like or by a deposition method such as CVD, PECVD, low pressure chemical vapor deposition (LPCVD) or the like.

8th shows the production of openings 66 by etching. Then it will be in 9 a dielectric spacer layer 68 produced by deposition, and it is fabricated as a conformal or substantially conformal layer whose horizontal and vertical parts have thicknesses, for example, with a difference of less than about 10% of the horizontal thickness. The deposition can be done by ALD, CVD or the like. The dielectric spacer layer 68 may consist of a dielectric material selected from the group SiN, SiON, SiCN, SiC, SiOCN, AlON, AlN, HfO _x, or combinations thereof and / or multiple layers thereof.

10 shows an anisotropic etching for removing the horizontal parts of the dielectric spacer layer 68 , so contact spacers 70 arise. The corresponding step is through the step 206 represented in the in 26 indicated process flow is indicated. By the anisotropic etching of the dielectric spacer layer 68 ( 9 ) can use the remaining openings 66 have an upper width W1 and a lower width W2, wherein the ratio W1 / W2 may be in the range of about 1.0 to about 2.0. The upper portions of the inner edges of the contact spacers 70 may be tapered and curved, with the curved inner edges toward the openings 60 demonstrate. The lower parts of the contact spacers 70 can essentially have straight edges leading to the openings 66 demonstrate. Again, in the plan view of the wafer 2 the contact spacers 70 Rings, which are the respective openings 66 enclose.

Then the contact openings 66 with one or more conductive materials 72 filled, as in 11 is shown. Then, a planarization process (eg, a CMP) is performed in which the portions of the one or more conductive materials 72 above the ILD1 64. The - remaining parts of the conductive materials 72 remain after planarization and are considered upper source / drain pins 74 referred to in 12 are shown. In some embodiments of the present invention, the tapered portions of the contact spacers 70 removed at the planarization, and the remaining contact spacers 70 have essentially straight inner edges, which are the contact pins 74 to contact. The corresponding step is through the step 208 represented in the in 26 indicated process flow is indicated.

In alternative embodiments of the present invention, the tapered portions of the contact spacers 70 Parts that remain after planarization (not shown) and the inner edges of the remaining contact spacers 70 have curved upper parts (which in 11 shown) in physical contact with the contact pins 74 are. In some embodiments of the present invention, the material is the upper source / drain contact pins 74 that of the source / drain pins 60 similar. For example, the source / drain pins 74 conductive barrier layers and a metal such as tungsten, aluminum, copper or the like over the diffusion barrier layer.

The 13 to 20 show the fabrication of a gate pin and other source / drain pins. In some embodiments of the present invention, as shown in FIG 13 an etch stop layer is shown 76 and then a dielectric layer is formed 78 which may be referred to throughout the specification as ILD2 78. In alternative embodiments of the present invention, the etch stop layer 76 not manufactured, and the dielectric layer 78 is in contact with the ILD1 64. The etch stop layer 76 is represented by dashed lines to indicate that it may or may not be made. In some embodiments of the present invention, the etch stop layer 76 and the dielectric layer 78 made from the materials selected from the same group of candidate materials as for the etch stop layer 62 or the dielectric layer 64 are selected. In alternative embodiments of the present invention, the dielectric layer is 78 low-k dielectric material which may be a carbonaceous low-k dielectric material such as hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ) or the like.

In 14 becomes a photolithographic process using a patterned lithographic mask 80 performed to the layers 78 . 76 . 64 and 62 durchzuätzen, so that a gate contact opening 82 arises. The lithographic mask 80 can be a lower layer 80A which consists of a photoresist, a middle layer 80B made of an inorganic material and an upper layer 80C include, which consists of a further photoresist. Then the exposed part of the hard mask 34 ( 13 ), leaving the gate contact opening 82 in the space between opposing gate spacers 36 reaches into it. The corresponding step is through the step 210 represented in the in 26 indicated process flow is indicated. In some embodiments of the present invention, the fabrication involves the gate contact opening 82 an anisotropic etching. The sidewalls of the gate spacers 36 may be connected to the gate contact opening 82 be exposed. The etchant may be chosen to be the gate spacer 36 does not attack, and therefore the exposed spacers 32 not be etched. In alternative embodiments of the present invention, the gate contact opening is 82 closer to the hard mask 34 , and therefore some edge parts of the hardmask remain 34 (not shown) on either side of the gate contact opening 82 back. 14 shows the middle layer 80B and the upper layer 80C but can practically at the time of manufacture of the gate contact opening 82 the middle layer 80B and the upper layer 80C already used up. Then the remaining lithographic mask 80 removed, and the resulting wafer 2 is in 15 shown.

In 16 becomes another structured lithographic mask 84 made in the gate contact opening 82 ( 15 ). The corresponding step is through the step 212 represented in the in 26 indicated process flow is indicated. The textured lithographic mask 84 is used as an etch mask to further etch the layers 78 and 76 used so that source / drain contact openings 86 arise. The contact pins 74 and the contact spacers 70 be through the contact openings 86 exposed. Until the time of manufacture of the contact openings 86 may be the middle layer and the upper layer of the lithographic mask 84 already used up. Then the remaining lithographic mask 84 removed, and the resulting wafer 2 is in 17 shown.

18 shows the preparation of a dielectric spacer layer 88 entering the gate contact opening 82 and the source / drain contact openings 86 reaches into it. The manufacturing methods and the materials for the dielectric spacer layer 88 may be from the same groups of candidate materials as for the dielectric spacer layer fabrication 68 ( 9 ) to get voted. For example, the materials of interest include for the preparation of the dielectric spacer layer 88 SiN, SiON, SiCN, SiC, SiOCN, AlON, AlN and HfO _x, among others. The dielectric spacer layer 88 is also compliant or substantially compliant. In addition, the dielectric spacer layer is sufficient 88 in the gate contact opening 82 and the source / drain contact openings 86 into it.

Then, an anisotropic etch is performed, and the remaining portions of the dielectric spacer layer 88 form contact spacers 90 and 92 , as in 19 is shown. The corresponding step is through the step 214 represented in the in 26 indicated process flow is indicated. Then it becomes a conductive material 94 deposited to the remaining contact openings 86 and 86 to fill ( 18 ). Subsequently, a planarization process is performed, and the remaining conductive material 94 forms source / drain pins 96 and a gate pin 98 , as in 20 is shown. The corresponding step is through the step 216 represented in the in 26 indicated process flow is indicated. As in the 15 to 19 shows the manufacture of the contact pins 96 and 98 the production of respective contact openings 82 and 86 ( 17 ) by double structuring, so that the contact openings 82 and 86 can be arranged closely spaced from each other so that no optical proximity effect arises. In addition, the contact openings 82 and 86 filled simultaneously to reduce manufacturing costs.

20 also shows the widths of the contact pins 96 and 98 and the distances between adjacent pins 96 and 98 , The contact pins 96 have a width W3, and the contact pin 98 has a width W3 '. The distance between adjacent pins 96 and 98 is S1. In some embodiments of the present invention, the ratio S1 / W3 and the ratio S2 / W3 'are in the range of about 1.0 to 2.0.

The 21 to 25 show the production of a lower metal layer (hereinafter referred to as metal layer 1 or M1) and overlying vias with single damascene processes. In 21 become an etch stop layer 102 and a dielectric layer 104 produced. In some embodiments of the present invention, the etch stop layer is 102 made of a material that consists of the same group of candidate materials as for the etch stop layer 76 is selected, and the dielectric layer 104 may consist of a low-k dielectric material having a dielectric constant less than 3.8. For example, the low-k dielectric layer 104 may be comprised of a carbonaceous low-k dielectric material, HSQ, MSQ, or the like.

22 shows the production of trenches 106 wherein the fabrication comprises etching the low-k dielectric layer 104 and the etch stop layer 102 includes, causing the contact pins 96 and 98 be exposed. Then, as in 23 shown is metal pipes 108 and metal line spacers 110 produced. The appropriate step is through the step 218 represented in the in 26 indicated process flow is indicated. The manufacturing process may be the process for the preparation of the contact spacers 70 or the contact pins 74 be similar, and therefore the details of the manufacturing process will not be repeated here. The metal pipe spacers 110 may be made of a dielectric material selected from the same group of candidate materials as for the preparation of the contact spacers 70 is selected. The metal pipes 108 may include conductive diffusion barriers and a copper-containing metal material over the conductive diffusion barrier.

Then, vias become over the metal lines 108 made with a damascene process. In 23 become an etch stop layer 112 and a dielectric layer 114 produced. In some embodiments of the present invention, the etch stop layer is 112 made of a material that consists of the same group of candidate materials as for the etch stop layers 76 and 102 is selected, and the dielectric layer 114 may be made of a low-k dielectric material similar to the material of the low-k dielectric layer 104. 24 shows the production of via openings 115 and a dielectric layer 116 which may be a conformal or substantially conformal layer deposited by ALD, CVD or the like. The dielectric layer 116 reaches into the via openings 115 into it.

25 shows the production of vias 118 and via spacers 120 , The corresponding step is represented by step 220, which is in the in 26 indicated process flow is indicated. The manufacturing method may be the method for the preparation of the contact spacers 70 and the contact pins 74 be similar, and therefore the details of the manufacturing process will not be repeated here. The via spacers 120 may be made of a dielectric material selected from the same group of candidate materials as for the preparation of the contact spacers 70 is selected. The vias 118 may include conductive diffusion barriers and a copper-containing metal material over the respective conductive diffusion barriers. In subsequent processes, the processes for the production of metal lines 108 , the metal conduit spacer 110 , the vias 118 and the via spacer 120 to produce overlying metal lines (such as M2, M3, M4 ... Mtop) and vias. The overlying metal lines and vias can with single damascene processes (which in the 21 to 25 or dual damascene processes, wherein a dielectric layer is deposited and anisotropically etched before the respective vias and metal lines are filled into the via openings or trenches.

The embodiments of the present application have several advantages. By fabricating contact spacers, metal line spacers, and / or via spacers, additional dielectric spacers are provided to prevent electrical shorting of underlying conductive features with overlying conductive features in a masking displacement. This enlarges the process window.

In some embodiments of the present invention, a method includes forming a lower source / drain contact pin in a lower interlayer dielectric. The lower source / drain contact pin is electrically connected to a source / drain region of a transistor. The method further includes forming an interlayer dielectric over the lower source / drain contact pin. In the inter-layer dielectric, a source / drain contact opening is made exposing the lower source / drain contact pin through the source / drain contact opening. A dielectric spacer layer is fabricated to have a first portion that extends into the source / drain contact opening and a second portion over the interlayer dielectric. Anisotropic etch is performed on the dielectric spacer layer with a remaining vertical portion of the dielectric spacer layer forming a source / drain contact spacer. The remaining portion of the source / drain contact opening is filled to form an upper source / drain contact pin.

In some embodiments of the present invention, a method comprises the steps of: fabricating a first source / drain contact pin in a first interlayer dielectric, wherein the first source / drain contact pin is electrically connected to a source / drain region of a transistor is connected; Forming a second interlayer dielectric over the first interlayer dielectric; Forming a second source / drain contact pin in the second interlayer dielectric; Forming a third interlayer dielectric over the second interlayer dielectric; and etching the second interlayer dielectric and the third interlayer dielectric to produce a gate contact opening. A gate of the transistor is exposed to the gate contact hole. In the gate contact opening, a gate contact spacer is produced. The gate contact spacer passes through the second interlayer dielectric and the third interlayer dielectric. In the gate contact opening, a gate contact pin is produced, wherein the gate contact pin is enclosed by the gate contact spacer.

In some embodiments of the present invention, a device comprises: a semiconductor substrate; a gate electrode over the semiconductor substrate; a source / drain region on one side of the gate electrode; a first interlayer dielectric over the source / drain region, wherein at least a portion of the gate electrode is in the first interlayer dielectric; a second interlayer dielectric over the first interlayer dielectric; a third interlayer dielectric over the second interlayer dielectric; a gate contact spacer passing through the second interlayer dielectric and the third interlayer dielectric; and a gate contact pin electrically connected to the gate electrode, the gate contact pin being enclosed by the gate contact spacer.

Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present invention. Those skilled in the art will appreciate that they may readily use the present invention as a basis for designing or modifying other methods and structures to achieve the same objects and / or advantages of the same as the embodiments or examples presented herein. Those skilled in the art should also recognize that such equivalent interpretations do not depart from the spirit and scope of the present invention and that they may make various changes, substitutions and alterations here without departing from the spirit and scope of the present invention.

Claims (20)

Procedure with the following steps: Forming a lower source / drain contact pin in a lower interlayer dielectric, wherein the lower source / drain contact pin is electrically connected to a source / drain region of a transistor; Forming a first interlayer dielectric over the lower source / drain pin; Forming a first source / drain contact opening in the first interlayer dielectric, wherein the lower source / drain contact pin is exposed by the first source / drain contact opening; Forming a first dielectric spacer layer, the first dielectric spacer layer having a first portion extending into the first source / drain contact opening and a second portion over the first interlayer dielectric; Performing an anisotropic etch on the first dielectric spacer layer, wherein a remaining vertical portion of the first dielectric spacer layer forms a first source / drain contact spacer; and Filling a remaining portion of the first source / drain contact opening to produce a first source / drain contact pin. Method according to Claim 1 method further comprising: forming a first etch stop layer over and in contact with a gate spacer of the transistor and the lower source / drain contact pin, wherein the first interlayer dielectric is disposed over and contacts the first etch stop layer. The method of any one of the preceding claims, further comprising: Etching the first interlayer dielectric to produce a gate contact opening; Etching a hard mask between gate spacers of the transistor to increase the gate contact opening between the gate spacers; Forming a second spacer layer having a portion extending into the gate contact opening; Etching the second spacer layer to make a gate contact spacer in the gate contact opening; and Producing a gate contact pin in the gate contact opening. Method according to Claim 3 , further comprising: forming a second interlayer dielectric over the first interlayer dielectric; Etching the second interlayer dielectric to produce a second source / drain contact opening, the second spacer layer extending further into the second source / drain contact opening, and further comprising a second source / drain contact spacer in the second spacer layer second source / drain contact opening is formed; and forming a second source / drain contact pin in the second source / drain contact opening. The method of any one of the preceding claims, further comprising: Forming a first low-k dielectric layer over the first inter-layer dielectric; Forming a metal line in the first low-k dielectric layer, wherein the metal line is electrically connected to the source / drain region; and manufacturing a dielectric metal line spacer enclosing the metal line. Method according to Claim 5 method further comprising: forming a second low-k dielectric layer over the first low-k dielectric layer; Forming a metal via in the second low-k dielectric layer, wherein the via is electrically connected to the source / drain region; and forming a dielectric via spacer enclosing the metal via. The method of any one of the preceding claims, further comprising: Forming a sacrificial layer over a gate stack of the transistor; Etching the sacrificial layer and the lower interlayer dielectric to produce a lower source / drain contact opening; Forming a lower contact spacer in the lower source / drain contact opening; Filling the lower source / drain contact opening with a conductive material; and Performing planarization to remove the sacrificial layer and portions of the conductive material over the lower interlayer dielectric to produce the lower source / drain contact pin. Procedure with the following steps: Forming a first source / drain contact pin in a first interlayer dielectric, wherein the first source / drain contact pin is electrically connected to a source / drain region of a transistor; Forming a second interlayer dielectric over the first interlayer dielectric; Forming a second source / drain contact pin in the second interlayer dielectric; Forming a third interlayer dielectric over the second interlayer dielectric; Etching the second interlayer dielectric and the third interlayer dielectric to make a gate contact opening exposing a gate electrode of the transistor to the gate contact opening; Forming a gate contact spacer in the gate contact opening, the gate contact spacer passing through the second interlayer dielectric and the third interlayer dielectric; and Producing a gate contact pin in the gate contact opening, wherein the gate contact pin is enclosed by the gate contact spacer. Method according to Claim 8 further comprising: etching the third interlayer dielectric to make a source / drain contact opening exposing the second source / drain contact pin through the source / drain contact opening; Forming a source / drain contact spacer in the source / drain contact opening; and fabricating a third source / drain contact pin in the source / drain contact opening, wherein the second source / drain contact pin is enclosed by the source / drain contact spacer. Method according to Claim 9 wherein a common deposition process and a common etching process are used for the fabrication of the gate contact spacer and for the fabrication of the source / drain contact spacer. Method according to one of Claims 8 to 10 wherein the fabrication of the gate contact spacer comprises: depositing a dielectric spacer layer that extends into the gate contact opening and passes through the second interlayer dielectric and the third interlayer dielectric; and performing an anisotropic etch on the dielectric spacer layer, wherein a remaining portion of the dielectric spacer layer forms the gate contact spacer. Method according to one of Claims 8 to 11 further comprising etching a hard mask between gate spacers of the transistor to increase the gate contact opening between the gate spacers after the second interlayer dielectric and the third interlayer dielectric have been etched to form the gate contact opening. Method according to Claim 12 wherein the gate contact spacer and the gate contact pin extend to a level lower than tops of the gate spacers. Method according to one of Claims 8 to 13 method further comprising: forming a first low-k dielectric layer over the third interlayer dielectric; Forming a metal line in the first low-k dielectric layer, wherein the metal line is electrically connected to the source / drain region; and Producing a dielectric metal line spacer enclosing the metal line. Method according to Claim 14 method further comprising: forming a second low-k dielectric layer over the first low-k dielectric layer; Forming a via in the second low-k dielectric layer, wherein the via is electrically connected to the source / drain region; and forming a dielectric via spacer enclosing the metal via. Device with: a semiconductor substrate; a gate electrode over the semiconductor substrate; a source / drain region on one side of the gate electrode; a first interlayer dielectric over the source / drain region, wherein at least a portion of the gate electrode is in the first interlayer dielectric; a second interlayer dielectric over the first interlayer dielectric; a third interlayer dielectric over the second interlayer dielectric; a gate contact spacer passing through the second interlayer dielectric and the third interlayer dielectric; and a gate contact pin electrically connected to the gate electrode, the gate contact pin being enclosed by the gate contact spacer. Device after Claim 16 , further comprising: gate spacers on opposite sides of the gate electrode, wherein top surfaces of the gate spacers are higher than an upper surface of the gate electrode and the gate contact spacer extends between the gate spacers. Device after Claim 16 or 17 wherein the gate contact spacer extends continuously from an upper surface of the third interlayer dielectric to an underside of the second interlayer dielectric without a detectable interface therebetween. Device according to one of Claims 16 to 18 further comprising: a first source / drain contact pin in the first interlayer dielectric; a second source / drain contact pin in the second interlayer dielectric having a detectable interface between the first source / drain contact pin and the second source / drain contact pin; and a source / drain contact spacer in the second interlayer dielectric surrounding the second source / drain contact pin. Device according to one of Claims 16 to 19 further comprising: a low-k dielectric layer over the third interlayer dielectric; a metal line in the low-k dielectric layer, the metal line being electrically connected to the source / drain region; and a dielectric metal line spacer surrounding the metal line.

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